pci.c revision 1.103.22.9
1 /* $NetBSD: pci.c,v 1.103.22.9 2007/12/01 04:25:37 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.103.22.9 2007/12/01 04:25:37 jmcneill Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 56 #include "locators.h" 57 58 static bool pci_child_register(device_t); 59 60 #ifdef PCI_CONFIG_DUMP 61 int pci_config_dump = 1; 62 #else 63 int pci_config_dump = 0; 64 #endif 65 66 int pciprint(void *, const char *); 67 68 #ifdef PCI_MACHDEP_ENUMERATE_BUS 69 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 70 #else 71 int pci_enumerate_bus(struct pci_softc *, const int *, 72 int (*)(struct pci_attach_args *), struct pci_attach_args *); 73 #endif 74 75 /* 76 * Important note about PCI-ISA bridges: 77 * 78 * Callbacks are used to configure these devices so that ISA/EISA bridges 79 * can attach their child busses after PCI configuration is done. 80 * 81 * This works because: 82 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 83 * (2) any ISA/EISA bridges must be attached to primary PCI 84 * busses (i.e. bus zero). 85 * 86 * That boils down to: there can only be one of these outstanding 87 * at a time, it is cleared when configuring PCI bus 0 before any 88 * subdevices have been found, and it is run after all subdevices 89 * of PCI bus 0 have been found. 90 * 91 * This is needed because there are some (legacy) PCI devices which 92 * can show up as ISA/EISA devices as well (the prime example of which 93 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 94 * and the bridge is seen before the video board is, the board can show 95 * up as an ISA device, and that can (bogusly) complicate the PCI device's 96 * attach code, or make the PCI device not be properly attached at all. 97 * 98 * We use the generic config_defer() facility to achieve this. 99 */ 100 101 static int 102 pcirescan(struct device *sc, const char *ifattr, const int *locators) 103 { 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 109 return (0); 110 } 111 112 static int 113 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return (0); 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return (0); 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return (1); 131 } 132 133 static void 134 pciattach(struct device *parent, struct device *self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = (struct pci_softc *)self; 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 pci_attach_hook(parent, self, pba); 145 146 aprint_naive("\n"); 147 aprint_normal("\n"); 148 149 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 150 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 151 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 152 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 153 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 154 155 if (io_enabled == 0 && mem_enabled == 0) { 156 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 157 return; 158 } 159 160 #define PRINT(str) \ 161 do { \ 162 aprint_normal("%s%s", sep, str); \ 163 sep = ", "; \ 164 } while (/*CONSTCOND*/0) 165 166 aprint_normal("%s: ", self->dv_xname); 167 168 if (io_enabled) 169 PRINT("i/o space"); 170 if (mem_enabled) 171 PRINT("memory space"); 172 aprint_normal(" enabled"); 173 174 if (mrl_enabled || mrm_enabled || mwi_enabled) { 175 if (mrl_enabled) 176 PRINT("rd/line"); 177 if (mrm_enabled) 178 PRINT("rd/mult"); 179 if (mwi_enabled) 180 PRINT("wr/inv"); 181 aprint_normal(" ok"); 182 } 183 184 aprint_normal("\n"); 185 186 #undef PRINT 187 188 sc->sc_iot = pba->pba_iot; 189 sc->sc_memt = pba->pba_memt; 190 sc->sc_dmat = pba->pba_dmat; 191 sc->sc_dmat64 = pba->pba_dmat64; 192 sc->sc_pc = pba->pba_pc; 193 sc->sc_bus = pba->pba_bus; 194 sc->sc_bridgetag = pba->pba_bridgetag; 195 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 196 sc->sc_intrswiz = pba->pba_intrswiz; 197 sc->sc_intrtag = pba->pba_intrtag; 198 sc->sc_flags = pba->pba_flags; 199 200 device_pnp_driver_set_child_register(&sc->sc_dev, pci_child_register); 201 202 pcirescan(&sc->sc_dev, "pci", wildcard); 203 204 if (!pnp_device_register(self, NULL, NULL)) 205 aprint_error_dev(self, "couldn't establish power handler\n"); 206 } 207 208 static int 209 pcidetach(struct device *self, int flags) 210 { 211 pnp_device_deregister(self); 212 return 0; 213 } 214 215 int 216 pciprint(void *aux, const char *pnp) 217 { 218 struct pci_attach_args *pa = aux; 219 char devinfo[256]; 220 const struct pci_quirkdata *qd; 221 222 if (pnp) { 223 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 224 aprint_normal("%s at %s", devinfo, pnp); 225 } 226 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 227 if (pci_config_dump) { 228 printf(": "); 229 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 230 if (!pnp) 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 printf("%s at %s", devinfo, pnp ? pnp : "?"); 233 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 234 #ifdef __i386__ 235 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 236 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 237 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 238 #else 239 printf("intrswiz %#lx, intrpin %#lx", 240 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 241 #endif 242 printf(", i/o %s, mem %s,", 243 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 244 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 245 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 246 PCI_PRODUCT(pa->pa_id)); 247 if (qd == NULL) { 248 printf(" no quirks"); 249 } else { 250 bitmask_snprintf(qd->quirks, 251 "\002\001multifn\002singlefn\003skipfunc0" 252 "\004skipfunc1\005skipfunc2\006skipfunc3" 253 "\007skipfunc4\010skipfunc5\011skipfunc6" 254 "\012skipfunc7", 255 devinfo, sizeof (devinfo)); 256 printf(" quirks %s", devinfo); 257 } 258 printf(")"); 259 } 260 return (UNCONF); 261 } 262 263 int 264 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 265 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 266 { 267 pci_chipset_tag_t pc = sc->sc_pc; 268 struct pci_attach_args pa; 269 pcireg_t id, csr, class, intr, bhlcr; 270 int ret, pin, bus, device, function; 271 int locs[PCICF_NLOCS]; 272 struct device *subdev; 273 274 pci_decompose_tag(pc, tag, &bus, &device, &function); 275 276 /* a driver already attached? */ 277 if (sc->PCI_SC_DEVICESC(device, function) && !match) 278 return (0); 279 280 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 281 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 282 return (0); 283 284 id = pci_conf_read(pc, tag, PCI_ID_REG); 285 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 286 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 287 288 /* Invalid vendor ID value? */ 289 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 290 return (0); 291 /* XXX Not invalid, but we've done this ~forever. */ 292 if (PCI_VENDOR(id) == 0) 293 return (0); 294 295 pa.pa_iot = sc->sc_iot; 296 pa.pa_memt = sc->sc_memt; 297 pa.pa_dmat = sc->sc_dmat; 298 pa.pa_dmat64 = sc->sc_dmat64; 299 pa.pa_pc = pc; 300 pa.pa_bus = bus; 301 pa.pa_device = device; 302 pa.pa_function = function; 303 pa.pa_tag = tag; 304 pa.pa_id = id; 305 pa.pa_class = class; 306 307 /* 308 * Set up memory, I/O enable, and PCI command flags 309 * as appropriate. 310 */ 311 pa.pa_flags = sc->sc_flags; 312 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 313 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 314 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 315 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 316 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 317 } else if ((csr & PCI_COMMAND_IO_ENABLE) == 0 || 318 (csr & PCI_COMMAND_MEM_ENABLE) == 0) { 319 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 320 csr | sc->sc_flags); 321 } 322 323 /* 324 * If the cache line size is not configured, then 325 * clear the MRL/MRM/MWI command-ok flags. 326 */ 327 if (PCI_CACHELINE(bhlcr) == 0) 328 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 329 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 330 331 if (sc->sc_bridgetag == NULL) { 332 pa.pa_intrswiz = 0; 333 pa.pa_intrtag = tag; 334 } else { 335 pa.pa_intrswiz = sc->sc_intrswiz + device; 336 pa.pa_intrtag = sc->sc_intrtag; 337 } 338 339 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 340 341 pin = PCI_INTERRUPT_PIN(intr); 342 pa.pa_rawintrpin = pin; 343 if (pin == PCI_INTERRUPT_PIN_NONE) { 344 /* no interrupt */ 345 pa.pa_intrpin = 0; 346 } else { 347 /* 348 * swizzle it based on the number of busses we're 349 * behind and our device number. 350 */ 351 pa.pa_intrpin = /* XXX */ 352 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 353 } 354 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 355 356 if (match != NULL) { 357 ret = (*match)(&pa); 358 if (ret != 0 && pap != NULL) 359 *pap = pa; 360 } else { 361 locs[PCICF_DEV] = device; 362 locs[PCICF_FUNCTION] = function; 363 364 subdev = config_found_sm_loc(&sc->sc_dev, "pci", locs, &pa, 365 pciprint, config_stdsubmatch); 366 sc->PCI_SC_DEVICESC(device, function) = subdev; 367 ret = (subdev != NULL); 368 } 369 370 return (ret); 371 } 372 373 static void 374 pcidevdetached(struct device *sc, struct device *dev) 375 { 376 struct pci_softc *psc = (struct pci_softc *)sc; 377 int d, f; 378 379 d = device_locator(dev, PCICF_DEV); 380 f = device_locator(dev, PCICF_FUNCTION); 381 382 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 383 384 psc->PCI_SC_DEVICESC(d, f) = 0; 385 } 386 387 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 388 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached); 389 390 int 391 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 392 int *offset, pcireg_t *value) 393 { 394 pcireg_t reg; 395 unsigned int ofs; 396 397 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 398 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 399 return (0); 400 401 /* Determine the Capability List Pointer register to start with. */ 402 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 403 switch (PCI_HDRTYPE_TYPE(reg)) { 404 case 0: /* standard device header */ 405 case 1: /* PCI-PCI bridge header */ 406 ofs = PCI_CAPLISTPTR_REG; 407 break; 408 case 2: /* PCI-CardBus Bridge header */ 409 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 410 break; 411 default: 412 return (0); 413 } 414 415 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 416 while (ofs != 0) { 417 #ifdef DIAGNOSTIC 418 if ((ofs & 3) || (ofs < 0x40)) 419 panic("pci_get_capability"); 420 #endif 421 reg = pci_conf_read(pc, tag, ofs); 422 if (PCI_CAPLIST_CAP(reg) == capid) { 423 if (offset) 424 *offset = ofs; 425 if (value) 426 *value = reg; 427 return (1); 428 } 429 ofs = PCI_CAPLIST_NEXT(reg); 430 } 431 432 return (0); 433 } 434 435 int 436 pci_find_device(struct pci_attach_args *pa, 437 int (*match)(struct pci_attach_args *)) 438 { 439 extern struct cfdriver pci_cd; 440 struct device *pcidev; 441 int i; 442 static const int wildcard[2] = { 443 PCICF_DEV_DEFAULT, 444 PCICF_FUNCTION_DEFAULT 445 }; 446 447 for (i = 0; i < pci_cd.cd_ndevs; i++) { 448 pcidev = pci_cd.cd_devs[i]; 449 if (pcidev != NULL && 450 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 451 match, pa) != 0) 452 return (1); 453 } 454 return (0); 455 } 456 457 #ifndef PCI_MACHDEP_ENUMERATE_BUS 458 /* 459 * Generic PCI bus enumeration routine. Used unless machine-dependent 460 * code needs to provide something else. 461 */ 462 int 463 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 464 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 465 { 466 pci_chipset_tag_t pc = sc->sc_pc; 467 int device, function, nfunctions, ret; 468 const struct pci_quirkdata *qd; 469 pcireg_t id, bhlcr; 470 pcitag_t tag; 471 #ifdef __PCI_BUS_DEVORDER 472 char devs[32]; 473 int i; 474 #endif 475 476 #ifdef __PCI_BUS_DEVORDER 477 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 478 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 479 #else 480 for (device = 0; device < sc->sc_maxndevs; device++) 481 #endif 482 { 483 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 484 (locators[PCICF_DEV] != device)) 485 continue; 486 487 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 488 489 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 490 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 491 continue; 492 493 id = pci_conf_read(pc, tag, PCI_ID_REG); 494 495 /* Invalid vendor ID value? */ 496 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 497 continue; 498 /* XXX Not invalid, but we've done this ~forever. */ 499 if (PCI_VENDOR(id) == 0) 500 continue; 501 502 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 503 504 if (qd != NULL && 505 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 506 nfunctions = 8; 507 else if (qd != NULL && 508 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 509 nfunctions = 1; 510 else 511 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 512 513 for (function = 0; function < nfunctions; function++) { 514 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 515 && (locators[PCICF_FUNCTION] != function)) 516 continue; 517 518 if (qd != NULL && 519 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 520 continue; 521 tag = pci_make_tag(pc, sc->sc_bus, device, function); 522 ret = pci_probe_device(sc, tag, match, pap); 523 if (match != NULL && ret != 0) 524 return (ret); 525 } 526 } 527 return (0); 528 } 529 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 530 531 532 /* 533 * Vital Product Data (PCI 2.2) 534 */ 535 536 int 537 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 538 pcireg_t *data) 539 { 540 uint32_t reg; 541 int ofs, i, j; 542 543 KASSERT(data != NULL); 544 KASSERT((offset + count) < 0x7fff); 545 546 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 547 return (1); 548 549 for (i = 0; i < count; offset += sizeof(*data), i++) { 550 reg &= 0x0000ffff; 551 reg &= ~PCI_VPD_OPFLAG; 552 reg |= PCI_VPD_ADDRESS(offset); 553 pci_conf_write(pc, tag, ofs, reg); 554 555 /* 556 * PCI 2.2 does not specify how long we should poll 557 * for completion nor whether the operation can fail. 558 */ 559 j = 0; 560 do { 561 if (j++ == 20) 562 return (1); 563 delay(4); 564 reg = pci_conf_read(pc, tag, ofs); 565 } while ((reg & PCI_VPD_OPFLAG) == 0); 566 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 567 } 568 569 return (0); 570 } 571 572 int 573 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 574 pcireg_t *data) 575 { 576 pcireg_t reg; 577 int ofs, i, j; 578 579 KASSERT(data != NULL); 580 KASSERT((offset + count) < 0x7fff); 581 582 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 583 return (1); 584 585 for (i = 0; i < count; offset += sizeof(*data), i++) { 586 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 587 588 reg &= 0x0000ffff; 589 reg |= PCI_VPD_OPFLAG; 590 reg |= PCI_VPD_ADDRESS(offset); 591 pci_conf_write(pc, tag, ofs, reg); 592 593 /* 594 * PCI 2.2 does not specify how long we should poll 595 * for completion nor whether the operation can fail. 596 */ 597 j = 0; 598 do { 599 if (j++ == 20) 600 return (1); 601 delay(1); 602 reg = pci_conf_read(pc, tag, ofs); 603 } while (reg & PCI_VPD_OPFLAG); 604 } 605 606 return (0); 607 } 608 609 int 610 pci_dma64_available(struct pci_attach_args *pa) 611 { 612 #ifdef _PCI_HAVE_DMA64 613 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 614 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 615 return 1; 616 #endif 617 return 0; 618 } 619 620 void 621 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 622 struct pci_conf_state *pcs) 623 { 624 int off; 625 626 for (off = 0; off < 16; off++) 627 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 628 629 return; 630 } 631 632 void 633 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 634 struct pci_conf_state *pcs) 635 { 636 int off; 637 pcireg_t val; 638 639 for (off = 15; off >= 0; off--) { 640 val = pci_conf_read(pc, tag, (off * 4)); 641 if (val != pcs->reg[off]) 642 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 643 } 644 645 return; 646 } 647 648 /* 649 * Power Management Capability (Rev 2.2) 650 */ 651 static int 652 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 653 int offset) 654 { 655 pcireg_t value, now; 656 657 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 658 now = value & PCI_PMCSR_STATE_MASK; 659 switch (now) { 660 case PCI_PMCSR_STATE_D0: 661 case PCI_PMCSR_STATE_D1: 662 case PCI_PMCSR_STATE_D2: 663 case PCI_PMCSR_STATE_D3: 664 *state = now; 665 return 0; 666 default: 667 return EINVAL; 668 } 669 } 670 671 int 672 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 673 { 674 int offset; 675 pcireg_t value; 676 677 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 678 return EOPNOTSUPP; 679 680 return pci_get_powerstate_int(pc, tag, state, offset); 681 } 682 683 static int 684 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 685 int offset, pcireg_t cap_reg) 686 { 687 pcireg_t value, cap, now; 688 689 cap = cap_reg >> PCI_PMCR_SHIFT; 690 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 691 now = value & PCI_PMCSR_STATE_MASK; 692 value &= ~PCI_PMCSR_STATE_MASK; 693 694 if (now == state) 695 return 0; 696 switch (state) { 697 case PCI_PMCSR_STATE_D0: 698 value |= PCI_PMCSR_STATE_D0; 699 break; 700 case PCI_PMCSR_STATE_D1: 701 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 702 printf("invalid transition from %d to D1\n", (int)now); 703 return EINVAL; 704 } 705 if (!(cap & PCI_PMCR_D1SUPP)) { 706 printf("D1 not supported\n"); 707 return EOPNOTSUPP; 708 } 709 value |= PCI_PMCSR_STATE_D1; 710 break; 711 case PCI_PMCSR_STATE_D2: 712 if (now == PCI_PMCSR_STATE_D3) { 713 printf("invalid transition from %d to D2\n", (int)now); 714 return EINVAL; 715 } 716 if (!(cap & PCI_PMCR_D2SUPP)) { 717 printf("D2 not supported\n"); 718 return EOPNOTSUPP; 719 } 720 value |= PCI_PMCSR_STATE_D2; 721 break; 722 case PCI_PMCSR_STATE_D3: 723 value |= PCI_PMCSR_STATE_D3; 724 break; 725 default: 726 return EINVAL; 727 } 728 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 729 DELAY(1000); 730 return 0; 731 } 732 733 int 734 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 735 { 736 int offset; 737 pcireg_t value; 738 739 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 740 printf("pci_set_powerstate not supported\n"); 741 return EOPNOTSUPP; 742 } 743 744 return pci_set_powerstate_int(pc, tag, state, offset, value); 745 } 746 747 int 748 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, void *sc, 749 int (*wakefun)(pci_chipset_tag_t, pcitag_t, void *, pcireg_t)) 750 { 751 struct device *dv = sc; 752 pcireg_t pmode; 753 int error; 754 755 if ((error = pci_get_powerstate(pc, tag, &pmode))) 756 return error; 757 758 switch (pmode) { 759 case PCI_PMCSR_STATE_D0: 760 break; 761 case PCI_PMCSR_STATE_D3: 762 if (wakefun == NULL) { 763 /* 764 * The card has lost all configuration data in 765 * this state, so punt. 766 */ 767 aprint_error( 768 "%s: unable to wake up from power state D3\n", 769 dv->dv_xname); 770 return EOPNOTSUPP; 771 } 772 /*FALLTHROUGH*/ 773 default: 774 if (wakefun) { 775 error = (*wakefun)(pc, tag, sc, pmode); 776 if (error) 777 return error; 778 } 779 aprint_normal("%s: waking up from power state D%d\n", 780 dv->dv_xname, pmode); 781 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 782 return error; 783 } 784 return 0; 785 } 786 787 int 788 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 789 void *sc, pcireg_t state) 790 { 791 return 0; 792 } 793 794 void 795 pci_disable_retry(pci_chipset_tag_t pc, pcitag_t tag) 796 { 797 pcireg_t retry; 798 799 /* 800 * Disable retry timeout to keep PCI Tx retries from 801 * interfering with ACPI C3 CPU state. 802 */ 803 retry = pci_conf_read(pc, tag, PCI_RETRY_TIMEOUT_REG); 804 retry &= ~PCI_RETRY_TIMEOUT_REG_MASK; 805 pci_conf_write(pc, tag, PCI_RETRY_TIMEOUT_REG, retry); 806 } 807 808 struct pci_child_power { 809 struct pci_conf_state p_pciconf; 810 pci_chipset_tag_t p_pc; 811 pcitag_t p_tag; 812 bool p_has_pm; 813 int p_pm_offset; 814 pcireg_t p_pm_cap; 815 pcireg_t p_class; 816 }; 817 818 static bool 819 pci_child_suspend(device_t dv) 820 { 821 struct pci_child_power *priv = device_pnp_bus_private(dv); 822 823 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 824 825 if (priv->p_has_pm && 826 PCI_CLASS(priv->p_class) != PCI_CLASS_DISPLAY && 827 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 828 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 829 aprint_error_dev(dv, "unsupported state, continuing.\n"); 830 return false; 831 } 832 return true; 833 } 834 835 static bool 836 pci_child_resume(device_t dv) 837 { 838 struct pci_child_power *priv = device_pnp_bus_private(dv); 839 840 if (priv->p_has_pm && 841 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 842 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 843 aprint_error_dev(dv, "unsupported state, continuing.\n"); 844 return false; 845 } 846 847 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 848 849 return true; 850 } 851 852 static void 853 pci_child_deregister(device_t dv) 854 { 855 struct pci_child_power *priv = device_pnp_bus_private(dv); 856 857 free(priv, M_DEVBUF); 858 } 859 860 static bool 861 pci_child_register(device_t child) 862 { 863 device_t self = device_parent(child); 864 struct pci_softc *sc = device_private(self); 865 struct pci_child_power *priv; 866 int device, function, off; 867 pcireg_t reg; 868 869 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 870 871 device = device_locator(child, PCICF_DEV); 872 function = device_locator(child, PCICF_FUNCTION); 873 874 priv->p_pc = sc->sc_pc; 875 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 876 function); 877 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 878 879 if (pci_get_capability(priv->p_pc, priv->p_tag, 880 PCI_CAP_PWRMGMT, &off, ®)) { 881 priv->p_has_pm = true; 882 priv->p_pm_offset = off; 883 priv->p_pm_cap = reg; 884 } else { 885 priv->p_has_pm = false; 886 priv->p_pm_offset = -1; 887 } 888 889 device_pnp_bus_register(child, priv, pci_child_suspend, 890 pci_child_resume, pci_child_deregister); 891 892 return true; 893 } 894
Indexes created Tue Sep 30 20:09:53 GMT 2025