pci.c revision 1.107
1 /* $NetBSD: pci.c,v 1.107 2007/12/09 20:28:11 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.107 2007/12/09 20:28:11 jmcneill Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 56 #include "locators.h" 57 58 static bool pci_child_register(device_t); 59 60 #ifdef PCI_CONFIG_DUMP 61 int pci_config_dump = 1; 62 #else 63 int pci_config_dump = 0; 64 #endif 65 66 int pciprint(void *, const char *); 67 68 #ifdef PCI_MACHDEP_ENUMERATE_BUS 69 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 70 #else 71 int pci_enumerate_bus(struct pci_softc *, const int *, 72 int (*)(struct pci_attach_args *), struct pci_attach_args *); 73 #endif 74 75 /* 76 * Important note about PCI-ISA bridges: 77 * 78 * Callbacks are used to configure these devices so that ISA/EISA bridges 79 * can attach their child busses after PCI configuration is done. 80 * 81 * This works because: 82 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 83 * (2) any ISA/EISA bridges must be attached to primary PCI 84 * busses (i.e. bus zero). 85 * 86 * That boils down to: there can only be one of these outstanding 87 * at a time, it is cleared when configuring PCI bus 0 before any 88 * subdevices have been found, and it is run after all subdevices 89 * of PCI bus 0 have been found. 90 * 91 * This is needed because there are some (legacy) PCI devices which 92 * can show up as ISA/EISA devices as well (the prime example of which 93 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 94 * and the bridge is seen before the video board is, the board can show 95 * up as an ISA device, and that can (bogusly) complicate the PCI device's 96 * attach code, or make the PCI device not be properly attached at all. 97 * 98 * We use the generic config_defer() facility to achieve this. 99 */ 100 101 static int 102 pcirescan(struct device *sc, const char *ifattr, const int *locators) 103 { 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 109 return (0); 110 } 111 112 static int 113 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return (0); 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return (0); 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return (1); 131 } 132 133 static void 134 pciattach(struct device *parent, struct device *self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = (struct pci_softc *)self; 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 pci_attach_hook(parent, self, pba); 145 146 aprint_naive("\n"); 147 aprint_normal("\n"); 148 149 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 150 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 151 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 152 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 153 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 154 155 if (io_enabled == 0 && mem_enabled == 0) { 156 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 157 goto fail; 158 } 159 160 #define PRINT(str) \ 161 do { \ 162 aprint_verbose("%s%s", sep, str); \ 163 sep = ", "; \ 164 } while (/*CONSTCOND*/0) 165 166 aprint_verbose("%s: ", self->dv_xname); 167 168 if (io_enabled) 169 PRINT("i/o space"); 170 if (mem_enabled) 171 PRINT("memory space"); 172 aprint_verbose(" enabled"); 173 174 if (mrl_enabled || mrm_enabled || mwi_enabled) { 175 if (mrl_enabled) 176 PRINT("rd/line"); 177 if (mrm_enabled) 178 PRINT("rd/mult"); 179 if (mwi_enabled) 180 PRINT("wr/inv"); 181 aprint_verbose(" ok"); 182 } 183 184 aprint_verbose("\n"); 185 186 #undef PRINT 187 188 sc->sc_iot = pba->pba_iot; 189 sc->sc_memt = pba->pba_memt; 190 sc->sc_dmat = pba->pba_dmat; 191 sc->sc_dmat64 = pba->pba_dmat64; 192 sc->sc_pc = pba->pba_pc; 193 sc->sc_bus = pba->pba_bus; 194 sc->sc_bridgetag = pba->pba_bridgetag; 195 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 196 sc->sc_intrswiz = pba->pba_intrswiz; 197 sc->sc_intrtag = pba->pba_intrtag; 198 sc->sc_flags = pba->pba_flags; 199 200 device_pmf_driver_set_child_register(&sc->sc_dev, pci_child_register); 201 202 pcirescan(&sc->sc_dev, "pci", wildcard); 203 204 fail: 205 if (!pmf_device_register(self, NULL, NULL)) 206 aprint_error_dev(self, "couldn't establish power handler\n"); 207 } 208 209 static int 210 pcidetach(struct device *self, int flags) 211 { 212 pmf_device_deregister(self); 213 return 0; 214 } 215 216 int 217 pciprint(void *aux, const char *pnp) 218 { 219 struct pci_attach_args *pa = aux; 220 char devinfo[256]; 221 const struct pci_quirkdata *qd; 222 223 if (pnp) { 224 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 225 aprint_normal("%s at %s", devinfo, pnp); 226 } 227 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 228 if (pci_config_dump) { 229 printf(": "); 230 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 231 if (!pnp) 232 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 233 printf("%s at %s", devinfo, pnp ? pnp : "?"); 234 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 235 #ifdef __i386__ 236 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 237 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 238 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 239 #else 240 printf("intrswiz %#lx, intrpin %#lx", 241 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 242 #endif 243 printf(", i/o %s, mem %s,", 244 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 245 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 246 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 247 PCI_PRODUCT(pa->pa_id)); 248 if (qd == NULL) { 249 printf(" no quirks"); 250 } else { 251 bitmask_snprintf(qd->quirks, 252 "\002\001multifn\002singlefn\003skipfunc0" 253 "\004skipfunc1\005skipfunc2\006skipfunc3" 254 "\007skipfunc4\010skipfunc5\011skipfunc6" 255 "\012skipfunc7", 256 devinfo, sizeof (devinfo)); 257 printf(" quirks %s", devinfo); 258 } 259 printf(")"); 260 } 261 return (UNCONF); 262 } 263 264 int 265 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 266 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 267 { 268 pci_chipset_tag_t pc = sc->sc_pc; 269 struct pci_attach_args pa; 270 pcireg_t id, csr, class, intr, bhlcr; 271 int ret, pin, bus, device, function; 272 int locs[PCICF_NLOCS]; 273 struct device *subdev; 274 275 pci_decompose_tag(pc, tag, &bus, &device, &function); 276 277 /* a driver already attached? */ 278 if (sc->PCI_SC_DEVICESC(device, function) && !match) 279 return (0); 280 281 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 282 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 283 return (0); 284 285 id = pci_conf_read(pc, tag, PCI_ID_REG); 286 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 287 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 288 289 /* Invalid vendor ID value? */ 290 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 291 return (0); 292 /* XXX Not invalid, but we've done this ~forever. */ 293 if (PCI_VENDOR(id) == 0) 294 return (0); 295 296 pa.pa_iot = sc->sc_iot; 297 pa.pa_memt = sc->sc_memt; 298 pa.pa_dmat = sc->sc_dmat; 299 pa.pa_dmat64 = sc->sc_dmat64; 300 pa.pa_pc = pc; 301 pa.pa_bus = bus; 302 pa.pa_device = device; 303 pa.pa_function = function; 304 pa.pa_tag = tag; 305 pa.pa_id = id; 306 pa.pa_class = class; 307 308 /* 309 * Set up memory, I/O enable, and PCI command flags 310 * as appropriate. 311 */ 312 pa.pa_flags = sc->sc_flags; 313 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 314 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 315 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 316 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 317 318 /* 319 * If the cache line size is not configured, then 320 * clear the MRL/MRM/MWI command-ok flags. 321 */ 322 if (PCI_CACHELINE(bhlcr) == 0) 323 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 324 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 325 326 if (sc->sc_bridgetag == NULL) { 327 pa.pa_intrswiz = 0; 328 pa.pa_intrtag = tag; 329 } else { 330 pa.pa_intrswiz = sc->sc_intrswiz + device; 331 pa.pa_intrtag = sc->sc_intrtag; 332 } 333 334 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 335 336 pin = PCI_INTERRUPT_PIN(intr); 337 pa.pa_rawintrpin = pin; 338 if (pin == PCI_INTERRUPT_PIN_NONE) { 339 /* no interrupt */ 340 pa.pa_intrpin = 0; 341 } else { 342 /* 343 * swizzle it based on the number of busses we're 344 * behind and our device number. 345 */ 346 pa.pa_intrpin = /* XXX */ 347 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 348 } 349 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 350 351 if (match != NULL) { 352 ret = (*match)(&pa); 353 if (ret != 0 && pap != NULL) 354 *pap = pa; 355 } else { 356 locs[PCICF_DEV] = device; 357 locs[PCICF_FUNCTION] = function; 358 359 subdev = config_found_sm_loc(&sc->sc_dev, "pci", locs, &pa, 360 pciprint, config_stdsubmatch); 361 sc->PCI_SC_DEVICESC(device, function) = subdev; 362 ret = (subdev != NULL); 363 } 364 365 return (ret); 366 } 367 368 static void 369 pcidevdetached(struct device *sc, struct device *dev) 370 { 371 struct pci_softc *psc = (struct pci_softc *)sc; 372 int d, f; 373 374 d = device_locator(dev, PCICF_DEV); 375 f = device_locator(dev, PCICF_FUNCTION); 376 377 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 378 379 psc->PCI_SC_DEVICESC(d, f) = 0; 380 } 381 382 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 383 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached); 384 385 int 386 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 387 int *offset, pcireg_t *value) 388 { 389 pcireg_t reg; 390 unsigned int ofs; 391 392 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 393 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 394 return (0); 395 396 /* Determine the Capability List Pointer register to start with. */ 397 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 398 switch (PCI_HDRTYPE_TYPE(reg)) { 399 case 0: /* standard device header */ 400 case 1: /* PCI-PCI bridge header */ 401 ofs = PCI_CAPLISTPTR_REG; 402 break; 403 case 2: /* PCI-CardBus Bridge header */ 404 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 405 break; 406 default: 407 return (0); 408 } 409 410 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 411 while (ofs != 0) { 412 #ifdef DIAGNOSTIC 413 if ((ofs & 3) || (ofs < 0x40)) 414 panic("pci_get_capability"); 415 #endif 416 reg = pci_conf_read(pc, tag, ofs); 417 if (PCI_CAPLIST_CAP(reg) == capid) { 418 if (offset) 419 *offset = ofs; 420 if (value) 421 *value = reg; 422 return (1); 423 } 424 ofs = PCI_CAPLIST_NEXT(reg); 425 } 426 427 return (0); 428 } 429 430 int 431 pci_find_device(struct pci_attach_args *pa, 432 int (*match)(struct pci_attach_args *)) 433 { 434 extern struct cfdriver pci_cd; 435 struct device *pcidev; 436 int i; 437 static const int wildcard[2] = { 438 PCICF_DEV_DEFAULT, 439 PCICF_FUNCTION_DEFAULT 440 }; 441 442 for (i = 0; i < pci_cd.cd_ndevs; i++) { 443 pcidev = pci_cd.cd_devs[i]; 444 if (pcidev != NULL && 445 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 446 match, pa) != 0) 447 return (1); 448 } 449 return (0); 450 } 451 452 #ifndef PCI_MACHDEP_ENUMERATE_BUS 453 /* 454 * Generic PCI bus enumeration routine. Used unless machine-dependent 455 * code needs to provide something else. 456 */ 457 int 458 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 459 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 460 { 461 pci_chipset_tag_t pc = sc->sc_pc; 462 int device, function, nfunctions, ret; 463 const struct pci_quirkdata *qd; 464 pcireg_t id, bhlcr; 465 pcitag_t tag; 466 #ifdef __PCI_BUS_DEVORDER 467 char devs[32]; 468 int i; 469 #endif 470 471 #ifdef __PCI_BUS_DEVORDER 472 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 473 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 474 #else 475 for (device = 0; device < sc->sc_maxndevs; device++) 476 #endif 477 { 478 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 479 (locators[PCICF_DEV] != device)) 480 continue; 481 482 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 483 484 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 485 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 486 continue; 487 488 id = pci_conf_read(pc, tag, PCI_ID_REG); 489 490 /* Invalid vendor ID value? */ 491 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 492 continue; 493 /* XXX Not invalid, but we've done this ~forever. */ 494 if (PCI_VENDOR(id) == 0) 495 continue; 496 497 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 498 499 if (qd != NULL && 500 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 501 nfunctions = 8; 502 else if (qd != NULL && 503 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 504 nfunctions = 1; 505 else 506 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 507 508 for (function = 0; function < nfunctions; function++) { 509 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 510 && (locators[PCICF_FUNCTION] != function)) 511 continue; 512 513 if (qd != NULL && 514 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 515 continue; 516 tag = pci_make_tag(pc, sc->sc_bus, device, function); 517 ret = pci_probe_device(sc, tag, match, pap); 518 if (match != NULL && ret != 0) 519 return (ret); 520 } 521 } 522 return (0); 523 } 524 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 525 526 527 /* 528 * Vital Product Data (PCI 2.2) 529 */ 530 531 int 532 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 533 pcireg_t *data) 534 { 535 uint32_t reg; 536 int ofs, i, j; 537 538 KASSERT(data != NULL); 539 KASSERT((offset + count) < 0x7fff); 540 541 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 542 return (1); 543 544 for (i = 0; i < count; offset += sizeof(*data), i++) { 545 reg &= 0x0000ffff; 546 reg &= ~PCI_VPD_OPFLAG; 547 reg |= PCI_VPD_ADDRESS(offset); 548 pci_conf_write(pc, tag, ofs, reg); 549 550 /* 551 * PCI 2.2 does not specify how long we should poll 552 * for completion nor whether the operation can fail. 553 */ 554 j = 0; 555 do { 556 if (j++ == 20) 557 return (1); 558 delay(4); 559 reg = pci_conf_read(pc, tag, ofs); 560 } while ((reg & PCI_VPD_OPFLAG) == 0); 561 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 562 } 563 564 return (0); 565 } 566 567 int 568 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 569 pcireg_t *data) 570 { 571 pcireg_t reg; 572 int ofs, i, j; 573 574 KASSERT(data != NULL); 575 KASSERT((offset + count) < 0x7fff); 576 577 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 578 return (1); 579 580 for (i = 0; i < count; offset += sizeof(*data), i++) { 581 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 582 583 reg &= 0x0000ffff; 584 reg |= PCI_VPD_OPFLAG; 585 reg |= PCI_VPD_ADDRESS(offset); 586 pci_conf_write(pc, tag, ofs, reg); 587 588 /* 589 * PCI 2.2 does not specify how long we should poll 590 * for completion nor whether the operation can fail. 591 */ 592 j = 0; 593 do { 594 if (j++ == 20) 595 return (1); 596 delay(1); 597 reg = pci_conf_read(pc, tag, ofs); 598 } while (reg & PCI_VPD_OPFLAG); 599 } 600 601 return (0); 602 } 603 604 int 605 pci_dma64_available(struct pci_attach_args *pa) 606 { 607 #ifdef _PCI_HAVE_DMA64 608 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 609 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 610 return 1; 611 #endif 612 return 0; 613 } 614 615 void 616 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 617 struct pci_conf_state *pcs) 618 { 619 int off; 620 621 for (off = 0; off < 16; off++) 622 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 623 624 return; 625 } 626 627 void 628 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 629 struct pci_conf_state *pcs) 630 { 631 int off; 632 pcireg_t val; 633 634 for (off = 15; off >= 0; off--) { 635 val = pci_conf_read(pc, tag, (off * 4)); 636 if (val != pcs->reg[off]) 637 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 638 } 639 640 return; 641 } 642 643 /* 644 * Power Management Capability (Rev 2.2) 645 */ 646 static int 647 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 648 int offset) 649 { 650 pcireg_t value, now; 651 652 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 653 now = value & PCI_PMCSR_STATE_MASK; 654 switch (now) { 655 case PCI_PMCSR_STATE_D0: 656 case PCI_PMCSR_STATE_D1: 657 case PCI_PMCSR_STATE_D2: 658 case PCI_PMCSR_STATE_D3: 659 *state = now; 660 return 0; 661 default: 662 return EINVAL; 663 } 664 } 665 666 int 667 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 668 { 669 int offset; 670 pcireg_t value; 671 672 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 673 return EOPNOTSUPP; 674 675 return pci_get_powerstate_int(pc, tag, state, offset); 676 } 677 678 static int 679 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 680 int offset, pcireg_t cap_reg) 681 { 682 pcireg_t value, cap, now; 683 684 cap = cap_reg >> PCI_PMCR_SHIFT; 685 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 686 now = value & PCI_PMCSR_STATE_MASK; 687 value &= ~PCI_PMCSR_STATE_MASK; 688 689 if (now == state) 690 return 0; 691 switch (state) { 692 case PCI_PMCSR_STATE_D0: 693 value |= PCI_PMCSR_STATE_D0; 694 break; 695 case PCI_PMCSR_STATE_D1: 696 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 697 printf("invalid transition from %d to D1\n", (int)now); 698 return EINVAL; 699 } 700 if (!(cap & PCI_PMCR_D1SUPP)) { 701 printf("D1 not supported\n"); 702 return EOPNOTSUPP; 703 } 704 value |= PCI_PMCSR_STATE_D1; 705 break; 706 case PCI_PMCSR_STATE_D2: 707 if (now == PCI_PMCSR_STATE_D3) { 708 printf("invalid transition from %d to D2\n", (int)now); 709 return EINVAL; 710 } 711 if (!(cap & PCI_PMCR_D2SUPP)) { 712 printf("D2 not supported\n"); 713 return EOPNOTSUPP; 714 } 715 value |= PCI_PMCSR_STATE_D2; 716 break; 717 case PCI_PMCSR_STATE_D3: 718 value |= PCI_PMCSR_STATE_D3; 719 break; 720 default: 721 return EINVAL; 722 } 723 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 724 DELAY(1000); 725 return 0; 726 } 727 728 int 729 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 730 { 731 int offset; 732 pcireg_t value; 733 734 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 735 printf("pci_set_powerstate not supported\n"); 736 return EOPNOTSUPP; 737 } 738 739 return pci_set_powerstate_int(pc, tag, state, offset, value); 740 } 741 742 int 743 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, void *sc, 744 int (*wakefun)(pci_chipset_tag_t, pcitag_t, void *, pcireg_t)) 745 { 746 struct device *dv = sc; 747 pcireg_t pmode; 748 int error; 749 750 if ((error = pci_get_powerstate(pc, tag, &pmode))) 751 return error; 752 753 switch (pmode) { 754 case PCI_PMCSR_STATE_D0: 755 break; 756 case PCI_PMCSR_STATE_D3: 757 if (wakefun == NULL) { 758 /* 759 * The card has lost all configuration data in 760 * this state, so punt. 761 */ 762 aprint_error( 763 "%s: unable to wake up from power state D3\n", 764 dv->dv_xname); 765 return EOPNOTSUPP; 766 } 767 /*FALLTHROUGH*/ 768 default: 769 if (wakefun) { 770 error = (*wakefun)(pc, tag, sc, pmode); 771 if (error) 772 return error; 773 } 774 aprint_normal("%s: waking up from power state D%d\n", 775 dv->dv_xname, pmode); 776 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 777 return error; 778 } 779 return 0; 780 } 781 782 int 783 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 784 void *sc, pcireg_t state) 785 { 786 return 0; 787 } 788 789 void 790 pci_disable_retry(pci_chipset_tag_t pc, pcitag_t tag) 791 { 792 pcireg_t retry; 793 794 /* 795 * Disable retry timeout to keep PCI Tx retries from 796 * interfering with ACPI C3 CPU state. 797 */ 798 retry = pci_conf_read(pc, tag, PCI_RETRY_TIMEOUT_REG); 799 retry &= ~PCI_RETRY_TIMEOUT_REG_MASK; 800 pci_conf_write(pc, tag, PCI_RETRY_TIMEOUT_REG, retry); 801 } 802 803 struct pci_child_power { 804 struct pci_conf_state p_pciconf; 805 pci_chipset_tag_t p_pc; 806 pcitag_t p_tag; 807 bool p_has_pm; 808 int p_pm_offset; 809 pcireg_t p_pm_cap; 810 pcireg_t p_class; 811 }; 812 813 static bool 814 pci_child_suspend(device_t dv) 815 { 816 struct pci_child_power *priv = device_pmf_bus_private(dv); 817 818 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 819 820 if (priv->p_has_pm && 821 PCI_CLASS(priv->p_class) != PCI_CLASS_DISPLAY && 822 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 823 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 824 aprint_error_dev(dv, "unsupported state, continuing.\n"); 825 return false; 826 } 827 return true; 828 } 829 830 static bool 831 pci_child_resume(device_t dv) 832 { 833 struct pci_child_power *priv = device_pmf_bus_private(dv); 834 835 if (priv->p_has_pm && 836 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 837 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 838 aprint_error_dev(dv, "unsupported state, continuing.\n"); 839 return false; 840 } 841 842 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 843 844 return true; 845 } 846 847 static void 848 pci_child_deregister(device_t dv) 849 { 850 struct pci_child_power *priv = device_pmf_bus_private(dv); 851 852 free(priv, M_DEVBUF); 853 } 854 855 static bool 856 pci_child_register(device_t child) 857 { 858 device_t self = device_parent(child); 859 struct pci_softc *sc = device_private(self); 860 struct pci_child_power *priv; 861 int device, function, off; 862 pcireg_t reg; 863 864 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 865 866 device = device_locator(child, PCICF_DEV); 867 function = device_locator(child, PCICF_FUNCTION); 868 869 priv->p_pc = sc->sc_pc; 870 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 871 function); 872 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 873 874 if (pci_get_capability(priv->p_pc, priv->p_tag, 875 PCI_CAP_PWRMGMT, &off, ®)) { 876 priv->p_has_pm = true; 877 priv->p_pm_offset = off; 878 priv->p_pm_cap = reg; 879 } else { 880 priv->p_has_pm = false; 881 priv->p_pm_offset = -1; 882 } 883 884 device_pmf_bus_register(child, priv, pci_child_suspend, 885 pci_child_resume, pci_child_deregister); 886 887 return true; 888 } 889
Indexes created Wed Sep 24 05:09:52 GMT 2025