pci.c revision 1.116
1 /* $NetBSD: pci.c,v 1.116 2008/04/09 17:01:53 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.116 2008/04/09 17:01:53 dyoung Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 56 #include "locators.h" 57 58 static bool pci_child_register(device_t); 59 60 #ifdef PCI_CONFIG_DUMP 61 int pci_config_dump = 1; 62 #else 63 int pci_config_dump = 0; 64 #endif 65 66 int pciprint(void *, const char *); 67 68 #ifdef PCI_MACHDEP_ENUMERATE_BUS 69 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 70 #else 71 int pci_enumerate_bus(struct pci_softc *, const int *, 72 int (*)(struct pci_attach_args *), struct pci_attach_args *); 73 #endif 74 75 /* 76 * Important note about PCI-ISA bridges: 77 * 78 * Callbacks are used to configure these devices so that ISA/EISA bridges 79 * can attach their child busses after PCI configuration is done. 80 * 81 * This works because: 82 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 83 * (2) any ISA/EISA bridges must be attached to primary PCI 84 * busses (i.e. bus zero). 85 * 86 * That boils down to: there can only be one of these outstanding 87 * at a time, it is cleared when configuring PCI bus 0 before any 88 * subdevices have been found, and it is run after all subdevices 89 * of PCI bus 0 have been found. 90 * 91 * This is needed because there are some (legacy) PCI devices which 92 * can show up as ISA/EISA devices as well (the prime example of which 93 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 94 * and the bridge is seen before the video board is, the board can show 95 * up as an ISA device, and that can (bogusly) complicate the PCI device's 96 * attach code, or make the PCI device not be properly attached at all. 97 * 98 * We use the generic config_defer() facility to achieve this. 99 */ 100 101 int 102 pcirescan(device_t self, const char *ifattr, const int *locators) 103 { 104 struct pci_softc *sc = device_private(self); 105 106 KASSERT(ifattr && !strcmp(ifattr, "pci")); 107 KASSERT(locators); 108 109 pci_enumerate_bus(sc, locators, NULL, NULL); 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return (0); 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return (0); 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return (1); 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 bitmask_snprintf(qd->quirks, 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", 263 devinfo, sizeof (devinfo)); 264 printf(" quirks %s", devinfo); 265 } 266 printf(")"); 267 } 268 return (UNCONF); 269 } 270 271 int 272 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 273 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, csr, class, intr, bhlcr; 278 int ret, pin, bus, device, function; 279 int locs[PCICF_NLOCS]; 280 device_t subdev; 281 282 pci_decompose_tag(pc, tag, &bus, &device, &function); 283 284 /* a driver already attached? */ 285 if (sc->PCI_SC_DEVICESC(device, function) && !match) 286 return (0); 287 288 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 289 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 290 return (0); 291 292 id = pci_conf_read(pc, tag, PCI_ID_REG); 293 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 294 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 295 296 /* Invalid vendor ID value? */ 297 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 298 return (0); 299 /* XXX Not invalid, but we've done this ~forever. */ 300 if (PCI_VENDOR(id) == 0) 301 return (0); 302 303 pa.pa_iot = sc->sc_iot; 304 pa.pa_memt = sc->sc_memt; 305 pa.pa_dmat = sc->sc_dmat; 306 pa.pa_dmat64 = sc->sc_dmat64; 307 pa.pa_pc = pc; 308 pa.pa_bus = bus; 309 pa.pa_device = device; 310 pa.pa_function = function; 311 pa.pa_tag = tag; 312 pa.pa_id = id; 313 pa.pa_class = class; 314 315 /* 316 * Set up memory, I/O enable, and PCI command flags 317 * as appropriate. 318 */ 319 pa.pa_flags = sc->sc_flags; 320 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 321 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 322 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 323 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 324 325 /* 326 * If the cache line size is not configured, then 327 * clear the MRL/MRM/MWI command-ok flags. 328 */ 329 if (PCI_CACHELINE(bhlcr) == 0) 330 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 331 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 332 333 if (sc->sc_bridgetag == NULL) { 334 pa.pa_intrswiz = 0; 335 pa.pa_intrtag = tag; 336 } else { 337 pa.pa_intrswiz = sc->sc_intrswiz + device; 338 pa.pa_intrtag = sc->sc_intrtag; 339 } 340 341 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 342 343 pin = PCI_INTERRUPT_PIN(intr); 344 pa.pa_rawintrpin = pin; 345 if (pin == PCI_INTERRUPT_PIN_NONE) { 346 /* no interrupt */ 347 pa.pa_intrpin = 0; 348 } else { 349 /* 350 * swizzle it based on the number of busses we're 351 * behind and our device number. 352 */ 353 pa.pa_intrpin = /* XXX */ 354 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 355 } 356 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 357 358 if (match != NULL) { 359 ret = (*match)(&pa); 360 if (ret != 0 && pap != NULL) 361 *pap = pa; 362 } else { 363 locs[PCICF_DEV] = device; 364 locs[PCICF_FUNCTION] = function; 365 366 subdev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 367 pciprint, config_stdsubmatch); 368 sc->PCI_SC_DEVICESC(device, function) = subdev; 369 ret = (subdev != NULL); 370 } 371 372 return (ret); 373 } 374 375 void 376 pcidevdetached(device_t self, device_t child) 377 { 378 struct pci_softc *psc = device_private(self); 379 int d, f; 380 381 d = device_locator(child, PCICF_DEV); 382 f = device_locator(child, PCICF_FUNCTION); 383 384 KASSERT(psc->PCI_SC_DEVICESC(d, f) == child); 385 386 psc->PCI_SC_DEVICESC(d, f) = 0; 387 } 388 389 CFATTACH_DECL2_NEW(pci, sizeof(struct pci_softc), 390 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached); 391 392 int 393 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 394 int *offset, pcireg_t *value) 395 { 396 pcireg_t reg; 397 unsigned int ofs; 398 399 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 400 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 401 return (0); 402 403 /* Determine the Capability List Pointer register to start with. */ 404 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 405 switch (PCI_HDRTYPE_TYPE(reg)) { 406 case 0: /* standard device header */ 407 case 1: /* PCI-PCI bridge header */ 408 ofs = PCI_CAPLISTPTR_REG; 409 break; 410 case 2: /* PCI-CardBus Bridge header */ 411 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 412 break; 413 default: 414 return (0); 415 } 416 417 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 418 while (ofs != 0) { 419 #ifdef DIAGNOSTIC 420 if ((ofs & 3) || (ofs < 0x40)) 421 panic("pci_get_capability"); 422 #endif 423 reg = pci_conf_read(pc, tag, ofs); 424 if (PCI_CAPLIST_CAP(reg) == capid) { 425 if (offset) 426 *offset = ofs; 427 if (value) 428 *value = reg; 429 return (1); 430 } 431 ofs = PCI_CAPLIST_NEXT(reg); 432 } 433 434 return (0); 435 } 436 437 int 438 pci_find_device(struct pci_attach_args *pa, 439 int (*match)(struct pci_attach_args *)) 440 { 441 extern struct cfdriver pci_cd; 442 device_t pcidev; 443 int i; 444 static const int wildcard[2] = { 445 PCICF_DEV_DEFAULT, 446 PCICF_FUNCTION_DEFAULT 447 }; 448 449 for (i = 0; i < pci_cd.cd_ndevs; i++) { 450 pcidev = pci_cd.cd_devs[i]; 451 if (pcidev != NULL && 452 pci_enumerate_bus(device_private(pcidev), wildcard, 453 match, pa) != 0) 454 return (1); 455 } 456 return (0); 457 } 458 459 #ifndef PCI_MACHDEP_ENUMERATE_BUS 460 /* 461 * Generic PCI bus enumeration routine. Used unless machine-dependent 462 * code needs to provide something else. 463 */ 464 int 465 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 466 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 467 { 468 pci_chipset_tag_t pc = sc->sc_pc; 469 int device, function, nfunctions, ret; 470 const struct pci_quirkdata *qd; 471 pcireg_t id, bhlcr; 472 pcitag_t tag; 473 #ifdef __PCI_BUS_DEVORDER 474 char devs[32]; 475 int i; 476 #endif 477 478 #ifdef __PCI_BUS_DEVORDER 479 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 480 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 481 #else 482 for (device = 0; device < sc->sc_maxndevs; device++) 483 #endif 484 { 485 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 486 (locators[PCICF_DEV] != device)) 487 continue; 488 489 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 490 491 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 492 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 493 continue; 494 495 id = pci_conf_read(pc, tag, PCI_ID_REG); 496 497 /* Invalid vendor ID value? */ 498 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 499 continue; 500 /* XXX Not invalid, but we've done this ~forever. */ 501 if (PCI_VENDOR(id) == 0) 502 continue; 503 504 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 505 506 if (qd != NULL && 507 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 508 nfunctions = 8; 509 else if (qd != NULL && 510 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 511 nfunctions = 1; 512 else 513 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 514 515 for (function = 0; function < nfunctions; function++) { 516 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 517 && (locators[PCICF_FUNCTION] != function)) 518 continue; 519 520 if (qd != NULL && 521 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 522 continue; 523 tag = pci_make_tag(pc, sc->sc_bus, device, function); 524 ret = pci_probe_device(sc, tag, match, pap); 525 if (match != NULL && ret != 0) 526 return (ret); 527 } 528 } 529 return (0); 530 } 531 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 532 533 534 /* 535 * Vital Product Data (PCI 2.2) 536 */ 537 538 int 539 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 540 pcireg_t *data) 541 { 542 uint32_t reg; 543 int ofs, i, j; 544 545 KASSERT(data != NULL); 546 KASSERT((offset + count) < 0x7fff); 547 548 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 549 return (1); 550 551 for (i = 0; i < count; offset += sizeof(*data), i++) { 552 reg &= 0x0000ffff; 553 reg &= ~PCI_VPD_OPFLAG; 554 reg |= PCI_VPD_ADDRESS(offset); 555 pci_conf_write(pc, tag, ofs, reg); 556 557 /* 558 * PCI 2.2 does not specify how long we should poll 559 * for completion nor whether the operation can fail. 560 */ 561 j = 0; 562 do { 563 if (j++ == 20) 564 return (1); 565 delay(4); 566 reg = pci_conf_read(pc, tag, ofs); 567 } while ((reg & PCI_VPD_OPFLAG) == 0); 568 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 569 } 570 571 return (0); 572 } 573 574 int 575 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 576 pcireg_t *data) 577 { 578 pcireg_t reg; 579 int ofs, i, j; 580 581 KASSERT(data != NULL); 582 KASSERT((offset + count) < 0x7fff); 583 584 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 585 return (1); 586 587 for (i = 0; i < count; offset += sizeof(*data), i++) { 588 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 589 590 reg &= 0x0000ffff; 591 reg |= PCI_VPD_OPFLAG; 592 reg |= PCI_VPD_ADDRESS(offset); 593 pci_conf_write(pc, tag, ofs, reg); 594 595 /* 596 * PCI 2.2 does not specify how long we should poll 597 * for completion nor whether the operation can fail. 598 */ 599 j = 0; 600 do { 601 if (j++ == 20) 602 return (1); 603 delay(1); 604 reg = pci_conf_read(pc, tag, ofs); 605 } while (reg & PCI_VPD_OPFLAG); 606 } 607 608 return (0); 609 } 610 611 int 612 pci_dma64_available(struct pci_attach_args *pa) 613 { 614 #ifdef _PCI_HAVE_DMA64 615 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 616 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 617 return 1; 618 #endif 619 return 0; 620 } 621 622 void 623 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 624 struct pci_conf_state *pcs) 625 { 626 int off; 627 628 for (off = 0; off < 16; off++) 629 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 630 631 return; 632 } 633 634 void 635 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 636 struct pci_conf_state *pcs) 637 { 638 int off; 639 pcireg_t val; 640 641 for (off = 15; off >= 0; off--) { 642 val = pci_conf_read(pc, tag, (off * 4)); 643 if (val != pcs->reg[off]) 644 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 645 } 646 647 return; 648 } 649 650 /* 651 * Power Management Capability (Rev 2.2) 652 */ 653 static int 654 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 655 int offset) 656 { 657 pcireg_t value, now; 658 659 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 660 now = value & PCI_PMCSR_STATE_MASK; 661 switch (now) { 662 case PCI_PMCSR_STATE_D0: 663 case PCI_PMCSR_STATE_D1: 664 case PCI_PMCSR_STATE_D2: 665 case PCI_PMCSR_STATE_D3: 666 *state = now; 667 return 0; 668 default: 669 return EINVAL; 670 } 671 } 672 673 int 674 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 675 { 676 int offset; 677 pcireg_t value; 678 679 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 680 return EOPNOTSUPP; 681 682 return pci_get_powerstate_int(pc, tag, state, offset); 683 } 684 685 static int 686 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 687 int offset, pcireg_t cap_reg) 688 { 689 pcireg_t value, cap, now; 690 691 cap = cap_reg >> PCI_PMCR_SHIFT; 692 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 693 now = value & PCI_PMCSR_STATE_MASK; 694 value &= ~PCI_PMCSR_STATE_MASK; 695 696 if (now == state) 697 return 0; 698 switch (state) { 699 case PCI_PMCSR_STATE_D0: 700 break; 701 case PCI_PMCSR_STATE_D1: 702 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 703 printf("invalid transition from %d to D1\n", (int)now); 704 return EINVAL; 705 } 706 if (!(cap & PCI_PMCR_D1SUPP)) { 707 printf("D1 not supported\n"); 708 return EOPNOTSUPP; 709 } 710 break; 711 case PCI_PMCSR_STATE_D2: 712 if (now == PCI_PMCSR_STATE_D3) { 713 printf("invalid transition from %d to D2\n", (int)now); 714 return EINVAL; 715 } 716 if (!(cap & PCI_PMCR_D2SUPP)) { 717 printf("D2 not supported\n"); 718 return EOPNOTSUPP; 719 } 720 break; 721 case PCI_PMCSR_STATE_D3: 722 break; 723 default: 724 return EINVAL; 725 } 726 value |= state; 727 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 728 /* delay according to pcipm1.2, ch. 5.6.1 */ 729 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 730 DELAY(10000); 731 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 732 DELAY(200); 733 734 return 0; 735 } 736 737 int 738 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 739 { 740 int offset; 741 pcireg_t value; 742 743 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 744 printf("pci_set_powerstate not supported\n"); 745 return EOPNOTSUPP; 746 } 747 748 return pci_set_powerstate_int(pc, tag, state, offset, value); 749 } 750 751 int 752 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 753 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 754 { 755 pcireg_t pmode; 756 int error; 757 758 if ((error = pci_get_powerstate(pc, tag, &pmode))) 759 return error; 760 761 switch (pmode) { 762 case PCI_PMCSR_STATE_D0: 763 break; 764 case PCI_PMCSR_STATE_D3: 765 if (wakefun == NULL) { 766 /* 767 * The card has lost all configuration data in 768 * this state, so punt. 769 */ 770 aprint_error_dev(dev, 771 "unable to wake up from power state D3\n"); 772 return EOPNOTSUPP; 773 } 774 /*FALLTHROUGH*/ 775 default: 776 if (wakefun) { 777 error = (*wakefun)(pc, tag, dev, pmode); 778 if (error) 779 return error; 780 } 781 aprint_normal_dev(dev, "waking up from power state D%d\n", 782 pmode); 783 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 784 return error; 785 } 786 return 0; 787 } 788 789 int 790 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 791 device_t dev, pcireg_t state) 792 { 793 return 0; 794 } 795 796 /* I have disabled this code for now. --dyoung 797 * 798 * Insofar as I understand what the PCI retry timeout is [1], 799 * I see no justification for any driver to disable when it 800 * attaches/resumes a device. 801 * 802 * A PCI bus bridge may tell a bus master to retry its transaction 803 * at a later time if the resources to complete the transaction 804 * are not immediately available. Taking a guess, PCI bus masters 805 * that implement a PCI retry timeout register count down from the 806 * retry timeout to 0 while it retries a delayed PCI transaction. 807 * When it reaches 0, it stops retrying. A PCI master is *never* 808 * supposed to stop retrying a delayed transaction, though. 809 * 810 * Incidentally, I initially suspected that writing 0 to the register 811 * would not disable *retries*, but would disable the timeout. 812 * That is, any device whose retry timeout was set to 0 would 813 * *never* timeout. However, I found out, by using PCI debug 814 * facilities on the AMD Elan SC520, that if I write 0 to the retry 815 * timeout register on an ath(4) MiniPCI card, the card really does 816 * not retry transactions. 817 * 818 * Some uses of this register have mentioned "interference" with 819 * a CPU's "C3 sleep state." It seems to me that if a bus master 820 * is properly put to sleep, it will neither initiate new transactions, 821 * nor retry delayed transactions, so disabling retries should not 822 * be necessary. 823 * 824 * [1] The timeout does not appear to be documented in any PCI 825 * standard, and we have no documentation of it for the devices by 826 * Atheros, and others, that supposedly implement it. 827 */ 828 void 829 pci_disable_retry(pci_chipset_tag_t pc, pcitag_t tag) 830 { 831 #if 0 832 pcireg_t retry; 833 834 /* 835 * Disable retry timeout to keep PCI Tx retries from 836 * interfering with ACPI C3 CPU state. 837 */ 838 retry = pci_conf_read(pc, tag, PCI_RETRY_TIMEOUT_REG); 839 retry &= ~PCI_RETRY_TIMEOUT_REG_MASK; 840 pci_conf_write(pc, tag, PCI_RETRY_TIMEOUT_REG, retry); 841 #endif 842 } 843 844 struct pci_child_power { 845 struct pci_conf_state p_pciconf; 846 pci_chipset_tag_t p_pc; 847 pcitag_t p_tag; 848 bool p_has_pm; 849 int p_pm_offset; 850 pcireg_t p_pm_cap; 851 pcireg_t p_class; 852 }; 853 854 static bool 855 pci_child_suspend(device_t dv PMF_FN_ARGS) 856 { 857 struct pci_child_power *priv = device_pmf_bus_private(dv); 858 pcireg_t ocsr, csr; 859 860 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 861 862 if (!priv->p_has_pm) 863 return true; /* ??? hopefully handled by ACPI */ 864 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 865 return true; /* XXX */ 866 867 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 868 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 869 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 870 | PCI_COMMAND_MASTER_ENABLE); 871 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 872 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 873 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 874 pci_conf_write(priv->p_pc, priv->p_tag, 875 PCI_COMMAND_STATUS_REG, ocsr); 876 aprint_error_dev(dv, "unsupported state, continuing.\n"); 877 return false; 878 } 879 return true; 880 } 881 882 static bool 883 pci_child_resume(device_t dv PMF_FN_ARGS) 884 { 885 struct pci_child_power *priv = device_pmf_bus_private(dv); 886 887 if (priv->p_has_pm && 888 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 889 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 890 aprint_error_dev(dv, "unsupported state, continuing.\n"); 891 return false; 892 } 893 894 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 895 896 return true; 897 } 898 899 static bool 900 pci_child_shutdown(device_t dv, int how) 901 { 902 struct pci_child_power *priv = device_pmf_bus_private(dv); 903 pcireg_t csr; 904 905 /* disable busmastering */ 906 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 907 csr &= ~PCI_COMMAND_MASTER_ENABLE; 908 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 909 return true; 910 } 911 912 static void 913 pci_child_deregister(device_t dv) 914 { 915 struct pci_child_power *priv = device_pmf_bus_private(dv); 916 917 free(priv, M_DEVBUF); 918 } 919 920 static bool 921 pci_child_register(device_t child) 922 { 923 device_t self = device_parent(child); 924 struct pci_softc *sc = device_private(self); 925 struct pci_child_power *priv; 926 int device, function, off; 927 pcireg_t reg; 928 929 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 930 931 device = device_locator(child, PCICF_DEV); 932 function = device_locator(child, PCICF_FUNCTION); 933 934 priv->p_pc = sc->sc_pc; 935 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 936 function); 937 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 938 939 if (pci_get_capability(priv->p_pc, priv->p_tag, 940 PCI_CAP_PWRMGMT, &off, ®)) { 941 priv->p_has_pm = true; 942 priv->p_pm_offset = off; 943 priv->p_pm_cap = reg; 944 } else { 945 priv->p_has_pm = false; 946 priv->p_pm_offset = -1; 947 } 948 949 device_pmf_bus_register(child, priv, pci_child_suspend, 950 pci_child_resume, pci_child_shutdown, pci_child_deregister); 951 952 return true; 953 } 954
Indexes created Mon Sep 22 13:09:51 GMT 2025