pci.c revision 1.127.2.1
1 /* $NetBSD: pci.c,v 1.127.2.1 2010/05/30 05:17:36 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.127.2.1 2010/05/30 05:17:36 rmind Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <net/if.h> 56 57 #include "locators.h" 58 59 static bool pci_child_register(device_t); 60 61 #ifdef PCI_CONFIG_DUMP 62 int pci_config_dump = 1; 63 #else 64 int pci_config_dump = 0; 65 #endif 66 67 int pciprint(void *, const char *); 68 69 #ifdef PCI_MACHDEP_ENUMERATE_BUS 70 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 71 #else 72 int pci_enumerate_bus(struct pci_softc *, const int *, 73 int (*)(struct pci_attach_args *), struct pci_attach_args *); 74 #endif 75 76 /* 77 * Important note about PCI-ISA bridges: 78 * 79 * Callbacks are used to configure these devices so that ISA/EISA bridges 80 * can attach their child busses after PCI configuration is done. 81 * 82 * This works because: 83 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 84 * (2) any ISA/EISA bridges must be attached to primary PCI 85 * busses (i.e. bus zero). 86 * 87 * That boils down to: there can only be one of these outstanding 88 * at a time, it is cleared when configuring PCI bus 0 before any 89 * subdevices have been found, and it is run after all subdevices 90 * of PCI bus 0 have been found. 91 * 92 * This is needed because there are some (legacy) PCI devices which 93 * can show up as ISA/EISA devices as well (the prime example of which 94 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 95 * and the bridge is seen before the video board is, the board can show 96 * up as an ISA device, and that can (bogusly) complicate the PCI device's 97 * attach code, or make the PCI device not be properly attached at all. 98 * 99 * We use the generic config_defer() facility to achieve this. 100 */ 101 102 int 103 pcirescan(device_t self, const char *ifattr, const int *locators) 104 { 105 struct pci_softc *sc = device_private(self); 106 107 KASSERT(ifattr && !strcmp(ifattr, "pci")); 108 KASSERT(locators); 109 110 pci_verbose_ctl(true); /* Try to load the pciverbose module */ 111 112 pci_enumerate_bus(sc, locators, NULL, NULL); 113 114 pci_verbose_ctl(false); /* Now try to unload it */ 115 116 return 0; 117 } 118 119 int 120 pcimatch(device_t parent, cfdata_t cf, void *aux) 121 { 122 struct pcibus_attach_args *pba = aux; 123 124 /* Check the locators */ 125 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 126 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 127 return 0; 128 129 /* sanity */ 130 if (pba->pba_bus < 0 || pba->pba_bus > 255) 131 return 0; 132 133 /* 134 * XXX check other (hardware?) indicators 135 */ 136 137 return 1; 138 } 139 140 void 141 pciattach(device_t parent, device_t self, void *aux) 142 { 143 struct pcibus_attach_args *pba = aux; 144 struct pci_softc *sc = device_private(self); 145 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 146 const char *sep = ""; 147 static const int wildcard[PCICF_NLOCS] = { 148 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 149 }; 150 151 sc->sc_dev = self; 152 153 pci_attach_hook(parent, self, pba); 154 155 aprint_naive("\n"); 156 aprint_normal("\n"); 157 158 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 159 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 160 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 161 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 162 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 163 164 if (io_enabled == 0 && mem_enabled == 0) { 165 aprint_error_dev(self, "no spaces enabled!\n"); 166 goto fail; 167 } 168 169 #define PRINT(str) \ 170 do { \ 171 aprint_verbose("%s%s", sep, str); \ 172 sep = ", "; \ 173 } while (/*CONSTCOND*/0) 174 175 aprint_verbose_dev(self, ""); 176 177 if (io_enabled) 178 PRINT("i/o space"); 179 if (mem_enabled) 180 PRINT("memory space"); 181 aprint_verbose(" enabled"); 182 183 if (mrl_enabled || mrm_enabled || mwi_enabled) { 184 if (mrl_enabled) 185 PRINT("rd/line"); 186 if (mrm_enabled) 187 PRINT("rd/mult"); 188 if (mwi_enabled) 189 PRINT("wr/inv"); 190 aprint_verbose(" ok"); 191 } 192 193 aprint_verbose("\n"); 194 195 #undef PRINT 196 197 sc->sc_iot = pba->pba_iot; 198 sc->sc_memt = pba->pba_memt; 199 sc->sc_dmat = pba->pba_dmat; 200 sc->sc_dmat64 = pba->pba_dmat64; 201 sc->sc_pc = pba->pba_pc; 202 sc->sc_bus = pba->pba_bus; 203 sc->sc_bridgetag = pba->pba_bridgetag; 204 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 205 sc->sc_intrswiz = pba->pba_intrswiz; 206 sc->sc_intrtag = pba->pba_intrtag; 207 sc->sc_flags = pba->pba_flags; 208 209 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 210 211 pcirescan(sc->sc_dev, "pci", wildcard); 212 213 fail: 214 if (!pmf_device_register(self, NULL, NULL)) 215 aprint_error_dev(self, "couldn't establish power handler\n"); 216 } 217 218 int 219 pcidetach(device_t self, int flags) 220 { 221 int rc; 222 223 if ((rc = config_detach_children(self, flags)) != 0) 224 return rc; 225 pmf_device_deregister(self); 226 return 0; 227 } 228 229 int 230 pciprint(void *aux, const char *pnp) 231 { 232 struct pci_attach_args *pa = aux; 233 char devinfo[256]; 234 const struct pci_quirkdata *qd; 235 236 if (pnp) { 237 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 238 aprint_normal("%s at %s", devinfo, pnp); 239 } 240 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 241 if (pci_config_dump) { 242 printf(": "); 243 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 244 if (!pnp) 245 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 246 printf("%s at %s", devinfo, pnp ? pnp : "?"); 247 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 248 #ifdef __i386__ 249 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 250 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 251 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 252 #else 253 printf("intrswiz %#lx, intrpin %#lx", 254 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 255 #endif 256 printf(", i/o %s, mem %s,", 257 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 258 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 259 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 260 PCI_PRODUCT(pa->pa_id)); 261 if (qd == NULL) { 262 printf(" no quirks"); 263 } else { 264 snprintb(devinfo, sizeof (devinfo), 265 "\002\001multifn\002singlefn\003skipfunc0" 266 "\004skipfunc1\005skipfunc2\006skipfunc3" 267 "\007skipfunc4\010skipfunc5\011skipfunc6" 268 "\012skipfunc7", qd->quirks); 269 printf(" quirks %s", devinfo); 270 } 271 printf(")"); 272 } 273 return UNCONF; 274 } 275 276 int 277 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 278 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 279 { 280 pci_chipset_tag_t pc = sc->sc_pc; 281 struct pci_attach_args pa; 282 pcireg_t id, csr, class, intr, bhlcr; 283 int ret, pin, bus, device, function; 284 int locs[PCICF_NLOCS]; 285 286 pci_decompose_tag(pc, tag, &bus, &device, &function); 287 288 /* a driver already attached? */ 289 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 290 return 0; 291 292 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 293 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 294 return 0; 295 296 id = pci_conf_read(pc, tag, PCI_ID_REG); 297 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 298 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 299 300 /* Invalid vendor ID value? */ 301 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 302 return 0; 303 /* XXX Not invalid, but we've done this ~forever. */ 304 if (PCI_VENDOR(id) == 0) 305 return 0; 306 307 pa.pa_iot = sc->sc_iot; 308 pa.pa_memt = sc->sc_memt; 309 pa.pa_dmat = sc->sc_dmat; 310 pa.pa_dmat64 = sc->sc_dmat64; 311 pa.pa_pc = pc; 312 pa.pa_bus = bus; 313 pa.pa_device = device; 314 pa.pa_function = function; 315 pa.pa_tag = tag; 316 pa.pa_id = id; 317 pa.pa_class = class; 318 319 /* 320 * Set up memory, I/O enable, and PCI command flags 321 * as appropriate. 322 */ 323 pa.pa_flags = sc->sc_flags; 324 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 325 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 326 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 327 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 328 329 /* 330 * If the cache line size is not configured, then 331 * clear the MRL/MRM/MWI command-ok flags. 332 */ 333 if (PCI_CACHELINE(bhlcr) == 0) 334 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 335 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 336 337 if (sc->sc_bridgetag == NULL) { 338 pa.pa_intrswiz = 0; 339 pa.pa_intrtag = tag; 340 } else { 341 pa.pa_intrswiz = sc->sc_intrswiz + device; 342 pa.pa_intrtag = sc->sc_intrtag; 343 } 344 345 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 346 347 pin = PCI_INTERRUPT_PIN(intr); 348 pa.pa_rawintrpin = pin; 349 if (pin == PCI_INTERRUPT_PIN_NONE) { 350 /* no interrupt */ 351 pa.pa_intrpin = 0; 352 } else { 353 /* 354 * swizzle it based on the number of busses we're 355 * behind and our device number. 356 */ 357 pa.pa_intrpin = /* XXX */ 358 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 359 } 360 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 361 362 if (match != NULL) { 363 ret = (*match)(&pa); 364 if (ret != 0 && pap != NULL) 365 *pap = pa; 366 } else { 367 struct pci_child *c; 368 locs[PCICF_DEV] = device; 369 locs[PCICF_FUNCTION] = function; 370 371 c = &sc->PCI_SC_DEVICESC(device, function); 372 pci_conf_capture(pc, tag, &c->c_conf); 373 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 374 c->c_psok = true; 375 else 376 c->c_psok = false; 377 378 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 379 pciprint, config_stdsubmatch); 380 381 ret = (c->c_dev != NULL); 382 } 383 384 return ret; 385 } 386 387 void 388 pcidevdetached(device_t self, device_t child) 389 { 390 struct pci_softc *sc = device_private(self); 391 int d, f; 392 pcitag_t tag; 393 struct pci_child *c; 394 395 d = device_locator(child, PCICF_DEV); 396 f = device_locator(child, PCICF_FUNCTION); 397 398 c = &sc->PCI_SC_DEVICESC(d, f); 399 400 KASSERT(c->c_dev == child); 401 402 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 403 if (c->c_psok) 404 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 405 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 406 c->c_dev = NULL; 407 } 408 409 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 410 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 411 DVF_DETACH_SHUTDOWN); 412 413 int 414 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 415 int *offset, pcireg_t *value) 416 { 417 pcireg_t reg; 418 unsigned int ofs; 419 420 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 421 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 422 return 0; 423 424 /* Determine the Capability List Pointer register to start with. */ 425 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 426 switch (PCI_HDRTYPE_TYPE(reg)) { 427 case 0: /* standard device header */ 428 case 1: /* PCI-PCI bridge header */ 429 ofs = PCI_CAPLISTPTR_REG; 430 break; 431 case 2: /* PCI-CardBus Bridge header */ 432 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 433 break; 434 default: 435 return 0; 436 } 437 438 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 439 while (ofs != 0) { 440 if ((ofs & 3) || (ofs < 0x40)) { 441 int bus, device, function; 442 443 pci_decompose_tag(pc, tag, &bus, &device, &function); 444 445 printf("Skipping broken PCI header on %d:%d:%d\n", 446 bus, device, function); 447 break; 448 } 449 reg = pci_conf_read(pc, tag, ofs); 450 if (PCI_CAPLIST_CAP(reg) == capid) { 451 if (offset) 452 *offset = ofs; 453 if (value) 454 *value = reg; 455 return 1; 456 } 457 ofs = PCI_CAPLIST_NEXT(reg); 458 } 459 460 return 0; 461 } 462 463 int 464 pci_find_device(struct pci_attach_args *pa, 465 int (*match)(struct pci_attach_args *)) 466 { 467 extern struct cfdriver pci_cd; 468 device_t pcidev; 469 int i; 470 static const int wildcard[2] = { 471 PCICF_DEV_DEFAULT, 472 PCICF_FUNCTION_DEFAULT 473 }; 474 475 for (i = 0; i < pci_cd.cd_ndevs; i++) { 476 pcidev = device_lookup(&pci_cd, i); 477 if (pcidev != NULL && 478 pci_enumerate_bus(device_private(pcidev), wildcard, 479 match, pa) != 0) 480 return 1; 481 } 482 return 0; 483 } 484 485 #ifndef PCI_MACHDEP_ENUMERATE_BUS 486 /* 487 * Generic PCI bus enumeration routine. Used unless machine-dependent 488 * code needs to provide something else. 489 */ 490 int 491 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 492 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 493 { 494 pci_chipset_tag_t pc = sc->sc_pc; 495 int device, function, nfunctions, ret; 496 const struct pci_quirkdata *qd; 497 pcireg_t id, bhlcr; 498 pcitag_t tag; 499 #ifdef __PCI_BUS_DEVORDER 500 char devs[32]; 501 int i; 502 #endif 503 504 #ifdef __PCI_BUS_DEVORDER 505 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 506 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 507 #else 508 for (device = 0; device < sc->sc_maxndevs; device++) 509 #endif 510 { 511 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 512 (locators[PCICF_DEV] != device)) 513 continue; 514 515 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 516 517 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 518 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 519 continue; 520 521 id = pci_conf_read(pc, tag, PCI_ID_REG); 522 523 /* Invalid vendor ID value? */ 524 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 525 continue; 526 /* XXX Not invalid, but we've done this ~forever. */ 527 if (PCI_VENDOR(id) == 0) 528 continue; 529 530 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 531 532 if (qd != NULL && 533 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 534 nfunctions = 8; 535 else if (qd != NULL && 536 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 537 nfunctions = 1; 538 else 539 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 540 541 for (function = 0; function < nfunctions; function++) { 542 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 543 && (locators[PCICF_FUNCTION] != function)) 544 continue; 545 546 if (qd != NULL && 547 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 548 continue; 549 tag = pci_make_tag(pc, sc->sc_bus, device, function); 550 ret = pci_probe_device(sc, tag, match, pap); 551 if (match != NULL && ret != 0) 552 return ret; 553 } 554 } 555 return 0; 556 } 557 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 558 559 560 /* 561 * Vital Product Data (PCI 2.2) 562 */ 563 564 int 565 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 566 pcireg_t *data) 567 { 568 uint32_t reg; 569 int ofs, i, j; 570 571 KASSERT(data != NULL); 572 KASSERT((offset + count) < 0x7fff); 573 574 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 575 return 1; 576 577 for (i = 0; i < count; offset += sizeof(*data), i++) { 578 reg &= 0x0000ffff; 579 reg &= ~PCI_VPD_OPFLAG; 580 reg |= PCI_VPD_ADDRESS(offset); 581 pci_conf_write(pc, tag, ofs, reg); 582 583 /* 584 * PCI 2.2 does not specify how long we should poll 585 * for completion nor whether the operation can fail. 586 */ 587 j = 0; 588 do { 589 if (j++ == 20) 590 return 1; 591 delay(4); 592 reg = pci_conf_read(pc, tag, ofs); 593 } while ((reg & PCI_VPD_OPFLAG) == 0); 594 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 595 } 596 597 return 0; 598 } 599 600 int 601 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 602 pcireg_t *data) 603 { 604 pcireg_t reg; 605 int ofs, i, j; 606 607 KASSERT(data != NULL); 608 KASSERT((offset + count) < 0x7fff); 609 610 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 611 return 1; 612 613 for (i = 0; i < count; offset += sizeof(*data), i++) { 614 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 615 616 reg &= 0x0000ffff; 617 reg |= PCI_VPD_OPFLAG; 618 reg |= PCI_VPD_ADDRESS(offset); 619 pci_conf_write(pc, tag, ofs, reg); 620 621 /* 622 * PCI 2.2 does not specify how long we should poll 623 * for completion nor whether the operation can fail. 624 */ 625 j = 0; 626 do { 627 if (j++ == 20) 628 return 1; 629 delay(1); 630 reg = pci_conf_read(pc, tag, ofs); 631 } while (reg & PCI_VPD_OPFLAG); 632 } 633 634 return 0; 635 } 636 637 int 638 pci_dma64_available(struct pci_attach_args *pa) 639 { 640 #ifdef _PCI_HAVE_DMA64 641 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 642 return 1; 643 #endif 644 return 0; 645 } 646 647 void 648 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 649 struct pci_conf_state *pcs) 650 { 651 int off; 652 653 for (off = 0; off < 16; off++) 654 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 655 656 return; 657 } 658 659 void 660 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 661 struct pci_conf_state *pcs) 662 { 663 int off; 664 pcireg_t val; 665 666 for (off = 15; off >= 0; off--) { 667 val = pci_conf_read(pc, tag, (off * 4)); 668 if (val != pcs->reg[off]) 669 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 670 } 671 672 return; 673 } 674 675 /* 676 * Power Management Capability (Rev 2.2) 677 */ 678 static int 679 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 680 int offset) 681 { 682 pcireg_t value, now; 683 684 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 685 now = value & PCI_PMCSR_STATE_MASK; 686 switch (now) { 687 case PCI_PMCSR_STATE_D0: 688 case PCI_PMCSR_STATE_D1: 689 case PCI_PMCSR_STATE_D2: 690 case PCI_PMCSR_STATE_D3: 691 *state = now; 692 return 0; 693 default: 694 return EINVAL; 695 } 696 } 697 698 int 699 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 700 { 701 int offset; 702 pcireg_t value; 703 704 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 705 return EOPNOTSUPP; 706 707 return pci_get_powerstate_int(pc, tag, state, offset); 708 } 709 710 static int 711 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 712 int offset, pcireg_t cap_reg) 713 { 714 pcireg_t value, cap, now; 715 716 cap = cap_reg >> PCI_PMCR_SHIFT; 717 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 718 now = value & PCI_PMCSR_STATE_MASK; 719 value &= ~PCI_PMCSR_STATE_MASK; 720 721 if (now == state) 722 return 0; 723 switch (state) { 724 case PCI_PMCSR_STATE_D0: 725 break; 726 case PCI_PMCSR_STATE_D1: 727 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 728 printf("invalid transition from %d to D1\n", (int)now); 729 return EINVAL; 730 } 731 if (!(cap & PCI_PMCR_D1SUPP)) { 732 printf("D1 not supported\n"); 733 return EOPNOTSUPP; 734 } 735 break; 736 case PCI_PMCSR_STATE_D2: 737 if (now == PCI_PMCSR_STATE_D3) { 738 printf("invalid transition from %d to D2\n", (int)now); 739 return EINVAL; 740 } 741 if (!(cap & PCI_PMCR_D2SUPP)) { 742 printf("D2 not supported\n"); 743 return EOPNOTSUPP; 744 } 745 break; 746 case PCI_PMCSR_STATE_D3: 747 break; 748 default: 749 return EINVAL; 750 } 751 value |= state; 752 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 753 /* delay according to pcipm1.2, ch. 5.6.1 */ 754 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 755 DELAY(10000); 756 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 757 DELAY(200); 758 759 return 0; 760 } 761 762 int 763 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 764 { 765 int offset; 766 pcireg_t value; 767 768 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 769 printf("pci_set_powerstate not supported\n"); 770 return EOPNOTSUPP; 771 } 772 773 return pci_set_powerstate_int(pc, tag, state, offset, value); 774 } 775 776 int 777 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 778 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 779 { 780 pcireg_t pmode; 781 int error; 782 783 if ((error = pci_get_powerstate(pc, tag, &pmode))) 784 return error; 785 786 switch (pmode) { 787 case PCI_PMCSR_STATE_D0: 788 break; 789 case PCI_PMCSR_STATE_D3: 790 if (wakefun == NULL) { 791 /* 792 * The card has lost all configuration data in 793 * this state, so punt. 794 */ 795 aprint_error_dev(dev, 796 "unable to wake up from power state D3\n"); 797 return EOPNOTSUPP; 798 } 799 /*FALLTHROUGH*/ 800 default: 801 if (wakefun) { 802 error = (*wakefun)(pc, tag, dev, pmode); 803 if (error) 804 return error; 805 } 806 aprint_normal_dev(dev, "waking up from power state D%d\n", 807 pmode); 808 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 809 return error; 810 } 811 return 0; 812 } 813 814 int 815 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 816 device_t dev, pcireg_t state) 817 { 818 return 0; 819 } 820 821 struct pci_child_power { 822 struct pci_conf_state p_pciconf; 823 pci_chipset_tag_t p_pc; 824 pcitag_t p_tag; 825 bool p_has_pm; 826 int p_pm_offset; 827 pcireg_t p_pm_cap; 828 pcireg_t p_class; 829 }; 830 831 static bool 832 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 833 { 834 struct pci_child_power *priv = device_pmf_bus_private(dv); 835 pcireg_t ocsr, csr; 836 837 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 838 839 if (!priv->p_has_pm) 840 return true; /* ??? hopefully handled by ACPI */ 841 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 842 return true; /* XXX */ 843 844 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 845 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 846 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 847 | PCI_COMMAND_MASTER_ENABLE); 848 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 849 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 850 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 851 pci_conf_write(priv->p_pc, priv->p_tag, 852 PCI_COMMAND_STATUS_REG, ocsr); 853 aprint_error_dev(dv, "unsupported state, continuing.\n"); 854 return false; 855 } 856 return true; 857 } 858 859 static bool 860 pci_child_resume(device_t dv, const pmf_qual_t *qual) 861 { 862 struct pci_child_power *priv = device_pmf_bus_private(dv); 863 864 if (priv->p_has_pm && 865 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 866 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 867 aprint_error_dev(dv, "unsupported state, continuing.\n"); 868 return false; 869 } 870 871 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 872 873 return true; 874 } 875 876 static bool 877 pci_child_shutdown(device_t dv, int how) 878 { 879 struct pci_child_power *priv = device_pmf_bus_private(dv); 880 pcireg_t csr; 881 882 /* disable busmastering */ 883 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 884 csr &= ~PCI_COMMAND_MASTER_ENABLE; 885 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 886 return true; 887 } 888 889 static void 890 pci_child_deregister(device_t dv) 891 { 892 struct pci_child_power *priv = device_pmf_bus_private(dv); 893 894 free(priv, M_DEVBUF); 895 } 896 897 static bool 898 pci_child_register(device_t child) 899 { 900 device_t self = device_parent(child); 901 struct pci_softc *sc = device_private(self); 902 struct pci_child_power *priv; 903 int device, function, off; 904 pcireg_t reg; 905 906 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 907 908 device = device_locator(child, PCICF_DEV); 909 function = device_locator(child, PCICF_FUNCTION); 910 911 priv->p_pc = sc->sc_pc; 912 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 913 function); 914 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 915 916 if (pci_get_capability(priv->p_pc, priv->p_tag, 917 PCI_CAP_PWRMGMT, &off, ®)) { 918 priv->p_has_pm = true; 919 priv->p_pm_offset = off; 920 priv->p_pm_cap = reg; 921 } else { 922 priv->p_has_pm = false; 923 priv->p_pm_offset = -1; 924 } 925 926 device_pmf_bus_register(child, priv, pci_child_suspend, 927 pci_child_resume, pci_child_shutdown, pci_child_deregister); 928 929 return true; 930 } 931
Indexes created Tue Sep 30 20:09:53 GMT 2025