pci.c revision 1.127.2.4
1 /* $NetBSD: pci.c,v 1.127.2.4 2011/04/21 01:41:52 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.127.2.4 2011/04/21 01:41:52 rmind Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(const struct pci_attach_args *), 272 struct pci_attach_args *pap) 273 { 274 pci_chipset_tag_t pc = sc->sc_pc; 275 struct pci_attach_args pa; 276 pcireg_t id, csr, class, intr, bhlcr, bar, endbar; 277 int ret, pin, bus, device, function, i, width; 278 int locs[PCICF_NLOCS]; 279 280 pci_decompose_tag(pc, tag, &bus, &device, &function); 281 282 /* a driver already attached? */ 283 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 284 return 0; 285 286 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 287 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 288 return 0; 289 290 id = pci_conf_read(pc, tag, PCI_ID_REG); 291 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 292 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 293 294 /* Invalid vendor ID value? */ 295 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 296 return 0; 297 /* XXX Not invalid, but we've done this ~forever. */ 298 if (PCI_VENDOR(id) == 0) 299 return 0; 300 301 /* Collect memory range info */ 302 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 303 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 304 i = 0; 305 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 306 case PCI_HDRTYPE_PPB: 307 endbar = PCI_MAPREG_PPB_END; 308 break; 309 case PCI_HDRTYPE_PCB: 310 endbar = PCI_MAPREG_PCB_END; 311 break; 312 default: 313 endbar = PCI_MAPREG_END; 314 break; 315 } 316 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 317 struct pci_range *r; 318 pcireg_t type; 319 320 width = 4; 321 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 322 continue; 323 324 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 325 if (PCI_MAPREG_MEM_TYPE(type) == 326 PCI_MAPREG_MEM_TYPE_64BIT) 327 width = 8; 328 329 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 330 if (pci_mapreg_info(pc, tag, bar, type, 331 &r->r_offset, &r->r_size, &r->r_flags) != 0) 332 break; 333 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 334 && (r->r_size == 0x1000000)) { 335 struct pci_range *nr; 336 /* 337 * this has to be a mach64 338 * split things up so each half-aperture can 339 * be mapped PREFETCHABLE except the last page 340 * which may contain registers 341 */ 342 r->r_size = 0x7ff000; 343 r->r_flags = BUS_SPACE_MAP_LINEAR | 344 BUS_SPACE_MAP_PREFETCHABLE; 345 nr = &sc->PCI_SC_DEVICESC(device, 346 function).c_range[i++]; 347 nr->r_offset = r->r_offset + 0x800000; 348 nr->r_size = 0x7ff000; 349 nr->r_flags = BUS_SPACE_MAP_LINEAR | 350 BUS_SPACE_MAP_PREFETCHABLE; 351 } 352 353 } 354 } 355 356 pa.pa_iot = sc->sc_iot; 357 pa.pa_memt = sc->sc_memt; 358 pa.pa_dmat = sc->sc_dmat; 359 pa.pa_dmat64 = sc->sc_dmat64; 360 pa.pa_pc = pc; 361 pa.pa_bus = bus; 362 pa.pa_device = device; 363 pa.pa_function = function; 364 pa.pa_tag = tag; 365 pa.pa_id = id; 366 pa.pa_class = class; 367 368 /* 369 * Set up memory, I/O enable, and PCI command flags 370 * as appropriate. 371 */ 372 pa.pa_flags = sc->sc_flags; 373 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 374 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 375 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 376 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 377 378 /* 379 * If the cache line size is not configured, then 380 * clear the MRL/MRM/MWI command-ok flags. 381 */ 382 if (PCI_CACHELINE(bhlcr) == 0) { 383 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 384 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 385 } 386 387 if (sc->sc_bridgetag == NULL) { 388 pa.pa_intrswiz = 0; 389 pa.pa_intrtag = tag; 390 } else { 391 pa.pa_intrswiz = sc->sc_intrswiz + device; 392 pa.pa_intrtag = sc->sc_intrtag; 393 } 394 395 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 396 397 pin = PCI_INTERRUPT_PIN(intr); 398 pa.pa_rawintrpin = pin; 399 if (pin == PCI_INTERRUPT_PIN_NONE) { 400 /* no interrupt */ 401 pa.pa_intrpin = 0; 402 } else { 403 /* 404 * swizzle it based on the number of busses we're 405 * behind and our device number. 406 */ 407 pa.pa_intrpin = /* XXX */ 408 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 409 } 410 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 411 412 if (match != NULL) { 413 ret = (*match)(&pa); 414 if (ret != 0 && pap != NULL) 415 *pap = pa; 416 } else { 417 struct pci_child *c; 418 locs[PCICF_DEV] = device; 419 locs[PCICF_FUNCTION] = function; 420 421 c = &sc->PCI_SC_DEVICESC(device, function); 422 pci_conf_capture(pc, tag, &c->c_conf); 423 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 424 c->c_psok = true; 425 else 426 c->c_psok = false; 427 428 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 429 pciprint, config_stdsubmatch); 430 431 ret = (c->c_dev != NULL); 432 } 433 434 return ret; 435 } 436 437 void 438 pcidevdetached(device_t self, device_t child) 439 { 440 struct pci_softc *sc = device_private(self); 441 int d, f; 442 pcitag_t tag; 443 struct pci_child *c; 444 445 d = device_locator(child, PCICF_DEV); 446 f = device_locator(child, PCICF_FUNCTION); 447 448 c = &sc->PCI_SC_DEVICESC(d, f); 449 450 KASSERT(c->c_dev == child); 451 452 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 453 if (c->c_psok) 454 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 455 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 456 c->c_dev = NULL; 457 } 458 459 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 460 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 461 DVF_DETACH_SHUTDOWN); 462 463 int 464 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 465 int *offset, pcireg_t *value) 466 { 467 pcireg_t reg; 468 unsigned int ofs; 469 470 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 471 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 472 return 0; 473 474 /* Determine the Capability List Pointer register to start with. */ 475 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 476 switch (PCI_HDRTYPE_TYPE(reg)) { 477 case 0: /* standard device header */ 478 case 1: /* PCI-PCI bridge header */ 479 ofs = PCI_CAPLISTPTR_REG; 480 break; 481 case 2: /* PCI-CardBus Bridge header */ 482 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 483 break; 484 default: 485 return 0; 486 } 487 488 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 489 while (ofs != 0) { 490 if ((ofs & 3) || (ofs < 0x40)) { 491 int bus, device, function; 492 493 pci_decompose_tag(pc, tag, &bus, &device, &function); 494 495 printf("Skipping broken PCI header on %d:%d:%d\n", 496 bus, device, function); 497 break; 498 } 499 reg = pci_conf_read(pc, tag, ofs); 500 if (PCI_CAPLIST_CAP(reg) == capid) { 501 if (offset) 502 *offset = ofs; 503 if (value) 504 *value = reg; 505 return 1; 506 } 507 ofs = PCI_CAPLIST_NEXT(reg); 508 } 509 510 return 0; 511 } 512 513 int 514 pci_find_device(struct pci_attach_args *pa, 515 int (*match)(const struct pci_attach_args *)) 516 { 517 extern struct cfdriver pci_cd; 518 device_t pcidev; 519 int i; 520 static const int wildcard[2] = { 521 PCICF_DEV_DEFAULT, 522 PCICF_FUNCTION_DEFAULT 523 }; 524 525 for (i = 0; i < pci_cd.cd_ndevs; i++) { 526 pcidev = device_lookup(&pci_cd, i); 527 if (pcidev != NULL && 528 pci_enumerate_bus(device_private(pcidev), wildcard, 529 match, pa) != 0) 530 return 1; 531 } 532 return 0; 533 } 534 535 #ifndef PCI_MACHDEP_ENUMERATE_BUS 536 /* 537 * Generic PCI bus enumeration routine. Used unless machine-dependent 538 * code needs to provide something else. 539 */ 540 int 541 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 542 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 543 { 544 pci_chipset_tag_t pc = sc->sc_pc; 545 int device, function, nfunctions, ret; 546 const struct pci_quirkdata *qd; 547 pcireg_t id, bhlcr; 548 pcitag_t tag; 549 #ifdef __PCI_BUS_DEVORDER 550 char devs[32]; 551 int i; 552 #endif 553 554 #ifdef __PCI_BUS_DEVORDER 555 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 556 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 557 #else 558 for (device = 0; device < sc->sc_maxndevs; device++) 559 #endif 560 { 561 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 562 (locators[PCICF_DEV] != device)) 563 continue; 564 565 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 566 567 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 568 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 569 continue; 570 571 id = pci_conf_read(pc, tag, PCI_ID_REG); 572 573 /* Invalid vendor ID value? */ 574 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 575 continue; 576 /* XXX Not invalid, but we've done this ~forever. */ 577 if (PCI_VENDOR(id) == 0) 578 continue; 579 580 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 581 582 if (qd != NULL && 583 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 584 nfunctions = 8; 585 else if (qd != NULL && 586 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 587 nfunctions = 1; 588 else 589 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 590 591 for (function = 0; function < nfunctions; function++) { 592 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 593 && (locators[PCICF_FUNCTION] != function)) 594 continue; 595 596 if (qd != NULL && 597 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 598 continue; 599 tag = pci_make_tag(pc, sc->sc_bus, device, function); 600 ret = pci_probe_device(sc, tag, match, pap); 601 if (match != NULL && ret != 0) 602 return ret; 603 } 604 } 605 return 0; 606 } 607 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 608 609 610 /* 611 * Vital Product Data (PCI 2.2) 612 */ 613 614 int 615 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 616 pcireg_t *data) 617 { 618 uint32_t reg; 619 int ofs, i, j; 620 621 KASSERT(data != NULL); 622 KASSERT((offset + count) < 0x7fff); 623 624 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 625 return 1; 626 627 for (i = 0; i < count; offset += sizeof(*data), i++) { 628 reg &= 0x0000ffff; 629 reg &= ~PCI_VPD_OPFLAG; 630 reg |= PCI_VPD_ADDRESS(offset); 631 pci_conf_write(pc, tag, ofs, reg); 632 633 /* 634 * PCI 2.2 does not specify how long we should poll 635 * for completion nor whether the operation can fail. 636 */ 637 j = 0; 638 do { 639 if (j++ == 20) 640 return 1; 641 delay(4); 642 reg = pci_conf_read(pc, tag, ofs); 643 } while ((reg & PCI_VPD_OPFLAG) == 0); 644 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 645 } 646 647 return 0; 648 } 649 650 int 651 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 652 pcireg_t *data) 653 { 654 pcireg_t reg; 655 int ofs, i, j; 656 657 KASSERT(data != NULL); 658 KASSERT((offset + count) < 0x7fff); 659 660 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 661 return 1; 662 663 for (i = 0; i < count; offset += sizeof(*data), i++) { 664 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 665 666 reg &= 0x0000ffff; 667 reg |= PCI_VPD_OPFLAG; 668 reg |= PCI_VPD_ADDRESS(offset); 669 pci_conf_write(pc, tag, ofs, reg); 670 671 /* 672 * PCI 2.2 does not specify how long we should poll 673 * for completion nor whether the operation can fail. 674 */ 675 j = 0; 676 do { 677 if (j++ == 20) 678 return 1; 679 delay(1); 680 reg = pci_conf_read(pc, tag, ofs); 681 } while (reg & PCI_VPD_OPFLAG); 682 } 683 684 return 0; 685 } 686 687 int 688 pci_dma64_available(const struct pci_attach_args *pa) 689 { 690 #ifdef _PCI_HAVE_DMA64 691 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 692 return 1; 693 #endif 694 return 0; 695 } 696 697 void 698 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 699 struct pci_conf_state *pcs) 700 { 701 int off; 702 703 for (off = 0; off < 16; off++) 704 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 705 706 return; 707 } 708 709 void 710 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 711 struct pci_conf_state *pcs) 712 { 713 int off; 714 pcireg_t val; 715 716 for (off = 15; off >= 0; off--) { 717 val = pci_conf_read(pc, tag, (off * 4)); 718 if (val != pcs->reg[off]) 719 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 720 } 721 722 return; 723 } 724 725 /* 726 * Power Management Capability (Rev 2.2) 727 */ 728 static int 729 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 730 int offset) 731 { 732 pcireg_t value, now; 733 734 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 735 now = value & PCI_PMCSR_STATE_MASK; 736 switch (now) { 737 case PCI_PMCSR_STATE_D0: 738 case PCI_PMCSR_STATE_D1: 739 case PCI_PMCSR_STATE_D2: 740 case PCI_PMCSR_STATE_D3: 741 *state = now; 742 return 0; 743 default: 744 return EINVAL; 745 } 746 } 747 748 int 749 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 750 { 751 int offset; 752 pcireg_t value; 753 754 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 755 return EOPNOTSUPP; 756 757 return pci_get_powerstate_int(pc, tag, state, offset); 758 } 759 760 static int 761 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 762 int offset, pcireg_t cap_reg) 763 { 764 pcireg_t value, cap, now; 765 766 cap = cap_reg >> PCI_PMCR_SHIFT; 767 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 768 now = value & PCI_PMCSR_STATE_MASK; 769 value &= ~PCI_PMCSR_STATE_MASK; 770 771 if (now == state) 772 return 0; 773 switch (state) { 774 case PCI_PMCSR_STATE_D0: 775 break; 776 case PCI_PMCSR_STATE_D1: 777 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 778 printf("invalid transition from %d to D1\n", (int)now); 779 return EINVAL; 780 } 781 if (!(cap & PCI_PMCR_D1SUPP)) { 782 printf("D1 not supported\n"); 783 return EOPNOTSUPP; 784 } 785 break; 786 case PCI_PMCSR_STATE_D2: 787 if (now == PCI_PMCSR_STATE_D3) { 788 printf("invalid transition from %d to D2\n", (int)now); 789 return EINVAL; 790 } 791 if (!(cap & PCI_PMCR_D2SUPP)) { 792 printf("D2 not supported\n"); 793 return EOPNOTSUPP; 794 } 795 break; 796 case PCI_PMCSR_STATE_D3: 797 break; 798 default: 799 return EINVAL; 800 } 801 value |= state; 802 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 803 /* delay according to pcipm1.2, ch. 5.6.1 */ 804 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 805 DELAY(10000); 806 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 807 DELAY(200); 808 809 return 0; 810 } 811 812 int 813 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 814 { 815 int offset; 816 pcireg_t value; 817 818 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 819 printf("pci_set_powerstate not supported\n"); 820 return EOPNOTSUPP; 821 } 822 823 return pci_set_powerstate_int(pc, tag, state, offset, value); 824 } 825 826 int 827 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 828 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 829 { 830 pcireg_t pmode; 831 int error; 832 833 if ((error = pci_get_powerstate(pc, tag, &pmode))) 834 return error; 835 836 switch (pmode) { 837 case PCI_PMCSR_STATE_D0: 838 break; 839 case PCI_PMCSR_STATE_D3: 840 if (wakefun == NULL) { 841 /* 842 * The card has lost all configuration data in 843 * this state, so punt. 844 */ 845 aprint_error_dev(dev, 846 "unable to wake up from power state D3\n"); 847 return EOPNOTSUPP; 848 } 849 /*FALLTHROUGH*/ 850 default: 851 if (wakefun) { 852 error = (*wakefun)(pc, tag, dev, pmode); 853 if (error) 854 return error; 855 } 856 aprint_normal_dev(dev, "waking up from power state D%d\n", 857 pmode); 858 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 859 return error; 860 } 861 return 0; 862 } 863 864 int 865 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 866 device_t dev, pcireg_t state) 867 { 868 return 0; 869 } 870 871 struct pci_child_power { 872 struct pci_conf_state p_pciconf; 873 pci_chipset_tag_t p_pc; 874 pcitag_t p_tag; 875 bool p_has_pm; 876 int p_pm_offset; 877 pcireg_t p_pm_cap; 878 pcireg_t p_class; 879 pcireg_t p_csr; 880 }; 881 882 static bool 883 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 884 { 885 struct pci_child_power *priv = device_pmf_bus_private(dv); 886 pcireg_t ocsr, csr; 887 888 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 889 890 if (!priv->p_has_pm) 891 return true; /* ??? hopefully handled by ACPI */ 892 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 893 return true; /* XXX */ 894 895 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 896 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 897 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 898 | PCI_COMMAND_MASTER_ENABLE); 899 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 900 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 901 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 902 pci_conf_write(priv->p_pc, priv->p_tag, 903 PCI_COMMAND_STATUS_REG, ocsr); 904 aprint_error_dev(dv, "unsupported state, continuing.\n"); 905 return false; 906 } 907 return true; 908 } 909 910 static bool 911 pci_child_resume(device_t dv, const pmf_qual_t *qual) 912 { 913 struct pci_child_power *priv = device_pmf_bus_private(dv); 914 915 if (priv->p_has_pm && 916 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 917 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 918 aprint_error_dev(dv, "unsupported state, continuing.\n"); 919 return false; 920 } 921 922 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 923 924 return true; 925 } 926 927 static bool 928 pci_child_shutdown(device_t dv, int how) 929 { 930 struct pci_child_power *priv = device_pmf_bus_private(dv); 931 pcireg_t csr; 932 933 /* restore original bus-mastering state */ 934 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 935 csr &= ~PCI_COMMAND_MASTER_ENABLE; 936 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 937 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 938 return true; 939 } 940 941 static void 942 pci_child_deregister(device_t dv) 943 { 944 struct pci_child_power *priv = device_pmf_bus_private(dv); 945 946 free(priv, M_DEVBUF); 947 } 948 949 static bool 950 pci_child_register(device_t child) 951 { 952 device_t self = device_parent(child); 953 struct pci_softc *sc = device_private(self); 954 struct pci_child_power *priv; 955 int device, function, off; 956 pcireg_t reg; 957 958 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 959 960 device = device_locator(child, PCICF_DEV); 961 function = device_locator(child, PCICF_FUNCTION); 962 963 priv->p_pc = sc->sc_pc; 964 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 965 function); 966 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 967 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 968 PCI_COMMAND_STATUS_REG); 969 970 if (pci_get_capability(priv->p_pc, priv->p_tag, 971 PCI_CAP_PWRMGMT, &off, ®)) { 972 priv->p_has_pm = true; 973 priv->p_pm_offset = off; 974 priv->p_pm_cap = reg; 975 } else { 976 priv->p_has_pm = false; 977 priv->p_pm_offset = -1; 978 } 979 980 device_pmf_bus_register(child, priv, pci_child_suspend, 981 pci_child_resume, pci_child_shutdown, pci_child_deregister); 982 983 return true; 984 } 985
Indexes created Tue Sep 30 20:09:53 GMT 2025