pci.c revision 1.127.2.5
1 /* $NetBSD: pci.c,v 1.127.2.5 2011/05/31 03:04:42 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.127.2.5 2011/05/31 03:04:42 rmind Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(const struct pci_attach_args *), 272 struct pci_attach_args *pap) 273 { 274 pci_chipset_tag_t pc = sc->sc_pc; 275 struct pci_attach_args pa; 276 pcireg_t id, csr, class, intr, bhlcr, bar, endbar; 277 int ret, pin, bus, device, function, i, width; 278 int locs[PCICF_NLOCS]; 279 280 pci_decompose_tag(pc, tag, &bus, &device, &function); 281 282 /* a driver already attached? */ 283 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 284 return 0; 285 286 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 287 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 288 return 0; 289 290 id = pci_conf_read(pc, tag, PCI_ID_REG); 291 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 292 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 293 294 /* Invalid vendor ID value? */ 295 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 296 return 0; 297 /* XXX Not invalid, but we've done this ~forever. */ 298 if (PCI_VENDOR(id) == 0) 299 return 0; 300 301 /* Collect memory range info */ 302 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 303 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 304 i = 0; 305 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 306 case PCI_HDRTYPE_PPB: 307 endbar = PCI_MAPREG_PPB_END; 308 break; 309 case PCI_HDRTYPE_PCB: 310 endbar = PCI_MAPREG_PCB_END; 311 break; 312 default: 313 endbar = PCI_MAPREG_END; 314 break; 315 } 316 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 317 struct pci_range *r; 318 pcireg_t type; 319 320 width = 4; 321 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 322 continue; 323 324 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 325 if (PCI_MAPREG_MEM_TYPE(type) == 326 PCI_MAPREG_MEM_TYPE_64BIT) 327 width = 8; 328 329 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 330 if (pci_mapreg_info(pc, tag, bar, type, 331 &r->r_offset, &r->r_size, &r->r_flags) != 0) 332 break; 333 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 334 && (r->r_size == 0x1000000)) { 335 struct pci_range *nr; 336 /* 337 * this has to be a mach64 338 * split things up so each half-aperture can 339 * be mapped PREFETCHABLE except the last page 340 * which may contain registers 341 */ 342 r->r_size = 0x7ff000; 343 r->r_flags = BUS_SPACE_MAP_LINEAR | 344 BUS_SPACE_MAP_PREFETCHABLE; 345 nr = &sc->PCI_SC_DEVICESC(device, 346 function).c_range[i++]; 347 nr->r_offset = r->r_offset + 0x800000; 348 nr->r_size = 0x7ff000; 349 nr->r_flags = BUS_SPACE_MAP_LINEAR | 350 BUS_SPACE_MAP_PREFETCHABLE; 351 } 352 353 } 354 } 355 356 pa.pa_iot = sc->sc_iot; 357 pa.pa_memt = sc->sc_memt; 358 pa.pa_dmat = sc->sc_dmat; 359 pa.pa_dmat64 = sc->sc_dmat64; 360 pa.pa_pc = pc; 361 pa.pa_bus = bus; 362 pa.pa_device = device; 363 pa.pa_function = function; 364 pa.pa_tag = tag; 365 pa.pa_id = id; 366 pa.pa_class = class; 367 368 /* 369 * Set up memory, I/O enable, and PCI command flags 370 * as appropriate. 371 */ 372 pa.pa_flags = sc->sc_flags; 373 374 /* 375 * If the cache line size is not configured, then 376 * clear the MRL/MRM/MWI command-ok flags. 377 */ 378 if (PCI_CACHELINE(bhlcr) == 0) { 379 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 380 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 381 } 382 383 if (sc->sc_bridgetag == NULL) { 384 pa.pa_intrswiz = 0; 385 pa.pa_intrtag = tag; 386 } else { 387 pa.pa_intrswiz = sc->sc_intrswiz + device; 388 pa.pa_intrtag = sc->sc_intrtag; 389 } 390 391 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 392 393 pin = PCI_INTERRUPT_PIN(intr); 394 pa.pa_rawintrpin = pin; 395 if (pin == PCI_INTERRUPT_PIN_NONE) { 396 /* no interrupt */ 397 pa.pa_intrpin = 0; 398 } else { 399 /* 400 * swizzle it based on the number of busses we're 401 * behind and our device number. 402 */ 403 pa.pa_intrpin = /* XXX */ 404 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 405 } 406 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 407 408 if (match != NULL) { 409 ret = (*match)(&pa); 410 if (ret != 0 && pap != NULL) 411 *pap = pa; 412 } else { 413 struct pci_child *c; 414 locs[PCICF_DEV] = device; 415 locs[PCICF_FUNCTION] = function; 416 417 c = &sc->PCI_SC_DEVICESC(device, function); 418 pci_conf_capture(pc, tag, &c->c_conf); 419 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 420 c->c_psok = true; 421 else 422 c->c_psok = false; 423 424 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 425 pciprint, config_stdsubmatch); 426 427 ret = (c->c_dev != NULL); 428 } 429 430 return ret; 431 } 432 433 void 434 pcidevdetached(device_t self, device_t child) 435 { 436 struct pci_softc *sc = device_private(self); 437 int d, f; 438 pcitag_t tag; 439 struct pci_child *c; 440 441 d = device_locator(child, PCICF_DEV); 442 f = device_locator(child, PCICF_FUNCTION); 443 444 c = &sc->PCI_SC_DEVICESC(d, f); 445 446 KASSERT(c->c_dev == child); 447 448 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 449 if (c->c_psok) 450 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 451 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 452 c->c_dev = NULL; 453 } 454 455 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 456 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 457 DVF_DETACH_SHUTDOWN); 458 459 int 460 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 461 int *offset, pcireg_t *value) 462 { 463 pcireg_t reg; 464 unsigned int ofs; 465 466 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 467 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 468 return 0; 469 470 /* Determine the Capability List Pointer register to start with. */ 471 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 472 switch (PCI_HDRTYPE_TYPE(reg)) { 473 case 0: /* standard device header */ 474 case 1: /* PCI-PCI bridge header */ 475 ofs = PCI_CAPLISTPTR_REG; 476 break; 477 case 2: /* PCI-CardBus Bridge header */ 478 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 479 break; 480 default: 481 return 0; 482 } 483 484 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 485 while (ofs != 0) { 486 if ((ofs & 3) || (ofs < 0x40)) { 487 int bus, device, function; 488 489 pci_decompose_tag(pc, tag, &bus, &device, &function); 490 491 printf("Skipping broken PCI header on %d:%d:%d\n", 492 bus, device, function); 493 break; 494 } 495 reg = pci_conf_read(pc, tag, ofs); 496 if (PCI_CAPLIST_CAP(reg) == capid) { 497 if (offset) 498 *offset = ofs; 499 if (value) 500 *value = reg; 501 return 1; 502 } 503 ofs = PCI_CAPLIST_NEXT(reg); 504 } 505 506 return 0; 507 } 508 509 int 510 pci_find_device(struct pci_attach_args *pa, 511 int (*match)(const struct pci_attach_args *)) 512 { 513 extern struct cfdriver pci_cd; 514 device_t pcidev; 515 int i; 516 static const int wildcard[2] = { 517 PCICF_DEV_DEFAULT, 518 PCICF_FUNCTION_DEFAULT 519 }; 520 521 for (i = 0; i < pci_cd.cd_ndevs; i++) { 522 pcidev = device_lookup(&pci_cd, i); 523 if (pcidev != NULL && 524 pci_enumerate_bus(device_private(pcidev), wildcard, 525 match, pa) != 0) 526 return 1; 527 } 528 return 0; 529 } 530 531 #ifndef PCI_MACHDEP_ENUMERATE_BUS 532 /* 533 * Generic PCI bus enumeration routine. Used unless machine-dependent 534 * code needs to provide something else. 535 */ 536 int 537 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 538 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 539 { 540 pci_chipset_tag_t pc = sc->sc_pc; 541 int device, function, nfunctions, ret; 542 const struct pci_quirkdata *qd; 543 pcireg_t id, bhlcr; 544 pcitag_t tag; 545 #ifdef __PCI_BUS_DEVORDER 546 char devs[32]; 547 int i; 548 #endif 549 550 #ifdef __PCI_BUS_DEVORDER 551 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 552 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 553 #else 554 for (device = 0; device < sc->sc_maxndevs; device++) 555 #endif 556 { 557 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 558 (locators[PCICF_DEV] != device)) 559 continue; 560 561 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 562 563 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 564 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 565 continue; 566 567 id = pci_conf_read(pc, tag, PCI_ID_REG); 568 569 /* Invalid vendor ID value? */ 570 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 571 continue; 572 /* XXX Not invalid, but we've done this ~forever. */ 573 if (PCI_VENDOR(id) == 0) 574 continue; 575 576 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 577 578 if (qd != NULL && 579 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 580 nfunctions = 8; 581 else if (qd != NULL && 582 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 583 nfunctions = 1; 584 else 585 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 586 587 for (function = 0; function < nfunctions; function++) { 588 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 589 && (locators[PCICF_FUNCTION] != function)) 590 continue; 591 592 if (qd != NULL && 593 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 594 continue; 595 tag = pci_make_tag(pc, sc->sc_bus, device, function); 596 ret = pci_probe_device(sc, tag, match, pap); 597 if (match != NULL && ret != 0) 598 return ret; 599 } 600 } 601 return 0; 602 } 603 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 604 605 606 /* 607 * Vital Product Data (PCI 2.2) 608 */ 609 610 int 611 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 612 pcireg_t *data) 613 { 614 uint32_t reg; 615 int ofs, i, j; 616 617 KASSERT(data != NULL); 618 KASSERT((offset + count) < 0x7fff); 619 620 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 621 return 1; 622 623 for (i = 0; i < count; offset += sizeof(*data), i++) { 624 reg &= 0x0000ffff; 625 reg &= ~PCI_VPD_OPFLAG; 626 reg |= PCI_VPD_ADDRESS(offset); 627 pci_conf_write(pc, tag, ofs, reg); 628 629 /* 630 * PCI 2.2 does not specify how long we should poll 631 * for completion nor whether the operation can fail. 632 */ 633 j = 0; 634 do { 635 if (j++ == 20) 636 return 1; 637 delay(4); 638 reg = pci_conf_read(pc, tag, ofs); 639 } while ((reg & PCI_VPD_OPFLAG) == 0); 640 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 641 } 642 643 return 0; 644 } 645 646 int 647 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 648 pcireg_t *data) 649 { 650 pcireg_t reg; 651 int ofs, i, j; 652 653 KASSERT(data != NULL); 654 KASSERT((offset + count) < 0x7fff); 655 656 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 657 return 1; 658 659 for (i = 0; i < count; offset += sizeof(*data), i++) { 660 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 661 662 reg &= 0x0000ffff; 663 reg |= PCI_VPD_OPFLAG; 664 reg |= PCI_VPD_ADDRESS(offset); 665 pci_conf_write(pc, tag, ofs, reg); 666 667 /* 668 * PCI 2.2 does not specify how long we should poll 669 * for completion nor whether the operation can fail. 670 */ 671 j = 0; 672 do { 673 if (j++ == 20) 674 return 1; 675 delay(1); 676 reg = pci_conf_read(pc, tag, ofs); 677 } while (reg & PCI_VPD_OPFLAG); 678 } 679 680 return 0; 681 } 682 683 int 684 pci_dma64_available(const struct pci_attach_args *pa) 685 { 686 #ifdef _PCI_HAVE_DMA64 687 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 688 return 1; 689 #endif 690 return 0; 691 } 692 693 void 694 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 695 struct pci_conf_state *pcs) 696 { 697 int off; 698 699 for (off = 0; off < 16; off++) 700 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 701 702 return; 703 } 704 705 void 706 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 707 struct pci_conf_state *pcs) 708 { 709 int off; 710 pcireg_t val; 711 712 for (off = 15; off >= 0; off--) { 713 val = pci_conf_read(pc, tag, (off * 4)); 714 if (val != pcs->reg[off]) 715 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 716 } 717 718 return; 719 } 720 721 /* 722 * Power Management Capability (Rev 2.2) 723 */ 724 static int 725 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 726 int offset) 727 { 728 pcireg_t value, now; 729 730 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 731 now = value & PCI_PMCSR_STATE_MASK; 732 switch (now) { 733 case PCI_PMCSR_STATE_D0: 734 case PCI_PMCSR_STATE_D1: 735 case PCI_PMCSR_STATE_D2: 736 case PCI_PMCSR_STATE_D3: 737 *state = now; 738 return 0; 739 default: 740 return EINVAL; 741 } 742 } 743 744 int 745 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 746 { 747 int offset; 748 pcireg_t value; 749 750 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 751 return EOPNOTSUPP; 752 753 return pci_get_powerstate_int(pc, tag, state, offset); 754 } 755 756 static int 757 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 758 int offset, pcireg_t cap_reg) 759 { 760 pcireg_t value, cap, now; 761 762 cap = cap_reg >> PCI_PMCR_SHIFT; 763 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 764 now = value & PCI_PMCSR_STATE_MASK; 765 value &= ~PCI_PMCSR_STATE_MASK; 766 767 if (now == state) 768 return 0; 769 switch (state) { 770 case PCI_PMCSR_STATE_D0: 771 break; 772 case PCI_PMCSR_STATE_D1: 773 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 774 printf("invalid transition from %d to D1\n", (int)now); 775 return EINVAL; 776 } 777 if (!(cap & PCI_PMCR_D1SUPP)) { 778 printf("D1 not supported\n"); 779 return EOPNOTSUPP; 780 } 781 break; 782 case PCI_PMCSR_STATE_D2: 783 if (now == PCI_PMCSR_STATE_D3) { 784 printf("invalid transition from %d to D2\n", (int)now); 785 return EINVAL; 786 } 787 if (!(cap & PCI_PMCR_D2SUPP)) { 788 printf("D2 not supported\n"); 789 return EOPNOTSUPP; 790 } 791 break; 792 case PCI_PMCSR_STATE_D3: 793 break; 794 default: 795 return EINVAL; 796 } 797 value |= state; 798 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 799 /* delay according to pcipm1.2, ch. 5.6.1 */ 800 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 801 DELAY(10000); 802 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 803 DELAY(200); 804 805 return 0; 806 } 807 808 int 809 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 810 { 811 int offset; 812 pcireg_t value; 813 814 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 815 printf("pci_set_powerstate not supported\n"); 816 return EOPNOTSUPP; 817 } 818 819 return pci_set_powerstate_int(pc, tag, state, offset, value); 820 } 821 822 int 823 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 824 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 825 { 826 pcireg_t pmode; 827 int error; 828 829 if ((error = pci_get_powerstate(pc, tag, &pmode))) 830 return error; 831 832 switch (pmode) { 833 case PCI_PMCSR_STATE_D0: 834 break; 835 case PCI_PMCSR_STATE_D3: 836 if (wakefun == NULL) { 837 /* 838 * The card has lost all configuration data in 839 * this state, so punt. 840 */ 841 aprint_error_dev(dev, 842 "unable to wake up from power state D3\n"); 843 return EOPNOTSUPP; 844 } 845 /*FALLTHROUGH*/ 846 default: 847 if (wakefun) { 848 error = (*wakefun)(pc, tag, dev, pmode); 849 if (error) 850 return error; 851 } 852 aprint_normal_dev(dev, "waking up from power state D%d\n", 853 pmode); 854 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 855 return error; 856 } 857 return 0; 858 } 859 860 int 861 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 862 device_t dev, pcireg_t state) 863 { 864 return 0; 865 } 866 867 struct pci_child_power { 868 struct pci_conf_state p_pciconf; 869 pci_chipset_tag_t p_pc; 870 pcitag_t p_tag; 871 bool p_has_pm; 872 int p_pm_offset; 873 pcireg_t p_pm_cap; 874 pcireg_t p_class; 875 pcireg_t p_csr; 876 }; 877 878 static bool 879 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 880 { 881 struct pci_child_power *priv = device_pmf_bus_private(dv); 882 pcireg_t ocsr, csr; 883 884 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 885 886 if (!priv->p_has_pm) 887 return true; /* ??? hopefully handled by ACPI */ 888 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 889 return true; /* XXX */ 890 891 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 892 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 893 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 894 | PCI_COMMAND_MASTER_ENABLE); 895 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 896 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 897 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 898 pci_conf_write(priv->p_pc, priv->p_tag, 899 PCI_COMMAND_STATUS_REG, ocsr); 900 aprint_error_dev(dv, "unsupported state, continuing.\n"); 901 return false; 902 } 903 return true; 904 } 905 906 static bool 907 pci_child_resume(device_t dv, const pmf_qual_t *qual) 908 { 909 struct pci_child_power *priv = device_pmf_bus_private(dv); 910 911 if (priv->p_has_pm && 912 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 913 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 914 aprint_error_dev(dv, "unsupported state, continuing.\n"); 915 return false; 916 } 917 918 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 919 920 return true; 921 } 922 923 static bool 924 pci_child_shutdown(device_t dv, int how) 925 { 926 struct pci_child_power *priv = device_pmf_bus_private(dv); 927 pcireg_t csr; 928 929 /* restore original bus-mastering state */ 930 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 931 csr &= ~PCI_COMMAND_MASTER_ENABLE; 932 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 933 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 934 return true; 935 } 936 937 static void 938 pci_child_deregister(device_t dv) 939 { 940 struct pci_child_power *priv = device_pmf_bus_private(dv); 941 942 free(priv, M_DEVBUF); 943 } 944 945 static bool 946 pci_child_register(device_t child) 947 { 948 device_t self = device_parent(child); 949 struct pci_softc *sc = device_private(self); 950 struct pci_child_power *priv; 951 int device, function, off; 952 pcireg_t reg; 953 954 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 955 956 device = device_locator(child, PCICF_DEV); 957 function = device_locator(child, PCICF_FUNCTION); 958 959 priv->p_pc = sc->sc_pc; 960 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 961 function); 962 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 963 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 964 PCI_COMMAND_STATUS_REG); 965 966 if (pci_get_capability(priv->p_pc, priv->p_tag, 967 PCI_CAP_PWRMGMT, &off, ®)) { 968 priv->p_has_pm = true; 969 priv->p_pm_offset = off; 970 priv->p_pm_cap = reg; 971 } else { 972 priv->p_has_pm = false; 973 priv->p_pm_offset = -1; 974 } 975 976 device_pmf_bus_register(child, priv, pci_child_suspend, 977 pci_child_resume, pci_child_shutdown, pci_child_deregister); 978 979 return true; 980 } 981
Indexes created Tue Sep 30 20:09:53 GMT 2025