pci.c revision 1.130.4.1
1 /* $NetBSD: pci.c,v 1.130.4.1 2011/02/08 16:19:51 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.130.4.1 2011/02/08 16:19:51 bouyer Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 272 { 273 pci_chipset_tag_t pc = sc->sc_pc; 274 struct pci_attach_args pa; 275 pcireg_t id, csr, class, intr, bhlcr; 276 int ret, pin, bus, device, function; 277 int locs[PCICF_NLOCS]; 278 279 pci_decompose_tag(pc, tag, &bus, &device, &function); 280 281 /* a driver already attached? */ 282 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 283 return 0; 284 285 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 286 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 287 return 0; 288 289 id = pci_conf_read(pc, tag, PCI_ID_REG); 290 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 291 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 pa.pa_iot = sc->sc_iot; 301 pa.pa_memt = sc->sc_memt; 302 pa.pa_dmat = sc->sc_dmat; 303 pa.pa_dmat64 = sc->sc_dmat64; 304 pa.pa_pc = pc; 305 pa.pa_bus = bus; 306 pa.pa_device = device; 307 pa.pa_function = function; 308 pa.pa_tag = tag; 309 pa.pa_id = id; 310 pa.pa_class = class; 311 312 /* 313 * Set up memory, I/O enable, and PCI command flags 314 * as appropriate. 315 */ 316 pa.pa_flags = sc->sc_flags; 317 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 318 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 319 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 320 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 321 322 /* 323 * If the cache line size is not configured, then 324 * clear the MRL/MRM/MWI command-ok flags. 325 */ 326 if (PCI_CACHELINE(bhlcr) == 0) 327 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 328 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 329 330 if (sc->sc_bridgetag == NULL) { 331 pa.pa_intrswiz = 0; 332 pa.pa_intrtag = tag; 333 } else { 334 pa.pa_intrswiz = sc->sc_intrswiz + device; 335 pa.pa_intrtag = sc->sc_intrtag; 336 } 337 338 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 339 340 pin = PCI_INTERRUPT_PIN(intr); 341 pa.pa_rawintrpin = pin; 342 if (pin == PCI_INTERRUPT_PIN_NONE) { 343 /* no interrupt */ 344 pa.pa_intrpin = 0; 345 } else { 346 /* 347 * swizzle it based on the number of busses we're 348 * behind and our device number. 349 */ 350 pa.pa_intrpin = /* XXX */ 351 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 352 } 353 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 354 355 if (match != NULL) { 356 ret = (*match)(&pa); 357 if (ret != 0 && pap != NULL) 358 *pap = pa; 359 } else { 360 struct pci_child *c; 361 locs[PCICF_DEV] = device; 362 locs[PCICF_FUNCTION] = function; 363 364 c = &sc->PCI_SC_DEVICESC(device, function); 365 pci_conf_capture(pc, tag, &c->c_conf); 366 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 367 c->c_psok = true; 368 else 369 c->c_psok = false; 370 371 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 372 pciprint, config_stdsubmatch); 373 374 ret = (c->c_dev != NULL); 375 } 376 377 return ret; 378 } 379 380 void 381 pcidevdetached(device_t self, device_t child) 382 { 383 struct pci_softc *sc = device_private(self); 384 int d, f; 385 pcitag_t tag; 386 struct pci_child *c; 387 388 d = device_locator(child, PCICF_DEV); 389 f = device_locator(child, PCICF_FUNCTION); 390 391 c = &sc->PCI_SC_DEVICESC(d, f); 392 393 KASSERT(c->c_dev == child); 394 395 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 396 if (c->c_psok) 397 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 398 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 399 c->c_dev = NULL; 400 } 401 402 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 403 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 404 DVF_DETACH_SHUTDOWN); 405 406 int 407 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 408 int *offset, pcireg_t *value) 409 { 410 pcireg_t reg; 411 unsigned int ofs; 412 413 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 414 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 415 return 0; 416 417 /* Determine the Capability List Pointer register to start with. */ 418 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 419 switch (PCI_HDRTYPE_TYPE(reg)) { 420 case 0: /* standard device header */ 421 case 1: /* PCI-PCI bridge header */ 422 ofs = PCI_CAPLISTPTR_REG; 423 break; 424 case 2: /* PCI-CardBus Bridge header */ 425 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 426 break; 427 default: 428 return 0; 429 } 430 431 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 432 while (ofs != 0) { 433 if ((ofs & 3) || (ofs < 0x40)) { 434 int bus, device, function; 435 436 pci_decompose_tag(pc, tag, &bus, &device, &function); 437 438 printf("Skipping broken PCI header on %d:%d:%d\n", 439 bus, device, function); 440 break; 441 } 442 reg = pci_conf_read(pc, tag, ofs); 443 if (PCI_CAPLIST_CAP(reg) == capid) { 444 if (offset) 445 *offset = ofs; 446 if (value) 447 *value = reg; 448 return 1; 449 } 450 ofs = PCI_CAPLIST_NEXT(reg); 451 } 452 453 return 0; 454 } 455 456 int 457 pci_find_device(struct pci_attach_args *pa, 458 int (*match)(struct pci_attach_args *)) 459 { 460 extern struct cfdriver pci_cd; 461 device_t pcidev; 462 int i; 463 static const int wildcard[2] = { 464 PCICF_DEV_DEFAULT, 465 PCICF_FUNCTION_DEFAULT 466 }; 467 468 for (i = 0; i < pci_cd.cd_ndevs; i++) { 469 pcidev = device_lookup(&pci_cd, i); 470 if (pcidev != NULL && 471 pci_enumerate_bus(device_private(pcidev), wildcard, 472 match, pa) != 0) 473 return 1; 474 } 475 return 0; 476 } 477 478 #ifndef PCI_MACHDEP_ENUMERATE_BUS 479 /* 480 * Generic PCI bus enumeration routine. Used unless machine-dependent 481 * code needs to provide something else. 482 */ 483 int 484 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 485 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 486 { 487 pci_chipset_tag_t pc = sc->sc_pc; 488 int device, function, nfunctions, ret; 489 const struct pci_quirkdata *qd; 490 pcireg_t id, bhlcr; 491 pcitag_t tag; 492 #ifdef __PCI_BUS_DEVORDER 493 char devs[32]; 494 int i; 495 #endif 496 497 #ifdef __PCI_BUS_DEVORDER 498 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 499 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 500 #else 501 for (device = 0; device < sc->sc_maxndevs; device++) 502 #endif 503 { 504 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 505 (locators[PCICF_DEV] != device)) 506 continue; 507 508 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 509 510 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 511 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 512 continue; 513 514 id = pci_conf_read(pc, tag, PCI_ID_REG); 515 516 /* Invalid vendor ID value? */ 517 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 518 continue; 519 /* XXX Not invalid, but we've done this ~forever. */ 520 if (PCI_VENDOR(id) == 0) 521 continue; 522 523 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 524 525 if (qd != NULL && 526 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 527 nfunctions = 8; 528 else if (qd != NULL && 529 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 530 nfunctions = 1; 531 else 532 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 533 534 for (function = 0; function < nfunctions; function++) { 535 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 536 && (locators[PCICF_FUNCTION] != function)) 537 continue; 538 539 if (qd != NULL && 540 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 541 continue; 542 tag = pci_make_tag(pc, sc->sc_bus, device, function); 543 ret = pci_probe_device(sc, tag, match, pap); 544 if (match != NULL && ret != 0) 545 return ret; 546 } 547 } 548 return 0; 549 } 550 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 551 552 553 /* 554 * Vital Product Data (PCI 2.2) 555 */ 556 557 int 558 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 559 pcireg_t *data) 560 { 561 uint32_t reg; 562 int ofs, i, j; 563 564 KASSERT(data != NULL); 565 KASSERT((offset + count) < 0x7fff); 566 567 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 568 return 1; 569 570 for (i = 0; i < count; offset += sizeof(*data), i++) { 571 reg &= 0x0000ffff; 572 reg &= ~PCI_VPD_OPFLAG; 573 reg |= PCI_VPD_ADDRESS(offset); 574 pci_conf_write(pc, tag, ofs, reg); 575 576 /* 577 * PCI 2.2 does not specify how long we should poll 578 * for completion nor whether the operation can fail. 579 */ 580 j = 0; 581 do { 582 if (j++ == 20) 583 return 1; 584 delay(4); 585 reg = pci_conf_read(pc, tag, ofs); 586 } while ((reg & PCI_VPD_OPFLAG) == 0); 587 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 588 } 589 590 return 0; 591 } 592 593 int 594 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 595 pcireg_t *data) 596 { 597 pcireg_t reg; 598 int ofs, i, j; 599 600 KASSERT(data != NULL); 601 KASSERT((offset + count) < 0x7fff); 602 603 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 604 return 1; 605 606 for (i = 0; i < count; offset += sizeof(*data), i++) { 607 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 608 609 reg &= 0x0000ffff; 610 reg |= PCI_VPD_OPFLAG; 611 reg |= PCI_VPD_ADDRESS(offset); 612 pci_conf_write(pc, tag, ofs, reg); 613 614 /* 615 * PCI 2.2 does not specify how long we should poll 616 * for completion nor whether the operation can fail. 617 */ 618 j = 0; 619 do { 620 if (j++ == 20) 621 return 1; 622 delay(1); 623 reg = pci_conf_read(pc, tag, ofs); 624 } while (reg & PCI_VPD_OPFLAG); 625 } 626 627 return 0; 628 } 629 630 int 631 pci_dma64_available(struct pci_attach_args *pa) 632 { 633 #ifdef _PCI_HAVE_DMA64 634 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 635 return 1; 636 #endif 637 return 0; 638 } 639 640 void 641 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 642 struct pci_conf_state *pcs) 643 { 644 int off; 645 646 for (off = 0; off < 16; off++) 647 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 648 649 return; 650 } 651 652 void 653 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 654 struct pci_conf_state *pcs) 655 { 656 int off; 657 pcireg_t val; 658 659 for (off = 15; off >= 0; off--) { 660 val = pci_conf_read(pc, tag, (off * 4)); 661 if (val != pcs->reg[off]) 662 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 663 } 664 665 return; 666 } 667 668 /* 669 * Power Management Capability (Rev 2.2) 670 */ 671 static int 672 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 673 int offset) 674 { 675 pcireg_t value, now; 676 677 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 678 now = value & PCI_PMCSR_STATE_MASK; 679 switch (now) { 680 case PCI_PMCSR_STATE_D0: 681 case PCI_PMCSR_STATE_D1: 682 case PCI_PMCSR_STATE_D2: 683 case PCI_PMCSR_STATE_D3: 684 *state = now; 685 return 0; 686 default: 687 return EINVAL; 688 } 689 } 690 691 int 692 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 693 { 694 int offset; 695 pcireg_t value; 696 697 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 698 return EOPNOTSUPP; 699 700 return pci_get_powerstate_int(pc, tag, state, offset); 701 } 702 703 static int 704 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 705 int offset, pcireg_t cap_reg) 706 { 707 pcireg_t value, cap, now; 708 709 cap = cap_reg >> PCI_PMCR_SHIFT; 710 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 711 now = value & PCI_PMCSR_STATE_MASK; 712 value &= ~PCI_PMCSR_STATE_MASK; 713 714 if (now == state) 715 return 0; 716 switch (state) { 717 case PCI_PMCSR_STATE_D0: 718 break; 719 case PCI_PMCSR_STATE_D1: 720 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 721 printf("invalid transition from %d to D1\n", (int)now); 722 return EINVAL; 723 } 724 if (!(cap & PCI_PMCR_D1SUPP)) { 725 printf("D1 not supported\n"); 726 return EOPNOTSUPP; 727 } 728 break; 729 case PCI_PMCSR_STATE_D2: 730 if (now == PCI_PMCSR_STATE_D3) { 731 printf("invalid transition from %d to D2\n", (int)now); 732 return EINVAL; 733 } 734 if (!(cap & PCI_PMCR_D2SUPP)) { 735 printf("D2 not supported\n"); 736 return EOPNOTSUPP; 737 } 738 break; 739 case PCI_PMCSR_STATE_D3: 740 break; 741 default: 742 return EINVAL; 743 } 744 value |= state; 745 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 746 /* delay according to pcipm1.2, ch. 5.6.1 */ 747 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 748 DELAY(10000); 749 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 750 DELAY(200); 751 752 return 0; 753 } 754 755 int 756 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 757 { 758 int offset; 759 pcireg_t value; 760 761 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 762 printf("pci_set_powerstate not supported\n"); 763 return EOPNOTSUPP; 764 } 765 766 return pci_set_powerstate_int(pc, tag, state, offset, value); 767 } 768 769 int 770 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 771 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 772 { 773 pcireg_t pmode; 774 int error; 775 776 if ((error = pci_get_powerstate(pc, tag, &pmode))) 777 return error; 778 779 switch (pmode) { 780 case PCI_PMCSR_STATE_D0: 781 break; 782 case PCI_PMCSR_STATE_D3: 783 if (wakefun == NULL) { 784 /* 785 * The card has lost all configuration data in 786 * this state, so punt. 787 */ 788 aprint_error_dev(dev, 789 "unable to wake up from power state D3\n"); 790 return EOPNOTSUPP; 791 } 792 /*FALLTHROUGH*/ 793 default: 794 if (wakefun) { 795 error = (*wakefun)(pc, tag, dev, pmode); 796 if (error) 797 return error; 798 } 799 aprint_normal_dev(dev, "waking up from power state D%d\n", 800 pmode); 801 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 802 return error; 803 } 804 return 0; 805 } 806 807 int 808 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 809 device_t dev, pcireg_t state) 810 { 811 return 0; 812 } 813 814 struct pci_child_power { 815 struct pci_conf_state p_pciconf; 816 pci_chipset_tag_t p_pc; 817 pcitag_t p_tag; 818 bool p_has_pm; 819 int p_pm_offset; 820 pcireg_t p_pm_cap; 821 pcireg_t p_class; 822 pcireg_t p_csr; 823 }; 824 825 static bool 826 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 827 { 828 struct pci_child_power *priv = device_pmf_bus_private(dv); 829 pcireg_t ocsr, csr; 830 831 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 832 833 if (!priv->p_has_pm) 834 return true; /* ??? hopefully handled by ACPI */ 835 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 836 return true; /* XXX */ 837 838 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 839 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 840 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 841 | PCI_COMMAND_MASTER_ENABLE); 842 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 843 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 844 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 845 pci_conf_write(priv->p_pc, priv->p_tag, 846 PCI_COMMAND_STATUS_REG, ocsr); 847 aprint_error_dev(dv, "unsupported state, continuing.\n"); 848 return false; 849 } 850 return true; 851 } 852 853 static bool 854 pci_child_resume(device_t dv, const pmf_qual_t *qual) 855 { 856 struct pci_child_power *priv = device_pmf_bus_private(dv); 857 858 if (priv->p_has_pm && 859 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 860 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 861 aprint_error_dev(dv, "unsupported state, continuing.\n"); 862 return false; 863 } 864 865 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 866 867 return true; 868 } 869 870 static bool 871 pci_child_shutdown(device_t dv, int how) 872 { 873 struct pci_child_power *priv = device_pmf_bus_private(dv); 874 pcireg_t csr; 875 876 /* restore original bus-mastering state */ 877 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 878 csr &= ~PCI_COMMAND_MASTER_ENABLE; 879 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 880 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 881 return true; 882 } 883 884 static void 885 pci_child_deregister(device_t dv) 886 { 887 struct pci_child_power *priv = device_pmf_bus_private(dv); 888 889 free(priv, M_DEVBUF); 890 } 891 892 static bool 893 pci_child_register(device_t child) 894 { 895 device_t self = device_parent(child); 896 struct pci_softc *sc = device_private(self); 897 struct pci_child_power *priv; 898 int device, function, off; 899 pcireg_t reg; 900 901 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 902 903 device = device_locator(child, PCICF_DEV); 904 function = device_locator(child, PCICF_FUNCTION); 905 906 priv->p_pc = sc->sc_pc; 907 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 908 function); 909 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 910 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 911 PCI_COMMAND_STATUS_REG); 912 913 if (pci_get_capability(priv->p_pc, priv->p_tag, 914 PCI_CAP_PWRMGMT, &off, ®)) { 915 priv->p_has_pm = true; 916 priv->p_pm_offset = off; 917 priv->p_pm_cap = reg; 918 } else { 919 priv->p_has_pm = false; 920 priv->p_pm_offset = -1; 921 } 922 923 device_pmf_bus_register(child, priv, pci_child_suspend, 924 pci_child_resume, pci_child_shutdown, pci_child_deregister); 925 926 return true; 927 } 928
Indexes created Tue Sep 30 17:09:57 GMT 2025