pci.c revision 1.130.4.3
1 /* $NetBSD: pci.c,v 1.130.4.3 2011/03/05 15:10:24 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.130.4.3 2011/03/05 15:10:24 bouyer Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 272 { 273 pci_chipset_tag_t pc = sc->sc_pc; 274 struct pci_attach_args pa; 275 pcireg_t id, csr, class, intr, bhlcr, bar, endbar; 276 int ret, pin, bus, device, function, i, width; 277 int locs[PCICF_NLOCS]; 278 279 pci_decompose_tag(pc, tag, &bus, &device, &function); 280 281 /* a driver already attached? */ 282 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 283 return 0; 284 285 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 286 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 287 return 0; 288 289 id = pci_conf_read(pc, tag, PCI_ID_REG); 290 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 291 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 /* Collect memory range info */ 301 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 302 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 303 i = 0; 304 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 305 case PCI_HDRTYPE_PPB: endbar = PCI_MAPREG_PPB_END; break; 306 case PCI_HDRTYPE_PCB: endbar = PCI_MAPREG_PCB_END; break; 307 default: endbar = PCI_MAPREG_END; break; 308 } 309 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 310 struct pci_range *r; 311 pcireg_t type; 312 313 width = 4; 314 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 315 continue; 316 317 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 318 if (PCI_MAPREG_MEM_TYPE(type) == 319 PCI_MAPREG_MEM_TYPE_64BIT) 320 width = 8; 321 322 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 323 if (pci_mapreg_info(pc, tag, bar, type, 324 &r->r_offset, &r->r_size, &r->r_flags) != 0) 325 break; 326 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 327 && (r->r_size = 0x1000000)) { 328 struct pci_range *nr; 329 /* 330 * this has to be a mach64 331 * split things up so each half-aperture can 332 * be mapped PREFETCHABLE except the last page 333 * which may contain registers 334 */ 335 r->r_size = 0x7ff000; 336 r->r_flags = BUS_SPACE_MAP_LINEAR | 337 BUS_SPACE_MAP_PREFETCHABLE; 338 nr = &sc->PCI_SC_DEVICESC(device, 339 function).c_range[i++]; 340 nr->r_offset = r->r_offset + 0x800000; 341 nr->r_size = 0x7ff000; 342 nr->r_flags = BUS_SPACE_MAP_LINEAR | 343 BUS_SPACE_MAP_PREFETCHABLE; 344 } 345 346 } 347 } 348 349 pa.pa_iot = sc->sc_iot; 350 pa.pa_memt = sc->sc_memt; 351 pa.pa_dmat = sc->sc_dmat; 352 pa.pa_dmat64 = sc->sc_dmat64; 353 pa.pa_pc = pc; 354 pa.pa_bus = bus; 355 pa.pa_device = device; 356 pa.pa_function = function; 357 pa.pa_tag = tag; 358 pa.pa_id = id; 359 pa.pa_class = class; 360 361 /* 362 * Set up memory, I/O enable, and PCI command flags 363 * as appropriate. 364 */ 365 pa.pa_flags = sc->sc_flags; 366 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 367 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 368 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 369 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 370 371 /* 372 * If the cache line size is not configured, then 373 * clear the MRL/MRM/MWI command-ok flags. 374 */ 375 if (PCI_CACHELINE(bhlcr) == 0) 376 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 377 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 378 379 if (sc->sc_bridgetag == NULL) { 380 pa.pa_intrswiz = 0; 381 pa.pa_intrtag = tag; 382 } else { 383 pa.pa_intrswiz = sc->sc_intrswiz + device; 384 pa.pa_intrtag = sc->sc_intrtag; 385 } 386 387 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 388 389 pin = PCI_INTERRUPT_PIN(intr); 390 pa.pa_rawintrpin = pin; 391 if (pin == PCI_INTERRUPT_PIN_NONE) { 392 /* no interrupt */ 393 pa.pa_intrpin = 0; 394 } else { 395 /* 396 * swizzle it based on the number of busses we're 397 * behind and our device number. 398 */ 399 pa.pa_intrpin = /* XXX */ 400 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 401 } 402 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 403 404 if (match != NULL) { 405 ret = (*match)(&pa); 406 if (ret != 0 && pap != NULL) 407 *pap = pa; 408 } else { 409 struct pci_child *c; 410 locs[PCICF_DEV] = device; 411 locs[PCICF_FUNCTION] = function; 412 413 c = &sc->PCI_SC_DEVICESC(device, function); 414 pci_conf_capture(pc, tag, &c->c_conf); 415 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 416 c->c_psok = true; 417 else 418 c->c_psok = false; 419 420 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 421 pciprint, config_stdsubmatch); 422 423 ret = (c->c_dev != NULL); 424 } 425 426 return ret; 427 } 428 429 void 430 pcidevdetached(device_t self, device_t child) 431 { 432 struct pci_softc *sc = device_private(self); 433 int d, f; 434 pcitag_t tag; 435 struct pci_child *c; 436 437 d = device_locator(child, PCICF_DEV); 438 f = device_locator(child, PCICF_FUNCTION); 439 440 c = &sc->PCI_SC_DEVICESC(d, f); 441 442 KASSERT(c->c_dev == child); 443 444 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 445 if (c->c_psok) 446 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 447 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 448 c->c_dev = NULL; 449 } 450 451 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 452 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 453 DVF_DETACH_SHUTDOWN); 454 455 int 456 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 457 int *offset, pcireg_t *value) 458 { 459 pcireg_t reg; 460 unsigned int ofs; 461 462 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 463 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 464 return 0; 465 466 /* Determine the Capability List Pointer register to start with. */ 467 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 468 switch (PCI_HDRTYPE_TYPE(reg)) { 469 case 0: /* standard device header */ 470 case 1: /* PCI-PCI bridge header */ 471 ofs = PCI_CAPLISTPTR_REG; 472 break; 473 case 2: /* PCI-CardBus Bridge header */ 474 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 475 break; 476 default: 477 return 0; 478 } 479 480 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 481 while (ofs != 0) { 482 if ((ofs & 3) || (ofs < 0x40)) { 483 int bus, device, function; 484 485 pci_decompose_tag(pc, tag, &bus, &device, &function); 486 487 printf("Skipping broken PCI header on %d:%d:%d\n", 488 bus, device, function); 489 break; 490 } 491 reg = pci_conf_read(pc, tag, ofs); 492 if (PCI_CAPLIST_CAP(reg) == capid) { 493 if (offset) 494 *offset = ofs; 495 if (value) 496 *value = reg; 497 return 1; 498 } 499 ofs = PCI_CAPLIST_NEXT(reg); 500 } 501 502 return 0; 503 } 504 505 int 506 pci_find_device(struct pci_attach_args *pa, 507 int (*match)(struct pci_attach_args *)) 508 { 509 extern struct cfdriver pci_cd; 510 device_t pcidev; 511 int i; 512 static const int wildcard[2] = { 513 PCICF_DEV_DEFAULT, 514 PCICF_FUNCTION_DEFAULT 515 }; 516 517 for (i = 0; i < pci_cd.cd_ndevs; i++) { 518 pcidev = device_lookup(&pci_cd, i); 519 if (pcidev != NULL && 520 pci_enumerate_bus(device_private(pcidev), wildcard, 521 match, pa) != 0) 522 return 1; 523 } 524 return 0; 525 } 526 527 #ifndef PCI_MACHDEP_ENUMERATE_BUS 528 /* 529 * Generic PCI bus enumeration routine. Used unless machine-dependent 530 * code needs to provide something else. 531 */ 532 int 533 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 534 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 535 { 536 pci_chipset_tag_t pc = sc->sc_pc; 537 int device, function, nfunctions, ret; 538 const struct pci_quirkdata *qd; 539 pcireg_t id, bhlcr; 540 pcitag_t tag; 541 #ifdef __PCI_BUS_DEVORDER 542 char devs[32]; 543 int i; 544 #endif 545 546 #ifdef __PCI_BUS_DEVORDER 547 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 548 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 549 #else 550 for (device = 0; device < sc->sc_maxndevs; device++) 551 #endif 552 { 553 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 554 (locators[PCICF_DEV] != device)) 555 continue; 556 557 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 558 559 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 560 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 561 continue; 562 563 id = pci_conf_read(pc, tag, PCI_ID_REG); 564 565 /* Invalid vendor ID value? */ 566 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 567 continue; 568 /* XXX Not invalid, but we've done this ~forever. */ 569 if (PCI_VENDOR(id) == 0) 570 continue; 571 572 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 573 574 if (qd != NULL && 575 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 576 nfunctions = 8; 577 else if (qd != NULL && 578 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 579 nfunctions = 1; 580 else 581 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 582 583 for (function = 0; function < nfunctions; function++) { 584 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 585 && (locators[PCICF_FUNCTION] != function)) 586 continue; 587 588 if (qd != NULL && 589 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 590 continue; 591 tag = pci_make_tag(pc, sc->sc_bus, device, function); 592 ret = pci_probe_device(sc, tag, match, pap); 593 if (match != NULL && ret != 0) 594 return ret; 595 } 596 } 597 return 0; 598 } 599 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 600 601 602 /* 603 * Vital Product Data (PCI 2.2) 604 */ 605 606 int 607 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 608 pcireg_t *data) 609 { 610 uint32_t reg; 611 int ofs, i, j; 612 613 KASSERT(data != NULL); 614 KASSERT((offset + count) < 0x7fff); 615 616 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 617 return 1; 618 619 for (i = 0; i < count; offset += sizeof(*data), i++) { 620 reg &= 0x0000ffff; 621 reg &= ~PCI_VPD_OPFLAG; 622 reg |= PCI_VPD_ADDRESS(offset); 623 pci_conf_write(pc, tag, ofs, reg); 624 625 /* 626 * PCI 2.2 does not specify how long we should poll 627 * for completion nor whether the operation can fail. 628 */ 629 j = 0; 630 do { 631 if (j++ == 20) 632 return 1; 633 delay(4); 634 reg = pci_conf_read(pc, tag, ofs); 635 } while ((reg & PCI_VPD_OPFLAG) == 0); 636 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 637 } 638 639 return 0; 640 } 641 642 int 643 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 644 pcireg_t *data) 645 { 646 pcireg_t reg; 647 int ofs, i, j; 648 649 KASSERT(data != NULL); 650 KASSERT((offset + count) < 0x7fff); 651 652 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 653 return 1; 654 655 for (i = 0; i < count; offset += sizeof(*data), i++) { 656 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 657 658 reg &= 0x0000ffff; 659 reg |= PCI_VPD_OPFLAG; 660 reg |= PCI_VPD_ADDRESS(offset); 661 pci_conf_write(pc, tag, ofs, reg); 662 663 /* 664 * PCI 2.2 does not specify how long we should poll 665 * for completion nor whether the operation can fail. 666 */ 667 j = 0; 668 do { 669 if (j++ == 20) 670 return 1; 671 delay(1); 672 reg = pci_conf_read(pc, tag, ofs); 673 } while (reg & PCI_VPD_OPFLAG); 674 } 675 676 return 0; 677 } 678 679 int 680 pci_dma64_available(struct pci_attach_args *pa) 681 { 682 #ifdef _PCI_HAVE_DMA64 683 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 684 return 1; 685 #endif 686 return 0; 687 } 688 689 void 690 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 691 struct pci_conf_state *pcs) 692 { 693 int off; 694 695 for (off = 0; off < 16; off++) 696 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 697 698 return; 699 } 700 701 void 702 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 703 struct pci_conf_state *pcs) 704 { 705 int off; 706 pcireg_t val; 707 708 for (off = 15; off >= 0; off--) { 709 val = pci_conf_read(pc, tag, (off * 4)); 710 if (val != pcs->reg[off]) 711 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 712 } 713 714 return; 715 } 716 717 /* 718 * Power Management Capability (Rev 2.2) 719 */ 720 static int 721 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 722 int offset) 723 { 724 pcireg_t value, now; 725 726 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 727 now = value & PCI_PMCSR_STATE_MASK; 728 switch (now) { 729 case PCI_PMCSR_STATE_D0: 730 case PCI_PMCSR_STATE_D1: 731 case PCI_PMCSR_STATE_D2: 732 case PCI_PMCSR_STATE_D3: 733 *state = now; 734 return 0; 735 default: 736 return EINVAL; 737 } 738 } 739 740 int 741 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 742 { 743 int offset; 744 pcireg_t value; 745 746 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 747 return EOPNOTSUPP; 748 749 return pci_get_powerstate_int(pc, tag, state, offset); 750 } 751 752 static int 753 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 754 int offset, pcireg_t cap_reg) 755 { 756 pcireg_t value, cap, now; 757 758 cap = cap_reg >> PCI_PMCR_SHIFT; 759 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 760 now = value & PCI_PMCSR_STATE_MASK; 761 value &= ~PCI_PMCSR_STATE_MASK; 762 763 if (now == state) 764 return 0; 765 switch (state) { 766 case PCI_PMCSR_STATE_D0: 767 break; 768 case PCI_PMCSR_STATE_D1: 769 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 770 printf("invalid transition from %d to D1\n", (int)now); 771 return EINVAL; 772 } 773 if (!(cap & PCI_PMCR_D1SUPP)) { 774 printf("D1 not supported\n"); 775 return EOPNOTSUPP; 776 } 777 break; 778 case PCI_PMCSR_STATE_D2: 779 if (now == PCI_PMCSR_STATE_D3) { 780 printf("invalid transition from %d to D2\n", (int)now); 781 return EINVAL; 782 } 783 if (!(cap & PCI_PMCR_D2SUPP)) { 784 printf("D2 not supported\n"); 785 return EOPNOTSUPP; 786 } 787 break; 788 case PCI_PMCSR_STATE_D3: 789 break; 790 default: 791 return EINVAL; 792 } 793 value |= state; 794 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 795 /* delay according to pcipm1.2, ch. 5.6.1 */ 796 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 797 DELAY(10000); 798 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 799 DELAY(200); 800 801 return 0; 802 } 803 804 int 805 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 806 { 807 int offset; 808 pcireg_t value; 809 810 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 811 printf("pci_set_powerstate not supported\n"); 812 return EOPNOTSUPP; 813 } 814 815 return pci_set_powerstate_int(pc, tag, state, offset, value); 816 } 817 818 int 819 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 820 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 821 { 822 pcireg_t pmode; 823 int error; 824 825 if ((error = pci_get_powerstate(pc, tag, &pmode))) 826 return error; 827 828 switch (pmode) { 829 case PCI_PMCSR_STATE_D0: 830 break; 831 case PCI_PMCSR_STATE_D3: 832 if (wakefun == NULL) { 833 /* 834 * The card has lost all configuration data in 835 * this state, so punt. 836 */ 837 aprint_error_dev(dev, 838 "unable to wake up from power state D3\n"); 839 return EOPNOTSUPP; 840 } 841 /*FALLTHROUGH*/ 842 default: 843 if (wakefun) { 844 error = (*wakefun)(pc, tag, dev, pmode); 845 if (error) 846 return error; 847 } 848 aprint_normal_dev(dev, "waking up from power state D%d\n", 849 pmode); 850 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 851 return error; 852 } 853 return 0; 854 } 855 856 int 857 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 858 device_t dev, pcireg_t state) 859 { 860 return 0; 861 } 862 863 struct pci_child_power { 864 struct pci_conf_state p_pciconf; 865 pci_chipset_tag_t p_pc; 866 pcitag_t p_tag; 867 bool p_has_pm; 868 int p_pm_offset; 869 pcireg_t p_pm_cap; 870 pcireg_t p_class; 871 pcireg_t p_csr; 872 }; 873 874 static bool 875 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 876 { 877 struct pci_child_power *priv = device_pmf_bus_private(dv); 878 pcireg_t ocsr, csr; 879 880 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 881 882 if (!priv->p_has_pm) 883 return true; /* ??? hopefully handled by ACPI */ 884 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 885 return true; /* XXX */ 886 887 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 888 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 889 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 890 | PCI_COMMAND_MASTER_ENABLE); 891 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 892 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 893 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 894 pci_conf_write(priv->p_pc, priv->p_tag, 895 PCI_COMMAND_STATUS_REG, ocsr); 896 aprint_error_dev(dv, "unsupported state, continuing.\n"); 897 return false; 898 } 899 return true; 900 } 901 902 static bool 903 pci_child_resume(device_t dv, const pmf_qual_t *qual) 904 { 905 struct pci_child_power *priv = device_pmf_bus_private(dv); 906 907 if (priv->p_has_pm && 908 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 909 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 910 aprint_error_dev(dv, "unsupported state, continuing.\n"); 911 return false; 912 } 913 914 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 915 916 return true; 917 } 918 919 static bool 920 pci_child_shutdown(device_t dv, int how) 921 { 922 struct pci_child_power *priv = device_pmf_bus_private(dv); 923 pcireg_t csr; 924 925 /* restore original bus-mastering state */ 926 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 927 csr &= ~PCI_COMMAND_MASTER_ENABLE; 928 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 929 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 930 return true; 931 } 932 933 static void 934 pci_child_deregister(device_t dv) 935 { 936 struct pci_child_power *priv = device_pmf_bus_private(dv); 937 938 free(priv, M_DEVBUF); 939 } 940 941 static bool 942 pci_child_register(device_t child) 943 { 944 device_t self = device_parent(child); 945 struct pci_softc *sc = device_private(self); 946 struct pci_child_power *priv; 947 int device, function, off; 948 pcireg_t reg; 949 950 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 951 952 device = device_locator(child, PCICF_DEV); 953 function = device_locator(child, PCICF_FUNCTION); 954 955 priv->p_pc = sc->sc_pc; 956 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 957 function); 958 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 959 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 960 PCI_COMMAND_STATUS_REG); 961 962 if (pci_get_capability(priv->p_pc, priv->p_tag, 963 PCI_CAP_PWRMGMT, &off, ®)) { 964 priv->p_has_pm = true; 965 priv->p_pm_offset = off; 966 priv->p_pm_cap = reg; 967 } else { 968 priv->p_has_pm = false; 969 priv->p_pm_offset = -1; 970 } 971 972 device_pmf_bus_register(child, priv, pci_child_suspend, 973 pci_child_resume, pci_child_shutdown, pci_child_deregister); 974 975 return true; 976 } 977
Indexes created Tue Sep 30 20:09:53 GMT 2025