pci.c revision 1.132
1 /* $NetBSD: pci.c,v 1.132 2011/02/10 12:37:58 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.132 2011/02/10 12:37:58 jmcneill Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 272 { 273 pci_chipset_tag_t pc = sc->sc_pc; 274 struct pci_attach_args pa; 275 pcireg_t id, csr, class, intr, bhlcr, bar; 276 int ret, pin, bus, device, function, i, width; 277 int locs[PCICF_NLOCS]; 278 279 pci_decompose_tag(pc, tag, &bus, &device, &function); 280 281 /* a driver already attached? */ 282 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 283 return 0; 284 285 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 286 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 287 return 0; 288 289 id = pci_conf_read(pc, tag, PCI_ID_REG); 290 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 291 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 /* Collect memory range info */ 301 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 302 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 303 i = 0; 304 for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END; bar += width) { 305 int type = pci_mapreg_type(pc, tag, bar); 306 struct pci_range *r; 307 308 width = 4; 309 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 310 if (PCI_MAPREG_MEM_TYPE(type) == 311 PCI_MAPREG_MEM_TYPE_64BIT) 312 width = 8; 313 314 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 315 if (pci_mapreg_info(pc, tag, bar, type, 316 &r->r_offset, &r->r_size, &r->r_flags) != 0) 317 break; 318 } 319 } 320 321 pa.pa_iot = sc->sc_iot; 322 pa.pa_memt = sc->sc_memt; 323 pa.pa_dmat = sc->sc_dmat; 324 pa.pa_dmat64 = sc->sc_dmat64; 325 pa.pa_pc = pc; 326 pa.pa_bus = bus; 327 pa.pa_device = device; 328 pa.pa_function = function; 329 pa.pa_tag = tag; 330 pa.pa_id = id; 331 pa.pa_class = class; 332 333 /* 334 * Set up memory, I/O enable, and PCI command flags 335 * as appropriate. 336 */ 337 pa.pa_flags = sc->sc_flags; 338 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 339 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 340 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 341 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 342 343 /* 344 * If the cache line size is not configured, then 345 * clear the MRL/MRM/MWI command-ok flags. 346 */ 347 if (PCI_CACHELINE(bhlcr) == 0) 348 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 349 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 350 351 if (sc->sc_bridgetag == NULL) { 352 pa.pa_intrswiz = 0; 353 pa.pa_intrtag = tag; 354 } else { 355 pa.pa_intrswiz = sc->sc_intrswiz + device; 356 pa.pa_intrtag = sc->sc_intrtag; 357 } 358 359 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 360 361 pin = PCI_INTERRUPT_PIN(intr); 362 pa.pa_rawintrpin = pin; 363 if (pin == PCI_INTERRUPT_PIN_NONE) { 364 /* no interrupt */ 365 pa.pa_intrpin = 0; 366 } else { 367 /* 368 * swizzle it based on the number of busses we're 369 * behind and our device number. 370 */ 371 pa.pa_intrpin = /* XXX */ 372 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 373 } 374 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 375 376 if (match != NULL) { 377 ret = (*match)(&pa); 378 if (ret != 0 && pap != NULL) 379 *pap = pa; 380 } else { 381 struct pci_child *c; 382 locs[PCICF_DEV] = device; 383 locs[PCICF_FUNCTION] = function; 384 385 c = &sc->PCI_SC_DEVICESC(device, function); 386 pci_conf_capture(pc, tag, &c->c_conf); 387 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 388 c->c_psok = true; 389 else 390 c->c_psok = false; 391 392 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 393 pciprint, config_stdsubmatch); 394 395 ret = (c->c_dev != NULL); 396 } 397 398 return ret; 399 } 400 401 void 402 pcidevdetached(device_t self, device_t child) 403 { 404 struct pci_softc *sc = device_private(self); 405 int d, f; 406 pcitag_t tag; 407 struct pci_child *c; 408 409 d = device_locator(child, PCICF_DEV); 410 f = device_locator(child, PCICF_FUNCTION); 411 412 c = &sc->PCI_SC_DEVICESC(d, f); 413 414 KASSERT(c->c_dev == child); 415 416 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 417 if (c->c_psok) 418 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 419 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 420 c->c_dev = NULL; 421 } 422 423 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 424 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 425 DVF_DETACH_SHUTDOWN); 426 427 int 428 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 429 int *offset, pcireg_t *value) 430 { 431 pcireg_t reg; 432 unsigned int ofs; 433 434 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 435 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 436 return 0; 437 438 /* Determine the Capability List Pointer register to start with. */ 439 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 440 switch (PCI_HDRTYPE_TYPE(reg)) { 441 case 0: /* standard device header */ 442 case 1: /* PCI-PCI bridge header */ 443 ofs = PCI_CAPLISTPTR_REG; 444 break; 445 case 2: /* PCI-CardBus Bridge header */ 446 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 447 break; 448 default: 449 return 0; 450 } 451 452 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 453 while (ofs != 0) { 454 if ((ofs & 3) || (ofs < 0x40)) { 455 int bus, device, function; 456 457 pci_decompose_tag(pc, tag, &bus, &device, &function); 458 459 printf("Skipping broken PCI header on %d:%d:%d\n", 460 bus, device, function); 461 break; 462 } 463 reg = pci_conf_read(pc, tag, ofs); 464 if (PCI_CAPLIST_CAP(reg) == capid) { 465 if (offset) 466 *offset = ofs; 467 if (value) 468 *value = reg; 469 return 1; 470 } 471 ofs = PCI_CAPLIST_NEXT(reg); 472 } 473 474 return 0; 475 } 476 477 int 478 pci_find_device(struct pci_attach_args *pa, 479 int (*match)(struct pci_attach_args *)) 480 { 481 extern struct cfdriver pci_cd; 482 device_t pcidev; 483 int i; 484 static const int wildcard[2] = { 485 PCICF_DEV_DEFAULT, 486 PCICF_FUNCTION_DEFAULT 487 }; 488 489 for (i = 0; i < pci_cd.cd_ndevs; i++) { 490 pcidev = device_lookup(&pci_cd, i); 491 if (pcidev != NULL && 492 pci_enumerate_bus(device_private(pcidev), wildcard, 493 match, pa) != 0) 494 return 1; 495 } 496 return 0; 497 } 498 499 #ifndef PCI_MACHDEP_ENUMERATE_BUS 500 /* 501 * Generic PCI bus enumeration routine. Used unless machine-dependent 502 * code needs to provide something else. 503 */ 504 int 505 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 506 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 507 { 508 pci_chipset_tag_t pc = sc->sc_pc; 509 int device, function, nfunctions, ret; 510 const struct pci_quirkdata *qd; 511 pcireg_t id, bhlcr; 512 pcitag_t tag; 513 #ifdef __PCI_BUS_DEVORDER 514 char devs[32]; 515 int i; 516 #endif 517 518 #ifdef __PCI_BUS_DEVORDER 519 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 520 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 521 #else 522 for (device = 0; device < sc->sc_maxndevs; device++) 523 #endif 524 { 525 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 526 (locators[PCICF_DEV] != device)) 527 continue; 528 529 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 530 531 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 532 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 533 continue; 534 535 id = pci_conf_read(pc, tag, PCI_ID_REG); 536 537 /* Invalid vendor ID value? */ 538 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 539 continue; 540 /* XXX Not invalid, but we've done this ~forever. */ 541 if (PCI_VENDOR(id) == 0) 542 continue; 543 544 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 545 546 if (qd != NULL && 547 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 548 nfunctions = 8; 549 else if (qd != NULL && 550 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 551 nfunctions = 1; 552 else 553 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 554 555 for (function = 0; function < nfunctions; function++) { 556 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 557 && (locators[PCICF_FUNCTION] != function)) 558 continue; 559 560 if (qd != NULL && 561 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 562 continue; 563 tag = pci_make_tag(pc, sc->sc_bus, device, function); 564 ret = pci_probe_device(sc, tag, match, pap); 565 if (match != NULL && ret != 0) 566 return ret; 567 } 568 } 569 return 0; 570 } 571 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 572 573 574 /* 575 * Vital Product Data (PCI 2.2) 576 */ 577 578 int 579 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 580 pcireg_t *data) 581 { 582 uint32_t reg; 583 int ofs, i, j; 584 585 KASSERT(data != NULL); 586 KASSERT((offset + count) < 0x7fff); 587 588 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 589 return 1; 590 591 for (i = 0; i < count; offset += sizeof(*data), i++) { 592 reg &= 0x0000ffff; 593 reg &= ~PCI_VPD_OPFLAG; 594 reg |= PCI_VPD_ADDRESS(offset); 595 pci_conf_write(pc, tag, ofs, reg); 596 597 /* 598 * PCI 2.2 does not specify how long we should poll 599 * for completion nor whether the operation can fail. 600 */ 601 j = 0; 602 do { 603 if (j++ == 20) 604 return 1; 605 delay(4); 606 reg = pci_conf_read(pc, tag, ofs); 607 } while ((reg & PCI_VPD_OPFLAG) == 0); 608 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 609 } 610 611 return 0; 612 } 613 614 int 615 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 616 pcireg_t *data) 617 { 618 pcireg_t reg; 619 int ofs, i, j; 620 621 KASSERT(data != NULL); 622 KASSERT((offset + count) < 0x7fff); 623 624 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 625 return 1; 626 627 for (i = 0; i < count; offset += sizeof(*data), i++) { 628 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 629 630 reg &= 0x0000ffff; 631 reg |= PCI_VPD_OPFLAG; 632 reg |= PCI_VPD_ADDRESS(offset); 633 pci_conf_write(pc, tag, ofs, reg); 634 635 /* 636 * PCI 2.2 does not specify how long we should poll 637 * for completion nor whether the operation can fail. 638 */ 639 j = 0; 640 do { 641 if (j++ == 20) 642 return 1; 643 delay(1); 644 reg = pci_conf_read(pc, tag, ofs); 645 } while (reg & PCI_VPD_OPFLAG); 646 } 647 648 return 0; 649 } 650 651 int 652 pci_dma64_available(struct pci_attach_args *pa) 653 { 654 #ifdef _PCI_HAVE_DMA64 655 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 656 return 1; 657 #endif 658 return 0; 659 } 660 661 void 662 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 663 struct pci_conf_state *pcs) 664 { 665 int off; 666 667 for (off = 0; off < 16; off++) 668 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 669 670 return; 671 } 672 673 void 674 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 675 struct pci_conf_state *pcs) 676 { 677 int off; 678 pcireg_t val; 679 680 for (off = 15; off >= 0; off--) { 681 val = pci_conf_read(pc, tag, (off * 4)); 682 if (val != pcs->reg[off]) 683 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 684 } 685 686 return; 687 } 688 689 /* 690 * Power Management Capability (Rev 2.2) 691 */ 692 static int 693 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 694 int offset) 695 { 696 pcireg_t value, now; 697 698 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 699 now = value & PCI_PMCSR_STATE_MASK; 700 switch (now) { 701 case PCI_PMCSR_STATE_D0: 702 case PCI_PMCSR_STATE_D1: 703 case PCI_PMCSR_STATE_D2: 704 case PCI_PMCSR_STATE_D3: 705 *state = now; 706 return 0; 707 default: 708 return EINVAL; 709 } 710 } 711 712 int 713 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 714 { 715 int offset; 716 pcireg_t value; 717 718 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 719 return EOPNOTSUPP; 720 721 return pci_get_powerstate_int(pc, tag, state, offset); 722 } 723 724 static int 725 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 726 int offset, pcireg_t cap_reg) 727 { 728 pcireg_t value, cap, now; 729 730 cap = cap_reg >> PCI_PMCR_SHIFT; 731 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 732 now = value & PCI_PMCSR_STATE_MASK; 733 value &= ~PCI_PMCSR_STATE_MASK; 734 735 if (now == state) 736 return 0; 737 switch (state) { 738 case PCI_PMCSR_STATE_D0: 739 break; 740 case PCI_PMCSR_STATE_D1: 741 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 742 printf("invalid transition from %d to D1\n", (int)now); 743 return EINVAL; 744 } 745 if (!(cap & PCI_PMCR_D1SUPP)) { 746 printf("D1 not supported\n"); 747 return EOPNOTSUPP; 748 } 749 break; 750 case PCI_PMCSR_STATE_D2: 751 if (now == PCI_PMCSR_STATE_D3) { 752 printf("invalid transition from %d to D2\n", (int)now); 753 return EINVAL; 754 } 755 if (!(cap & PCI_PMCR_D2SUPP)) { 756 printf("D2 not supported\n"); 757 return EOPNOTSUPP; 758 } 759 break; 760 case PCI_PMCSR_STATE_D3: 761 break; 762 default: 763 return EINVAL; 764 } 765 value |= state; 766 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 767 /* delay according to pcipm1.2, ch. 5.6.1 */ 768 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 769 DELAY(10000); 770 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 771 DELAY(200); 772 773 return 0; 774 } 775 776 int 777 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 778 { 779 int offset; 780 pcireg_t value; 781 782 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 783 printf("pci_set_powerstate not supported\n"); 784 return EOPNOTSUPP; 785 } 786 787 return pci_set_powerstate_int(pc, tag, state, offset, value); 788 } 789 790 int 791 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 792 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 793 { 794 pcireg_t pmode; 795 int error; 796 797 if ((error = pci_get_powerstate(pc, tag, &pmode))) 798 return error; 799 800 switch (pmode) { 801 case PCI_PMCSR_STATE_D0: 802 break; 803 case PCI_PMCSR_STATE_D3: 804 if (wakefun == NULL) { 805 /* 806 * The card has lost all configuration data in 807 * this state, so punt. 808 */ 809 aprint_error_dev(dev, 810 "unable to wake up from power state D3\n"); 811 return EOPNOTSUPP; 812 } 813 /*FALLTHROUGH*/ 814 default: 815 if (wakefun) { 816 error = (*wakefun)(pc, tag, dev, pmode); 817 if (error) 818 return error; 819 } 820 aprint_normal_dev(dev, "waking up from power state D%d\n", 821 pmode); 822 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 823 return error; 824 } 825 return 0; 826 } 827 828 int 829 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 830 device_t dev, pcireg_t state) 831 { 832 return 0; 833 } 834 835 struct pci_child_power { 836 struct pci_conf_state p_pciconf; 837 pci_chipset_tag_t p_pc; 838 pcitag_t p_tag; 839 bool p_has_pm; 840 int p_pm_offset; 841 pcireg_t p_pm_cap; 842 pcireg_t p_class; 843 pcireg_t p_csr; 844 }; 845 846 static bool 847 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 848 { 849 struct pci_child_power *priv = device_pmf_bus_private(dv); 850 pcireg_t ocsr, csr; 851 852 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 853 854 if (!priv->p_has_pm) 855 return true; /* ??? hopefully handled by ACPI */ 856 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 857 return true; /* XXX */ 858 859 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 860 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 861 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 862 | PCI_COMMAND_MASTER_ENABLE); 863 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 864 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 865 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 866 pci_conf_write(priv->p_pc, priv->p_tag, 867 PCI_COMMAND_STATUS_REG, ocsr); 868 aprint_error_dev(dv, "unsupported state, continuing.\n"); 869 return false; 870 } 871 return true; 872 } 873 874 static bool 875 pci_child_resume(device_t dv, const pmf_qual_t *qual) 876 { 877 struct pci_child_power *priv = device_pmf_bus_private(dv); 878 879 if (priv->p_has_pm && 880 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 881 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 882 aprint_error_dev(dv, "unsupported state, continuing.\n"); 883 return false; 884 } 885 886 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 887 888 return true; 889 } 890 891 static bool 892 pci_child_shutdown(device_t dv, int how) 893 { 894 struct pci_child_power *priv = device_pmf_bus_private(dv); 895 pcireg_t csr; 896 897 /* restore original bus-mastering state */ 898 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 899 csr &= ~PCI_COMMAND_MASTER_ENABLE; 900 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 901 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 902 return true; 903 } 904 905 static void 906 pci_child_deregister(device_t dv) 907 { 908 struct pci_child_power *priv = device_pmf_bus_private(dv); 909 910 free(priv, M_DEVBUF); 911 } 912 913 static bool 914 pci_child_register(device_t child) 915 { 916 device_t self = device_parent(child); 917 struct pci_softc *sc = device_private(self); 918 struct pci_child_power *priv; 919 int device, function, off; 920 pcireg_t reg; 921 922 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 923 924 device = device_locator(child, PCICF_DEV); 925 function = device_locator(child, PCICF_FUNCTION); 926 927 priv->p_pc = sc->sc_pc; 928 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 929 function); 930 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 931 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 932 PCI_COMMAND_STATUS_REG); 933 934 if (pci_get_capability(priv->p_pc, priv->p_tag, 935 PCI_CAP_PWRMGMT, &off, ®)) { 936 priv->p_has_pm = true; 937 priv->p_pm_offset = off; 938 priv->p_pm_cap = reg; 939 } else { 940 priv->p_has_pm = false; 941 priv->p_pm_offset = -1; 942 } 943 944 device_pmf_bus_register(child, priv, pci_child_suspend, 945 pci_child_resume, pci_child_shutdown, pci_child_deregister); 946 947 return true; 948 } 949
Indexes created Tue Sep 23 14:10:03 GMT 2025