pci.c revision 1.134
1 /* $NetBSD: pci.c,v 1.134 2011/02/27 18:10:25 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.134 2011/02/27 18:10:25 jmcneill Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 272 { 273 pci_chipset_tag_t pc = sc->sc_pc; 274 struct pci_attach_args pa; 275 pcireg_t id, csr, class, intr, bhlcr, bar; 276 int ret, pin, bus, device, function, i, width; 277 int locs[PCICF_NLOCS]; 278 279 pci_decompose_tag(pc, tag, &bus, &device, &function); 280 281 /* a driver already attached? */ 282 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 283 return 0; 284 285 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 286 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 287 return 0; 288 289 id = pci_conf_read(pc, tag, PCI_ID_REG); 290 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 291 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 /* Collect memory range info */ 301 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 302 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 303 i = 0; 304 for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END; bar += width) { 305 struct pci_range *r; 306 pcireg_t type; 307 308 width = 4; 309 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 310 continue; 311 312 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 313 if (PCI_MAPREG_MEM_TYPE(type) == 314 PCI_MAPREG_MEM_TYPE_64BIT) 315 width = 8; 316 317 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 318 if (pci_mapreg_info(pc, tag, bar, type, 319 &r->r_offset, &r->r_size, &r->r_flags) != 0) 320 break; 321 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 322 && (r->r_size = 0x1000000)) { 323 struct pci_range *nr; 324 /* 325 * this has to be a mach64 326 * split things up so each half-aperture can 327 * be mapped PREFETCHABLE except the last page 328 * which may contain registers 329 */ 330 r->r_size = 0x7ff000; 331 r->r_flags = BUS_SPACE_MAP_LINEAR | 332 BUS_SPACE_MAP_PREFETCHABLE; 333 nr = &sc->PCI_SC_DEVICESC(device, 334 function).c_range[i++]; 335 nr->r_offset = r->r_offset + 0x800000; 336 nr->r_size = 0x7ff000; 337 nr->r_flags = BUS_SPACE_MAP_LINEAR | 338 BUS_SPACE_MAP_PREFETCHABLE; 339 } 340 341 } 342 } 343 344 pa.pa_iot = sc->sc_iot; 345 pa.pa_memt = sc->sc_memt; 346 pa.pa_dmat = sc->sc_dmat; 347 pa.pa_dmat64 = sc->sc_dmat64; 348 pa.pa_pc = pc; 349 pa.pa_bus = bus; 350 pa.pa_device = device; 351 pa.pa_function = function; 352 pa.pa_tag = tag; 353 pa.pa_id = id; 354 pa.pa_class = class; 355 356 /* 357 * Set up memory, I/O enable, and PCI command flags 358 * as appropriate. 359 */ 360 pa.pa_flags = sc->sc_flags; 361 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 362 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 363 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 364 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 365 366 /* 367 * If the cache line size is not configured, then 368 * clear the MRL/MRM/MWI command-ok flags. 369 */ 370 if (PCI_CACHELINE(bhlcr) == 0) 371 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 372 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 373 374 if (sc->sc_bridgetag == NULL) { 375 pa.pa_intrswiz = 0; 376 pa.pa_intrtag = tag; 377 } else { 378 pa.pa_intrswiz = sc->sc_intrswiz + device; 379 pa.pa_intrtag = sc->sc_intrtag; 380 } 381 382 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 383 384 pin = PCI_INTERRUPT_PIN(intr); 385 pa.pa_rawintrpin = pin; 386 if (pin == PCI_INTERRUPT_PIN_NONE) { 387 /* no interrupt */ 388 pa.pa_intrpin = 0; 389 } else { 390 /* 391 * swizzle it based on the number of busses we're 392 * behind and our device number. 393 */ 394 pa.pa_intrpin = /* XXX */ 395 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 396 } 397 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 398 399 if (match != NULL) { 400 ret = (*match)(&pa); 401 if (ret != 0 && pap != NULL) 402 *pap = pa; 403 } else { 404 struct pci_child *c; 405 locs[PCICF_DEV] = device; 406 locs[PCICF_FUNCTION] = function; 407 408 c = &sc->PCI_SC_DEVICESC(device, function); 409 pci_conf_capture(pc, tag, &c->c_conf); 410 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 411 c->c_psok = true; 412 else 413 c->c_psok = false; 414 415 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 416 pciprint, config_stdsubmatch); 417 418 ret = (c->c_dev != NULL); 419 } 420 421 return ret; 422 } 423 424 void 425 pcidevdetached(device_t self, device_t child) 426 { 427 struct pci_softc *sc = device_private(self); 428 int d, f; 429 pcitag_t tag; 430 struct pci_child *c; 431 432 d = device_locator(child, PCICF_DEV); 433 f = device_locator(child, PCICF_FUNCTION); 434 435 c = &sc->PCI_SC_DEVICESC(d, f); 436 437 KASSERT(c->c_dev == child); 438 439 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 440 if (c->c_psok) 441 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 442 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 443 c->c_dev = NULL; 444 } 445 446 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 447 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 448 DVF_DETACH_SHUTDOWN); 449 450 int 451 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 452 int *offset, pcireg_t *value) 453 { 454 pcireg_t reg; 455 unsigned int ofs; 456 457 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 458 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 459 return 0; 460 461 /* Determine the Capability List Pointer register to start with. */ 462 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 463 switch (PCI_HDRTYPE_TYPE(reg)) { 464 case 0: /* standard device header */ 465 case 1: /* PCI-PCI bridge header */ 466 ofs = PCI_CAPLISTPTR_REG; 467 break; 468 case 2: /* PCI-CardBus Bridge header */ 469 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 470 break; 471 default: 472 return 0; 473 } 474 475 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 476 while (ofs != 0) { 477 if ((ofs & 3) || (ofs < 0x40)) { 478 int bus, device, function; 479 480 pci_decompose_tag(pc, tag, &bus, &device, &function); 481 482 printf("Skipping broken PCI header on %d:%d:%d\n", 483 bus, device, function); 484 break; 485 } 486 reg = pci_conf_read(pc, tag, ofs); 487 if (PCI_CAPLIST_CAP(reg) == capid) { 488 if (offset) 489 *offset = ofs; 490 if (value) 491 *value = reg; 492 return 1; 493 } 494 ofs = PCI_CAPLIST_NEXT(reg); 495 } 496 497 return 0; 498 } 499 500 int 501 pci_find_device(struct pci_attach_args *pa, 502 int (*match)(struct pci_attach_args *)) 503 { 504 extern struct cfdriver pci_cd; 505 device_t pcidev; 506 int i; 507 static const int wildcard[2] = { 508 PCICF_DEV_DEFAULT, 509 PCICF_FUNCTION_DEFAULT 510 }; 511 512 for (i = 0; i < pci_cd.cd_ndevs; i++) { 513 pcidev = device_lookup(&pci_cd, i); 514 if (pcidev != NULL && 515 pci_enumerate_bus(device_private(pcidev), wildcard, 516 match, pa) != 0) 517 return 1; 518 } 519 return 0; 520 } 521 522 #ifndef PCI_MACHDEP_ENUMERATE_BUS 523 /* 524 * Generic PCI bus enumeration routine. Used unless machine-dependent 525 * code needs to provide something else. 526 */ 527 int 528 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 529 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 530 { 531 pci_chipset_tag_t pc = sc->sc_pc; 532 int device, function, nfunctions, ret; 533 const struct pci_quirkdata *qd; 534 pcireg_t id, bhlcr; 535 pcitag_t tag; 536 #ifdef __PCI_BUS_DEVORDER 537 char devs[32]; 538 int i; 539 #endif 540 541 #ifdef __PCI_BUS_DEVORDER 542 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 543 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 544 #else 545 for (device = 0; device < sc->sc_maxndevs; device++) 546 #endif 547 { 548 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 549 (locators[PCICF_DEV] != device)) 550 continue; 551 552 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 553 554 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 555 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 556 continue; 557 558 id = pci_conf_read(pc, tag, PCI_ID_REG); 559 560 /* Invalid vendor ID value? */ 561 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 562 continue; 563 /* XXX Not invalid, but we've done this ~forever. */ 564 if (PCI_VENDOR(id) == 0) 565 continue; 566 567 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 568 569 if (qd != NULL && 570 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 571 nfunctions = 8; 572 else if (qd != NULL && 573 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 574 nfunctions = 1; 575 else 576 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 577 578 for (function = 0; function < nfunctions; function++) { 579 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 580 && (locators[PCICF_FUNCTION] != function)) 581 continue; 582 583 if (qd != NULL && 584 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 585 continue; 586 tag = pci_make_tag(pc, sc->sc_bus, device, function); 587 ret = pci_probe_device(sc, tag, match, pap); 588 if (match != NULL && ret != 0) 589 return ret; 590 } 591 } 592 return 0; 593 } 594 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 595 596 597 /* 598 * Vital Product Data (PCI 2.2) 599 */ 600 601 int 602 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 603 pcireg_t *data) 604 { 605 uint32_t reg; 606 int ofs, i, j; 607 608 KASSERT(data != NULL); 609 KASSERT((offset + count) < 0x7fff); 610 611 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 612 return 1; 613 614 for (i = 0; i < count; offset += sizeof(*data), i++) { 615 reg &= 0x0000ffff; 616 reg &= ~PCI_VPD_OPFLAG; 617 reg |= PCI_VPD_ADDRESS(offset); 618 pci_conf_write(pc, tag, ofs, reg); 619 620 /* 621 * PCI 2.2 does not specify how long we should poll 622 * for completion nor whether the operation can fail. 623 */ 624 j = 0; 625 do { 626 if (j++ == 20) 627 return 1; 628 delay(4); 629 reg = pci_conf_read(pc, tag, ofs); 630 } while ((reg & PCI_VPD_OPFLAG) == 0); 631 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 632 } 633 634 return 0; 635 } 636 637 int 638 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 639 pcireg_t *data) 640 { 641 pcireg_t reg; 642 int ofs, i, j; 643 644 KASSERT(data != NULL); 645 KASSERT((offset + count) < 0x7fff); 646 647 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 648 return 1; 649 650 for (i = 0; i < count; offset += sizeof(*data), i++) { 651 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 652 653 reg &= 0x0000ffff; 654 reg |= PCI_VPD_OPFLAG; 655 reg |= PCI_VPD_ADDRESS(offset); 656 pci_conf_write(pc, tag, ofs, reg); 657 658 /* 659 * PCI 2.2 does not specify how long we should poll 660 * for completion nor whether the operation can fail. 661 */ 662 j = 0; 663 do { 664 if (j++ == 20) 665 return 1; 666 delay(1); 667 reg = pci_conf_read(pc, tag, ofs); 668 } while (reg & PCI_VPD_OPFLAG); 669 } 670 671 return 0; 672 } 673 674 int 675 pci_dma64_available(struct pci_attach_args *pa) 676 { 677 #ifdef _PCI_HAVE_DMA64 678 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 679 return 1; 680 #endif 681 return 0; 682 } 683 684 void 685 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 686 struct pci_conf_state *pcs) 687 { 688 int off; 689 690 for (off = 0; off < 16; off++) 691 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 692 693 return; 694 } 695 696 void 697 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 698 struct pci_conf_state *pcs) 699 { 700 int off; 701 pcireg_t val; 702 703 for (off = 15; off >= 0; off--) { 704 val = pci_conf_read(pc, tag, (off * 4)); 705 if (val != pcs->reg[off]) 706 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 707 } 708 709 return; 710 } 711 712 /* 713 * Power Management Capability (Rev 2.2) 714 */ 715 static int 716 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 717 int offset) 718 { 719 pcireg_t value, now; 720 721 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 722 now = value & PCI_PMCSR_STATE_MASK; 723 switch (now) { 724 case PCI_PMCSR_STATE_D0: 725 case PCI_PMCSR_STATE_D1: 726 case PCI_PMCSR_STATE_D2: 727 case PCI_PMCSR_STATE_D3: 728 *state = now; 729 return 0; 730 default: 731 return EINVAL; 732 } 733 } 734 735 int 736 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 737 { 738 int offset; 739 pcireg_t value; 740 741 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 742 return EOPNOTSUPP; 743 744 return pci_get_powerstate_int(pc, tag, state, offset); 745 } 746 747 static int 748 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 749 int offset, pcireg_t cap_reg) 750 { 751 pcireg_t value, cap, now; 752 753 cap = cap_reg >> PCI_PMCR_SHIFT; 754 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 755 now = value & PCI_PMCSR_STATE_MASK; 756 value &= ~PCI_PMCSR_STATE_MASK; 757 758 if (now == state) 759 return 0; 760 switch (state) { 761 case PCI_PMCSR_STATE_D0: 762 break; 763 case PCI_PMCSR_STATE_D1: 764 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 765 printf("invalid transition from %d to D1\n", (int)now); 766 return EINVAL; 767 } 768 if (!(cap & PCI_PMCR_D1SUPP)) { 769 printf("D1 not supported\n"); 770 return EOPNOTSUPP; 771 } 772 break; 773 case PCI_PMCSR_STATE_D2: 774 if (now == PCI_PMCSR_STATE_D3) { 775 printf("invalid transition from %d to D2\n", (int)now); 776 return EINVAL; 777 } 778 if (!(cap & PCI_PMCR_D2SUPP)) { 779 printf("D2 not supported\n"); 780 return EOPNOTSUPP; 781 } 782 break; 783 case PCI_PMCSR_STATE_D3: 784 break; 785 default: 786 return EINVAL; 787 } 788 value |= state; 789 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 790 /* delay according to pcipm1.2, ch. 5.6.1 */ 791 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 792 DELAY(10000); 793 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 794 DELAY(200); 795 796 return 0; 797 } 798 799 int 800 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 801 { 802 int offset; 803 pcireg_t value; 804 805 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 806 printf("pci_set_powerstate not supported\n"); 807 return EOPNOTSUPP; 808 } 809 810 return pci_set_powerstate_int(pc, tag, state, offset, value); 811 } 812 813 int 814 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 815 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 816 { 817 pcireg_t pmode; 818 int error; 819 820 if ((error = pci_get_powerstate(pc, tag, &pmode))) 821 return error; 822 823 switch (pmode) { 824 case PCI_PMCSR_STATE_D0: 825 break; 826 case PCI_PMCSR_STATE_D3: 827 if (wakefun == NULL) { 828 /* 829 * The card has lost all configuration data in 830 * this state, so punt. 831 */ 832 aprint_error_dev(dev, 833 "unable to wake up from power state D3\n"); 834 return EOPNOTSUPP; 835 } 836 /*FALLTHROUGH*/ 837 default: 838 if (wakefun) { 839 error = (*wakefun)(pc, tag, dev, pmode); 840 if (error) 841 return error; 842 } 843 aprint_normal_dev(dev, "waking up from power state D%d\n", 844 pmode); 845 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 846 return error; 847 } 848 return 0; 849 } 850 851 int 852 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 853 device_t dev, pcireg_t state) 854 { 855 return 0; 856 } 857 858 struct pci_child_power { 859 struct pci_conf_state p_pciconf; 860 pci_chipset_tag_t p_pc; 861 pcitag_t p_tag; 862 bool p_has_pm; 863 int p_pm_offset; 864 pcireg_t p_pm_cap; 865 pcireg_t p_class; 866 pcireg_t p_csr; 867 }; 868 869 static bool 870 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 871 { 872 struct pci_child_power *priv = device_pmf_bus_private(dv); 873 pcireg_t ocsr, csr; 874 875 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 876 877 if (!priv->p_has_pm) 878 return true; /* ??? hopefully handled by ACPI */ 879 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 880 return true; /* XXX */ 881 882 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 883 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 884 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 885 | PCI_COMMAND_MASTER_ENABLE); 886 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 887 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 888 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 889 pci_conf_write(priv->p_pc, priv->p_tag, 890 PCI_COMMAND_STATUS_REG, ocsr); 891 aprint_error_dev(dv, "unsupported state, continuing.\n"); 892 return false; 893 } 894 return true; 895 } 896 897 static bool 898 pci_child_resume(device_t dv, const pmf_qual_t *qual) 899 { 900 struct pci_child_power *priv = device_pmf_bus_private(dv); 901 902 if (priv->p_has_pm && 903 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 904 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 905 aprint_error_dev(dv, "unsupported state, continuing.\n"); 906 return false; 907 } 908 909 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 910 911 return true; 912 } 913 914 static bool 915 pci_child_shutdown(device_t dv, int how) 916 { 917 struct pci_child_power *priv = device_pmf_bus_private(dv); 918 pcireg_t csr; 919 920 /* restore original bus-mastering state */ 921 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 922 csr &= ~PCI_COMMAND_MASTER_ENABLE; 923 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 924 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 925 return true; 926 } 927 928 static void 929 pci_child_deregister(device_t dv) 930 { 931 struct pci_child_power *priv = device_pmf_bus_private(dv); 932 933 free(priv, M_DEVBUF); 934 } 935 936 static bool 937 pci_child_register(device_t child) 938 { 939 device_t self = device_parent(child); 940 struct pci_softc *sc = device_private(self); 941 struct pci_child_power *priv; 942 int device, function, off; 943 pcireg_t reg; 944 945 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 946 947 device = device_locator(child, PCICF_DEV); 948 function = device_locator(child, PCICF_FUNCTION); 949 950 priv->p_pc = sc->sc_pc; 951 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 952 function); 953 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 954 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 955 PCI_COMMAND_STATUS_REG); 956 957 if (pci_get_capability(priv->p_pc, priv->p_tag, 958 PCI_CAP_PWRMGMT, &off, ®)) { 959 priv->p_has_pm = true; 960 priv->p_pm_offset = off; 961 priv->p_pm_cap = reg; 962 } else { 963 priv->p_has_pm = false; 964 priv->p_pm_offset = -1; 965 } 966 967 device_pmf_bus_register(child, priv, pci_child_suspend, 968 pci_child_resume, pci_child_shutdown, pci_child_deregister); 969 970 return true; 971 } 972
Indexes created Sun Sep 21 20:09:37 GMT 2025