pci.c revision 1.136
1 /* $NetBSD: pci.c,v 1.136 2011/04/04 20:37:56 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.136 2011/04/04 20:37:56 dyoung Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <net/if.h> 53 54 #include "locators.h" 55 56 static bool pci_child_register(device_t); 57 58 #ifdef PCI_CONFIG_DUMP 59 int pci_config_dump = 1; 60 #else 61 int pci_config_dump = 0; 62 #endif 63 64 int pciprint(void *, const char *); 65 66 #ifdef PCI_MACHDEP_ENUMERATE_BUS 67 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 68 #else 69 int pci_enumerate_bus(struct pci_softc *, const int *, 70 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(const struct pci_attach_args *), 272 struct pci_attach_args *pap) 273 { 274 pci_chipset_tag_t pc = sc->sc_pc; 275 struct pci_attach_args pa; 276 pcireg_t id, csr, class, intr, bhlcr, bar, endbar; 277 int ret, pin, bus, device, function, i, width; 278 int locs[PCICF_NLOCS]; 279 280 pci_decompose_tag(pc, tag, &bus, &device, &function); 281 282 /* a driver already attached? */ 283 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 284 return 0; 285 286 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 287 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 288 return 0; 289 290 id = pci_conf_read(pc, tag, PCI_ID_REG); 291 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 292 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 293 294 /* Invalid vendor ID value? */ 295 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 296 return 0; 297 /* XXX Not invalid, but we've done this ~forever. */ 298 if (PCI_VENDOR(id) == 0) 299 return 0; 300 301 /* Collect memory range info */ 302 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 303 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 304 i = 0; 305 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 306 case PCI_HDRTYPE_PPB: endbar = PCI_MAPREG_PPB_END; break; 307 case PCI_HDRTYPE_PCB: endbar = PCI_MAPREG_PCB_END; break; 308 default: endbar = PCI_MAPREG_END; break; 309 } 310 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 311 struct pci_range *r; 312 pcireg_t type; 313 314 width = 4; 315 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 316 continue; 317 318 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 319 if (PCI_MAPREG_MEM_TYPE(type) == 320 PCI_MAPREG_MEM_TYPE_64BIT) 321 width = 8; 322 323 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 324 if (pci_mapreg_info(pc, tag, bar, type, 325 &r->r_offset, &r->r_size, &r->r_flags) != 0) 326 break; 327 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 328 && (r->r_size = 0x1000000)) { 329 struct pci_range *nr; 330 /* 331 * this has to be a mach64 332 * split things up so each half-aperture can 333 * be mapped PREFETCHABLE except the last page 334 * which may contain registers 335 */ 336 r->r_size = 0x7ff000; 337 r->r_flags = BUS_SPACE_MAP_LINEAR | 338 BUS_SPACE_MAP_PREFETCHABLE; 339 nr = &sc->PCI_SC_DEVICESC(device, 340 function).c_range[i++]; 341 nr->r_offset = r->r_offset + 0x800000; 342 nr->r_size = 0x7ff000; 343 nr->r_flags = BUS_SPACE_MAP_LINEAR | 344 BUS_SPACE_MAP_PREFETCHABLE; 345 } 346 347 } 348 } 349 350 pa.pa_iot = sc->sc_iot; 351 pa.pa_memt = sc->sc_memt; 352 pa.pa_dmat = sc->sc_dmat; 353 pa.pa_dmat64 = sc->sc_dmat64; 354 pa.pa_pc = pc; 355 pa.pa_bus = bus; 356 pa.pa_device = device; 357 pa.pa_function = function; 358 pa.pa_tag = tag; 359 pa.pa_id = id; 360 pa.pa_class = class; 361 362 /* 363 * Set up memory, I/O enable, and PCI command flags 364 * as appropriate. 365 */ 366 pa.pa_flags = sc->sc_flags; 367 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 368 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 369 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 370 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 371 372 /* 373 * If the cache line size is not configured, then 374 * clear the MRL/MRM/MWI command-ok flags. 375 */ 376 if (PCI_CACHELINE(bhlcr) == 0) 377 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 378 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 379 380 if (sc->sc_bridgetag == NULL) { 381 pa.pa_intrswiz = 0; 382 pa.pa_intrtag = tag; 383 } else { 384 pa.pa_intrswiz = sc->sc_intrswiz + device; 385 pa.pa_intrtag = sc->sc_intrtag; 386 } 387 388 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 389 390 pin = PCI_INTERRUPT_PIN(intr); 391 pa.pa_rawintrpin = pin; 392 if (pin == PCI_INTERRUPT_PIN_NONE) { 393 /* no interrupt */ 394 pa.pa_intrpin = 0; 395 } else { 396 /* 397 * swizzle it based on the number of busses we're 398 * behind and our device number. 399 */ 400 pa.pa_intrpin = /* XXX */ 401 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 402 } 403 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 404 405 if (match != NULL) { 406 ret = (*match)(&pa); 407 if (ret != 0 && pap != NULL) 408 *pap = pa; 409 } else { 410 struct pci_child *c; 411 locs[PCICF_DEV] = device; 412 locs[PCICF_FUNCTION] = function; 413 414 c = &sc->PCI_SC_DEVICESC(device, function); 415 pci_conf_capture(pc, tag, &c->c_conf); 416 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 417 c->c_psok = true; 418 else 419 c->c_psok = false; 420 421 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 422 pciprint, config_stdsubmatch); 423 424 ret = (c->c_dev != NULL); 425 } 426 427 return ret; 428 } 429 430 void 431 pcidevdetached(device_t self, device_t child) 432 { 433 struct pci_softc *sc = device_private(self); 434 int d, f; 435 pcitag_t tag; 436 struct pci_child *c; 437 438 d = device_locator(child, PCICF_DEV); 439 f = device_locator(child, PCICF_FUNCTION); 440 441 c = &sc->PCI_SC_DEVICESC(d, f); 442 443 KASSERT(c->c_dev == child); 444 445 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 446 if (c->c_psok) 447 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 448 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 449 c->c_dev = NULL; 450 } 451 452 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 453 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 454 DVF_DETACH_SHUTDOWN); 455 456 int 457 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 458 int *offset, pcireg_t *value) 459 { 460 pcireg_t reg; 461 unsigned int ofs; 462 463 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 464 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 465 return 0; 466 467 /* Determine the Capability List Pointer register to start with. */ 468 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 469 switch (PCI_HDRTYPE_TYPE(reg)) { 470 case 0: /* standard device header */ 471 case 1: /* PCI-PCI bridge header */ 472 ofs = PCI_CAPLISTPTR_REG; 473 break; 474 case 2: /* PCI-CardBus Bridge header */ 475 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 476 break; 477 default: 478 return 0; 479 } 480 481 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 482 while (ofs != 0) { 483 if ((ofs & 3) || (ofs < 0x40)) { 484 int bus, device, function; 485 486 pci_decompose_tag(pc, tag, &bus, &device, &function); 487 488 printf("Skipping broken PCI header on %d:%d:%d\n", 489 bus, device, function); 490 break; 491 } 492 reg = pci_conf_read(pc, tag, ofs); 493 if (PCI_CAPLIST_CAP(reg) == capid) { 494 if (offset) 495 *offset = ofs; 496 if (value) 497 *value = reg; 498 return 1; 499 } 500 ofs = PCI_CAPLIST_NEXT(reg); 501 } 502 503 return 0; 504 } 505 506 int 507 pci_find_device(struct pci_attach_args *pa, 508 int (*match)(const struct pci_attach_args *)) 509 { 510 extern struct cfdriver pci_cd; 511 device_t pcidev; 512 int i; 513 static const int wildcard[2] = { 514 PCICF_DEV_DEFAULT, 515 PCICF_FUNCTION_DEFAULT 516 }; 517 518 for (i = 0; i < pci_cd.cd_ndevs; i++) { 519 pcidev = device_lookup(&pci_cd, i); 520 if (pcidev != NULL && 521 pci_enumerate_bus(device_private(pcidev), wildcard, 522 match, pa) != 0) 523 return 1; 524 } 525 return 0; 526 } 527 528 #ifndef PCI_MACHDEP_ENUMERATE_BUS 529 /* 530 * Generic PCI bus enumeration routine. Used unless machine-dependent 531 * code needs to provide something else. 532 */ 533 int 534 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 535 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 536 { 537 pci_chipset_tag_t pc = sc->sc_pc; 538 int device, function, nfunctions, ret; 539 const struct pci_quirkdata *qd; 540 pcireg_t id, bhlcr; 541 pcitag_t tag; 542 #ifdef __PCI_BUS_DEVORDER 543 char devs[32]; 544 int i; 545 #endif 546 547 #ifdef __PCI_BUS_DEVORDER 548 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 549 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 550 #else 551 for (device = 0; device < sc->sc_maxndevs; device++) 552 #endif 553 { 554 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 555 (locators[PCICF_DEV] != device)) 556 continue; 557 558 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 559 560 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 561 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 562 continue; 563 564 id = pci_conf_read(pc, tag, PCI_ID_REG); 565 566 /* Invalid vendor ID value? */ 567 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 568 continue; 569 /* XXX Not invalid, but we've done this ~forever. */ 570 if (PCI_VENDOR(id) == 0) 571 continue; 572 573 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 574 575 if (qd != NULL && 576 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 577 nfunctions = 8; 578 else if (qd != NULL && 579 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 580 nfunctions = 1; 581 else 582 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 583 584 for (function = 0; function < nfunctions; function++) { 585 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 586 && (locators[PCICF_FUNCTION] != function)) 587 continue; 588 589 if (qd != NULL && 590 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 591 continue; 592 tag = pci_make_tag(pc, sc->sc_bus, device, function); 593 ret = pci_probe_device(sc, tag, match, pap); 594 if (match != NULL && ret != 0) 595 return ret; 596 } 597 } 598 return 0; 599 } 600 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 601 602 603 /* 604 * Vital Product Data (PCI 2.2) 605 */ 606 607 int 608 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 609 pcireg_t *data) 610 { 611 uint32_t reg; 612 int ofs, i, j; 613 614 KASSERT(data != NULL); 615 KASSERT((offset + count) < 0x7fff); 616 617 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 618 return 1; 619 620 for (i = 0; i < count; offset += sizeof(*data), i++) { 621 reg &= 0x0000ffff; 622 reg &= ~PCI_VPD_OPFLAG; 623 reg |= PCI_VPD_ADDRESS(offset); 624 pci_conf_write(pc, tag, ofs, reg); 625 626 /* 627 * PCI 2.2 does not specify how long we should poll 628 * for completion nor whether the operation can fail. 629 */ 630 j = 0; 631 do { 632 if (j++ == 20) 633 return 1; 634 delay(4); 635 reg = pci_conf_read(pc, tag, ofs); 636 } while ((reg & PCI_VPD_OPFLAG) == 0); 637 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 638 } 639 640 return 0; 641 } 642 643 int 644 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 645 pcireg_t *data) 646 { 647 pcireg_t reg; 648 int ofs, i, j; 649 650 KASSERT(data != NULL); 651 KASSERT((offset + count) < 0x7fff); 652 653 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 654 return 1; 655 656 for (i = 0; i < count; offset += sizeof(*data), i++) { 657 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 658 659 reg &= 0x0000ffff; 660 reg |= PCI_VPD_OPFLAG; 661 reg |= PCI_VPD_ADDRESS(offset); 662 pci_conf_write(pc, tag, ofs, reg); 663 664 /* 665 * PCI 2.2 does not specify how long we should poll 666 * for completion nor whether the operation can fail. 667 */ 668 j = 0; 669 do { 670 if (j++ == 20) 671 return 1; 672 delay(1); 673 reg = pci_conf_read(pc, tag, ofs); 674 } while (reg & PCI_VPD_OPFLAG); 675 } 676 677 return 0; 678 } 679 680 int 681 pci_dma64_available(const struct pci_attach_args *pa) 682 { 683 #ifdef _PCI_HAVE_DMA64 684 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 685 return 1; 686 #endif 687 return 0; 688 } 689 690 void 691 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 692 struct pci_conf_state *pcs) 693 { 694 int off; 695 696 for (off = 0; off < 16; off++) 697 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 698 699 return; 700 } 701 702 void 703 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 704 struct pci_conf_state *pcs) 705 { 706 int off; 707 pcireg_t val; 708 709 for (off = 15; off >= 0; off--) { 710 val = pci_conf_read(pc, tag, (off * 4)); 711 if (val != pcs->reg[off]) 712 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 713 } 714 715 return; 716 } 717 718 /* 719 * Power Management Capability (Rev 2.2) 720 */ 721 static int 722 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 723 int offset) 724 { 725 pcireg_t value, now; 726 727 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 728 now = value & PCI_PMCSR_STATE_MASK; 729 switch (now) { 730 case PCI_PMCSR_STATE_D0: 731 case PCI_PMCSR_STATE_D1: 732 case PCI_PMCSR_STATE_D2: 733 case PCI_PMCSR_STATE_D3: 734 *state = now; 735 return 0; 736 default: 737 return EINVAL; 738 } 739 } 740 741 int 742 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 743 { 744 int offset; 745 pcireg_t value; 746 747 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 748 return EOPNOTSUPP; 749 750 return pci_get_powerstate_int(pc, tag, state, offset); 751 } 752 753 static int 754 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 755 int offset, pcireg_t cap_reg) 756 { 757 pcireg_t value, cap, now; 758 759 cap = cap_reg >> PCI_PMCR_SHIFT; 760 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 761 now = value & PCI_PMCSR_STATE_MASK; 762 value &= ~PCI_PMCSR_STATE_MASK; 763 764 if (now == state) 765 return 0; 766 switch (state) { 767 case PCI_PMCSR_STATE_D0: 768 break; 769 case PCI_PMCSR_STATE_D1: 770 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 771 printf("invalid transition from %d to D1\n", (int)now); 772 return EINVAL; 773 } 774 if (!(cap & PCI_PMCR_D1SUPP)) { 775 printf("D1 not supported\n"); 776 return EOPNOTSUPP; 777 } 778 break; 779 case PCI_PMCSR_STATE_D2: 780 if (now == PCI_PMCSR_STATE_D3) { 781 printf("invalid transition from %d to D2\n", (int)now); 782 return EINVAL; 783 } 784 if (!(cap & PCI_PMCR_D2SUPP)) { 785 printf("D2 not supported\n"); 786 return EOPNOTSUPP; 787 } 788 break; 789 case PCI_PMCSR_STATE_D3: 790 break; 791 default: 792 return EINVAL; 793 } 794 value |= state; 795 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 796 /* delay according to pcipm1.2, ch. 5.6.1 */ 797 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 798 DELAY(10000); 799 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 800 DELAY(200); 801 802 return 0; 803 } 804 805 int 806 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 807 { 808 int offset; 809 pcireg_t value; 810 811 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 812 printf("pci_set_powerstate not supported\n"); 813 return EOPNOTSUPP; 814 } 815 816 return pci_set_powerstate_int(pc, tag, state, offset, value); 817 } 818 819 int 820 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 821 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 822 { 823 pcireg_t pmode; 824 int error; 825 826 if ((error = pci_get_powerstate(pc, tag, &pmode))) 827 return error; 828 829 switch (pmode) { 830 case PCI_PMCSR_STATE_D0: 831 break; 832 case PCI_PMCSR_STATE_D3: 833 if (wakefun == NULL) { 834 /* 835 * The card has lost all configuration data in 836 * this state, so punt. 837 */ 838 aprint_error_dev(dev, 839 "unable to wake up from power state D3\n"); 840 return EOPNOTSUPP; 841 } 842 /*FALLTHROUGH*/ 843 default: 844 if (wakefun) { 845 error = (*wakefun)(pc, tag, dev, pmode); 846 if (error) 847 return error; 848 } 849 aprint_normal_dev(dev, "waking up from power state D%d\n", 850 pmode); 851 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 852 return error; 853 } 854 return 0; 855 } 856 857 int 858 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 859 device_t dev, pcireg_t state) 860 { 861 return 0; 862 } 863 864 struct pci_child_power { 865 struct pci_conf_state p_pciconf; 866 pci_chipset_tag_t p_pc; 867 pcitag_t p_tag; 868 bool p_has_pm; 869 int p_pm_offset; 870 pcireg_t p_pm_cap; 871 pcireg_t p_class; 872 pcireg_t p_csr; 873 }; 874 875 static bool 876 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 877 { 878 struct pci_child_power *priv = device_pmf_bus_private(dv); 879 pcireg_t ocsr, csr; 880 881 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 882 883 if (!priv->p_has_pm) 884 return true; /* ??? hopefully handled by ACPI */ 885 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 886 return true; /* XXX */ 887 888 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 889 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 890 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 891 | PCI_COMMAND_MASTER_ENABLE); 892 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 893 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 894 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 895 pci_conf_write(priv->p_pc, priv->p_tag, 896 PCI_COMMAND_STATUS_REG, ocsr); 897 aprint_error_dev(dv, "unsupported state, continuing.\n"); 898 return false; 899 } 900 return true; 901 } 902 903 static bool 904 pci_child_resume(device_t dv, const pmf_qual_t *qual) 905 { 906 struct pci_child_power *priv = device_pmf_bus_private(dv); 907 908 if (priv->p_has_pm && 909 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 910 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 911 aprint_error_dev(dv, "unsupported state, continuing.\n"); 912 return false; 913 } 914 915 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 916 917 return true; 918 } 919 920 static bool 921 pci_child_shutdown(device_t dv, int how) 922 { 923 struct pci_child_power *priv = device_pmf_bus_private(dv); 924 pcireg_t csr; 925 926 /* restore original bus-mastering state */ 927 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 928 csr &= ~PCI_COMMAND_MASTER_ENABLE; 929 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 930 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 931 return true; 932 } 933 934 static void 935 pci_child_deregister(device_t dv) 936 { 937 struct pci_child_power *priv = device_pmf_bus_private(dv); 938 939 free(priv, M_DEVBUF); 940 } 941 942 static bool 943 pci_child_register(device_t child) 944 { 945 device_t self = device_parent(child); 946 struct pci_softc *sc = device_private(self); 947 struct pci_child_power *priv; 948 int device, function, off; 949 pcireg_t reg; 950 951 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 952 953 device = device_locator(child, PCICF_DEV); 954 function = device_locator(child, PCICF_FUNCTION); 955 956 priv->p_pc = sc->sc_pc; 957 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 958 function); 959 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 960 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 961 PCI_COMMAND_STATUS_REG); 962 963 if (pci_get_capability(priv->p_pc, priv->p_tag, 964 PCI_CAP_PWRMGMT, &off, ®)) { 965 priv->p_has_pm = true; 966 priv->p_pm_offset = off; 967 priv->p_pm_cap = reg; 968 } else { 969 priv->p_has_pm = false; 970 priv->p_pm_offset = -1; 971 } 972 973 device_pmf_bus_register(child, priv, pci_child_suspend, 974 pci_child_resume, pci_child_shutdown, pci_child_deregister); 975 976 return true; 977 } 978
Indexes created Sun Sep 21 20:09:37 GMT 2025