pci.c revision 1.142.12.1
1 /* $NetBSD: pci.c,v 1.142.12.1 2012/09/12 06:15:32 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.142.12.1 2012/09/12 06:15:32 tls Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/module.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <net/if.h> 54 55 #include "locators.h" 56 57 static bool pci_child_register(device_t); 58 59 #ifdef PCI_CONFIG_DUMP 60 int pci_config_dump = 1; 61 #else 62 int pci_config_dump = 0; 63 #endif 64 65 int pciprint(void *, const char *); 66 67 #ifdef PCI_MACHDEP_ENUMERATE_BUS 68 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 69 #else 70 int pci_enumerate_bus(struct pci_softc *, const int *, 71 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 /* Clamp the maximum transfer size. The hook may clamp it further. */ 146 self->dv_maxphys = MIN(parent->dv_maxphys, INT_MAX); 147 148 sc->sc_dev = self; 149 150 pci_attach_hook(parent, self, pba); 151 152 aprint_naive("\n"); 153 aprint_normal("\n"); 154 155 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 156 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 157 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 158 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 159 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 160 161 if (io_enabled == 0 && mem_enabled == 0) { 162 aprint_error_dev(self, "no spaces enabled!\n"); 163 goto fail; 164 } 165 166 #define PRINT(str) \ 167 do { \ 168 aprint_verbose("%s%s", sep, str); \ 169 sep = ", "; \ 170 } while (/*CONSTCOND*/0) 171 172 aprint_verbose_dev(self, ""); 173 174 if (io_enabled) 175 PRINT("i/o space"); 176 if (mem_enabled) 177 PRINT("memory space"); 178 aprint_verbose(" enabled"); 179 180 if (mrl_enabled || mrm_enabled || mwi_enabled) { 181 if (mrl_enabled) 182 PRINT("rd/line"); 183 if (mrm_enabled) 184 PRINT("rd/mult"); 185 if (mwi_enabled) 186 PRINT("wr/inv"); 187 aprint_verbose(" ok"); 188 } 189 190 aprint_verbose("\n"); 191 192 #undef PRINT 193 194 sc->sc_iot = pba->pba_iot; 195 sc->sc_memt = pba->pba_memt; 196 sc->sc_dmat = pba->pba_dmat; 197 sc->sc_dmat64 = pba->pba_dmat64; 198 sc->sc_pc = pba->pba_pc; 199 sc->sc_bus = pba->pba_bus; 200 sc->sc_bridgetag = pba->pba_bridgetag; 201 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 202 sc->sc_intrswiz = pba->pba_intrswiz; 203 sc->sc_intrtag = pba->pba_intrtag; 204 sc->sc_flags = pba->pba_flags; 205 206 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 207 208 pcirescan(sc->sc_dev, "pci", wildcard); 209 210 fail: 211 if (!pmf_device_register(self, NULL, NULL)) 212 aprint_error_dev(self, "couldn't establish power handler\n"); 213 } 214 215 int 216 pcidetach(device_t self, int flags) 217 { 218 int rc; 219 220 if ((rc = config_detach_children(self, flags)) != 0) 221 return rc; 222 pmf_device_deregister(self); 223 return 0; 224 } 225 226 int 227 pciprint(void *aux, const char *pnp) 228 { 229 struct pci_attach_args *pa = aux; 230 char devinfo[256]; 231 const struct pci_quirkdata *qd; 232 233 if (pnp) { 234 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 235 aprint_normal("%s at %s", devinfo, pnp); 236 } 237 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 238 if (pci_config_dump) { 239 printf(": "); 240 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 241 if (!pnp) 242 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 243 printf("%s at %s", devinfo, pnp ? pnp : "?"); 244 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 245 #ifdef __i386__ 246 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 247 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #else 250 printf("intrswiz %#lx, intrpin %#lx", 251 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 252 #endif 253 printf(", i/o %s, mem %s,", 254 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 255 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 256 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 257 PCI_PRODUCT(pa->pa_id)); 258 if (qd == NULL) { 259 printf(" no quirks"); 260 } else { 261 snprintb(devinfo, sizeof (devinfo), 262 "\002\001multifn\002singlefn\003skipfunc0" 263 "\004skipfunc1\005skipfunc2\006skipfunc3" 264 "\007skipfunc4\010skipfunc5\011skipfunc6" 265 "\012skipfunc7", qd->quirks); 266 printf(" quirks %s", devinfo); 267 } 268 printf(")"); 269 } 270 return UNCONF; 271 } 272 273 int 274 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 275 int (*match)(const struct pci_attach_args *), 276 struct pci_attach_args *pap) 277 { 278 pci_chipset_tag_t pc = sc->sc_pc; 279 struct pci_attach_args pa; 280 pcireg_t id, csr, class, intr, bhlcr, bar, endbar; 281 int ret, pin, bus, device, function, i, width; 282 int locs[PCICF_NLOCS]; 283 284 pci_decompose_tag(pc, tag, &bus, &device, &function); 285 286 /* a driver already attached? */ 287 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 288 return 0; 289 290 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 291 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 292 return 0; 293 294 id = pci_conf_read(pc, tag, PCI_ID_REG); 295 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 296 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 297 298 /* Invalid vendor ID value? */ 299 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 300 return 0; 301 /* XXX Not invalid, but we've done this ~forever. */ 302 if (PCI_VENDOR(id) == 0) 303 return 0; 304 305 /* Collect memory range info */ 306 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 307 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 308 i = 0; 309 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 310 case PCI_HDRTYPE_PPB: 311 endbar = PCI_MAPREG_PPB_END; 312 break; 313 case PCI_HDRTYPE_PCB: 314 endbar = PCI_MAPREG_PCB_END; 315 break; 316 default: 317 endbar = PCI_MAPREG_END; 318 break; 319 } 320 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 321 struct pci_range *r; 322 pcireg_t type; 323 324 width = 4; 325 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 326 continue; 327 328 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 329 if (PCI_MAPREG_MEM_TYPE(type) == 330 PCI_MAPREG_MEM_TYPE_64BIT) 331 width = 8; 332 333 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 334 if (pci_mapreg_info(pc, tag, bar, type, 335 &r->r_offset, &r->r_size, &r->r_flags) != 0) 336 break; 337 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 338 && (r->r_size == 0x1000000)) { 339 struct pci_range *nr; 340 /* 341 * this has to be a mach64 342 * split things up so each half-aperture can 343 * be mapped PREFETCHABLE except the last page 344 * which may contain registers 345 */ 346 r->r_size = 0x7ff000; 347 r->r_flags = BUS_SPACE_MAP_LINEAR | 348 BUS_SPACE_MAP_PREFETCHABLE; 349 nr = &sc->PCI_SC_DEVICESC(device, 350 function).c_range[i++]; 351 nr->r_offset = r->r_offset + 0x800000; 352 nr->r_size = 0x7ff000; 353 nr->r_flags = BUS_SPACE_MAP_LINEAR | 354 BUS_SPACE_MAP_PREFETCHABLE; 355 } 356 357 } 358 } 359 360 pa.pa_iot = sc->sc_iot; 361 pa.pa_memt = sc->sc_memt; 362 pa.pa_dmat = sc->sc_dmat; 363 pa.pa_dmat64 = sc->sc_dmat64; 364 pa.pa_pc = pc; 365 pa.pa_bus = bus; 366 pa.pa_device = device; 367 pa.pa_function = function; 368 pa.pa_tag = tag; 369 pa.pa_id = id; 370 pa.pa_class = class; 371 372 /* 373 * Set up memory, I/O enable, and PCI command flags 374 * as appropriate. 375 */ 376 pa.pa_flags = sc->sc_flags; 377 378 /* 379 * If the cache line size is not configured, then 380 * clear the MRL/MRM/MWI command-ok flags. 381 */ 382 if (PCI_CACHELINE(bhlcr) == 0) { 383 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 384 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 385 } 386 387 if (sc->sc_bridgetag == NULL) { 388 pa.pa_intrswiz = 0; 389 pa.pa_intrtag = tag; 390 } else { 391 pa.pa_intrswiz = sc->sc_intrswiz + device; 392 pa.pa_intrtag = sc->sc_intrtag; 393 } 394 395 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 396 397 pin = PCI_INTERRUPT_PIN(intr); 398 pa.pa_rawintrpin = pin; 399 if (pin == PCI_INTERRUPT_PIN_NONE) { 400 /* no interrupt */ 401 pa.pa_intrpin = 0; 402 } else { 403 /* 404 * swizzle it based on the number of busses we're 405 * behind and our device number. 406 */ 407 pa.pa_intrpin = /* XXX */ 408 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 409 } 410 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 411 412 if (match != NULL) { 413 ret = (*match)(&pa); 414 if (ret != 0 && pap != NULL) 415 *pap = pa; 416 } else { 417 struct pci_child *c; 418 locs[PCICF_DEV] = device; 419 locs[PCICF_FUNCTION] = function; 420 421 c = &sc->PCI_SC_DEVICESC(device, function); 422 pci_conf_capture(pc, tag, &c->c_conf); 423 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 424 c->c_psok = true; 425 else 426 c->c_psok = false; 427 428 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 429 pciprint, config_stdsubmatch); 430 431 ret = (c->c_dev != NULL); 432 } 433 434 return ret; 435 } 436 437 void 438 pcidevdetached(device_t self, device_t child) 439 { 440 struct pci_softc *sc = device_private(self); 441 int d, f; 442 pcitag_t tag; 443 struct pci_child *c; 444 445 d = device_locator(child, PCICF_DEV); 446 f = device_locator(child, PCICF_FUNCTION); 447 448 c = &sc->PCI_SC_DEVICESC(d, f); 449 450 KASSERT(c->c_dev == child); 451 452 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 453 if (c->c_psok) 454 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 455 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 456 c->c_dev = NULL; 457 } 458 459 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 460 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 461 DVF_DETACH_SHUTDOWN); 462 463 int 464 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 465 int *offset, pcireg_t *value) 466 { 467 pcireg_t reg; 468 unsigned int ofs; 469 470 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 471 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 472 return 0; 473 474 /* Determine the Capability List Pointer register to start with. */ 475 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 476 switch (PCI_HDRTYPE_TYPE(reg)) { 477 case 0: /* standard device header */ 478 case 1: /* PCI-PCI bridge header */ 479 ofs = PCI_CAPLISTPTR_REG; 480 break; 481 case 2: /* PCI-CardBus Bridge header */ 482 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 483 break; 484 default: 485 return 0; 486 } 487 488 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 489 while (ofs != 0) { 490 if ((ofs & 3) || (ofs < 0x40)) { 491 int bus, device, function; 492 493 pci_decompose_tag(pc, tag, &bus, &device, &function); 494 495 printf("Skipping broken PCI header on %d:%d:%d\n", 496 bus, device, function); 497 break; 498 } 499 reg = pci_conf_read(pc, tag, ofs); 500 if (PCI_CAPLIST_CAP(reg) == capid) { 501 if (offset) 502 *offset = ofs; 503 if (value) 504 *value = reg; 505 return 1; 506 } 507 ofs = PCI_CAPLIST_NEXT(reg); 508 } 509 510 return 0; 511 } 512 513 int 514 pci_find_device(struct pci_attach_args *pa, 515 int (*match)(const struct pci_attach_args *)) 516 { 517 extern struct cfdriver pci_cd; 518 device_t pcidev; 519 int i; 520 static const int wildcard[2] = { 521 PCICF_DEV_DEFAULT, 522 PCICF_FUNCTION_DEFAULT 523 }; 524 525 for (i = 0; i < pci_cd.cd_ndevs; i++) { 526 pcidev = device_lookup(&pci_cd, i); 527 if (pcidev != NULL && 528 pci_enumerate_bus(device_private(pcidev), wildcard, 529 match, pa) != 0) 530 return 1; 531 } 532 return 0; 533 } 534 535 #ifndef PCI_MACHDEP_ENUMERATE_BUS 536 /* 537 * Generic PCI bus enumeration routine. Used unless machine-dependent 538 * code needs to provide something else. 539 */ 540 int 541 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 542 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 543 { 544 pci_chipset_tag_t pc = sc->sc_pc; 545 int device, function, nfunctions, ret; 546 const struct pci_quirkdata *qd; 547 pcireg_t id, bhlcr; 548 pcitag_t tag; 549 uint8_t devs[32]; 550 int i, n; 551 552 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 553 for (i = 0; i < n; i++) { 554 device = devs[i]; 555 556 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 557 (locators[PCICF_DEV] != device)) 558 continue; 559 560 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 561 562 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 563 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 564 continue; 565 566 id = pci_conf_read(pc, tag, PCI_ID_REG); 567 568 /* Invalid vendor ID value? */ 569 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 570 continue; 571 /* XXX Not invalid, but we've done this ~forever. */ 572 if (PCI_VENDOR(id) == 0) 573 continue; 574 575 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 576 577 if (qd != NULL && 578 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 579 nfunctions = 8; 580 else if (qd != NULL && 581 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 582 nfunctions = 1; 583 else 584 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 585 586 for (function = 0; function < nfunctions; function++) { 587 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 588 && (locators[PCICF_FUNCTION] != function)) 589 continue; 590 591 if (qd != NULL && 592 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 593 continue; 594 tag = pci_make_tag(pc, sc->sc_bus, device, function); 595 ret = pci_probe_device(sc, tag, match, pap); 596 if (match != NULL && ret != 0) 597 return ret; 598 } 599 } 600 return 0; 601 } 602 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 603 604 605 /* 606 * Vital Product Data (PCI 2.2) 607 */ 608 609 int 610 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 611 pcireg_t *data) 612 { 613 uint32_t reg; 614 int ofs, i, j; 615 616 KASSERT(data != NULL); 617 KASSERT((offset + count) < 0x7fff); 618 619 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 620 return 1; 621 622 for (i = 0; i < count; offset += sizeof(*data), i++) { 623 reg &= 0x0000ffff; 624 reg &= ~PCI_VPD_OPFLAG; 625 reg |= PCI_VPD_ADDRESS(offset); 626 pci_conf_write(pc, tag, ofs, reg); 627 628 /* 629 * PCI 2.2 does not specify how long we should poll 630 * for completion nor whether the operation can fail. 631 */ 632 j = 0; 633 do { 634 if (j++ == 20) 635 return 1; 636 delay(4); 637 reg = pci_conf_read(pc, tag, ofs); 638 } while ((reg & PCI_VPD_OPFLAG) == 0); 639 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 640 } 641 642 return 0; 643 } 644 645 int 646 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 647 pcireg_t *data) 648 { 649 pcireg_t reg; 650 int ofs, i, j; 651 652 KASSERT(data != NULL); 653 KASSERT((offset + count) < 0x7fff); 654 655 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 656 return 1; 657 658 for (i = 0; i < count; offset += sizeof(*data), i++) { 659 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 660 661 reg &= 0x0000ffff; 662 reg |= PCI_VPD_OPFLAG; 663 reg |= PCI_VPD_ADDRESS(offset); 664 pci_conf_write(pc, tag, ofs, reg); 665 666 /* 667 * PCI 2.2 does not specify how long we should poll 668 * for completion nor whether the operation can fail. 669 */ 670 j = 0; 671 do { 672 if (j++ == 20) 673 return 1; 674 delay(1); 675 reg = pci_conf_read(pc, tag, ofs); 676 } while (reg & PCI_VPD_OPFLAG); 677 } 678 679 return 0; 680 } 681 682 int 683 pci_dma64_available(const struct pci_attach_args *pa) 684 { 685 #ifdef _PCI_HAVE_DMA64 686 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 687 return 1; 688 #endif 689 return 0; 690 } 691 692 void 693 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 694 struct pci_conf_state *pcs) 695 { 696 int off; 697 698 for (off = 0; off < 16; off++) 699 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 700 701 return; 702 } 703 704 void 705 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 706 struct pci_conf_state *pcs) 707 { 708 int off; 709 pcireg_t val; 710 711 for (off = 15; off >= 0; off--) { 712 val = pci_conf_read(pc, tag, (off * 4)); 713 if (val != pcs->reg[off]) 714 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 715 } 716 717 return; 718 } 719 720 /* 721 * Power Management Capability (Rev 2.2) 722 */ 723 static int 724 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 725 int offset) 726 { 727 pcireg_t value, now; 728 729 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 730 now = value & PCI_PMCSR_STATE_MASK; 731 switch (now) { 732 case PCI_PMCSR_STATE_D0: 733 case PCI_PMCSR_STATE_D1: 734 case PCI_PMCSR_STATE_D2: 735 case PCI_PMCSR_STATE_D3: 736 *state = now; 737 return 0; 738 default: 739 return EINVAL; 740 } 741 } 742 743 int 744 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 745 { 746 int offset; 747 pcireg_t value; 748 749 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 750 return EOPNOTSUPP; 751 752 return pci_get_powerstate_int(pc, tag, state, offset); 753 } 754 755 static int 756 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 757 int offset, pcireg_t cap_reg) 758 { 759 pcireg_t value, cap, now; 760 761 cap = cap_reg >> PCI_PMCR_SHIFT; 762 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 763 now = value & PCI_PMCSR_STATE_MASK; 764 value &= ~PCI_PMCSR_STATE_MASK; 765 766 if (now == state) 767 return 0; 768 switch (state) { 769 case PCI_PMCSR_STATE_D0: 770 break; 771 case PCI_PMCSR_STATE_D1: 772 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 773 printf("invalid transition from %d to D1\n", (int)now); 774 return EINVAL; 775 } 776 if (!(cap & PCI_PMCR_D1SUPP)) { 777 printf("D1 not supported\n"); 778 return EOPNOTSUPP; 779 } 780 break; 781 case PCI_PMCSR_STATE_D2: 782 if (now == PCI_PMCSR_STATE_D3) { 783 printf("invalid transition from %d to D2\n", (int)now); 784 return EINVAL; 785 } 786 if (!(cap & PCI_PMCR_D2SUPP)) { 787 printf("D2 not supported\n"); 788 return EOPNOTSUPP; 789 } 790 break; 791 case PCI_PMCSR_STATE_D3: 792 break; 793 default: 794 return EINVAL; 795 } 796 value |= state; 797 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 798 /* delay according to pcipm1.2, ch. 5.6.1 */ 799 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 800 DELAY(10000); 801 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 802 DELAY(200); 803 804 return 0; 805 } 806 807 int 808 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 809 { 810 int offset; 811 pcireg_t value; 812 813 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 814 printf("pci_set_powerstate not supported\n"); 815 return EOPNOTSUPP; 816 } 817 818 return pci_set_powerstate_int(pc, tag, state, offset, value); 819 } 820 821 int 822 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 823 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 824 { 825 pcireg_t pmode; 826 int error; 827 828 if ((error = pci_get_powerstate(pc, tag, &pmode))) 829 return error; 830 831 switch (pmode) { 832 case PCI_PMCSR_STATE_D0: 833 break; 834 case PCI_PMCSR_STATE_D3: 835 if (wakefun == NULL) { 836 /* 837 * The card has lost all configuration data in 838 * this state, so punt. 839 */ 840 aprint_error_dev(dev, 841 "unable to wake up from power state D3\n"); 842 return EOPNOTSUPP; 843 } 844 /*FALLTHROUGH*/ 845 default: 846 if (wakefun) { 847 error = (*wakefun)(pc, tag, dev, pmode); 848 if (error) 849 return error; 850 } 851 aprint_normal_dev(dev, "waking up from power state D%d\n", 852 pmode); 853 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 854 return error; 855 } 856 return 0; 857 } 858 859 int 860 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 861 device_t dev, pcireg_t state) 862 { 863 return 0; 864 } 865 866 struct pci_child_power { 867 struct pci_conf_state p_pciconf; 868 pci_chipset_tag_t p_pc; 869 pcitag_t p_tag; 870 bool p_has_pm; 871 int p_pm_offset; 872 pcireg_t p_pm_cap; 873 pcireg_t p_class; 874 pcireg_t p_csr; 875 }; 876 877 static bool 878 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 879 { 880 struct pci_child_power *priv = device_pmf_bus_private(dv); 881 pcireg_t ocsr, csr; 882 883 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 884 885 if (!priv->p_has_pm) 886 return true; /* ??? hopefully handled by ACPI */ 887 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 888 return true; /* XXX */ 889 890 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 891 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 892 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 893 | PCI_COMMAND_MASTER_ENABLE); 894 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 895 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 896 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 897 pci_conf_write(priv->p_pc, priv->p_tag, 898 PCI_COMMAND_STATUS_REG, ocsr); 899 aprint_error_dev(dv, "unsupported state, continuing.\n"); 900 return false; 901 } 902 return true; 903 } 904 905 static bool 906 pci_child_resume(device_t dv, const pmf_qual_t *qual) 907 { 908 struct pci_child_power *priv = device_pmf_bus_private(dv); 909 910 if (priv->p_has_pm && 911 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 912 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 913 aprint_error_dev(dv, "unsupported state, continuing.\n"); 914 return false; 915 } 916 917 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 918 919 return true; 920 } 921 922 static bool 923 pci_child_shutdown(device_t dv, int how) 924 { 925 struct pci_child_power *priv = device_pmf_bus_private(dv); 926 pcireg_t csr; 927 928 /* restore original bus-mastering state */ 929 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 930 csr &= ~PCI_COMMAND_MASTER_ENABLE; 931 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 932 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 933 return true; 934 } 935 936 static void 937 pci_child_deregister(device_t dv) 938 { 939 struct pci_child_power *priv = device_pmf_bus_private(dv); 940 941 free(priv, M_DEVBUF); 942 } 943 944 static bool 945 pci_child_register(device_t child) 946 { 947 device_t self = device_parent(child); 948 struct pci_softc *sc = device_private(self); 949 struct pci_child_power *priv; 950 int device, function, off; 951 pcireg_t reg; 952 953 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 954 955 device = device_locator(child, PCICF_DEV); 956 function = device_locator(child, PCICF_FUNCTION); 957 958 priv->p_pc = sc->sc_pc; 959 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 960 function); 961 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 962 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 963 PCI_COMMAND_STATUS_REG); 964 965 if (pci_get_capability(priv->p_pc, priv->p_tag, 966 PCI_CAP_PWRMGMT, &off, ®)) { 967 priv->p_has_pm = true; 968 priv->p_pm_offset = off; 969 priv->p_pm_cap = reg; 970 } else { 971 priv->p_has_pm = false; 972 priv->p_pm_offset = -1; 973 } 974 975 device_pmf_bus_register(child, priv, pci_child_suspend, 976 pci_child_resume, pci_child_shutdown, pci_child_deregister); 977 978 return true; 979 } 980 981 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 982 983 static int 984 pci_modcmd(modcmd_t cmd, void *priv) 985 { 986 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 987 return 0; 988 return ENOTTY; 989 } 990
Indexes created Tue Sep 30 11:09:46 GMT 2025