pci.c revision 1.142.12.4
1 /* $NetBSD: pci.c,v 1.142.12.4 2017/12/03 11:37:08 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.142.12.4 2017/12/03 11:37:08 jdolecek Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <net/if.h> 57 58 #include "locators.h" 59 60 static bool pci_child_register(device_t); 61 62 #ifdef PCI_CONFIG_DUMP 63 int pci_config_dump = 1; 64 #else 65 int pci_config_dump = 0; 66 #endif 67 68 int pciprint(void *, const char *); 69 70 #ifdef PCI_MACHDEP_ENUMERATE_BUS 71 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 /* Clamp the maximum transfer size. The hook may clamp it further. */ 146 self->dv_maxphys = MIN(parent->dv_maxphys, INT_MAX); 147 148 sc->sc_dev = self; 149 150 pci_attach_hook(parent, self, pba); 151 152 aprint_naive("\n"); 153 aprint_normal("\n"); 154 155 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 156 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 157 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 158 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 159 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 160 161 if (io_enabled == 0 && mem_enabled == 0) { 162 aprint_error_dev(self, "no spaces enabled!\n"); 163 goto fail; 164 } 165 166 #define PRINT(str) \ 167 do { \ 168 aprint_verbose("%s%s", sep, str); \ 169 sep = ", "; \ 170 } while (/*CONSTCOND*/0) 171 172 aprint_verbose_dev(self, ""); 173 174 if (io_enabled) 175 PRINT("i/o space"); 176 if (mem_enabled) 177 PRINT("memory space"); 178 aprint_verbose(" enabled"); 179 180 if (mrl_enabled || mrm_enabled || mwi_enabled) { 181 if (mrl_enabled) 182 PRINT("rd/line"); 183 if (mrm_enabled) 184 PRINT("rd/mult"); 185 if (mwi_enabled) 186 PRINT("wr/inv"); 187 aprint_verbose(" ok"); 188 } 189 190 aprint_verbose("\n"); 191 192 #undef PRINT 193 194 sc->sc_iot = pba->pba_iot; 195 sc->sc_memt = pba->pba_memt; 196 sc->sc_dmat = pba->pba_dmat; 197 sc->sc_dmat64 = pba->pba_dmat64; 198 sc->sc_pc = pba->pba_pc; 199 sc->sc_bus = pba->pba_bus; 200 sc->sc_bridgetag = pba->pba_bridgetag; 201 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 202 sc->sc_intrswiz = pba->pba_intrswiz; 203 sc->sc_intrtag = pba->pba_intrtag; 204 sc->sc_flags = pba->pba_flags; 205 206 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 207 208 pcirescan(sc->sc_dev, "pci", wildcard); 209 210 fail: 211 if (!pmf_device_register(self, NULL, NULL)) 212 aprint_error_dev(self, "couldn't establish power handler\n"); 213 } 214 215 int 216 pcidetach(device_t self, int flags) 217 { 218 int rc; 219 220 if ((rc = config_detach_children(self, flags)) != 0) 221 return rc; 222 pmf_device_deregister(self); 223 return 0; 224 } 225 226 int 227 pciprint(void *aux, const char *pnp) 228 { 229 struct pci_attach_args *pa = aux; 230 char devinfo[256]; 231 const struct pci_quirkdata *qd; 232 233 if (pnp) { 234 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 235 aprint_normal("%s at %s", devinfo, pnp); 236 } 237 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 238 if (pci_config_dump) { 239 printf(": "); 240 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 241 if (!pnp) 242 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 243 printf("%s at %s", devinfo, pnp ? pnp : "?"); 244 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 245 #ifdef __i386__ 246 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 247 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #else 250 printf("intrswiz %#lx, intrpin %#lx", 251 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 252 #endif 253 printf(", i/o %s, mem %s,", 254 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 255 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 256 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 257 PCI_PRODUCT(pa->pa_id)); 258 if (qd == NULL) { 259 printf(" no quirks"); 260 } else { 261 snprintb(devinfo, sizeof (devinfo), 262 "\002\001multifn\002singlefn\003skipfunc0" 263 "\004skipfunc1\005skipfunc2\006skipfunc3" 264 "\007skipfunc4\010skipfunc5\011skipfunc6" 265 "\012skipfunc7", qd->quirks); 266 printf(" quirks %s", devinfo); 267 } 268 printf(")"); 269 } 270 return UNCONF; 271 } 272 273 int 274 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 275 int (*match)(const struct pci_attach_args *), 276 struct pci_attach_args *pap) 277 { 278 pci_chipset_tag_t pc = sc->sc_pc; 279 struct pci_attach_args pa; 280 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 281 #ifdef __HAVE_PCI_MSI_MSIX 282 pcireg_t cap; 283 int off; 284 #endif 285 int ret, pin, bus, device, function, i, width; 286 int locs[PCICF_NLOCS]; 287 288 pci_decompose_tag(pc, tag, &bus, &device, &function); 289 290 /* a driver already attached? */ 291 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 292 return 0; 293 294 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 295 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 296 return 0; 297 298 id = pci_conf_read(pc, tag, PCI_ID_REG); 299 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 300 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 301 302 /* Invalid vendor ID value? */ 303 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 304 return 0; 305 /* XXX Not invalid, but we've done this ~forever. */ 306 if (PCI_VENDOR(id) == 0) 307 return 0; 308 309 /* Collect memory range info */ 310 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 311 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 312 i = 0; 313 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 314 case PCI_HDRTYPE_PPB: 315 endbar = PCI_MAPREG_PPB_END; 316 break; 317 case PCI_HDRTYPE_PCB: 318 endbar = PCI_MAPREG_PCB_END; 319 break; 320 default: 321 endbar = PCI_MAPREG_END; 322 break; 323 } 324 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 325 struct pci_range *r; 326 pcireg_t type; 327 328 width = 4; 329 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 330 continue; 331 332 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 333 if (PCI_MAPREG_MEM_TYPE(type) == 334 PCI_MAPREG_MEM_TYPE_64BIT) 335 width = 8; 336 337 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 338 if (pci_mapreg_info(pc, tag, bar, type, 339 &r->r_offset, &r->r_size, &r->r_flags) != 0) 340 break; 341 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 342 && (r->r_size == 0x1000000)) { 343 struct pci_range *nr; 344 /* 345 * this has to be a mach64 346 * split things up so each half-aperture can 347 * be mapped PREFETCHABLE except the last page 348 * which may contain registers 349 */ 350 r->r_size = 0x7ff000; 351 r->r_flags = BUS_SPACE_MAP_LINEAR | 352 BUS_SPACE_MAP_PREFETCHABLE; 353 nr = &sc->PCI_SC_DEVICESC(device, 354 function).c_range[i++]; 355 nr->r_offset = r->r_offset + 0x800000; 356 nr->r_size = 0x7ff000; 357 nr->r_flags = BUS_SPACE_MAP_LINEAR | 358 BUS_SPACE_MAP_PREFETCHABLE; 359 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 360 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 361 (bar == 0x10)) { 362 r->r_flags = BUS_SPACE_MAP_LINEAR | 363 BUS_SPACE_MAP_PREFETCHABLE; 364 } 365 } 366 } 367 368 pa.pa_iot = sc->sc_iot; 369 pa.pa_memt = sc->sc_memt; 370 pa.pa_dmat = sc->sc_dmat; 371 pa.pa_dmat64 = sc->sc_dmat64; 372 pa.pa_pc = pc; 373 pa.pa_bus = bus; 374 pa.pa_device = device; 375 pa.pa_function = function; 376 pa.pa_tag = tag; 377 pa.pa_id = id; 378 pa.pa_class = pciclass; 379 380 /* 381 * Set up memory, I/O enable, and PCI command flags 382 * as appropriate. 383 */ 384 pa.pa_flags = sc->sc_flags; 385 386 /* 387 * If the cache line size is not configured, then 388 * clear the MRL/MRM/MWI command-ok flags. 389 */ 390 if (PCI_CACHELINE(bhlcr) == 0) { 391 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 392 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 393 } 394 395 if (sc->sc_bridgetag == NULL) { 396 pa.pa_intrswiz = 0; 397 pa.pa_intrtag = tag; 398 } else { 399 pa.pa_intrswiz = sc->sc_intrswiz + device; 400 pa.pa_intrtag = sc->sc_intrtag; 401 } 402 403 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 404 405 pin = PCI_INTERRUPT_PIN(intr); 406 pa.pa_rawintrpin = pin; 407 if (pin == PCI_INTERRUPT_PIN_NONE) { 408 /* no interrupt */ 409 pa.pa_intrpin = 0; 410 } else { 411 /* 412 * swizzle it based on the number of busses we're 413 * behind and our device number. 414 */ 415 pa.pa_intrpin = /* XXX */ 416 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 417 } 418 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 419 420 #ifdef __HAVE_PCI_MSI_MSIX 421 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 422 /* 423 * XXX Should we enable MSI mapping ourselves on 424 * systems that have it disabled? 425 */ 426 if (cap & PCI_HT_MSI_ENABLED) { 427 uint64_t addr; 428 if ((cap & PCI_HT_MSI_FIXED) == 0) { 429 addr = pci_conf_read(pc, tag, 430 off + PCI_HT_MSI_ADDR_LO); 431 addr |= (uint64_t)pci_conf_read(pc, tag, 432 off + PCI_HT_MSI_ADDR_HI) << 32; 433 } else 434 addr = PCI_HT_MSI_FIXED_ADDR; 435 436 /* 437 * XXX This will fail to enable MSI on systems 438 * that don't use the canonical address. 439 */ 440 if (addr == PCI_HT_MSI_FIXED_ADDR) { 441 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 442 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 443 } else 444 aprint_verbose_dev(sc->sc_dev, 445 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 446 } 447 } 448 #endif 449 450 if (match != NULL) { 451 ret = (*match)(&pa); 452 if (ret != 0 && pap != NULL) 453 *pap = pa; 454 } else { 455 struct pci_child *c; 456 locs[PCICF_DEV] = device; 457 locs[PCICF_FUNCTION] = function; 458 459 c = &sc->PCI_SC_DEVICESC(device, function); 460 pci_conf_capture(pc, tag, &c->c_conf); 461 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 462 c->c_psok = true; 463 else 464 c->c_psok = false; 465 466 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 467 pciprint, config_stdsubmatch); 468 469 ret = (c->c_dev != NULL); 470 } 471 472 return ret; 473 } 474 475 void 476 pcidevdetached(device_t self, device_t child) 477 { 478 struct pci_softc *sc = device_private(self); 479 int d, f; 480 pcitag_t tag; 481 struct pci_child *c; 482 483 d = device_locator(child, PCICF_DEV); 484 f = device_locator(child, PCICF_FUNCTION); 485 486 c = &sc->PCI_SC_DEVICESC(d, f); 487 488 KASSERT(c->c_dev == child); 489 490 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 491 if (c->c_psok) 492 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 493 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 494 c->c_dev = NULL; 495 } 496 497 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 498 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 499 DVF_DETACH_SHUTDOWN); 500 501 int 502 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 503 int *offset, pcireg_t *value) 504 { 505 pcireg_t reg; 506 unsigned int ofs; 507 508 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 509 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 510 return 0; 511 512 /* Determine the Capability List Pointer register to start with. */ 513 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 514 switch (PCI_HDRTYPE_TYPE(reg)) { 515 case 0: /* standard device header */ 516 case 1: /* PCI-PCI bridge header */ 517 ofs = PCI_CAPLISTPTR_REG; 518 break; 519 case 2: /* PCI-CardBus Bridge header */ 520 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 521 break; 522 default: 523 return 0; 524 } 525 526 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 527 while (ofs != 0) { 528 if ((ofs & 3) || (ofs < 0x40)) { 529 int bus, device, function; 530 531 pci_decompose_tag(pc, tag, &bus, &device, &function); 532 533 printf("Skipping broken PCI header on %d:%d:%d\n", 534 bus, device, function); 535 break; 536 } 537 reg = pci_conf_read(pc, tag, ofs); 538 if (PCI_CAPLIST_CAP(reg) == capid) { 539 if (offset) 540 *offset = ofs; 541 if (value) 542 *value = reg; 543 return 1; 544 } 545 ofs = PCI_CAPLIST_NEXT(reg); 546 } 547 548 return 0; 549 } 550 551 int 552 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 553 int *offset, pcireg_t *value) 554 { 555 pcireg_t reg; 556 unsigned int ofs; 557 558 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 559 return 0; 560 561 while (ofs != 0) { 562 #ifdef DIAGNOSTIC 563 if ((ofs & 3) || (ofs < 0x40)) 564 panic("pci_get_ht_capability"); 565 #endif 566 reg = pci_conf_read(pc, tag, ofs); 567 if (PCI_HT_CAP(reg) == capid) { 568 if (offset) 569 *offset = ofs; 570 if (value) 571 *value = reg; 572 return 1; 573 } 574 ofs = PCI_CAPLIST_NEXT(reg); 575 } 576 577 return 0; 578 } 579 580 /* 581 * return number of the devices's MSI vectors 582 * return 0 if the device does not support MSI 583 */ 584 int 585 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 586 { 587 pcireg_t reg; 588 uint32_t mmc; 589 int count, offset; 590 591 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 592 return 0; 593 594 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 595 mmc = PCI_MSI_CTL_MMC(reg); 596 count = 1 << mmc; 597 if (count > PCI_MSI_MAX_VECTORS) { 598 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 599 return 0; 600 } 601 602 return count; 603 } 604 605 /* 606 * return number of the devices's MSI-X vectors 607 * return 0 if the device does not support MSI-X 608 */ 609 int 610 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 611 { 612 pcireg_t reg; 613 int offset; 614 615 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 616 return 0; 617 618 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 619 620 return PCI_MSIX_CTL_TBLSIZE(reg); 621 } 622 623 int 624 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 625 int *offset, pcireg_t *value) 626 { 627 pcireg_t reg; 628 unsigned int ofs; 629 630 /* Only supported for PCI-express devices */ 631 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 632 return 0; 633 634 ofs = PCI_EXTCAPLIST_BASE; 635 reg = pci_conf_read(pc, tag, ofs); 636 if (reg == 0xffffffff || reg == 0) 637 return 0; 638 639 for (;;) { 640 #ifdef DIAGNOSTIC 641 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 642 panic("%s: invalid offset %u", __func__, ofs); 643 #endif 644 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 645 if (offset != NULL) 646 *offset = ofs; 647 if (value != NULL) 648 *value = reg; 649 return 1; 650 } 651 ofs = PCI_EXTCAPLIST_NEXT(reg); 652 if (ofs == 0) 653 break; 654 reg = pci_conf_read(pc, tag, ofs); 655 } 656 657 return 0; 658 } 659 660 int 661 pci_find_device(struct pci_attach_args *pa, 662 int (*match)(const struct pci_attach_args *)) 663 { 664 extern struct cfdriver pci_cd; 665 device_t pcidev; 666 int i; 667 static const int wildcard[2] = { 668 PCICF_DEV_DEFAULT, 669 PCICF_FUNCTION_DEFAULT 670 }; 671 672 for (i = 0; i < pci_cd.cd_ndevs; i++) { 673 pcidev = device_lookup(&pci_cd, i); 674 if (pcidev != NULL && 675 pci_enumerate_bus(device_private(pcidev), wildcard, 676 match, pa) != 0) 677 return 1; 678 } 679 return 0; 680 } 681 682 #ifndef PCI_MACHDEP_ENUMERATE_BUS 683 /* 684 * Generic PCI bus enumeration routine. Used unless machine-dependent 685 * code needs to provide something else. 686 */ 687 int 688 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 689 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 690 { 691 pci_chipset_tag_t pc = sc->sc_pc; 692 int device, function, nfunctions, ret; 693 const struct pci_quirkdata *qd; 694 pcireg_t id, bhlcr; 695 pcitag_t tag; 696 uint8_t devs[32]; 697 int i, n; 698 699 device_t bridgedev; 700 bool arien = false; 701 702 /* Check PCIe ARI */ 703 bridgedev = device_parent(sc->sc_dev); 704 if (device_is_a(bridgedev, "ppb")) { 705 struct ppb_softc *ppbsc = device_private(bridgedev); 706 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 707 pcitag_t ppbtag = ppbsc->sc_tag; 708 pcireg_t pciecap, reg; 709 710 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 711 &pciecap, NULL) != 0) { 712 reg = pci_conf_read(ppbpc, ppbtag, pciecap 713 + PCIE_DCSR2); 714 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 715 arien = true; 716 } 717 } 718 719 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 720 for (i = 0; i < n; i++) { 721 device = devs[i]; 722 723 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 724 (locators[PCICF_DEV] != device)) 725 continue; 726 727 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 728 729 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 730 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 731 continue; 732 733 id = pci_conf_read(pc, tag, PCI_ID_REG); 734 735 /* Invalid vendor ID value? */ 736 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 737 continue; 738 /* XXX Not invalid, but we've done this ~forever. */ 739 if (PCI_VENDOR(id) == 0) 740 continue; 741 742 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 743 744 if (qd != NULL && 745 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 746 nfunctions = 8; 747 else if (qd != NULL && 748 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 749 nfunctions = 1; 750 else if (arien) 751 nfunctions = 8; /* Scan all if ARI is enabled */ 752 else 753 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 754 755 #ifdef __PCI_DEV_FUNCORDER 756 char funcs[8]; 757 int j; 758 for (j = 0; j < nfunctions; j++) { 759 funcs[j] = j; 760 } 761 if (j < __arraycount(funcs)) 762 funcs[j] = -1; 763 if (nfunctions > 1) { 764 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 765 nfunctions, funcs); 766 } 767 for (j = 0; 768 j < 8 && (function = funcs[j]) < 8 && function >= 0; 769 j++) { 770 #else 771 for (function = 0; function < nfunctions; function++) { 772 #endif 773 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 774 && (locators[PCICF_FUNCTION] != function)) 775 continue; 776 777 if (qd != NULL && 778 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 779 continue; 780 tag = pci_make_tag(pc, sc->sc_bus, device, function); 781 ret = pci_probe_device(sc, tag, match, pap); 782 if (match != NULL && ret != 0) 783 return ret; 784 } 785 } 786 return 0; 787 } 788 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 789 790 791 /* 792 * Vital Product Data (PCI 2.2) 793 */ 794 795 int 796 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 797 pcireg_t *data) 798 { 799 uint32_t reg; 800 int ofs, i, j; 801 802 KASSERT(data != NULL); 803 KASSERT((offset + count) < 0x7fff); 804 805 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 806 return 1; 807 808 for (i = 0; i < count; offset += sizeof(*data), i++) { 809 reg &= 0x0000ffff; 810 reg &= ~PCI_VPD_OPFLAG; 811 reg |= PCI_VPD_ADDRESS(offset); 812 pci_conf_write(pc, tag, ofs, reg); 813 814 /* 815 * PCI 2.2 does not specify how long we should poll 816 * for completion nor whether the operation can fail. 817 */ 818 j = 0; 819 do { 820 if (j++ == 20) 821 return 1; 822 delay(4); 823 reg = pci_conf_read(pc, tag, ofs); 824 } while ((reg & PCI_VPD_OPFLAG) == 0); 825 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 826 } 827 828 return 0; 829 } 830 831 int 832 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 833 pcireg_t *data) 834 { 835 pcireg_t reg; 836 int ofs, i, j; 837 838 KASSERT(data != NULL); 839 KASSERT((offset + count) < 0x7fff); 840 841 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 842 return 1; 843 844 for (i = 0; i < count; offset += sizeof(*data), i++) { 845 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 846 847 reg &= 0x0000ffff; 848 reg |= PCI_VPD_OPFLAG; 849 reg |= PCI_VPD_ADDRESS(offset); 850 pci_conf_write(pc, tag, ofs, reg); 851 852 /* 853 * PCI 2.2 does not specify how long we should poll 854 * for completion nor whether the operation can fail. 855 */ 856 j = 0; 857 do { 858 if (j++ == 20) 859 return 1; 860 delay(1); 861 reg = pci_conf_read(pc, tag, ofs); 862 } while (reg & PCI_VPD_OPFLAG); 863 } 864 865 return 0; 866 } 867 868 int 869 pci_dma64_available(const struct pci_attach_args *pa) 870 { 871 #ifdef _PCI_HAVE_DMA64 872 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 873 return 1; 874 #endif 875 return 0; 876 } 877 878 void 879 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 880 struct pci_conf_state *pcs) 881 { 882 int off; 883 884 for (off = 0; off < 16; off++) 885 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 886 887 return; 888 } 889 890 void 891 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 892 struct pci_conf_state *pcs) 893 { 894 int off; 895 pcireg_t val; 896 897 for (off = 15; off >= 0; off--) { 898 val = pci_conf_read(pc, tag, (off * 4)); 899 if (val != pcs->reg[off]) 900 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 901 } 902 903 return; 904 } 905 906 /* 907 * Power Management Capability (Rev 2.2) 908 */ 909 static int 910 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 911 int offset) 912 { 913 pcireg_t value, now; 914 915 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 916 now = value & PCI_PMCSR_STATE_MASK; 917 switch (now) { 918 case PCI_PMCSR_STATE_D0: 919 case PCI_PMCSR_STATE_D1: 920 case PCI_PMCSR_STATE_D2: 921 case PCI_PMCSR_STATE_D3: 922 *state = now; 923 return 0; 924 default: 925 return EINVAL; 926 } 927 } 928 929 int 930 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 931 { 932 int offset; 933 pcireg_t value; 934 935 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 936 return EOPNOTSUPP; 937 938 return pci_get_powerstate_int(pc, tag, state, offset); 939 } 940 941 static int 942 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 943 int offset, pcireg_t cap_reg) 944 { 945 pcireg_t value, cap, now; 946 947 cap = cap_reg >> PCI_PMCR_SHIFT; 948 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 949 now = value & PCI_PMCSR_STATE_MASK; 950 value &= ~PCI_PMCSR_STATE_MASK; 951 952 if (now == state) 953 return 0; 954 switch (state) { 955 case PCI_PMCSR_STATE_D0: 956 break; 957 case PCI_PMCSR_STATE_D1: 958 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 959 printf("invalid transition from %d to D1\n", (int)now); 960 return EINVAL; 961 } 962 if (!(cap & PCI_PMCR_D1SUPP)) { 963 printf("D1 not supported\n"); 964 return EOPNOTSUPP; 965 } 966 break; 967 case PCI_PMCSR_STATE_D2: 968 if (now == PCI_PMCSR_STATE_D3) { 969 printf("invalid transition from %d to D2\n", (int)now); 970 return EINVAL; 971 } 972 if (!(cap & PCI_PMCR_D2SUPP)) { 973 printf("D2 not supported\n"); 974 return EOPNOTSUPP; 975 } 976 break; 977 case PCI_PMCSR_STATE_D3: 978 break; 979 default: 980 return EINVAL; 981 } 982 value |= state; 983 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 984 /* delay according to pcipm1.2, ch. 5.6.1 */ 985 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 986 DELAY(10000); 987 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 988 DELAY(200); 989 990 return 0; 991 } 992 993 int 994 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 995 { 996 int offset; 997 pcireg_t value; 998 999 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1000 printf("pci_set_powerstate not supported\n"); 1001 return EOPNOTSUPP; 1002 } 1003 1004 return pci_set_powerstate_int(pc, tag, state, offset, value); 1005 } 1006 1007 int 1008 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1009 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1010 { 1011 pcireg_t pmode; 1012 int error; 1013 1014 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1015 return error; 1016 1017 switch (pmode) { 1018 case PCI_PMCSR_STATE_D0: 1019 break; 1020 case PCI_PMCSR_STATE_D3: 1021 if (wakefun == NULL) { 1022 /* 1023 * The card has lost all configuration data in 1024 * this state, so punt. 1025 */ 1026 aprint_error_dev(dev, 1027 "unable to wake up from power state D3\n"); 1028 return EOPNOTSUPP; 1029 } 1030 /*FALLTHROUGH*/ 1031 default: 1032 if (wakefun) { 1033 error = (*wakefun)(pc, tag, dev, pmode); 1034 if (error) 1035 return error; 1036 } 1037 aprint_normal_dev(dev, "waking up from power state D%d\n", 1038 pmode); 1039 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1040 return error; 1041 } 1042 return 0; 1043 } 1044 1045 int 1046 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1047 device_t dev, pcireg_t state) 1048 { 1049 return 0; 1050 } 1051 1052 struct pci_child_power { 1053 struct pci_conf_state p_pciconf; 1054 pci_chipset_tag_t p_pc; 1055 pcitag_t p_tag; 1056 bool p_has_pm; 1057 int p_pm_offset; 1058 pcireg_t p_pm_cap; 1059 pcireg_t p_class; 1060 pcireg_t p_csr; 1061 }; 1062 1063 static bool 1064 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1065 { 1066 struct pci_child_power *priv = device_pmf_bus_private(dv); 1067 pcireg_t ocsr, csr; 1068 1069 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1070 1071 if (!priv->p_has_pm) 1072 return true; /* ??? hopefully handled by ACPI */ 1073 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1074 return true; /* XXX */ 1075 1076 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1077 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1078 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1079 | PCI_COMMAND_MASTER_ENABLE); 1080 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1081 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1082 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1083 pci_conf_write(priv->p_pc, priv->p_tag, 1084 PCI_COMMAND_STATUS_REG, ocsr); 1085 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1086 return false; 1087 } 1088 return true; 1089 } 1090 1091 static bool 1092 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1093 { 1094 struct pci_child_power *priv = device_pmf_bus_private(dv); 1095 1096 if (priv->p_has_pm && 1097 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1098 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1099 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1100 return false; 1101 } 1102 1103 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1104 1105 return true; 1106 } 1107 1108 static bool 1109 pci_child_shutdown(device_t dv, int how) 1110 { 1111 struct pci_child_power *priv = device_pmf_bus_private(dv); 1112 pcireg_t csr; 1113 1114 /* restore original bus-mastering state */ 1115 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1116 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1117 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1118 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1119 return true; 1120 } 1121 1122 static void 1123 pci_child_deregister(device_t dv) 1124 { 1125 struct pci_child_power *priv = device_pmf_bus_private(dv); 1126 1127 free(priv, M_DEVBUF); 1128 } 1129 1130 static bool 1131 pci_child_register(device_t child) 1132 { 1133 device_t self = device_parent(child); 1134 struct pci_softc *sc = device_private(self); 1135 struct pci_child_power *priv; 1136 int device, function, off; 1137 pcireg_t reg; 1138 1139 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1140 1141 device = device_locator(child, PCICF_DEV); 1142 function = device_locator(child, PCICF_FUNCTION); 1143 1144 priv->p_pc = sc->sc_pc; 1145 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1146 function); 1147 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1148 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1149 PCI_COMMAND_STATUS_REG); 1150 1151 if (pci_get_capability(priv->p_pc, priv->p_tag, 1152 PCI_CAP_PWRMGMT, &off, ®)) { 1153 priv->p_has_pm = true; 1154 priv->p_pm_offset = off; 1155 priv->p_pm_cap = reg; 1156 } else { 1157 priv->p_has_pm = false; 1158 priv->p_pm_offset = -1; 1159 } 1160 1161 device_pmf_bus_register(child, priv, pci_child_suspend, 1162 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1163 1164 return true; 1165 } 1166 1167 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1168 1169 static int 1170 pci_modcmd(modcmd_t cmd, void *priv) 1171 { 1172 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1173 return 0; 1174 return ENOTTY; 1175 } 1176
Indexes created Tue Sep 30 11:09:46 GMT 2025