pci.c revision 1.145.2.3
1 /* $NetBSD: pci.c,v 1.145.2.3 2015/12/27 12:09:50 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.145.2.3 2015/12/27 12:09:50 skrll Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <net/if.h> 56 57 #include "locators.h" 58 59 static bool pci_child_register(device_t); 60 61 #ifdef PCI_CONFIG_DUMP 62 int pci_config_dump = 1; 63 #else 64 int pci_config_dump = 0; 65 #endif 66 67 int pciprint(void *, const char *); 68 69 #ifdef PCI_MACHDEP_ENUMERATE_BUS 70 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 71 #endif 72 73 /* 74 * Important note about PCI-ISA bridges: 75 * 76 * Callbacks are used to configure these devices so that ISA/EISA bridges 77 * can attach their child busses after PCI configuration is done. 78 * 79 * This works because: 80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 81 * (2) any ISA/EISA bridges must be attached to primary PCI 82 * busses (i.e. bus zero). 83 * 84 * That boils down to: there can only be one of these outstanding 85 * at a time, it is cleared when configuring PCI bus 0 before any 86 * subdevices have been found, and it is run after all subdevices 87 * of PCI bus 0 have been found. 88 * 89 * This is needed because there are some (legacy) PCI devices which 90 * can show up as ISA/EISA devices as well (the prime example of which 91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 92 * and the bridge is seen before the video board is, the board can show 93 * up as an ISA device, and that can (bogusly) complicate the PCI device's 94 * attach code, or make the PCI device not be properly attached at all. 95 * 96 * We use the generic config_defer() facility to achieve this. 97 */ 98 99 int 100 pcirescan(device_t self, const char *ifattr, const int *locators) 101 { 102 struct pci_softc *sc = device_private(self); 103 104 KASSERT(ifattr && !strcmp(ifattr, "pci")); 105 KASSERT(locators); 106 107 pci_enumerate_bus(sc, locators, NULL, NULL); 108 109 return 0; 110 } 111 112 int 113 pcimatch(device_t parent, cfdata_t cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return 0; 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return 0; 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return 1; 131 } 132 133 void 134 pciattach(device_t parent, device_t self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = device_private(self); 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 sc->sc_dev = self; 145 146 pci_attach_hook(parent, self, pba); 147 148 aprint_naive("\n"); 149 aprint_normal("\n"); 150 151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 156 157 if (io_enabled == 0 && mem_enabled == 0) { 158 aprint_error_dev(self, "no spaces enabled!\n"); 159 goto fail; 160 } 161 162 #define PRINT(str) \ 163 do { \ 164 aprint_verbose("%s%s", sep, str); \ 165 sep = ", "; \ 166 } while (/*CONSTCOND*/0) 167 168 aprint_verbose_dev(self, ""); 169 170 if (io_enabled) 171 PRINT("i/o space"); 172 if (mem_enabled) 173 PRINT("memory space"); 174 aprint_verbose(" enabled"); 175 176 if (mrl_enabled || mrm_enabled || mwi_enabled) { 177 if (mrl_enabled) 178 PRINT("rd/line"); 179 if (mrm_enabled) 180 PRINT("rd/mult"); 181 if (mwi_enabled) 182 PRINT("wr/inv"); 183 aprint_verbose(" ok"); 184 } 185 186 aprint_verbose("\n"); 187 188 #undef PRINT 189 190 sc->sc_iot = pba->pba_iot; 191 sc->sc_memt = pba->pba_memt; 192 sc->sc_dmat = pba->pba_dmat; 193 sc->sc_dmat64 = pba->pba_dmat64; 194 sc->sc_pc = pba->pba_pc; 195 sc->sc_bus = pba->pba_bus; 196 sc->sc_bridgetag = pba->pba_bridgetag; 197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 198 sc->sc_intrswiz = pba->pba_intrswiz; 199 sc->sc_intrtag = pba->pba_intrtag; 200 sc->sc_flags = pba->pba_flags; 201 202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 203 204 pcirescan(sc->sc_dev, "pci", wildcard); 205 206 fail: 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 int 212 pcidetach(device_t self, int flags) 213 { 214 int rc; 215 216 if ((rc = config_detach_children(self, flags)) != 0) 217 return rc; 218 pmf_device_deregister(self); 219 return 0; 220 } 221 222 int 223 pciprint(void *aux, const char *pnp) 224 { 225 struct pci_attach_args *pa = aux; 226 char devinfo[256]; 227 const struct pci_quirkdata *qd; 228 229 if (pnp) { 230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 231 aprint_normal("%s at %s", devinfo, pnp); 232 } 233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 234 if (pci_config_dump) { 235 printf(": "); 236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 237 if (!pnp) 238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 239 printf("%s at %s", devinfo, pnp ? pnp : "?"); 240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 241 #ifdef __i386__ 242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 245 #else 246 printf("intrswiz %#lx, intrpin %#lx", 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #endif 249 printf(", i/o %s, mem %s,", 250 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 251 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 253 PCI_PRODUCT(pa->pa_id)); 254 if (qd == NULL) { 255 printf(" no quirks"); 256 } else { 257 snprintb(devinfo, sizeof (devinfo), 258 "\002\001multifn\002singlefn\003skipfunc0" 259 "\004skipfunc1\005skipfunc2\006skipfunc3" 260 "\007skipfunc4\010skipfunc5\011skipfunc6" 261 "\012skipfunc7", qd->quirks); 262 printf(" quirks %s", devinfo); 263 } 264 printf(")"); 265 } 266 return UNCONF; 267 } 268 269 int 270 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 271 int (*match)(const struct pci_attach_args *), 272 struct pci_attach_args *pap) 273 { 274 pci_chipset_tag_t pc = sc->sc_pc; 275 struct pci_attach_args pa; 276 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 277 #ifdef __HAVE_PCI_MSI_MSIX 278 pcireg_t cap; 279 int off; 280 #endif 281 int ret, pin, bus, device, function, i, width; 282 int locs[PCICF_NLOCS]; 283 284 pci_decompose_tag(pc, tag, &bus, &device, &function); 285 286 /* a driver already attached? */ 287 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 288 return 0; 289 290 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 291 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 292 return 0; 293 294 id = pci_conf_read(pc, tag, PCI_ID_REG); 295 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 296 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 297 298 /* Invalid vendor ID value? */ 299 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 300 return 0; 301 /* XXX Not invalid, but we've done this ~forever. */ 302 if (PCI_VENDOR(id) == 0) 303 return 0; 304 305 /* Collect memory range info */ 306 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 307 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 308 i = 0; 309 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 310 case PCI_HDRTYPE_PPB: 311 endbar = PCI_MAPREG_PPB_END; 312 break; 313 case PCI_HDRTYPE_PCB: 314 endbar = PCI_MAPREG_PCB_END; 315 break; 316 default: 317 endbar = PCI_MAPREG_END; 318 break; 319 } 320 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 321 struct pci_range *r; 322 pcireg_t type; 323 324 width = 4; 325 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 326 continue; 327 328 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 329 if (PCI_MAPREG_MEM_TYPE(type) == 330 PCI_MAPREG_MEM_TYPE_64BIT) 331 width = 8; 332 333 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 334 if (pci_mapreg_info(pc, tag, bar, type, 335 &r->r_offset, &r->r_size, &r->r_flags) != 0) 336 break; 337 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 338 && (r->r_size == 0x1000000)) { 339 struct pci_range *nr; 340 /* 341 * this has to be a mach64 342 * split things up so each half-aperture can 343 * be mapped PREFETCHABLE except the last page 344 * which may contain registers 345 */ 346 r->r_size = 0x7ff000; 347 r->r_flags = BUS_SPACE_MAP_LINEAR | 348 BUS_SPACE_MAP_PREFETCHABLE; 349 nr = &sc->PCI_SC_DEVICESC(device, 350 function).c_range[i++]; 351 nr->r_offset = r->r_offset + 0x800000; 352 nr->r_size = 0x7ff000; 353 nr->r_flags = BUS_SPACE_MAP_LINEAR | 354 BUS_SPACE_MAP_PREFETCHABLE; 355 } 356 357 } 358 } 359 360 pa.pa_iot = sc->sc_iot; 361 pa.pa_memt = sc->sc_memt; 362 pa.pa_dmat = sc->sc_dmat; 363 pa.pa_dmat64 = sc->sc_dmat64; 364 pa.pa_pc = pc; 365 pa.pa_bus = bus; 366 pa.pa_device = device; 367 pa.pa_function = function; 368 pa.pa_tag = tag; 369 pa.pa_id = id; 370 pa.pa_class = pciclass; 371 372 /* 373 * Set up memory, I/O enable, and PCI command flags 374 * as appropriate. 375 */ 376 pa.pa_flags = sc->sc_flags; 377 378 /* 379 * If the cache line size is not configured, then 380 * clear the MRL/MRM/MWI command-ok flags. 381 */ 382 if (PCI_CACHELINE(bhlcr) == 0) { 383 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 384 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 385 } 386 387 if (sc->sc_bridgetag == NULL) { 388 pa.pa_intrswiz = 0; 389 pa.pa_intrtag = tag; 390 } else { 391 pa.pa_intrswiz = sc->sc_intrswiz + device; 392 pa.pa_intrtag = sc->sc_intrtag; 393 } 394 395 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 396 397 pin = PCI_INTERRUPT_PIN(intr); 398 pa.pa_rawintrpin = pin; 399 if (pin == PCI_INTERRUPT_PIN_NONE) { 400 /* no interrupt */ 401 pa.pa_intrpin = 0; 402 } else { 403 /* 404 * swizzle it based on the number of busses we're 405 * behind and our device number. 406 */ 407 pa.pa_intrpin = /* XXX */ 408 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 409 } 410 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 411 412 #ifdef __HAVE_PCI_MSI_MSIX 413 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 414 /* 415 * XXX Should we enable MSI mapping ourselves on 416 * systems that have it disabled? 417 */ 418 if (cap & PCI_HT_MSI_ENABLED) { 419 uint64_t addr; 420 if ((cap & PCI_HT_MSI_FIXED) == 0) { 421 addr = pci_conf_read(pc, tag, 422 off + PCI_HT_MSI_ADDR_LO); 423 addr |= (uint64_t)pci_conf_read(pc, tag, 424 off + PCI_HT_MSI_ADDR_HI) << 32; 425 } else 426 addr = PCI_HT_MSI_FIXED_ADDR; 427 428 /* 429 * XXX This will fail to enable MSI on systems 430 * that don't use the canonical address. 431 */ 432 if (addr == PCI_HT_MSI_FIXED_ADDR) { 433 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 434 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 435 } else 436 aprint_verbose_dev(sc->sc_dev, 437 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 438 } 439 } 440 #endif 441 442 if (match != NULL) { 443 ret = (*match)(&pa); 444 if (ret != 0 && pap != NULL) 445 *pap = pa; 446 } else { 447 struct pci_child *c; 448 locs[PCICF_DEV] = device; 449 locs[PCICF_FUNCTION] = function; 450 451 c = &sc->PCI_SC_DEVICESC(device, function); 452 pci_conf_capture(pc, tag, &c->c_conf); 453 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 454 c->c_psok = true; 455 else 456 c->c_psok = false; 457 458 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 459 pciprint, config_stdsubmatch); 460 461 ret = (c->c_dev != NULL); 462 } 463 464 return ret; 465 } 466 467 void 468 pcidevdetached(device_t self, device_t child) 469 { 470 struct pci_softc *sc = device_private(self); 471 int d, f; 472 pcitag_t tag; 473 struct pci_child *c; 474 475 d = device_locator(child, PCICF_DEV); 476 f = device_locator(child, PCICF_FUNCTION); 477 478 c = &sc->PCI_SC_DEVICESC(d, f); 479 480 KASSERT(c->c_dev == child); 481 482 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 483 if (c->c_psok) 484 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 485 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 486 c->c_dev = NULL; 487 } 488 489 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 490 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 491 DVF_DETACH_SHUTDOWN); 492 493 int 494 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 495 int *offset, pcireg_t *value) 496 { 497 pcireg_t reg; 498 unsigned int ofs; 499 500 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 501 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 502 return 0; 503 504 /* Determine the Capability List Pointer register to start with. */ 505 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 506 switch (PCI_HDRTYPE_TYPE(reg)) { 507 case 0: /* standard device header */ 508 case 1: /* PCI-PCI bridge header */ 509 ofs = PCI_CAPLISTPTR_REG; 510 break; 511 case 2: /* PCI-CardBus Bridge header */ 512 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 513 break; 514 default: 515 return 0; 516 } 517 518 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 519 while (ofs != 0) { 520 if ((ofs & 3) || (ofs < 0x40)) { 521 int bus, device, function; 522 523 pci_decompose_tag(pc, tag, &bus, &device, &function); 524 525 printf("Skipping broken PCI header on %d:%d:%d\n", 526 bus, device, function); 527 break; 528 } 529 reg = pci_conf_read(pc, tag, ofs); 530 if (PCI_CAPLIST_CAP(reg) == capid) { 531 if (offset) 532 *offset = ofs; 533 if (value) 534 *value = reg; 535 return 1; 536 } 537 ofs = PCI_CAPLIST_NEXT(reg); 538 } 539 540 return 0; 541 } 542 543 int 544 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 545 int *offset, pcireg_t *value) 546 { 547 pcireg_t reg; 548 unsigned int ofs; 549 550 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 551 return 0; 552 553 while (ofs != 0) { 554 #ifdef DIAGNOSTIC 555 if ((ofs & 3) || (ofs < 0x40)) 556 panic("pci_get_ht_capability"); 557 #endif 558 reg = pci_conf_read(pc, tag, ofs); 559 if (PCI_HT_CAP(reg) == capid) { 560 if (offset) 561 *offset = ofs; 562 if (value) 563 *value = reg; 564 return 1; 565 } 566 ofs = PCI_CAPLIST_NEXT(reg); 567 } 568 569 return 0; 570 } 571 572 /* 573 * return number of the devices's MSI vectors 574 * return 0 if the device does not support MSI 575 */ 576 int 577 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 578 { 579 pcireg_t reg; 580 uint32_t mmc; 581 int count, offset; 582 583 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 584 return 0; 585 586 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 587 mmc = PCI_MSI_CTL_MMC(reg); 588 count = 1 << mmc; 589 if (count > PCI_MSI_MAX_VECTORS) { 590 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 591 return 0; 592 } 593 594 return count; 595 } 596 597 /* 598 * return number of the devices's MSI-X vectors 599 * return 0 if the device does not support MSI-X 600 */ 601 int 602 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 603 { 604 pcireg_t reg; 605 int offset; 606 607 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 608 return 0; 609 610 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 611 612 return PCI_MSIX_CTL_TBLSIZE(reg); 613 } 614 615 int 616 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 617 int *offset, pcireg_t *value) 618 { 619 pcireg_t reg; 620 unsigned int ofs; 621 622 /* Only supported for PCI-express devices */ 623 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 624 return 0; 625 626 ofs = PCI_EXTCAPLIST_BASE; 627 reg = pci_conf_read(pc, tag, ofs); 628 if (reg == 0xffffffff || reg == 0) 629 return 0; 630 631 for (;;) { 632 #ifdef DIAGNOSTIC 633 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 634 panic("%s: invalid offset %u", __func__, ofs); 635 #endif 636 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 637 if (offset != NULL) 638 *offset = ofs; 639 if (value != NULL) 640 *value = reg; 641 return 1; 642 } 643 ofs = PCI_EXTCAPLIST_NEXT(reg); 644 if (ofs == 0) 645 break; 646 reg = pci_conf_read(pc, tag, ofs); 647 } 648 649 return 0; 650 } 651 652 int 653 pci_find_device(struct pci_attach_args *pa, 654 int (*match)(const struct pci_attach_args *)) 655 { 656 extern struct cfdriver pci_cd; 657 device_t pcidev; 658 int i; 659 static const int wildcard[2] = { 660 PCICF_DEV_DEFAULT, 661 PCICF_FUNCTION_DEFAULT 662 }; 663 664 for (i = 0; i < pci_cd.cd_ndevs; i++) { 665 pcidev = device_lookup(&pci_cd, i); 666 if (pcidev != NULL && 667 pci_enumerate_bus(device_private(pcidev), wildcard, 668 match, pa) != 0) 669 return 1; 670 } 671 return 0; 672 } 673 674 #ifndef PCI_MACHDEP_ENUMERATE_BUS 675 /* 676 * Generic PCI bus enumeration routine. Used unless machine-dependent 677 * code needs to provide something else. 678 */ 679 int 680 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 681 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 682 { 683 pci_chipset_tag_t pc = sc->sc_pc; 684 int device, function, nfunctions, ret; 685 const struct pci_quirkdata *qd; 686 pcireg_t id, bhlcr; 687 pcitag_t tag; 688 uint8_t devs[32]; 689 int i, n; 690 691 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 692 for (i = 0; i < n; i++) { 693 device = devs[i]; 694 695 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 696 (locators[PCICF_DEV] != device)) 697 continue; 698 699 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 700 701 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 702 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 703 continue; 704 705 id = pci_conf_read(pc, tag, PCI_ID_REG); 706 707 /* Invalid vendor ID value? */ 708 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 709 continue; 710 /* XXX Not invalid, but we've done this ~forever. */ 711 if (PCI_VENDOR(id) == 0) 712 continue; 713 714 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 715 716 if (qd != NULL && 717 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 718 nfunctions = 8; 719 else if (qd != NULL && 720 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 721 nfunctions = 1; 722 else 723 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 724 725 #ifdef __PCI_DEV_FUNCORDER 726 char funcs[8]; 727 int j; 728 for (j = 0; j < nfunctions; j++) { 729 funcs[j] = j; 730 } 731 if (j < __arraycount(funcs)) 732 funcs[j] = -1; 733 if (nfunctions > 1) { 734 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 735 nfunctions, funcs); 736 } 737 for (j = 0; 738 j < 8 && (function = funcs[j]) < 8 && function >= 0; 739 j++) { 740 #else 741 for (function = 0; function < nfunctions; function++) { 742 #endif 743 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 744 && (locators[PCICF_FUNCTION] != function)) 745 continue; 746 747 if (qd != NULL && 748 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 749 continue; 750 tag = pci_make_tag(pc, sc->sc_bus, device, function); 751 ret = pci_probe_device(sc, tag, match, pap); 752 if (match != NULL && ret != 0) 753 return ret; 754 } 755 } 756 return 0; 757 } 758 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 759 760 761 /* 762 * Vital Product Data (PCI 2.2) 763 */ 764 765 int 766 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 767 pcireg_t *data) 768 { 769 uint32_t reg; 770 int ofs, i, j; 771 772 KASSERT(data != NULL); 773 KASSERT((offset + count) < 0x7fff); 774 775 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 776 return 1; 777 778 for (i = 0; i < count; offset += sizeof(*data), i++) { 779 reg &= 0x0000ffff; 780 reg &= ~PCI_VPD_OPFLAG; 781 reg |= PCI_VPD_ADDRESS(offset); 782 pci_conf_write(pc, tag, ofs, reg); 783 784 /* 785 * PCI 2.2 does not specify how long we should poll 786 * for completion nor whether the operation can fail. 787 */ 788 j = 0; 789 do { 790 if (j++ == 20) 791 return 1; 792 delay(4); 793 reg = pci_conf_read(pc, tag, ofs); 794 } while ((reg & PCI_VPD_OPFLAG) == 0); 795 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 796 } 797 798 return 0; 799 } 800 801 int 802 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 803 pcireg_t *data) 804 { 805 pcireg_t reg; 806 int ofs, i, j; 807 808 KASSERT(data != NULL); 809 KASSERT((offset + count) < 0x7fff); 810 811 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 812 return 1; 813 814 for (i = 0; i < count; offset += sizeof(*data), i++) { 815 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 816 817 reg &= 0x0000ffff; 818 reg |= PCI_VPD_OPFLAG; 819 reg |= PCI_VPD_ADDRESS(offset); 820 pci_conf_write(pc, tag, ofs, reg); 821 822 /* 823 * PCI 2.2 does not specify how long we should poll 824 * for completion nor whether the operation can fail. 825 */ 826 j = 0; 827 do { 828 if (j++ == 20) 829 return 1; 830 delay(1); 831 reg = pci_conf_read(pc, tag, ofs); 832 } while (reg & PCI_VPD_OPFLAG); 833 } 834 835 return 0; 836 } 837 838 int 839 pci_dma64_available(const struct pci_attach_args *pa) 840 { 841 #ifdef _PCI_HAVE_DMA64 842 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 843 return 1; 844 #endif 845 return 0; 846 } 847 848 void 849 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 850 struct pci_conf_state *pcs) 851 { 852 int off; 853 854 for (off = 0; off < 16; off++) 855 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 856 857 return; 858 } 859 860 void 861 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 862 struct pci_conf_state *pcs) 863 { 864 int off; 865 pcireg_t val; 866 867 for (off = 15; off >= 0; off--) { 868 val = pci_conf_read(pc, tag, (off * 4)); 869 if (val != pcs->reg[off]) 870 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 871 } 872 873 return; 874 } 875 876 /* 877 * Power Management Capability (Rev 2.2) 878 */ 879 static int 880 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 881 int offset) 882 { 883 pcireg_t value, now; 884 885 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 886 now = value & PCI_PMCSR_STATE_MASK; 887 switch (now) { 888 case PCI_PMCSR_STATE_D0: 889 case PCI_PMCSR_STATE_D1: 890 case PCI_PMCSR_STATE_D2: 891 case PCI_PMCSR_STATE_D3: 892 *state = now; 893 return 0; 894 default: 895 return EINVAL; 896 } 897 } 898 899 int 900 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 901 { 902 int offset; 903 pcireg_t value; 904 905 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 906 return EOPNOTSUPP; 907 908 return pci_get_powerstate_int(pc, tag, state, offset); 909 } 910 911 static int 912 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 913 int offset, pcireg_t cap_reg) 914 { 915 pcireg_t value, cap, now; 916 917 cap = cap_reg >> PCI_PMCR_SHIFT; 918 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 919 now = value & PCI_PMCSR_STATE_MASK; 920 value &= ~PCI_PMCSR_STATE_MASK; 921 922 if (now == state) 923 return 0; 924 switch (state) { 925 case PCI_PMCSR_STATE_D0: 926 break; 927 case PCI_PMCSR_STATE_D1: 928 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 929 printf("invalid transition from %d to D1\n", (int)now); 930 return EINVAL; 931 } 932 if (!(cap & PCI_PMCR_D1SUPP)) { 933 printf("D1 not supported\n"); 934 return EOPNOTSUPP; 935 } 936 break; 937 case PCI_PMCSR_STATE_D2: 938 if (now == PCI_PMCSR_STATE_D3) { 939 printf("invalid transition from %d to D2\n", (int)now); 940 return EINVAL; 941 } 942 if (!(cap & PCI_PMCR_D2SUPP)) { 943 printf("D2 not supported\n"); 944 return EOPNOTSUPP; 945 } 946 break; 947 case PCI_PMCSR_STATE_D3: 948 break; 949 default: 950 return EINVAL; 951 } 952 value |= state; 953 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 954 /* delay according to pcipm1.2, ch. 5.6.1 */ 955 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 956 DELAY(10000); 957 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 958 DELAY(200); 959 960 return 0; 961 } 962 963 int 964 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 965 { 966 int offset; 967 pcireg_t value; 968 969 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 970 printf("pci_set_powerstate not supported\n"); 971 return EOPNOTSUPP; 972 } 973 974 return pci_set_powerstate_int(pc, tag, state, offset, value); 975 } 976 977 int 978 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 979 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 980 { 981 pcireg_t pmode; 982 int error; 983 984 if ((error = pci_get_powerstate(pc, tag, &pmode))) 985 return error; 986 987 switch (pmode) { 988 case PCI_PMCSR_STATE_D0: 989 break; 990 case PCI_PMCSR_STATE_D3: 991 if (wakefun == NULL) { 992 /* 993 * The card has lost all configuration data in 994 * this state, so punt. 995 */ 996 aprint_error_dev(dev, 997 "unable to wake up from power state D3\n"); 998 return EOPNOTSUPP; 999 } 1000 /*FALLTHROUGH*/ 1001 default: 1002 if (wakefun) { 1003 error = (*wakefun)(pc, tag, dev, pmode); 1004 if (error) 1005 return error; 1006 } 1007 aprint_normal_dev(dev, "waking up from power state D%d\n", 1008 pmode); 1009 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1010 return error; 1011 } 1012 return 0; 1013 } 1014 1015 int 1016 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1017 device_t dev, pcireg_t state) 1018 { 1019 return 0; 1020 } 1021 1022 struct pci_child_power { 1023 struct pci_conf_state p_pciconf; 1024 pci_chipset_tag_t p_pc; 1025 pcitag_t p_tag; 1026 bool p_has_pm; 1027 int p_pm_offset; 1028 pcireg_t p_pm_cap; 1029 pcireg_t p_class; 1030 pcireg_t p_csr; 1031 }; 1032 1033 static bool 1034 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1035 { 1036 struct pci_child_power *priv = device_pmf_bus_private(dv); 1037 pcireg_t ocsr, csr; 1038 1039 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1040 1041 if (!priv->p_has_pm) 1042 return true; /* ??? hopefully handled by ACPI */ 1043 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1044 return true; /* XXX */ 1045 1046 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1047 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1048 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1049 | PCI_COMMAND_MASTER_ENABLE); 1050 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1051 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1052 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1053 pci_conf_write(priv->p_pc, priv->p_tag, 1054 PCI_COMMAND_STATUS_REG, ocsr); 1055 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1056 return false; 1057 } 1058 return true; 1059 } 1060 1061 static bool 1062 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1063 { 1064 struct pci_child_power *priv = device_pmf_bus_private(dv); 1065 1066 if (priv->p_has_pm && 1067 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1068 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1069 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1070 return false; 1071 } 1072 1073 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1074 1075 return true; 1076 } 1077 1078 static bool 1079 pci_child_shutdown(device_t dv, int how) 1080 { 1081 struct pci_child_power *priv = device_pmf_bus_private(dv); 1082 pcireg_t csr; 1083 1084 /* restore original bus-mastering state */ 1085 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1086 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1087 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1088 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1089 return true; 1090 } 1091 1092 static void 1093 pci_child_deregister(device_t dv) 1094 { 1095 struct pci_child_power *priv = device_pmf_bus_private(dv); 1096 1097 free(priv, M_DEVBUF); 1098 } 1099 1100 static bool 1101 pci_child_register(device_t child) 1102 { 1103 device_t self = device_parent(child); 1104 struct pci_softc *sc = device_private(self); 1105 struct pci_child_power *priv; 1106 int device, function, off; 1107 pcireg_t reg; 1108 1109 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1110 1111 device = device_locator(child, PCICF_DEV); 1112 function = device_locator(child, PCICF_FUNCTION); 1113 1114 priv->p_pc = sc->sc_pc; 1115 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1116 function); 1117 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1118 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1119 PCI_COMMAND_STATUS_REG); 1120 1121 if (pci_get_capability(priv->p_pc, priv->p_tag, 1122 PCI_CAP_PWRMGMT, &off, ®)) { 1123 priv->p_has_pm = true; 1124 priv->p_pm_offset = off; 1125 priv->p_pm_cap = reg; 1126 } else { 1127 priv->p_has_pm = false; 1128 priv->p_pm_offset = -1; 1129 } 1130 1131 device_pmf_bus_register(child, priv, pci_child_suspend, 1132 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1133 1134 return true; 1135 } 1136 1137 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1138 1139 static int 1140 pci_modcmd(modcmd_t cmd, void *priv) 1141 { 1142 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1143 return 0; 1144 return ENOTTY; 1145 } 1146
Indexes created Tue Sep 30 20:09:53 GMT 2025