pci.c revision 1.147
1 /* $NetBSD: pci.c,v 1.147 2015/08/13 04:39:33 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.147 2015/08/13 04:39:33 msaitoh Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/module.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <net/if.h> 54 55 #include "locators.h" 56 57 static bool pci_child_register(device_t); 58 59 #ifdef PCI_CONFIG_DUMP 60 int pci_config_dump = 1; 61 #else 62 int pci_config_dump = 0; 63 #endif 64 65 int pciprint(void *, const char *); 66 67 #ifdef PCI_MACHDEP_ENUMERATE_BUS 68 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 69 #else 70 int pci_enumerate_bus(struct pci_softc *, const int *, 71 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(const struct pci_attach_args *), 273 struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 278 #ifdef __HAVE_PCI_MSI_MSIX 279 pcireg_t cap; 280 int off; 281 #endif 282 int ret, pin, bus, device, function, i, width; 283 int locs[PCICF_NLOCS]; 284 285 pci_decompose_tag(pc, tag, &bus, &device, &function); 286 287 /* a driver already attached? */ 288 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 289 return 0; 290 291 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 292 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 293 return 0; 294 295 id = pci_conf_read(pc, tag, PCI_ID_REG); 296 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 297 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 298 299 /* Invalid vendor ID value? */ 300 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 301 return 0; 302 /* XXX Not invalid, but we've done this ~forever. */ 303 if (PCI_VENDOR(id) == 0) 304 return 0; 305 306 /* Collect memory range info */ 307 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 308 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 309 i = 0; 310 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 311 case PCI_HDRTYPE_PPB: 312 endbar = PCI_MAPREG_PPB_END; 313 break; 314 case PCI_HDRTYPE_PCB: 315 endbar = PCI_MAPREG_PCB_END; 316 break; 317 default: 318 endbar = PCI_MAPREG_END; 319 break; 320 } 321 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 322 struct pci_range *r; 323 pcireg_t type; 324 325 width = 4; 326 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 327 continue; 328 329 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 330 if (PCI_MAPREG_MEM_TYPE(type) == 331 PCI_MAPREG_MEM_TYPE_64BIT) 332 width = 8; 333 334 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 335 if (pci_mapreg_info(pc, tag, bar, type, 336 &r->r_offset, &r->r_size, &r->r_flags) != 0) 337 break; 338 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 339 && (r->r_size == 0x1000000)) { 340 struct pci_range *nr; 341 /* 342 * this has to be a mach64 343 * split things up so each half-aperture can 344 * be mapped PREFETCHABLE except the last page 345 * which may contain registers 346 */ 347 r->r_size = 0x7ff000; 348 r->r_flags = BUS_SPACE_MAP_LINEAR | 349 BUS_SPACE_MAP_PREFETCHABLE; 350 nr = &sc->PCI_SC_DEVICESC(device, 351 function).c_range[i++]; 352 nr->r_offset = r->r_offset + 0x800000; 353 nr->r_size = 0x7ff000; 354 nr->r_flags = BUS_SPACE_MAP_LINEAR | 355 BUS_SPACE_MAP_PREFETCHABLE; 356 } 357 358 } 359 } 360 361 pa.pa_iot = sc->sc_iot; 362 pa.pa_memt = sc->sc_memt; 363 pa.pa_dmat = sc->sc_dmat; 364 pa.pa_dmat64 = sc->sc_dmat64; 365 pa.pa_pc = pc; 366 pa.pa_bus = bus; 367 pa.pa_device = device; 368 pa.pa_function = function; 369 pa.pa_tag = tag; 370 pa.pa_id = id; 371 pa.pa_class = pciclass; 372 373 /* 374 * Set up memory, I/O enable, and PCI command flags 375 * as appropriate. 376 */ 377 pa.pa_flags = sc->sc_flags; 378 379 /* 380 * If the cache line size is not configured, then 381 * clear the MRL/MRM/MWI command-ok flags. 382 */ 383 if (PCI_CACHELINE(bhlcr) == 0) { 384 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 385 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 386 } 387 388 if (sc->sc_bridgetag == NULL) { 389 pa.pa_intrswiz = 0; 390 pa.pa_intrtag = tag; 391 } else { 392 pa.pa_intrswiz = sc->sc_intrswiz + device; 393 pa.pa_intrtag = sc->sc_intrtag; 394 } 395 396 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 397 398 pin = PCI_INTERRUPT_PIN(intr); 399 pa.pa_rawintrpin = pin; 400 if (pin == PCI_INTERRUPT_PIN_NONE) { 401 /* no interrupt */ 402 pa.pa_intrpin = 0; 403 } else { 404 /* 405 * swizzle it based on the number of busses we're 406 * behind and our device number. 407 */ 408 pa.pa_intrpin = /* XXX */ 409 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 410 } 411 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 412 413 #ifdef __HAVE_PCI_MSI_MSIX 414 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 415 /* 416 * XXX Should we enable MSI mapping ourselves on 417 * systems that have it disabled? 418 */ 419 if (cap & PCI_HT_MSI_ENABLED) { 420 uint64_t addr; 421 if ((cap & PCI_HT_MSI_FIXED) == 0) { 422 addr = pci_conf_read(pc, tag, 423 off + PCI_HT_MSI_ADDR_LO); 424 addr |= (uint64_t)pci_conf_read(pc, tag, 425 off + PCI_HT_MSI_ADDR_HI) << 32; 426 } else 427 addr = PCI_HT_MSI_FIXED_ADDR; 428 429 /* 430 * XXX This will fail to enable MSI on systems 431 * that don't use the canonical address. 432 */ 433 if (addr == PCI_HT_MSI_FIXED_ADDR) { 434 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 435 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 436 } 437 } 438 } 439 #endif 440 441 if (match != NULL) { 442 ret = (*match)(&pa); 443 if (ret != 0 && pap != NULL) 444 *pap = pa; 445 } else { 446 struct pci_child *c; 447 locs[PCICF_DEV] = device; 448 locs[PCICF_FUNCTION] = function; 449 450 c = &sc->PCI_SC_DEVICESC(device, function); 451 pci_conf_capture(pc, tag, &c->c_conf); 452 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 453 c->c_psok = true; 454 else 455 c->c_psok = false; 456 457 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 458 pciprint, config_stdsubmatch); 459 460 ret = (c->c_dev != NULL); 461 } 462 463 return ret; 464 } 465 466 void 467 pcidevdetached(device_t self, device_t child) 468 { 469 struct pci_softc *sc = device_private(self); 470 int d, f; 471 pcitag_t tag; 472 struct pci_child *c; 473 474 d = device_locator(child, PCICF_DEV); 475 f = device_locator(child, PCICF_FUNCTION); 476 477 c = &sc->PCI_SC_DEVICESC(d, f); 478 479 KASSERT(c->c_dev == child); 480 481 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 482 if (c->c_psok) 483 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 484 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 485 c->c_dev = NULL; 486 } 487 488 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 489 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 490 DVF_DETACH_SHUTDOWN); 491 492 int 493 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 494 int *offset, pcireg_t *value) 495 { 496 pcireg_t reg; 497 unsigned int ofs; 498 499 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 500 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 501 return 0; 502 503 /* Determine the Capability List Pointer register to start with. */ 504 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 505 switch (PCI_HDRTYPE_TYPE(reg)) { 506 case 0: /* standard device header */ 507 case 1: /* PCI-PCI bridge header */ 508 ofs = PCI_CAPLISTPTR_REG; 509 break; 510 case 2: /* PCI-CardBus Bridge header */ 511 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 512 break; 513 default: 514 return 0; 515 } 516 517 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 518 while (ofs != 0) { 519 if ((ofs & 3) || (ofs < 0x40)) { 520 int bus, device, function; 521 522 pci_decompose_tag(pc, tag, &bus, &device, &function); 523 524 printf("Skipping broken PCI header on %d:%d:%d\n", 525 bus, device, function); 526 break; 527 } 528 reg = pci_conf_read(pc, tag, ofs); 529 if (PCI_CAPLIST_CAP(reg) == capid) { 530 if (offset) 531 *offset = ofs; 532 if (value) 533 *value = reg; 534 return 1; 535 } 536 ofs = PCI_CAPLIST_NEXT(reg); 537 } 538 539 return 0; 540 } 541 542 int 543 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 544 int *offset, pcireg_t *value) 545 { 546 pcireg_t reg; 547 unsigned int ofs; 548 549 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 550 return 0; 551 552 while (ofs != 0) { 553 #ifdef DIAGNOSTIC 554 if ((ofs & 3) || (ofs < 0x40)) 555 panic("pci_get_ht_capability"); 556 #endif 557 reg = pci_conf_read(pc, tag, ofs); 558 if (PCI_HT_CAP(reg) == capid) { 559 if (offset) 560 *offset = ofs; 561 if (value) 562 *value = reg; 563 return 1; 564 } 565 ofs = PCI_CAPLIST_NEXT(reg); 566 } 567 568 return 0; 569 } 570 571 /* 572 * return number of the devices's MSI vectors 573 * return 0 if the device does not support MSI 574 */ 575 int 576 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 577 { 578 pcireg_t reg; 579 uint32_t mmc; 580 int count, offset; 581 582 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 583 return 0; 584 585 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 586 mmc = PCI_MSI_CTL_MMC(reg); 587 count = 1 << mmc; 588 if (count > PCI_MSI_MAX_VECTORS) { 589 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 590 return 0; 591 } 592 593 return count; 594 } 595 596 /* 597 * return number of the devices's MSI-X vectors 598 * return 0 if the device does not support MSI-X 599 */ 600 int 601 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 602 { 603 pcireg_t reg; 604 int offset; 605 606 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 607 return 0; 608 609 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 610 611 return PCI_MSIX_CTL_TBLSIZE(reg); 612 } 613 614 int 615 pci_find_device(struct pci_attach_args *pa, 616 int (*match)(const struct pci_attach_args *)) 617 { 618 extern struct cfdriver pci_cd; 619 device_t pcidev; 620 int i; 621 static const int wildcard[2] = { 622 PCICF_DEV_DEFAULT, 623 PCICF_FUNCTION_DEFAULT 624 }; 625 626 for (i = 0; i < pci_cd.cd_ndevs; i++) { 627 pcidev = device_lookup(&pci_cd, i); 628 if (pcidev != NULL && 629 pci_enumerate_bus(device_private(pcidev), wildcard, 630 match, pa) != 0) 631 return 1; 632 } 633 return 0; 634 } 635 636 #ifndef PCI_MACHDEP_ENUMERATE_BUS 637 /* 638 * Generic PCI bus enumeration routine. Used unless machine-dependent 639 * code needs to provide something else. 640 */ 641 int 642 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 643 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 644 { 645 pci_chipset_tag_t pc = sc->sc_pc; 646 int device, function, nfunctions, ret; 647 const struct pci_quirkdata *qd; 648 pcireg_t id, bhlcr; 649 pcitag_t tag; 650 uint8_t devs[32]; 651 int i, n; 652 653 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 654 for (i = 0; i < n; i++) { 655 device = devs[i]; 656 657 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 658 (locators[PCICF_DEV] != device)) 659 continue; 660 661 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 662 663 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 664 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 665 continue; 666 667 id = pci_conf_read(pc, tag, PCI_ID_REG); 668 669 /* Invalid vendor ID value? */ 670 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 671 continue; 672 /* XXX Not invalid, but we've done this ~forever. */ 673 if (PCI_VENDOR(id) == 0) 674 continue; 675 676 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 677 678 if (qd != NULL && 679 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 680 nfunctions = 8; 681 else if (qd != NULL && 682 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 683 nfunctions = 1; 684 else 685 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 686 687 #ifdef __PCI_DEV_FUNCORDER 688 char funcs[8]; 689 int j; 690 for (j = 0; j < nfunctions; j++) { 691 funcs[j] = j; 692 } 693 if (j < __arraycount(funcs)) 694 funcs[j] = -1; 695 if (nfunctions > 1) { 696 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 697 nfunctions, funcs); 698 } 699 for (j = 0; 700 j < 8 && (function = funcs[j]) < 8 && function >= 0; 701 j++) { 702 #else 703 for (function = 0; function < nfunctions; function++) { 704 #endif 705 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 706 && (locators[PCICF_FUNCTION] != function)) 707 continue; 708 709 if (qd != NULL && 710 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 711 continue; 712 tag = pci_make_tag(pc, sc->sc_bus, device, function); 713 ret = pci_probe_device(sc, tag, match, pap); 714 if (match != NULL && ret != 0) 715 return ret; 716 } 717 } 718 return 0; 719 } 720 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 721 722 723 /* 724 * Vital Product Data (PCI 2.2) 725 */ 726 727 int 728 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 729 pcireg_t *data) 730 { 731 uint32_t reg; 732 int ofs, i, j; 733 734 KASSERT(data != NULL); 735 KASSERT((offset + count) < 0x7fff); 736 737 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 738 return 1; 739 740 for (i = 0; i < count; offset += sizeof(*data), i++) { 741 reg &= 0x0000ffff; 742 reg &= ~PCI_VPD_OPFLAG; 743 reg |= PCI_VPD_ADDRESS(offset); 744 pci_conf_write(pc, tag, ofs, reg); 745 746 /* 747 * PCI 2.2 does not specify how long we should poll 748 * for completion nor whether the operation can fail. 749 */ 750 j = 0; 751 do { 752 if (j++ == 20) 753 return 1; 754 delay(4); 755 reg = pci_conf_read(pc, tag, ofs); 756 } while ((reg & PCI_VPD_OPFLAG) == 0); 757 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 758 } 759 760 return 0; 761 } 762 763 int 764 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 765 pcireg_t *data) 766 { 767 pcireg_t reg; 768 int ofs, i, j; 769 770 KASSERT(data != NULL); 771 KASSERT((offset + count) < 0x7fff); 772 773 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 774 return 1; 775 776 for (i = 0; i < count; offset += sizeof(*data), i++) { 777 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 778 779 reg &= 0x0000ffff; 780 reg |= PCI_VPD_OPFLAG; 781 reg |= PCI_VPD_ADDRESS(offset); 782 pci_conf_write(pc, tag, ofs, reg); 783 784 /* 785 * PCI 2.2 does not specify how long we should poll 786 * for completion nor whether the operation can fail. 787 */ 788 j = 0; 789 do { 790 if (j++ == 20) 791 return 1; 792 delay(1); 793 reg = pci_conf_read(pc, tag, ofs); 794 } while (reg & PCI_VPD_OPFLAG); 795 } 796 797 return 0; 798 } 799 800 int 801 pci_dma64_available(const struct pci_attach_args *pa) 802 { 803 #ifdef _PCI_HAVE_DMA64 804 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 805 return 1; 806 #endif 807 return 0; 808 } 809 810 void 811 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 812 struct pci_conf_state *pcs) 813 { 814 int off; 815 816 for (off = 0; off < 16; off++) 817 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 818 819 return; 820 } 821 822 void 823 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 824 struct pci_conf_state *pcs) 825 { 826 int off; 827 pcireg_t val; 828 829 for (off = 15; off >= 0; off--) { 830 val = pci_conf_read(pc, tag, (off * 4)); 831 if (val != pcs->reg[off]) 832 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 833 } 834 835 return; 836 } 837 838 /* 839 * Power Management Capability (Rev 2.2) 840 */ 841 static int 842 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 843 int offset) 844 { 845 pcireg_t value, now; 846 847 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 848 now = value & PCI_PMCSR_STATE_MASK; 849 switch (now) { 850 case PCI_PMCSR_STATE_D0: 851 case PCI_PMCSR_STATE_D1: 852 case PCI_PMCSR_STATE_D2: 853 case PCI_PMCSR_STATE_D3: 854 *state = now; 855 return 0; 856 default: 857 return EINVAL; 858 } 859 } 860 861 int 862 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 863 { 864 int offset; 865 pcireg_t value; 866 867 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 868 return EOPNOTSUPP; 869 870 return pci_get_powerstate_int(pc, tag, state, offset); 871 } 872 873 static int 874 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 875 int offset, pcireg_t cap_reg) 876 { 877 pcireg_t value, cap, now; 878 879 cap = cap_reg >> PCI_PMCR_SHIFT; 880 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 881 now = value & PCI_PMCSR_STATE_MASK; 882 value &= ~PCI_PMCSR_STATE_MASK; 883 884 if (now == state) 885 return 0; 886 switch (state) { 887 case PCI_PMCSR_STATE_D0: 888 break; 889 case PCI_PMCSR_STATE_D1: 890 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 891 printf("invalid transition from %d to D1\n", (int)now); 892 return EINVAL; 893 } 894 if (!(cap & PCI_PMCR_D1SUPP)) { 895 printf("D1 not supported\n"); 896 return EOPNOTSUPP; 897 } 898 break; 899 case PCI_PMCSR_STATE_D2: 900 if (now == PCI_PMCSR_STATE_D3) { 901 printf("invalid transition from %d to D2\n", (int)now); 902 return EINVAL; 903 } 904 if (!(cap & PCI_PMCR_D2SUPP)) { 905 printf("D2 not supported\n"); 906 return EOPNOTSUPP; 907 } 908 break; 909 case PCI_PMCSR_STATE_D3: 910 break; 911 default: 912 return EINVAL; 913 } 914 value |= state; 915 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 916 /* delay according to pcipm1.2, ch. 5.6.1 */ 917 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 918 DELAY(10000); 919 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 920 DELAY(200); 921 922 return 0; 923 } 924 925 int 926 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 927 { 928 int offset; 929 pcireg_t value; 930 931 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 932 printf("pci_set_powerstate not supported\n"); 933 return EOPNOTSUPP; 934 } 935 936 return pci_set_powerstate_int(pc, tag, state, offset, value); 937 } 938 939 int 940 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 941 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 942 { 943 pcireg_t pmode; 944 int error; 945 946 if ((error = pci_get_powerstate(pc, tag, &pmode))) 947 return error; 948 949 switch (pmode) { 950 case PCI_PMCSR_STATE_D0: 951 break; 952 case PCI_PMCSR_STATE_D3: 953 if (wakefun == NULL) { 954 /* 955 * The card has lost all configuration data in 956 * this state, so punt. 957 */ 958 aprint_error_dev(dev, 959 "unable to wake up from power state D3\n"); 960 return EOPNOTSUPP; 961 } 962 /*FALLTHROUGH*/ 963 default: 964 if (wakefun) { 965 error = (*wakefun)(pc, tag, dev, pmode); 966 if (error) 967 return error; 968 } 969 aprint_normal_dev(dev, "waking up from power state D%d\n", 970 pmode); 971 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 972 return error; 973 } 974 return 0; 975 } 976 977 int 978 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 979 device_t dev, pcireg_t state) 980 { 981 return 0; 982 } 983 984 struct pci_child_power { 985 struct pci_conf_state p_pciconf; 986 pci_chipset_tag_t p_pc; 987 pcitag_t p_tag; 988 bool p_has_pm; 989 int p_pm_offset; 990 pcireg_t p_pm_cap; 991 pcireg_t p_class; 992 pcireg_t p_csr; 993 }; 994 995 static bool 996 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 997 { 998 struct pci_child_power *priv = device_pmf_bus_private(dv); 999 pcireg_t ocsr, csr; 1000 1001 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1002 1003 if (!priv->p_has_pm) 1004 return true; /* ??? hopefully handled by ACPI */ 1005 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1006 return true; /* XXX */ 1007 1008 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1009 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1010 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1011 | PCI_COMMAND_MASTER_ENABLE); 1012 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1013 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1014 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1015 pci_conf_write(priv->p_pc, priv->p_tag, 1016 PCI_COMMAND_STATUS_REG, ocsr); 1017 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1018 return false; 1019 } 1020 return true; 1021 } 1022 1023 static bool 1024 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1025 { 1026 struct pci_child_power *priv = device_pmf_bus_private(dv); 1027 1028 if (priv->p_has_pm && 1029 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1030 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1031 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1032 return false; 1033 } 1034 1035 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1036 1037 return true; 1038 } 1039 1040 static bool 1041 pci_child_shutdown(device_t dv, int how) 1042 { 1043 struct pci_child_power *priv = device_pmf_bus_private(dv); 1044 pcireg_t csr; 1045 1046 /* restore original bus-mastering state */ 1047 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1048 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1049 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1050 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1051 return true; 1052 } 1053 1054 static void 1055 pci_child_deregister(device_t dv) 1056 { 1057 struct pci_child_power *priv = device_pmf_bus_private(dv); 1058 1059 free(priv, M_DEVBUF); 1060 } 1061 1062 static bool 1063 pci_child_register(device_t child) 1064 { 1065 device_t self = device_parent(child); 1066 struct pci_softc *sc = device_private(self); 1067 struct pci_child_power *priv; 1068 int device, function, off; 1069 pcireg_t reg; 1070 1071 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1072 1073 device = device_locator(child, PCICF_DEV); 1074 function = device_locator(child, PCICF_FUNCTION); 1075 1076 priv->p_pc = sc->sc_pc; 1077 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1078 function); 1079 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1080 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1081 PCI_COMMAND_STATUS_REG); 1082 1083 if (pci_get_capability(priv->p_pc, priv->p_tag, 1084 PCI_CAP_PWRMGMT, &off, ®)) { 1085 priv->p_has_pm = true; 1086 priv->p_pm_offset = off; 1087 priv->p_pm_cap = reg; 1088 } else { 1089 priv->p_has_pm = false; 1090 priv->p_pm_offset = -1; 1091 } 1092 1093 device_pmf_bus_register(child, priv, pci_child_suspend, 1094 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1095 1096 return true; 1097 } 1098 1099 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1100 1101 static int 1102 pci_modcmd(modcmd_t cmd, void *priv) 1103 { 1104 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1105 return 0; 1106 return ENOTTY; 1107 } 1108
Indexes created Tue Sep 23 07:09:52 GMT 2025