pci.c revision 1.156
1 /* $NetBSD: pci.c,v 1.156 2019/10/15 13:27:11 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.156 2019/10/15 13:27:11 jmcneill Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <net/if.h> 57 58 #include "locators.h" 59 60 static bool pci_child_register(device_t); 61 62 #ifdef PCI_CONFIG_DUMP 63 int pci_config_dump = 1; 64 #else 65 int pci_config_dump = 0; 66 #endif 67 68 int pciprint(void *, const char *); 69 70 #ifdef PCI_MACHDEP_ENUMERATE_BUS 71 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(const struct pci_attach_args *), 273 struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 278 #ifdef __HAVE_PCI_MSI_MSIX 279 pcireg_t cap; 280 int off; 281 #endif 282 int ret, pin, bus, device, function, i, width; 283 int locs[PCICF_NLOCS]; 284 285 pci_decompose_tag(pc, tag, &bus, &device, &function); 286 287 /* a driver already attached? */ 288 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 289 return 0; 290 291 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 292 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 293 return 0; 294 295 id = pci_conf_read(pc, tag, PCI_ID_REG); 296 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 297 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 298 299 /* Invalid vendor ID value? */ 300 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 301 return 0; 302 /* XXX Not invalid, but we've done this ~forever. */ 303 if (PCI_VENDOR(id) == 0) 304 return 0; 305 306 /* Collect memory range info */ 307 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 308 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 309 i = 0; 310 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 311 case PCI_HDRTYPE_PPB: 312 endbar = PCI_MAPREG_PPB_END; 313 break; 314 case PCI_HDRTYPE_PCB: 315 endbar = PCI_MAPREG_PCB_END; 316 break; 317 default: 318 endbar = PCI_MAPREG_END; 319 break; 320 } 321 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 322 struct pci_range *r; 323 pcireg_t type; 324 325 width = 4; 326 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 327 continue; 328 329 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 330 if (PCI_MAPREG_MEM_TYPE(type) == 331 PCI_MAPREG_MEM_TYPE_64BIT) 332 width = 8; 333 334 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 335 if (pci_mapreg_info(pc, tag, bar, type, 336 &r->r_offset, &r->r_size, &r->r_flags) != 0) 337 break; 338 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 339 && (r->r_size == 0x1000000)) { 340 struct pci_range *nr; 341 /* 342 * this has to be a mach64 343 * split things up so each half-aperture can 344 * be mapped PREFETCHABLE except the last page 345 * which may contain registers 346 */ 347 r->r_size = 0x7ff000; 348 r->r_flags = BUS_SPACE_MAP_LINEAR | 349 BUS_SPACE_MAP_PREFETCHABLE; 350 nr = &sc->PCI_SC_DEVICESC(device, 351 function).c_range[i++]; 352 nr->r_offset = r->r_offset + 0x800000; 353 nr->r_size = 0x7ff000; 354 nr->r_flags = BUS_SPACE_MAP_LINEAR | 355 BUS_SPACE_MAP_PREFETCHABLE; 356 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 357 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 358 (bar == 0x10)) { 359 r->r_flags = BUS_SPACE_MAP_LINEAR | 360 BUS_SPACE_MAP_PREFETCHABLE; 361 } 362 } 363 } 364 365 pa.pa_iot = sc->sc_iot; 366 pa.pa_memt = sc->sc_memt; 367 pa.pa_dmat = sc->sc_dmat; 368 pa.pa_dmat64 = sc->sc_dmat64; 369 pa.pa_pc = pc; 370 pa.pa_bus = bus; 371 pa.pa_device = device; 372 pa.pa_function = function; 373 pa.pa_tag = tag; 374 pa.pa_id = id; 375 pa.pa_class = pciclass; 376 377 /* 378 * Set up memory, I/O enable, and PCI command flags 379 * as appropriate. 380 */ 381 pa.pa_flags = sc->sc_flags; 382 383 /* 384 * If the cache line size is not configured, then 385 * clear the MRL/MRM/MWI command-ok flags. 386 */ 387 if (PCI_CACHELINE(bhlcr) == 0) { 388 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 389 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 390 } 391 392 if (sc->sc_bridgetag == NULL) { 393 pa.pa_intrswiz = 0; 394 pa.pa_intrtag = tag; 395 } else { 396 pa.pa_intrswiz = sc->sc_intrswiz + device; 397 pa.pa_intrtag = sc->sc_intrtag; 398 } 399 400 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 401 402 pin = PCI_INTERRUPT_PIN(intr); 403 pa.pa_rawintrpin = pin; 404 if (pin == PCI_INTERRUPT_PIN_NONE) { 405 /* no interrupt */ 406 pa.pa_intrpin = 0; 407 } else { 408 /* 409 * swizzle it based on the number of busses we're 410 * behind and our device number. 411 */ 412 pa.pa_intrpin = /* XXX */ 413 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 414 } 415 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 416 417 #ifdef __HAVE_PCI_MSI_MSIX 418 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 419 /* 420 * XXX Should we enable MSI mapping ourselves on 421 * systems that have it disabled? 422 */ 423 if (cap & PCI_HT_MSI_ENABLED) { 424 uint64_t addr; 425 if ((cap & PCI_HT_MSI_FIXED) == 0) { 426 addr = pci_conf_read(pc, tag, 427 off + PCI_HT_MSI_ADDR_LO); 428 addr |= (uint64_t)pci_conf_read(pc, tag, 429 off + PCI_HT_MSI_ADDR_HI) << 32; 430 } else 431 addr = PCI_HT_MSI_FIXED_ADDR; 432 433 /* 434 * XXX This will fail to enable MSI on systems 435 * that don't use the canonical address. 436 */ 437 if (addr == PCI_HT_MSI_FIXED_ADDR) { 438 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 439 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 440 } else 441 aprint_verbose_dev(sc->sc_dev, 442 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 443 } 444 } 445 #endif 446 447 if (match != NULL) { 448 ret = (*match)(&pa); 449 if (ret != 0 && pap != NULL) 450 *pap = pa; 451 } else { 452 struct pci_child *c; 453 locs[PCICF_DEV] = device; 454 locs[PCICF_FUNCTION] = function; 455 456 c = &sc->PCI_SC_DEVICESC(device, function); 457 pci_conf_capture(pc, tag, &c->c_conf); 458 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 459 c->c_psok = true; 460 else 461 c->c_psok = false; 462 463 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 464 pciprint, config_stdsubmatch); 465 466 ret = (c->c_dev != NULL); 467 } 468 469 return ret; 470 } 471 472 void 473 pcidevdetached(device_t self, device_t child) 474 { 475 struct pci_softc *sc = device_private(self); 476 int d, f; 477 pcitag_t tag; 478 struct pci_child *c; 479 480 d = device_locator(child, PCICF_DEV); 481 f = device_locator(child, PCICF_FUNCTION); 482 483 c = &sc->PCI_SC_DEVICESC(d, f); 484 485 KASSERT(c->c_dev == child); 486 487 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 488 if (c->c_psok) 489 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 490 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 491 c->c_dev = NULL; 492 } 493 494 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 495 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 496 DVF_DETACH_SHUTDOWN); 497 498 int 499 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 500 int *offset, pcireg_t *value) 501 { 502 pcireg_t reg; 503 unsigned int ofs; 504 505 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 506 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 507 return 0; 508 509 /* Determine the Capability List Pointer register to start with. */ 510 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 511 switch (PCI_HDRTYPE_TYPE(reg)) { 512 case 0: /* standard device header */ 513 case 1: /* PCI-PCI bridge header */ 514 ofs = PCI_CAPLISTPTR_REG; 515 break; 516 case 2: /* PCI-CardBus Bridge header */ 517 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 518 break; 519 default: 520 return 0; 521 } 522 523 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 524 while (ofs != 0) { 525 if ((ofs & 3) || (ofs < 0x40)) { 526 int bus, device, function; 527 528 pci_decompose_tag(pc, tag, &bus, &device, &function); 529 530 printf("Skipping broken PCI header on %d:%d:%d\n", 531 bus, device, function); 532 break; 533 } 534 reg = pci_conf_read(pc, tag, ofs); 535 if (PCI_CAPLIST_CAP(reg) == capid) { 536 if (offset) 537 *offset = ofs; 538 if (value) 539 *value = reg; 540 return 1; 541 } 542 ofs = PCI_CAPLIST_NEXT(reg); 543 } 544 545 return 0; 546 } 547 548 int 549 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 550 int *offset, pcireg_t *value) 551 { 552 pcireg_t reg; 553 unsigned int ofs; 554 555 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 556 return 0; 557 558 while (ofs != 0) { 559 #ifdef DIAGNOSTIC 560 if ((ofs & 3) || (ofs < 0x40)) 561 panic("pci_get_ht_capability"); 562 #endif 563 reg = pci_conf_read(pc, tag, ofs); 564 if (PCI_HT_CAP(reg) == capid) { 565 if (offset) 566 *offset = ofs; 567 if (value) 568 *value = reg; 569 return 1; 570 } 571 ofs = PCI_CAPLIST_NEXT(reg); 572 } 573 574 return 0; 575 } 576 577 /* 578 * return number of the devices's MSI vectors 579 * return 0 if the device does not support MSI 580 */ 581 int 582 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 583 { 584 pcireg_t reg; 585 uint32_t mmc; 586 int count, offset; 587 588 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 589 return 0; 590 591 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 592 mmc = PCI_MSI_CTL_MMC(reg); 593 count = 1 << mmc; 594 if (count > PCI_MSI_MAX_VECTORS) { 595 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 596 return 0; 597 } 598 599 return count; 600 } 601 602 /* 603 * return number of the devices's MSI-X vectors 604 * return 0 if the device does not support MSI-X 605 */ 606 int 607 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 608 { 609 pcireg_t reg; 610 int offset; 611 612 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 613 return 0; 614 615 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 616 617 return PCI_MSIX_CTL_TBLSIZE(reg); 618 } 619 620 int 621 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 622 int *offset, pcireg_t *value) 623 { 624 pcireg_t reg; 625 unsigned int ofs; 626 627 /* Only supported for PCI-express devices */ 628 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 629 return 0; 630 631 ofs = PCI_EXTCAPLIST_BASE; 632 reg = pci_conf_read(pc, tag, ofs); 633 if (reg == 0xffffffff || reg == 0) 634 return 0; 635 636 for (;;) { 637 #ifdef DIAGNOSTIC 638 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 639 panic("%s: invalid offset %u", __func__, ofs); 640 #endif 641 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 642 if (offset != NULL) 643 *offset = ofs; 644 if (value != NULL) 645 *value = reg; 646 return 1; 647 } 648 ofs = PCI_EXTCAPLIST_NEXT(reg); 649 if (ofs == 0) 650 break; 651 reg = pci_conf_read(pc, tag, ofs); 652 } 653 654 return 0; 655 } 656 657 int 658 pci_find_device(struct pci_attach_args *pa, 659 int (*match)(const struct pci_attach_args *)) 660 { 661 extern struct cfdriver pci_cd; 662 device_t pcidev; 663 int i; 664 static const int wildcard[2] = { 665 PCICF_DEV_DEFAULT, 666 PCICF_FUNCTION_DEFAULT 667 }; 668 669 for (i = 0; i < pci_cd.cd_ndevs; i++) { 670 pcidev = device_lookup(&pci_cd, i); 671 if (pcidev != NULL && 672 pci_enumerate_bus(device_private(pcidev), wildcard, 673 match, pa) != 0) 674 return 1; 675 } 676 return 0; 677 } 678 679 #ifndef PCI_MACHDEP_ENUMERATE_BUS 680 /* 681 * Generic PCI bus enumeration routine. Used unless machine-dependent 682 * code needs to provide something else. 683 */ 684 int 685 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 686 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 687 { 688 pci_chipset_tag_t pc = sc->sc_pc; 689 int device, function, nfunctions, ret; 690 const struct pci_quirkdata *qd; 691 pcireg_t id, bhlcr; 692 pcitag_t tag; 693 uint8_t devs[32]; 694 int i, n; 695 696 device_t bridgedev; 697 bool arien = false; 698 bool downstream_port = false; 699 700 /* Check PCIe ARI and port type */ 701 bridgedev = device_parent(sc->sc_dev); 702 if (device_is_a(bridgedev, "ppb")) { 703 struct ppb_softc *ppbsc = device_private(bridgedev); 704 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 705 pcitag_t ppbtag = ppbsc->sc_tag; 706 pcireg_t pciecap, capreg, reg; 707 708 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 709 &pciecap, &capreg) != 0) { 710 switch (PCIE_XCAP_TYPE(capreg)) { 711 case PCIE_XCAP_TYPE_ROOT: 712 case PCIE_XCAP_TYPE_DOWN: 713 case PCIE_XCAP_TYPE_PCI2PCIE: 714 downstream_port = true; 715 break; 716 } 717 718 reg = pci_conf_read(ppbpc, ppbtag, pciecap 719 + PCIE_DCSR2); 720 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 721 arien = true; 722 } 723 } 724 725 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 726 if (downstream_port) { 727 /* PCIe downstream ports only have a single child device */ 728 n = 1; 729 } 730 731 for (i = 0; i < n; i++) { 732 device = devs[i]; 733 734 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 735 (locators[PCICF_DEV] != device)) 736 continue; 737 738 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 739 740 id = pci_conf_read(pc, tag, PCI_ID_REG); 741 742 /* Invalid vendor ID value? */ 743 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 744 continue; 745 /* XXX Not invalid, but we've done this ~forever. */ 746 if (PCI_VENDOR(id) == 0) 747 continue; 748 749 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 750 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 751 continue; 752 753 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 754 755 if (qd != NULL && 756 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 757 nfunctions = 8; 758 else if (qd != NULL && 759 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 760 nfunctions = 1; 761 else if (arien) 762 nfunctions = 8; /* Scan all if ARI is enabled */ 763 else 764 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 765 766 #ifdef __PCI_DEV_FUNCORDER 767 char funcs[8]; 768 int j; 769 for (j = 0; j < nfunctions; j++) { 770 funcs[j] = j; 771 } 772 if (j < __arraycount(funcs)) 773 funcs[j] = -1; 774 if (nfunctions > 1) { 775 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 776 nfunctions, funcs); 777 } 778 for (j = 0; 779 j < 8 && (function = funcs[j]) < 8 && function >= 0; 780 j++) { 781 #else 782 for (function = 0; function < nfunctions; function++) { 783 #endif 784 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 785 && (locators[PCICF_FUNCTION] != function)) 786 continue; 787 788 if (qd != NULL && 789 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 790 continue; 791 tag = pci_make_tag(pc, sc->sc_bus, device, function); 792 ret = pci_probe_device(sc, tag, match, pap); 793 if (match != NULL && ret != 0) 794 return ret; 795 } 796 } 797 return 0; 798 } 799 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 800 801 802 /* 803 * Vital Product Data (PCI 2.2) 804 */ 805 806 int 807 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 808 pcireg_t *data) 809 { 810 uint32_t reg; 811 int ofs, i, j; 812 813 KASSERT(data != NULL); 814 KASSERT((offset + count) < 0x7fff); 815 816 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 817 return 1; 818 819 for (i = 0; i < count; offset += sizeof(*data), i++) { 820 reg &= 0x0000ffff; 821 reg &= ~PCI_VPD_OPFLAG; 822 reg |= PCI_VPD_ADDRESS(offset); 823 pci_conf_write(pc, tag, ofs, reg); 824 825 /* 826 * PCI 2.2 does not specify how long we should poll 827 * for completion nor whether the operation can fail. 828 */ 829 j = 0; 830 do { 831 if (j++ == 20) 832 return 1; 833 delay(4); 834 reg = pci_conf_read(pc, tag, ofs); 835 } while ((reg & PCI_VPD_OPFLAG) == 0); 836 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 837 } 838 839 return 0; 840 } 841 842 int 843 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 844 pcireg_t *data) 845 { 846 pcireg_t reg; 847 int ofs, i, j; 848 849 KASSERT(data != NULL); 850 KASSERT((offset + count) < 0x7fff); 851 852 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 853 return 1; 854 855 for (i = 0; i < count; offset += sizeof(*data), i++) { 856 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 857 858 reg &= 0x0000ffff; 859 reg |= PCI_VPD_OPFLAG; 860 reg |= PCI_VPD_ADDRESS(offset); 861 pci_conf_write(pc, tag, ofs, reg); 862 863 /* 864 * PCI 2.2 does not specify how long we should poll 865 * for completion nor whether the operation can fail. 866 */ 867 j = 0; 868 do { 869 if (j++ == 20) 870 return 1; 871 delay(1); 872 reg = pci_conf_read(pc, tag, ofs); 873 } while (reg & PCI_VPD_OPFLAG); 874 } 875 876 return 0; 877 } 878 879 int 880 pci_dma64_available(const struct pci_attach_args *pa) 881 { 882 #ifdef _PCI_HAVE_DMA64 883 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 884 return 1; 885 #endif 886 return 0; 887 } 888 889 void 890 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 891 struct pci_conf_state *pcs) 892 { 893 int off; 894 895 for (off = 0; off < 16; off++) 896 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 897 898 /* For PCI-X */ 899 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 900 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 901 902 /* For PCIe */ 903 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 904 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 905 unsigned int devtype; 906 907 devtype = PCIE_XCAP_TYPE(xcap); 908 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 909 910 if (PCIE_HAS_LINKREGS(devtype)) 911 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 912 off + PCIE_LCSR); 913 914 if ((xcap & PCIE_XCAP_SI) != 0) 915 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 916 off + PCIE_SLCSR); 917 918 if (PCIE_HAS_ROOTREGS(devtype)) 919 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 920 off + PCIE_RCR); 921 922 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 923 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 924 off + PCIE_DCSR2); 925 926 if (PCIE_HAS_LINKREGS(devtype)) 927 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 928 off + PCIE_LCSR2); 929 930 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 931 } 932 } 933 934 /* For MSI */ 935 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 936 bool bit64, pvmask; 937 938 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 939 940 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 941 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 942 943 /* Address */ 944 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 945 if (bit64) 946 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 947 off + PCI_MSI_MADDR64_HI); 948 949 /* Data */ 950 pcs->msi_mdata = pci_conf_read(pc, tag, 951 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 952 953 /* Per-vector masking */ 954 if (pvmask) 955 pcs->msi_mask = pci_conf_read(pc, tag, 956 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 957 } 958 959 /* For MSI-X */ 960 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 961 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 962 } 963 964 void 965 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 966 struct pci_conf_state *pcs) 967 { 968 int off; 969 pcireg_t val; 970 971 for (off = 15; off >= 0; off--) { 972 val = pci_conf_read(pc, tag, (off * 4)); 973 if (val != pcs->reg[off]) 974 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 975 } 976 977 /* For PCI-X */ 978 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 979 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 980 981 /* For PCIe */ 982 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 983 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 984 unsigned int devtype; 985 986 devtype = PCIE_XCAP_TYPE(xcap); 987 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 988 989 /* 990 * PCIe capability is variable sized. To not to write the next 991 * area, check the existence of each register. 992 */ 993 if (PCIE_HAS_LINKREGS(devtype)) 994 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 995 996 if ((xcap & PCIE_XCAP_SI) != 0) 997 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 998 999 if (PCIE_HAS_ROOTREGS(devtype)) 1000 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1001 1002 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1003 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1004 1005 if (PCIE_HAS_LINKREGS(devtype)) 1006 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1007 pcs->e_lcr2); 1008 1009 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1010 } 1011 } 1012 1013 /* For MSI */ 1014 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1015 pcireg_t reg; 1016 bool bit64, pvmask; 1017 1018 /* First, drop Enable bit in case it's already set. */ 1019 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1020 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1021 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1022 1023 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1024 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1025 1026 /* Address */ 1027 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1028 1029 if (bit64) 1030 pci_conf_write(pc, tag, 1031 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1032 1033 /* Data */ 1034 pci_conf_write(pc, tag, 1035 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1036 pcs->msi_mdata); 1037 1038 /* Per-vector masking */ 1039 if (pvmask) 1040 pci_conf_write(pc, tag, 1041 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1042 pcs->msi_mask); 1043 1044 /* Write CTRL register in the end */ 1045 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1046 } 1047 1048 /* For MSI-X */ 1049 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1050 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1051 } 1052 1053 /* 1054 * Power Management Capability (Rev 2.2) 1055 */ 1056 static int 1057 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1058 int offset) 1059 { 1060 pcireg_t value, now; 1061 1062 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1063 now = value & PCI_PMCSR_STATE_MASK; 1064 switch (now) { 1065 case PCI_PMCSR_STATE_D0: 1066 case PCI_PMCSR_STATE_D1: 1067 case PCI_PMCSR_STATE_D2: 1068 case PCI_PMCSR_STATE_D3: 1069 *state = now; 1070 return 0; 1071 default: 1072 return EINVAL; 1073 } 1074 } 1075 1076 int 1077 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1078 { 1079 int offset; 1080 pcireg_t value; 1081 1082 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1083 return EOPNOTSUPP; 1084 1085 return pci_get_powerstate_int(pc, tag, state, offset); 1086 } 1087 1088 static int 1089 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1090 int offset, pcireg_t cap_reg) 1091 { 1092 pcireg_t value, cap, now; 1093 1094 cap = cap_reg >> PCI_PMCR_SHIFT; 1095 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1096 now = value & PCI_PMCSR_STATE_MASK; 1097 value &= ~PCI_PMCSR_STATE_MASK; 1098 1099 if (now == state) 1100 return 0; 1101 switch (state) { 1102 case PCI_PMCSR_STATE_D0: 1103 break; 1104 case PCI_PMCSR_STATE_D1: 1105 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1106 printf("invalid transition from %d to D1\n", (int)now); 1107 return EINVAL; 1108 } 1109 if (!(cap & PCI_PMCR_D1SUPP)) { 1110 printf("D1 not supported\n"); 1111 return EOPNOTSUPP; 1112 } 1113 break; 1114 case PCI_PMCSR_STATE_D2: 1115 if (now == PCI_PMCSR_STATE_D3) { 1116 printf("invalid transition from %d to D2\n", (int)now); 1117 return EINVAL; 1118 } 1119 if (!(cap & PCI_PMCR_D2SUPP)) { 1120 printf("D2 not supported\n"); 1121 return EOPNOTSUPP; 1122 } 1123 break; 1124 case PCI_PMCSR_STATE_D3: 1125 break; 1126 default: 1127 return EINVAL; 1128 } 1129 value |= state; 1130 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1131 /* delay according to pcipm1.2, ch. 5.6.1 */ 1132 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1133 DELAY(10000); 1134 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1135 DELAY(200); 1136 1137 return 0; 1138 } 1139 1140 int 1141 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1142 { 1143 int offset; 1144 pcireg_t value; 1145 1146 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1147 printf("pci_set_powerstate not supported\n"); 1148 return EOPNOTSUPP; 1149 } 1150 1151 return pci_set_powerstate_int(pc, tag, state, offset, value); 1152 } 1153 1154 int 1155 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1156 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1157 { 1158 pcireg_t pmode; 1159 int error; 1160 1161 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1162 return error; 1163 1164 switch (pmode) { 1165 case PCI_PMCSR_STATE_D0: 1166 break; 1167 case PCI_PMCSR_STATE_D3: 1168 if (wakefun == NULL) { 1169 /* 1170 * The card has lost all configuration data in 1171 * this state, so punt. 1172 */ 1173 aprint_error_dev(dev, 1174 "unable to wake up from power state D3\n"); 1175 return EOPNOTSUPP; 1176 } 1177 /*FALLTHROUGH*/ 1178 default: 1179 if (wakefun) { 1180 error = (*wakefun)(pc, tag, dev, pmode); 1181 if (error) 1182 return error; 1183 } 1184 aprint_normal_dev(dev, "waking up from power state D%d\n", 1185 pmode); 1186 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1187 return error; 1188 } 1189 return 0; 1190 } 1191 1192 int 1193 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1194 device_t dev, pcireg_t state) 1195 { 1196 return 0; 1197 } 1198 1199 struct pci_child_power { 1200 struct pci_conf_state p_pciconf; 1201 pci_chipset_tag_t p_pc; 1202 pcitag_t p_tag; 1203 bool p_has_pm; 1204 int p_pm_offset; 1205 pcireg_t p_pm_cap; 1206 pcireg_t p_class; 1207 pcireg_t p_csr; 1208 }; 1209 1210 static bool 1211 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1212 { 1213 struct pci_child_power *priv = device_pmf_bus_private(dv); 1214 pcireg_t ocsr, csr; 1215 1216 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1217 1218 if (!priv->p_has_pm) 1219 return true; /* ??? hopefully handled by ACPI */ 1220 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1221 return true; /* XXX */ 1222 1223 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1224 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1225 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1226 | PCI_COMMAND_MASTER_ENABLE); 1227 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1228 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1229 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1230 pci_conf_write(priv->p_pc, priv->p_tag, 1231 PCI_COMMAND_STATUS_REG, ocsr); 1232 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1233 return false; 1234 } 1235 return true; 1236 } 1237 1238 static void 1239 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1240 int off) 1241 { 1242 pcireg_t pmcsr; 1243 1244 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1245 1246 if (pmcsr & PCI_PMCSR_PME_STS) { 1247 /* Clear W1C bit */ 1248 pmcsr |= PCI_PMCSR_PME_STS; 1249 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1250 aprint_verbose_dev(dv, "Clear PME# now\n"); 1251 } 1252 } 1253 1254 static bool 1255 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1256 { 1257 struct pci_child_power *priv = device_pmf_bus_private(dv); 1258 1259 if (priv->p_has_pm) { 1260 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1261 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1262 aprint_error_dev(dv, 1263 "unsupported state, continuing.\n"); 1264 return false; 1265 } 1266 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1267 priv->p_pm_offset); 1268 } 1269 1270 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1271 1272 return true; 1273 } 1274 1275 static bool 1276 pci_child_shutdown(device_t dv, int how) 1277 { 1278 struct pci_child_power *priv = device_pmf_bus_private(dv); 1279 pcireg_t csr; 1280 1281 /* restore original bus-mastering state */ 1282 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1283 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1284 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1285 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1286 return true; 1287 } 1288 1289 static void 1290 pci_child_deregister(device_t dv) 1291 { 1292 struct pci_child_power *priv = device_pmf_bus_private(dv); 1293 1294 free(priv, M_DEVBUF); 1295 } 1296 1297 static bool 1298 pci_child_register(device_t child) 1299 { 1300 device_t self = device_parent(child); 1301 struct pci_softc *sc = device_private(self); 1302 struct pci_child_power *priv; 1303 int device, function, off; 1304 pcireg_t reg; 1305 1306 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1307 1308 device = device_locator(child, PCICF_DEV); 1309 function = device_locator(child, PCICF_FUNCTION); 1310 1311 priv->p_pc = sc->sc_pc; 1312 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1313 function); 1314 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1315 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1316 PCI_COMMAND_STATUS_REG); 1317 1318 if (pci_get_capability(priv->p_pc, priv->p_tag, 1319 PCI_CAP_PWRMGMT, &off, ®)) { 1320 priv->p_has_pm = true; 1321 priv->p_pm_offset = off; 1322 priv->p_pm_cap = reg; 1323 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1324 } else { 1325 priv->p_has_pm = false; 1326 priv->p_pm_offset = -1; 1327 } 1328 1329 device_pmf_bus_register(child, priv, pci_child_suspend, 1330 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1331 1332 return true; 1333 } 1334 1335 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1336 1337 static int 1338 pci_modcmd(modcmd_t cmd, void *priv) 1339 { 1340 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1341 return 0; 1342 return ENOTTY; 1343 } 1344
Indexes created Tue Sep 23 20:09:58 GMT 2025