pci.c revision 1.158
1 /* $NetBSD: pci.c,v 1.158 2021/01/29 06:00:08 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.158 2021/01/29 06:00:08 skrll Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <net/if.h> 57 58 #include "locators.h" 59 60 static bool pci_child_register(device_t); 61 62 #ifdef PCI_CONFIG_DUMP 63 int pci_config_dump = 1; 64 #else 65 int pci_config_dump = 0; 66 #endif 67 68 int pciprint(void *, const char *); 69 70 #ifdef PCI_MACHDEP_ENUMERATE_BUS 71 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(const struct pci_attach_args *), 273 struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 278 #ifdef __HAVE_PCI_MSI_MSIX 279 pcireg_t cap; 280 int off; 281 #endif 282 int ret, pin, bus, device, function, i, width; 283 int locs[PCICF_NLOCS]; 284 285 pci_decompose_tag(pc, tag, &bus, &device, &function); 286 287 /* a driver already attached? */ 288 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 289 return 0; 290 291 id = pci_conf_read(pc, tag, PCI_ID_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 301 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 302 return 0; 303 304 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 305 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 306 307 /* Collect memory range info */ 308 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 309 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 310 i = 0; 311 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 312 case PCI_HDRTYPE_PPB: 313 endbar = PCI_MAPREG_PPB_END; 314 break; 315 case PCI_HDRTYPE_PCB: 316 endbar = PCI_MAPREG_PCB_END; 317 break; 318 default: 319 endbar = PCI_MAPREG_END; 320 break; 321 } 322 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 323 struct pci_range *r; 324 pcireg_t type; 325 326 width = 4; 327 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 328 continue; 329 330 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 331 if (PCI_MAPREG_MEM_TYPE(type) == 332 PCI_MAPREG_MEM_TYPE_64BIT) 333 width = 8; 334 335 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 336 if (pci_mapreg_info(pc, tag, bar, type, 337 &r->r_offset, &r->r_size, &r->r_flags) != 0) 338 break; 339 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 340 && (r->r_size == 0x1000000)) { 341 struct pci_range *nr; 342 /* 343 * this has to be a mach64 344 * split things up so each half-aperture can 345 * be mapped PREFETCHABLE except the last page 346 * which may contain registers 347 */ 348 r->r_size = 0x7ff000; 349 r->r_flags = BUS_SPACE_MAP_LINEAR | 350 BUS_SPACE_MAP_PREFETCHABLE; 351 nr = &sc->PCI_SC_DEVICESC(device, 352 function).c_range[i++]; 353 nr->r_offset = r->r_offset + 0x800000; 354 nr->r_size = 0x7ff000; 355 nr->r_flags = BUS_SPACE_MAP_LINEAR | 356 BUS_SPACE_MAP_PREFETCHABLE; 357 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 358 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 359 (bar == 0x10)) { 360 r->r_flags = BUS_SPACE_MAP_LINEAR | 361 BUS_SPACE_MAP_PREFETCHABLE; 362 } 363 } 364 } 365 366 pa.pa_iot = sc->sc_iot; 367 pa.pa_memt = sc->sc_memt; 368 pa.pa_dmat = sc->sc_dmat; 369 pa.pa_dmat64 = sc->sc_dmat64; 370 pa.pa_pc = pc; 371 pa.pa_bus = bus; 372 pa.pa_device = device; 373 pa.pa_function = function; 374 pa.pa_tag = tag; 375 pa.pa_id = id; 376 pa.pa_class = pciclass; 377 378 /* 379 * Set up memory, I/O enable, and PCI command flags 380 * as appropriate. 381 */ 382 pa.pa_flags = sc->sc_flags; 383 384 /* 385 * If the cache line size is not configured, then 386 * clear the MRL/MRM/MWI command-ok flags. 387 */ 388 if (PCI_CACHELINE(bhlcr) == 0) { 389 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 390 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 391 } 392 393 if (sc->sc_bridgetag == NULL) { 394 pa.pa_intrswiz = 0; 395 pa.pa_intrtag = tag; 396 } else { 397 pa.pa_intrswiz = sc->sc_intrswiz + device; 398 pa.pa_intrtag = sc->sc_intrtag; 399 } 400 401 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 402 403 pin = PCI_INTERRUPT_PIN(intr); 404 pa.pa_rawintrpin = pin; 405 if (pin == PCI_INTERRUPT_PIN_NONE) { 406 /* no interrupt */ 407 pa.pa_intrpin = 0; 408 } else { 409 /* 410 * swizzle it based on the number of busses we're 411 * behind and our device number. 412 */ 413 pa.pa_intrpin = /* XXX */ 414 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 415 } 416 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 417 418 #ifdef __HAVE_PCI_MSI_MSIX 419 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 420 /* 421 * XXX Should we enable MSI mapping ourselves on 422 * systems that have it disabled? 423 */ 424 if (cap & PCI_HT_MSI_ENABLED) { 425 uint64_t addr; 426 if ((cap & PCI_HT_MSI_FIXED) == 0) { 427 addr = pci_conf_read(pc, tag, 428 off + PCI_HT_MSI_ADDR_LO); 429 addr |= (uint64_t)pci_conf_read(pc, tag, 430 off + PCI_HT_MSI_ADDR_HI) << 32; 431 } else 432 addr = PCI_HT_MSI_FIXED_ADDR; 433 434 /* 435 * XXX This will fail to enable MSI on systems 436 * that don't use the canonical address. 437 */ 438 if (addr == PCI_HT_MSI_FIXED_ADDR) { 439 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 440 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 441 } else 442 aprint_verbose_dev(sc->sc_dev, 443 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 444 } 445 } 446 #endif 447 448 if (match != NULL) { 449 ret = (*match)(&pa); 450 if (ret != 0 && pap != NULL) 451 *pap = pa; 452 } else { 453 struct pci_child *c; 454 locs[PCICF_DEV] = device; 455 locs[PCICF_FUNCTION] = function; 456 457 c = &sc->PCI_SC_DEVICESC(device, function); 458 pci_conf_capture(pc, tag, &c->c_conf); 459 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 460 c->c_psok = true; 461 else 462 c->c_psok = false; 463 464 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 465 pciprint, config_stdsubmatch); 466 467 ret = (c->c_dev != NULL); 468 } 469 470 return ret; 471 } 472 473 void 474 pcidevdetached(device_t self, device_t child) 475 { 476 struct pci_softc *sc = device_private(self); 477 int d, f; 478 pcitag_t tag; 479 struct pci_child *c; 480 481 d = device_locator(child, PCICF_DEV); 482 f = device_locator(child, PCICF_FUNCTION); 483 484 c = &sc->PCI_SC_DEVICESC(d, f); 485 486 KASSERT(c->c_dev == child); 487 488 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 489 if (c->c_psok) 490 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 491 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 492 c->c_dev = NULL; 493 } 494 495 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 496 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 497 DVF_DETACH_SHUTDOWN); 498 499 int 500 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 501 int *offset, pcireg_t *value) 502 { 503 pcireg_t reg; 504 unsigned int ofs; 505 506 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 507 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 508 return 0; 509 510 /* Determine the Capability List Pointer register to start with. */ 511 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 512 switch (PCI_HDRTYPE_TYPE(reg)) { 513 case 0: /* standard device header */ 514 case 1: /* PCI-PCI bridge header */ 515 ofs = PCI_CAPLISTPTR_REG; 516 break; 517 case 2: /* PCI-CardBus Bridge header */ 518 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 519 break; 520 default: 521 return 0; 522 } 523 524 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 525 while (ofs != 0) { 526 if ((ofs & 3) || (ofs < 0x40)) { 527 int bus, device, function; 528 529 pci_decompose_tag(pc, tag, &bus, &device, &function); 530 531 printf("Skipping broken PCI header on %d:%d:%d\n", 532 bus, device, function); 533 break; 534 } 535 reg = pci_conf_read(pc, tag, ofs); 536 if (PCI_CAPLIST_CAP(reg) == capid) { 537 if (offset) 538 *offset = ofs; 539 if (value) 540 *value = reg; 541 return 1; 542 } 543 ofs = PCI_CAPLIST_NEXT(reg); 544 } 545 546 return 0; 547 } 548 549 int 550 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 551 int *offset, pcireg_t *value) 552 { 553 pcireg_t reg; 554 unsigned int ofs; 555 556 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 557 return 0; 558 559 while (ofs != 0) { 560 #ifdef DIAGNOSTIC 561 if ((ofs & 3) || (ofs < 0x40)) 562 panic("pci_get_ht_capability"); 563 #endif 564 reg = pci_conf_read(pc, tag, ofs); 565 if (PCI_HT_CAP(reg) == capid) { 566 if (offset) 567 *offset = ofs; 568 if (value) 569 *value = reg; 570 return 1; 571 } 572 ofs = PCI_CAPLIST_NEXT(reg); 573 } 574 575 return 0; 576 } 577 578 /* 579 * return number of the devices's MSI vectors 580 * return 0 if the device does not support MSI 581 */ 582 int 583 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 584 { 585 pcireg_t reg; 586 uint32_t mmc; 587 int count, offset; 588 589 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 590 return 0; 591 592 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 593 mmc = PCI_MSI_CTL_MMC(reg); 594 count = 1 << mmc; 595 if (count > PCI_MSI_MAX_VECTORS) { 596 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 597 return 0; 598 } 599 600 return count; 601 } 602 603 /* 604 * return number of the devices's MSI-X vectors 605 * return 0 if the device does not support MSI-X 606 */ 607 int 608 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 609 { 610 pcireg_t reg; 611 int offset; 612 613 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 614 return 0; 615 616 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 617 618 return PCI_MSIX_CTL_TBLSIZE(reg); 619 } 620 621 int 622 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 623 int *offset, pcireg_t *value) 624 { 625 pcireg_t reg; 626 unsigned int ofs; 627 628 /* Only supported for PCI-express devices */ 629 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 630 return 0; 631 632 ofs = PCI_EXTCAPLIST_BASE; 633 reg = pci_conf_read(pc, tag, ofs); 634 if (reg == 0xffffffff || reg == 0) 635 return 0; 636 637 for (;;) { 638 #ifdef DIAGNOSTIC 639 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 640 panic("%s: invalid offset %u", __func__, ofs); 641 #endif 642 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 643 if (offset != NULL) 644 *offset = ofs; 645 if (value != NULL) 646 *value = reg; 647 return 1; 648 } 649 ofs = PCI_EXTCAPLIST_NEXT(reg); 650 if (ofs == 0) 651 break; 652 reg = pci_conf_read(pc, tag, ofs); 653 } 654 655 return 0; 656 } 657 658 int 659 pci_find_device(struct pci_attach_args *pa, 660 int (*match)(const struct pci_attach_args *)) 661 { 662 extern struct cfdriver pci_cd; 663 device_t pcidev; 664 int i; 665 static const int wildcard[2] = { 666 PCICF_DEV_DEFAULT, 667 PCICF_FUNCTION_DEFAULT 668 }; 669 670 for (i = 0; i < pci_cd.cd_ndevs; i++) { 671 pcidev = device_lookup(&pci_cd, i); 672 if (pcidev != NULL && 673 pci_enumerate_bus(device_private(pcidev), wildcard, 674 match, pa) != 0) 675 return 1; 676 } 677 return 0; 678 } 679 680 #ifndef PCI_MACHDEP_ENUMERATE_BUS 681 /* 682 * Generic PCI bus enumeration routine. Used unless machine-dependent 683 * code needs to provide something else. 684 */ 685 int 686 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 687 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 688 { 689 pci_chipset_tag_t pc = sc->sc_pc; 690 int device, function, nfunctions, ret; 691 const struct pci_quirkdata *qd; 692 pcireg_t id, bhlcr; 693 pcitag_t tag; 694 uint8_t devs[32]; 695 int i, n; 696 697 device_t bridgedev; 698 bool arien = false; 699 bool downstream_port = false; 700 701 /* Check PCIe ARI and port type */ 702 bridgedev = device_parent(sc->sc_dev); 703 if (device_is_a(bridgedev, "ppb")) { 704 struct ppb_softc *ppbsc = device_private(bridgedev); 705 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 706 pcitag_t ppbtag = ppbsc->sc_tag; 707 pcireg_t pciecap, capreg, reg; 708 709 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 710 &pciecap, &capreg) != 0) { 711 switch (PCIE_XCAP_TYPE(capreg)) { 712 case PCIE_XCAP_TYPE_ROOT: 713 case PCIE_XCAP_TYPE_DOWN: 714 case PCIE_XCAP_TYPE_PCI2PCIE: 715 downstream_port = true; 716 break; 717 } 718 719 reg = pci_conf_read(ppbpc, ppbtag, pciecap 720 + PCIE_DCSR2); 721 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 722 arien = true; 723 } 724 } 725 726 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 727 if (downstream_port) { 728 /* PCIe downstream ports only have a single child device */ 729 n = 1; 730 } 731 732 for (i = 0; i < n; i++) { 733 device = devs[i]; 734 735 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 736 (locators[PCICF_DEV] != device)) 737 continue; 738 739 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 740 741 id = pci_conf_read(pc, tag, PCI_ID_REG); 742 743 /* Invalid vendor ID value? */ 744 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 745 continue; 746 /* XXX Not invalid, but we've done this ~forever. */ 747 if (PCI_VENDOR(id) == 0) 748 continue; 749 750 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 751 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 752 continue; 753 754 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 755 756 if (qd != NULL && 757 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 758 nfunctions = 8; 759 else if (qd != NULL && 760 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 761 nfunctions = 1; 762 else if (arien) 763 nfunctions = 8; /* Scan all if ARI is enabled */ 764 else 765 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 766 767 #ifdef __PCI_DEV_FUNCORDER 768 char funcs[8]; 769 int j; 770 for (j = 0; j < nfunctions; j++) { 771 funcs[j] = j; 772 } 773 if (j < __arraycount(funcs)) 774 funcs[j] = -1; 775 if (nfunctions > 1) { 776 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 777 nfunctions, funcs); 778 } 779 for (j = 0; 780 j < 8 && (function = funcs[j]) < 8 && function >= 0; 781 j++) { 782 #else 783 for (function = 0; function < nfunctions; function++) { 784 #endif 785 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 786 && (locators[PCICF_FUNCTION] != function)) 787 continue; 788 789 if (qd != NULL && 790 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 791 continue; 792 tag = pci_make_tag(pc, sc->sc_bus, device, function); 793 ret = pci_probe_device(sc, tag, match, pap); 794 if (match != NULL && ret != 0) 795 return ret; 796 } 797 } 798 return 0; 799 } 800 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 801 802 803 /* 804 * Vital Product Data (PCI 2.2) 805 */ 806 807 int 808 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 809 pcireg_t *data) 810 { 811 uint32_t reg; 812 int ofs, i, j; 813 814 KASSERT(data != NULL); 815 KASSERT((offset + count) < 0x7fff); 816 817 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 818 return 1; 819 820 for (i = 0; i < count; offset += sizeof(*data), i++) { 821 reg &= 0x0000ffff; 822 reg &= ~PCI_VPD_OPFLAG; 823 reg |= PCI_VPD_ADDRESS(offset); 824 pci_conf_write(pc, tag, ofs, reg); 825 826 /* 827 * PCI 2.2 does not specify how long we should poll 828 * for completion nor whether the operation can fail. 829 */ 830 j = 0; 831 do { 832 if (j++ == 20) 833 return 1; 834 delay(4); 835 reg = pci_conf_read(pc, tag, ofs); 836 } while ((reg & PCI_VPD_OPFLAG) == 0); 837 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 838 } 839 840 return 0; 841 } 842 843 int 844 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 845 pcireg_t *data) 846 { 847 pcireg_t reg; 848 int ofs, i, j; 849 850 KASSERT(data != NULL); 851 KASSERT((offset + count) < 0x7fff); 852 853 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 854 return 1; 855 856 for (i = 0; i < count; offset += sizeof(*data), i++) { 857 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 858 859 reg &= 0x0000ffff; 860 reg |= PCI_VPD_OPFLAG; 861 reg |= PCI_VPD_ADDRESS(offset); 862 pci_conf_write(pc, tag, ofs, reg); 863 864 /* 865 * PCI 2.2 does not specify how long we should poll 866 * for completion nor whether the operation can fail. 867 */ 868 j = 0; 869 do { 870 if (j++ == 20) 871 return 1; 872 delay(1); 873 reg = pci_conf_read(pc, tag, ofs); 874 } while (reg & PCI_VPD_OPFLAG); 875 } 876 877 return 0; 878 } 879 880 int 881 pci_dma64_available(const struct pci_attach_args *pa) 882 { 883 #ifdef _PCI_HAVE_DMA64 884 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 885 return 1; 886 #endif 887 return 0; 888 } 889 890 void 891 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 892 struct pci_conf_state *pcs) 893 { 894 int off; 895 896 for (off = 0; off < 16; off++) 897 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 898 899 /* For PCI-X */ 900 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 901 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 902 903 /* For PCIe */ 904 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 905 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 906 unsigned int devtype; 907 908 devtype = PCIE_XCAP_TYPE(xcap); 909 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 910 911 if (PCIE_HAS_LINKREGS(devtype)) 912 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 913 off + PCIE_LCSR); 914 915 if ((xcap & PCIE_XCAP_SI) != 0) 916 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 917 off + PCIE_SLCSR); 918 919 if (PCIE_HAS_ROOTREGS(devtype)) 920 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 921 off + PCIE_RCR); 922 923 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 924 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 925 off + PCIE_DCSR2); 926 927 if (PCIE_HAS_LINKREGS(devtype)) 928 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 929 off + PCIE_LCSR2); 930 931 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 932 } 933 } 934 935 /* For MSI */ 936 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 937 bool bit64, pvmask; 938 939 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 940 941 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 942 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 943 944 /* Address */ 945 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 946 if (bit64) 947 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 948 off + PCI_MSI_MADDR64_HI); 949 950 /* Data */ 951 pcs->msi_mdata = pci_conf_read(pc, tag, 952 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 953 954 /* Per-vector masking */ 955 if (pvmask) 956 pcs->msi_mask = pci_conf_read(pc, tag, 957 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 958 } 959 960 /* For MSI-X */ 961 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 962 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 963 } 964 965 void 966 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 967 struct pci_conf_state *pcs) 968 { 969 int off; 970 pcireg_t val; 971 972 for (off = 15; off >= 0; off--) { 973 val = pci_conf_read(pc, tag, (off * 4)); 974 if (val != pcs->reg[off]) 975 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 976 } 977 978 /* For PCI-X */ 979 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 980 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 981 982 /* For PCIe */ 983 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 984 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 985 unsigned int devtype; 986 987 devtype = PCIE_XCAP_TYPE(xcap); 988 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 989 990 /* 991 * PCIe capability is variable sized. To not to write the next 992 * area, check the existence of each register. 993 */ 994 if (PCIE_HAS_LINKREGS(devtype)) 995 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 996 997 if ((xcap & PCIE_XCAP_SI) != 0) 998 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 999 1000 if (PCIE_HAS_ROOTREGS(devtype)) 1001 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1002 1003 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1004 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1005 1006 if (PCIE_HAS_LINKREGS(devtype)) 1007 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1008 pcs->e_lcr2); 1009 1010 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1011 } 1012 } 1013 1014 /* For MSI */ 1015 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1016 pcireg_t reg; 1017 bool bit64, pvmask; 1018 1019 /* First, drop Enable bit in case it's already set. */ 1020 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1021 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1022 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1023 1024 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1025 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1026 1027 /* Address */ 1028 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1029 1030 if (bit64) 1031 pci_conf_write(pc, tag, 1032 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1033 1034 /* Data */ 1035 pci_conf_write(pc, tag, 1036 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1037 pcs->msi_mdata); 1038 1039 /* Per-vector masking */ 1040 if (pvmask) 1041 pci_conf_write(pc, tag, 1042 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1043 pcs->msi_mask); 1044 1045 /* Write CTRL register in the end */ 1046 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1047 } 1048 1049 /* For MSI-X */ 1050 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1051 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1052 } 1053 1054 /* 1055 * Power Management Capability (Rev 2.2) 1056 */ 1057 static int 1058 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1059 int offset) 1060 { 1061 pcireg_t value, now; 1062 1063 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1064 now = value & PCI_PMCSR_STATE_MASK; 1065 switch (now) { 1066 case PCI_PMCSR_STATE_D0: 1067 case PCI_PMCSR_STATE_D1: 1068 case PCI_PMCSR_STATE_D2: 1069 case PCI_PMCSR_STATE_D3: 1070 *state = now; 1071 return 0; 1072 default: 1073 return EINVAL; 1074 } 1075 } 1076 1077 int 1078 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1079 { 1080 int offset; 1081 pcireg_t value; 1082 1083 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1084 return EOPNOTSUPP; 1085 1086 return pci_get_powerstate_int(pc, tag, state, offset); 1087 } 1088 1089 static int 1090 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1091 int offset, pcireg_t cap_reg) 1092 { 1093 pcireg_t value, cap, now; 1094 1095 cap = cap_reg >> PCI_PMCR_SHIFT; 1096 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1097 now = value & PCI_PMCSR_STATE_MASK; 1098 value &= ~PCI_PMCSR_STATE_MASK; 1099 1100 if (now == state) 1101 return 0; 1102 switch (state) { 1103 case PCI_PMCSR_STATE_D0: 1104 break; 1105 case PCI_PMCSR_STATE_D1: 1106 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1107 printf("invalid transition from %d to D1\n", (int)now); 1108 return EINVAL; 1109 } 1110 if (!(cap & PCI_PMCR_D1SUPP)) { 1111 printf("D1 not supported\n"); 1112 return EOPNOTSUPP; 1113 } 1114 break; 1115 case PCI_PMCSR_STATE_D2: 1116 if (now == PCI_PMCSR_STATE_D3) { 1117 printf("invalid transition from %d to D2\n", (int)now); 1118 return EINVAL; 1119 } 1120 if (!(cap & PCI_PMCR_D2SUPP)) { 1121 printf("D2 not supported\n"); 1122 return EOPNOTSUPP; 1123 } 1124 break; 1125 case PCI_PMCSR_STATE_D3: 1126 break; 1127 default: 1128 return EINVAL; 1129 } 1130 value |= state; 1131 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1132 /* delay according to pcipm1.2, ch. 5.6.1 */ 1133 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1134 DELAY(10000); 1135 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1136 DELAY(200); 1137 1138 return 0; 1139 } 1140 1141 int 1142 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1143 { 1144 int offset; 1145 pcireg_t value; 1146 1147 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1148 printf("pci_set_powerstate not supported\n"); 1149 return EOPNOTSUPP; 1150 } 1151 1152 return pci_set_powerstate_int(pc, tag, state, offset, value); 1153 } 1154 1155 int 1156 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1157 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1158 { 1159 pcireg_t pmode; 1160 int error; 1161 1162 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1163 return error; 1164 1165 switch (pmode) { 1166 case PCI_PMCSR_STATE_D0: 1167 break; 1168 case PCI_PMCSR_STATE_D3: 1169 if (wakefun == NULL) { 1170 /* 1171 * The card has lost all configuration data in 1172 * this state, so punt. 1173 */ 1174 aprint_error_dev(dev, 1175 "unable to wake up from power state D3\n"); 1176 return EOPNOTSUPP; 1177 } 1178 /*FALLTHROUGH*/ 1179 default: 1180 if (wakefun) { 1181 error = (*wakefun)(pc, tag, dev, pmode); 1182 if (error) 1183 return error; 1184 } 1185 aprint_normal_dev(dev, "waking up from power state D%d\n", 1186 pmode); 1187 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1188 return error; 1189 } 1190 return 0; 1191 } 1192 1193 int 1194 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1195 device_t dev, pcireg_t state) 1196 { 1197 return 0; 1198 } 1199 1200 struct pci_child_power { 1201 struct pci_conf_state p_pciconf; 1202 pci_chipset_tag_t p_pc; 1203 pcitag_t p_tag; 1204 bool p_has_pm; 1205 int p_pm_offset; 1206 pcireg_t p_pm_cap; 1207 pcireg_t p_class; 1208 pcireg_t p_csr; 1209 }; 1210 1211 static bool 1212 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1213 { 1214 struct pci_child_power *priv = device_pmf_bus_private(dv); 1215 pcireg_t ocsr, csr; 1216 1217 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1218 1219 if (!priv->p_has_pm) 1220 return true; /* ??? hopefully handled by ACPI */ 1221 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1222 return true; /* XXX */ 1223 1224 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1225 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1226 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1227 | PCI_COMMAND_MASTER_ENABLE); 1228 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1229 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1230 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1231 pci_conf_write(priv->p_pc, priv->p_tag, 1232 PCI_COMMAND_STATUS_REG, ocsr); 1233 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1234 return false; 1235 } 1236 return true; 1237 } 1238 1239 static void 1240 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1241 int off) 1242 { 1243 pcireg_t pmcsr; 1244 1245 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1246 1247 if (pmcsr & PCI_PMCSR_PME_STS) { 1248 /* Clear W1C bit */ 1249 pmcsr |= PCI_PMCSR_PME_STS; 1250 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1251 aprint_verbose_dev(dv, "Clear PME# now\n"); 1252 } 1253 } 1254 1255 static bool 1256 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1257 { 1258 struct pci_child_power *priv = device_pmf_bus_private(dv); 1259 1260 if (priv->p_has_pm) { 1261 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1262 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1263 aprint_error_dev(dv, 1264 "unsupported state, continuing.\n"); 1265 return false; 1266 } 1267 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1268 priv->p_pm_offset); 1269 } 1270 1271 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1272 1273 return true; 1274 } 1275 1276 static bool 1277 pci_child_shutdown(device_t dv, int how) 1278 { 1279 struct pci_child_power *priv = device_pmf_bus_private(dv); 1280 pcireg_t csr; 1281 1282 /* restore original bus-mastering state */ 1283 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1284 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1285 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1286 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1287 return true; 1288 } 1289 1290 static void 1291 pci_child_deregister(device_t dv) 1292 { 1293 struct pci_child_power *priv = device_pmf_bus_private(dv); 1294 1295 free(priv, M_DEVBUF); 1296 } 1297 1298 static bool 1299 pci_child_register(device_t child) 1300 { 1301 device_t self = device_parent(child); 1302 struct pci_softc *sc = device_private(self); 1303 struct pci_child_power *priv; 1304 int device, function, off; 1305 pcireg_t reg; 1306 1307 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1308 1309 device = device_locator(child, PCICF_DEV); 1310 function = device_locator(child, PCICF_FUNCTION); 1311 1312 priv->p_pc = sc->sc_pc; 1313 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1314 function); 1315 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1316 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1317 PCI_COMMAND_STATUS_REG); 1318 1319 if (pci_get_capability(priv->p_pc, priv->p_tag, 1320 PCI_CAP_PWRMGMT, &off, ®)) { 1321 priv->p_has_pm = true; 1322 priv->p_pm_offset = off; 1323 priv->p_pm_cap = reg; 1324 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1325 } else { 1326 priv->p_has_pm = false; 1327 priv->p_pm_offset = -1; 1328 } 1329 1330 device_pmf_bus_register(child, priv, pci_child_suspend, 1331 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1332 1333 return true; 1334 } 1335 1336 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1337 1338 static int 1339 pci_modcmd(modcmd_t cmd, void *priv) 1340 { 1341 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1342 return 0; 1343 return ENOTTY; 1344 } 1345
Indexes created Sun Sep 21 20:09:37 GMT 2025