pci.c revision 1.158.2.1
1 /* $NetBSD: pci.c,v 1.158.2.1 2021/03/22 02:01:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.158.2.1 2021/03/22 02:01:01 thorpej Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <net/if.h> 57 58 #include "locators.h" 59 60 static bool pci_child_register(device_t); 61 62 #ifdef PCI_CONFIG_DUMP 63 int pci_config_dump = 1; 64 #else 65 int pci_config_dump = 0; 66 #endif 67 68 int pciprint(void *, const char *); 69 70 #ifdef PCI_MACHDEP_ENUMERATE_BUS 71 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(const struct pci_attach_args *), 273 struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 278 #ifdef __HAVE_PCI_MSI_MSIX 279 pcireg_t cap; 280 int off; 281 #endif 282 int ret, pin, bus, device, function, i, width; 283 int locs[PCICF_NLOCS]; 284 285 pci_decompose_tag(pc, tag, &bus, &device, &function); 286 287 /* a driver already attached? */ 288 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 289 return 0; 290 291 id = pci_conf_read(pc, tag, PCI_ID_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 301 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 302 return 0; 303 304 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 305 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 306 307 /* Collect memory range info */ 308 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 309 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 310 i = 0; 311 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 312 case PCI_HDRTYPE_PPB: 313 endbar = PCI_MAPREG_PPB_END; 314 break; 315 case PCI_HDRTYPE_PCB: 316 endbar = PCI_MAPREG_PCB_END; 317 break; 318 default: 319 endbar = PCI_MAPREG_END; 320 break; 321 } 322 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 323 struct pci_range *r; 324 pcireg_t type; 325 326 width = 4; 327 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 328 continue; 329 330 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 331 if (PCI_MAPREG_MEM_TYPE(type) == 332 PCI_MAPREG_MEM_TYPE_64BIT) 333 width = 8; 334 335 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 336 if (pci_mapreg_info(pc, tag, bar, type, 337 &r->r_offset, &r->r_size, &r->r_flags) != 0) 338 break; 339 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 340 && (r->r_size == 0x1000000)) { 341 struct pci_range *nr; 342 /* 343 * this has to be a mach64 344 * split things up so each half-aperture can 345 * be mapped PREFETCHABLE except the last page 346 * which may contain registers 347 */ 348 r->r_size = 0x7ff000; 349 r->r_flags = BUS_SPACE_MAP_LINEAR | 350 BUS_SPACE_MAP_PREFETCHABLE; 351 nr = &sc->PCI_SC_DEVICESC(device, 352 function).c_range[i++]; 353 nr->r_offset = r->r_offset + 0x800000; 354 nr->r_size = 0x7ff000; 355 nr->r_flags = BUS_SPACE_MAP_LINEAR | 356 BUS_SPACE_MAP_PREFETCHABLE; 357 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 358 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 359 (bar == 0x10)) { 360 r->r_flags = BUS_SPACE_MAP_LINEAR | 361 BUS_SPACE_MAP_PREFETCHABLE; 362 } 363 } 364 } 365 366 pa.pa_iot = sc->sc_iot; 367 pa.pa_memt = sc->sc_memt; 368 pa.pa_dmat = sc->sc_dmat; 369 pa.pa_dmat64 = sc->sc_dmat64; 370 pa.pa_pc = pc; 371 pa.pa_bus = bus; 372 pa.pa_device = device; 373 pa.pa_function = function; 374 pa.pa_tag = tag; 375 pa.pa_id = id; 376 pa.pa_class = pciclass; 377 378 /* 379 * Set up memory, I/O enable, and PCI command flags 380 * as appropriate. 381 */ 382 pa.pa_flags = sc->sc_flags; 383 384 /* 385 * If the cache line size is not configured, then 386 * clear the MRL/MRM/MWI command-ok flags. 387 */ 388 if (PCI_CACHELINE(bhlcr) == 0) { 389 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 390 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 391 } 392 393 if (sc->sc_bridgetag == NULL) { 394 pa.pa_intrswiz = 0; 395 pa.pa_intrtag = tag; 396 } else { 397 pa.pa_intrswiz = sc->sc_intrswiz + device; 398 pa.pa_intrtag = sc->sc_intrtag; 399 } 400 401 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 402 403 pin = PCI_INTERRUPT_PIN(intr); 404 pa.pa_rawintrpin = pin; 405 if (pin == PCI_INTERRUPT_PIN_NONE) { 406 /* no interrupt */ 407 pa.pa_intrpin = 0; 408 } else { 409 /* 410 * swizzle it based on the number of busses we're 411 * behind and our device number. 412 */ 413 pa.pa_intrpin = /* XXX */ 414 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 415 } 416 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 417 418 #ifdef __HAVE_PCI_MSI_MSIX 419 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 420 /* 421 * XXX Should we enable MSI mapping ourselves on 422 * systems that have it disabled? 423 */ 424 if (cap & PCI_HT_MSI_ENABLED) { 425 uint64_t addr; 426 if ((cap & PCI_HT_MSI_FIXED) == 0) { 427 addr = pci_conf_read(pc, tag, 428 off + PCI_HT_MSI_ADDR_LO); 429 addr |= (uint64_t)pci_conf_read(pc, tag, 430 off + PCI_HT_MSI_ADDR_HI) << 32; 431 } else 432 addr = PCI_HT_MSI_FIXED_ADDR; 433 434 /* 435 * XXX This will fail to enable MSI on systems 436 * that don't use the canonical address. 437 */ 438 if (addr == PCI_HT_MSI_FIXED_ADDR) { 439 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 440 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 441 } else 442 aprint_verbose_dev(sc->sc_dev, 443 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 444 } 445 } 446 #endif 447 448 if (match != NULL) { 449 ret = (*match)(&pa); 450 if (ret != 0 && pap != NULL) 451 *pap = pa; 452 } else { 453 struct pci_child *c; 454 locs[PCICF_DEV] = device; 455 locs[PCICF_FUNCTION] = function; 456 457 c = &sc->PCI_SC_DEVICESC(device, function); 458 pci_conf_capture(pc, tag, &c->c_conf); 459 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 460 c->c_psok = true; 461 else 462 c->c_psok = false; 463 464 c->c_dev = config_found(sc->sc_dev, &pa, pciprint, 465 CFARG_SUBMATCH, config_stdsubmatch, 466 CFARG_IATTR, "pci", 467 CFARG_LOCATORS, locs, 468 CFARG_EOL); 469 470 ret = (c->c_dev != NULL); 471 } 472 473 return ret; 474 } 475 476 void 477 pcidevdetached(device_t self, device_t child) 478 { 479 struct pci_softc *sc = device_private(self); 480 int d, f; 481 pcitag_t tag; 482 struct pci_child *c; 483 484 d = device_locator(child, PCICF_DEV); 485 f = device_locator(child, PCICF_FUNCTION); 486 487 c = &sc->PCI_SC_DEVICESC(d, f); 488 489 KASSERT(c->c_dev == child); 490 491 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 492 if (c->c_psok) 493 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 494 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 495 c->c_dev = NULL; 496 } 497 498 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 499 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 500 DVF_DETACH_SHUTDOWN); 501 502 int 503 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 504 int *offset, pcireg_t *value) 505 { 506 pcireg_t reg; 507 unsigned int ofs; 508 509 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 510 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 511 return 0; 512 513 /* Determine the Capability List Pointer register to start with. */ 514 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 515 switch (PCI_HDRTYPE_TYPE(reg)) { 516 case 0: /* standard device header */ 517 case 1: /* PCI-PCI bridge header */ 518 ofs = PCI_CAPLISTPTR_REG; 519 break; 520 case 2: /* PCI-CardBus Bridge header */ 521 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 522 break; 523 default: 524 return 0; 525 } 526 527 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 528 while (ofs != 0) { 529 if ((ofs & 3) || (ofs < 0x40)) { 530 int bus, device, function; 531 532 pci_decompose_tag(pc, tag, &bus, &device, &function); 533 534 printf("Skipping broken PCI header on %d:%d:%d\n", 535 bus, device, function); 536 break; 537 } 538 reg = pci_conf_read(pc, tag, ofs); 539 if (PCI_CAPLIST_CAP(reg) == capid) { 540 if (offset) 541 *offset = ofs; 542 if (value) 543 *value = reg; 544 return 1; 545 } 546 ofs = PCI_CAPLIST_NEXT(reg); 547 } 548 549 return 0; 550 } 551 552 int 553 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 554 int *offset, pcireg_t *value) 555 { 556 pcireg_t reg; 557 unsigned int ofs; 558 559 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 560 return 0; 561 562 while (ofs != 0) { 563 #ifdef DIAGNOSTIC 564 if ((ofs & 3) || (ofs < 0x40)) 565 panic("pci_get_ht_capability"); 566 #endif 567 reg = pci_conf_read(pc, tag, ofs); 568 if (PCI_HT_CAP(reg) == capid) { 569 if (offset) 570 *offset = ofs; 571 if (value) 572 *value = reg; 573 return 1; 574 } 575 ofs = PCI_CAPLIST_NEXT(reg); 576 } 577 578 return 0; 579 } 580 581 /* 582 * return number of the devices's MSI vectors 583 * return 0 if the device does not support MSI 584 */ 585 int 586 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 587 { 588 pcireg_t reg; 589 uint32_t mmc; 590 int count, offset; 591 592 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 593 return 0; 594 595 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 596 mmc = PCI_MSI_CTL_MMC(reg); 597 count = 1 << mmc; 598 if (count > PCI_MSI_MAX_VECTORS) { 599 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 600 return 0; 601 } 602 603 return count; 604 } 605 606 /* 607 * return number of the devices's MSI-X vectors 608 * return 0 if the device does not support MSI-X 609 */ 610 int 611 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 612 { 613 pcireg_t reg; 614 int offset; 615 616 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 617 return 0; 618 619 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 620 621 return PCI_MSIX_CTL_TBLSIZE(reg); 622 } 623 624 int 625 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 626 int *offset, pcireg_t *value) 627 { 628 pcireg_t reg; 629 unsigned int ofs; 630 631 /* Only supported for PCI-express devices */ 632 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 633 return 0; 634 635 ofs = PCI_EXTCAPLIST_BASE; 636 reg = pci_conf_read(pc, tag, ofs); 637 if (reg == 0xffffffff || reg == 0) 638 return 0; 639 640 for (;;) { 641 #ifdef DIAGNOSTIC 642 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 643 panic("%s: invalid offset %u", __func__, ofs); 644 #endif 645 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 646 if (offset != NULL) 647 *offset = ofs; 648 if (value != NULL) 649 *value = reg; 650 return 1; 651 } 652 ofs = PCI_EXTCAPLIST_NEXT(reg); 653 if (ofs == 0) 654 break; 655 reg = pci_conf_read(pc, tag, ofs); 656 } 657 658 return 0; 659 } 660 661 int 662 pci_find_device(struct pci_attach_args *pa, 663 int (*match)(const struct pci_attach_args *)) 664 { 665 extern struct cfdriver pci_cd; 666 device_t pcidev; 667 int i; 668 static const int wildcard[2] = { 669 PCICF_DEV_DEFAULT, 670 PCICF_FUNCTION_DEFAULT 671 }; 672 673 for (i = 0; i < pci_cd.cd_ndevs; i++) { 674 pcidev = device_lookup(&pci_cd, i); 675 if (pcidev != NULL && 676 pci_enumerate_bus(device_private(pcidev), wildcard, 677 match, pa) != 0) 678 return 1; 679 } 680 return 0; 681 } 682 683 #ifndef PCI_MACHDEP_ENUMERATE_BUS 684 /* 685 * Generic PCI bus enumeration routine. Used unless machine-dependent 686 * code needs to provide something else. 687 */ 688 int 689 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 690 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 691 { 692 pci_chipset_tag_t pc = sc->sc_pc; 693 int device, function, nfunctions, ret; 694 const struct pci_quirkdata *qd; 695 pcireg_t id, bhlcr; 696 pcitag_t tag; 697 uint8_t devs[32]; 698 int i, n; 699 700 device_t bridgedev; 701 bool arien = false; 702 bool downstream_port = false; 703 704 /* Check PCIe ARI and port type */ 705 bridgedev = device_parent(sc->sc_dev); 706 if (device_is_a(bridgedev, "ppb")) { 707 struct ppb_softc *ppbsc = device_private(bridgedev); 708 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 709 pcitag_t ppbtag = ppbsc->sc_tag; 710 pcireg_t pciecap, capreg, reg; 711 712 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 713 &pciecap, &capreg) != 0) { 714 switch (PCIE_XCAP_TYPE(capreg)) { 715 case PCIE_XCAP_TYPE_ROOT: 716 case PCIE_XCAP_TYPE_DOWN: 717 case PCIE_XCAP_TYPE_PCI2PCIE: 718 downstream_port = true; 719 break; 720 } 721 722 reg = pci_conf_read(ppbpc, ppbtag, pciecap 723 + PCIE_DCSR2); 724 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 725 arien = true; 726 } 727 } 728 729 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 730 if (downstream_port) { 731 /* PCIe downstream ports only have a single child device */ 732 n = 1; 733 } 734 735 for (i = 0; i < n; i++) { 736 device = devs[i]; 737 738 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 739 (locators[PCICF_DEV] != device)) 740 continue; 741 742 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 743 744 id = pci_conf_read(pc, tag, PCI_ID_REG); 745 746 /* Invalid vendor ID value? */ 747 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 748 continue; 749 /* XXX Not invalid, but we've done this ~forever. */ 750 if (PCI_VENDOR(id) == 0) 751 continue; 752 753 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 754 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 755 continue; 756 757 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 758 759 if (qd != NULL && 760 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 761 nfunctions = 8; 762 else if (qd != NULL && 763 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 764 nfunctions = 1; 765 else if (arien) 766 nfunctions = 8; /* Scan all if ARI is enabled */ 767 else 768 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 769 770 #ifdef __PCI_DEV_FUNCORDER 771 char funcs[8]; 772 int j; 773 for (j = 0; j < nfunctions; j++) { 774 funcs[j] = j; 775 } 776 if (j < __arraycount(funcs)) 777 funcs[j] = -1; 778 if (nfunctions > 1) { 779 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 780 nfunctions, funcs); 781 } 782 for (j = 0; 783 j < 8 && (function = funcs[j]) < 8 && function >= 0; 784 j++) { 785 #else 786 for (function = 0; function < nfunctions; function++) { 787 #endif 788 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 789 && (locators[PCICF_FUNCTION] != function)) 790 continue; 791 792 if (qd != NULL && 793 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 794 continue; 795 tag = pci_make_tag(pc, sc->sc_bus, device, function); 796 ret = pci_probe_device(sc, tag, match, pap); 797 if (match != NULL && ret != 0) 798 return ret; 799 } 800 } 801 return 0; 802 } 803 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 804 805 806 /* 807 * Vital Product Data (PCI 2.2) 808 */ 809 810 int 811 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 812 pcireg_t *data) 813 { 814 uint32_t reg; 815 int ofs, i, j; 816 817 KASSERT(data != NULL); 818 KASSERT((offset + count) < 0x7fff); 819 820 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 821 return 1; 822 823 for (i = 0; i < count; offset += sizeof(*data), i++) { 824 reg &= 0x0000ffff; 825 reg &= ~PCI_VPD_OPFLAG; 826 reg |= PCI_VPD_ADDRESS(offset); 827 pci_conf_write(pc, tag, ofs, reg); 828 829 /* 830 * PCI 2.2 does not specify how long we should poll 831 * for completion nor whether the operation can fail. 832 */ 833 j = 0; 834 do { 835 if (j++ == 20) 836 return 1; 837 delay(4); 838 reg = pci_conf_read(pc, tag, ofs); 839 } while ((reg & PCI_VPD_OPFLAG) == 0); 840 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 841 } 842 843 return 0; 844 } 845 846 int 847 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 848 pcireg_t *data) 849 { 850 pcireg_t reg; 851 int ofs, i, j; 852 853 KASSERT(data != NULL); 854 KASSERT((offset + count) < 0x7fff); 855 856 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 857 return 1; 858 859 for (i = 0; i < count; offset += sizeof(*data), i++) { 860 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 861 862 reg &= 0x0000ffff; 863 reg |= PCI_VPD_OPFLAG; 864 reg |= PCI_VPD_ADDRESS(offset); 865 pci_conf_write(pc, tag, ofs, reg); 866 867 /* 868 * PCI 2.2 does not specify how long we should poll 869 * for completion nor whether the operation can fail. 870 */ 871 j = 0; 872 do { 873 if (j++ == 20) 874 return 1; 875 delay(1); 876 reg = pci_conf_read(pc, tag, ofs); 877 } while (reg & PCI_VPD_OPFLAG); 878 } 879 880 return 0; 881 } 882 883 int 884 pci_dma64_available(const struct pci_attach_args *pa) 885 { 886 #ifdef _PCI_HAVE_DMA64 887 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 888 return 1; 889 #endif 890 return 0; 891 } 892 893 void 894 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 895 struct pci_conf_state *pcs) 896 { 897 int off; 898 899 for (off = 0; off < 16; off++) 900 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 901 902 /* For PCI-X */ 903 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 904 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 905 906 /* For PCIe */ 907 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 908 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 909 unsigned int devtype; 910 911 devtype = PCIE_XCAP_TYPE(xcap); 912 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 913 914 if (PCIE_HAS_LINKREGS(devtype)) 915 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 916 off + PCIE_LCSR); 917 918 if ((xcap & PCIE_XCAP_SI) != 0) 919 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 920 off + PCIE_SLCSR); 921 922 if (PCIE_HAS_ROOTREGS(devtype)) 923 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 924 off + PCIE_RCR); 925 926 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 927 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 928 off + PCIE_DCSR2); 929 930 if (PCIE_HAS_LINKREGS(devtype)) 931 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 932 off + PCIE_LCSR2); 933 934 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 935 } 936 } 937 938 /* For MSI */ 939 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 940 bool bit64, pvmask; 941 942 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 943 944 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 945 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 946 947 /* Address */ 948 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 949 if (bit64) 950 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 951 off + PCI_MSI_MADDR64_HI); 952 953 /* Data */ 954 pcs->msi_mdata = pci_conf_read(pc, tag, 955 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 956 957 /* Per-vector masking */ 958 if (pvmask) 959 pcs->msi_mask = pci_conf_read(pc, tag, 960 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 961 } 962 963 /* For MSI-X */ 964 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 965 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 966 } 967 968 void 969 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 970 struct pci_conf_state *pcs) 971 { 972 int off; 973 pcireg_t val; 974 975 for (off = 15; off >= 0; off--) { 976 val = pci_conf_read(pc, tag, (off * 4)); 977 if (val != pcs->reg[off]) 978 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 979 } 980 981 /* For PCI-X */ 982 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 983 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 984 985 /* For PCIe */ 986 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 987 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 988 unsigned int devtype; 989 990 devtype = PCIE_XCAP_TYPE(xcap); 991 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 992 993 /* 994 * PCIe capability is variable sized. To not to write the next 995 * area, check the existence of each register. 996 */ 997 if (PCIE_HAS_LINKREGS(devtype)) 998 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 999 1000 if ((xcap & PCIE_XCAP_SI) != 0) 1001 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 1002 1003 if (PCIE_HAS_ROOTREGS(devtype)) 1004 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1005 1006 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1007 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1008 1009 if (PCIE_HAS_LINKREGS(devtype)) 1010 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1011 pcs->e_lcr2); 1012 1013 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1014 } 1015 } 1016 1017 /* For MSI */ 1018 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1019 pcireg_t reg; 1020 bool bit64, pvmask; 1021 1022 /* First, drop Enable bit in case it's already set. */ 1023 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1024 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1025 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1026 1027 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1028 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1029 1030 /* Address */ 1031 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1032 1033 if (bit64) 1034 pci_conf_write(pc, tag, 1035 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1036 1037 /* Data */ 1038 pci_conf_write(pc, tag, 1039 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1040 pcs->msi_mdata); 1041 1042 /* Per-vector masking */ 1043 if (pvmask) 1044 pci_conf_write(pc, tag, 1045 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1046 pcs->msi_mask); 1047 1048 /* Write CTRL register in the end */ 1049 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1050 } 1051 1052 /* For MSI-X */ 1053 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1054 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1055 } 1056 1057 /* 1058 * Power Management Capability (Rev 2.2) 1059 */ 1060 static int 1061 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1062 int offset) 1063 { 1064 pcireg_t value, now; 1065 1066 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1067 now = value & PCI_PMCSR_STATE_MASK; 1068 switch (now) { 1069 case PCI_PMCSR_STATE_D0: 1070 case PCI_PMCSR_STATE_D1: 1071 case PCI_PMCSR_STATE_D2: 1072 case PCI_PMCSR_STATE_D3: 1073 *state = now; 1074 return 0; 1075 default: 1076 return EINVAL; 1077 } 1078 } 1079 1080 int 1081 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1082 { 1083 int offset; 1084 pcireg_t value; 1085 1086 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1087 return EOPNOTSUPP; 1088 1089 return pci_get_powerstate_int(pc, tag, state, offset); 1090 } 1091 1092 static int 1093 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1094 int offset, pcireg_t cap_reg) 1095 { 1096 pcireg_t value, cap, now; 1097 1098 cap = cap_reg >> PCI_PMCR_SHIFT; 1099 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1100 now = value & PCI_PMCSR_STATE_MASK; 1101 value &= ~PCI_PMCSR_STATE_MASK; 1102 1103 if (now == state) 1104 return 0; 1105 switch (state) { 1106 case PCI_PMCSR_STATE_D0: 1107 break; 1108 case PCI_PMCSR_STATE_D1: 1109 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1110 printf("invalid transition from %d to D1\n", (int)now); 1111 return EINVAL; 1112 } 1113 if (!(cap & PCI_PMCR_D1SUPP)) { 1114 printf("D1 not supported\n"); 1115 return EOPNOTSUPP; 1116 } 1117 break; 1118 case PCI_PMCSR_STATE_D2: 1119 if (now == PCI_PMCSR_STATE_D3) { 1120 printf("invalid transition from %d to D2\n", (int)now); 1121 return EINVAL; 1122 } 1123 if (!(cap & PCI_PMCR_D2SUPP)) { 1124 printf("D2 not supported\n"); 1125 return EOPNOTSUPP; 1126 } 1127 break; 1128 case PCI_PMCSR_STATE_D3: 1129 break; 1130 default: 1131 return EINVAL; 1132 } 1133 value |= state; 1134 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1135 /* delay according to pcipm1.2, ch. 5.6.1 */ 1136 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1137 DELAY(10000); 1138 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1139 DELAY(200); 1140 1141 return 0; 1142 } 1143 1144 int 1145 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1146 { 1147 int offset; 1148 pcireg_t value; 1149 1150 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1151 printf("pci_set_powerstate not supported\n"); 1152 return EOPNOTSUPP; 1153 } 1154 1155 return pci_set_powerstate_int(pc, tag, state, offset, value); 1156 } 1157 1158 int 1159 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1160 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1161 { 1162 pcireg_t pmode; 1163 int error; 1164 1165 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1166 return error; 1167 1168 switch (pmode) { 1169 case PCI_PMCSR_STATE_D0: 1170 break; 1171 case PCI_PMCSR_STATE_D3: 1172 if (wakefun == NULL) { 1173 /* 1174 * The card has lost all configuration data in 1175 * this state, so punt. 1176 */ 1177 aprint_error_dev(dev, 1178 "unable to wake up from power state D3\n"); 1179 return EOPNOTSUPP; 1180 } 1181 /*FALLTHROUGH*/ 1182 default: 1183 if (wakefun) { 1184 error = (*wakefun)(pc, tag, dev, pmode); 1185 if (error) 1186 return error; 1187 } 1188 aprint_normal_dev(dev, "waking up from power state D%d\n", 1189 pmode); 1190 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1191 return error; 1192 } 1193 return 0; 1194 } 1195 1196 int 1197 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1198 device_t dev, pcireg_t state) 1199 { 1200 return 0; 1201 } 1202 1203 struct pci_child_power { 1204 struct pci_conf_state p_pciconf; 1205 pci_chipset_tag_t p_pc; 1206 pcitag_t p_tag; 1207 bool p_has_pm; 1208 int p_pm_offset; 1209 pcireg_t p_pm_cap; 1210 pcireg_t p_class; 1211 pcireg_t p_csr; 1212 }; 1213 1214 static bool 1215 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1216 { 1217 struct pci_child_power *priv = device_pmf_bus_private(dv); 1218 pcireg_t ocsr, csr; 1219 1220 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1221 1222 if (!priv->p_has_pm) 1223 return true; /* ??? hopefully handled by ACPI */ 1224 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1225 return true; /* XXX */ 1226 1227 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1228 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1229 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1230 | PCI_COMMAND_MASTER_ENABLE); 1231 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1232 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1233 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1234 pci_conf_write(priv->p_pc, priv->p_tag, 1235 PCI_COMMAND_STATUS_REG, ocsr); 1236 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1237 return false; 1238 } 1239 return true; 1240 } 1241 1242 static void 1243 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1244 int off) 1245 { 1246 pcireg_t pmcsr; 1247 1248 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1249 1250 if (pmcsr & PCI_PMCSR_PME_STS) { 1251 /* Clear W1C bit */ 1252 pmcsr |= PCI_PMCSR_PME_STS; 1253 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1254 aprint_verbose_dev(dv, "Clear PME# now\n"); 1255 } 1256 } 1257 1258 static bool 1259 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1260 { 1261 struct pci_child_power *priv = device_pmf_bus_private(dv); 1262 1263 if (priv->p_has_pm) { 1264 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1265 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1266 aprint_error_dev(dv, 1267 "unsupported state, continuing.\n"); 1268 return false; 1269 } 1270 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1271 priv->p_pm_offset); 1272 } 1273 1274 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1275 1276 return true; 1277 } 1278 1279 static bool 1280 pci_child_shutdown(device_t dv, int how) 1281 { 1282 struct pci_child_power *priv = device_pmf_bus_private(dv); 1283 pcireg_t csr; 1284 1285 /* restore original bus-mastering state */ 1286 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1287 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1288 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1289 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1290 return true; 1291 } 1292 1293 static void 1294 pci_child_deregister(device_t dv) 1295 { 1296 struct pci_child_power *priv = device_pmf_bus_private(dv); 1297 1298 free(priv, M_DEVBUF); 1299 } 1300 1301 static bool 1302 pci_child_register(device_t child) 1303 { 1304 device_t self = device_parent(child); 1305 struct pci_softc *sc = device_private(self); 1306 struct pci_child_power *priv; 1307 int device, function, off; 1308 pcireg_t reg; 1309 1310 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1311 1312 device = device_locator(child, PCICF_DEV); 1313 function = device_locator(child, PCICF_FUNCTION); 1314 1315 priv->p_pc = sc->sc_pc; 1316 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1317 function); 1318 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1319 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1320 PCI_COMMAND_STATUS_REG); 1321 1322 if (pci_get_capability(priv->p_pc, priv->p_tag, 1323 PCI_CAP_PWRMGMT, &off, ®)) { 1324 priv->p_has_pm = true; 1325 priv->p_pm_offset = off; 1326 priv->p_pm_cap = reg; 1327 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1328 } else { 1329 priv->p_has_pm = false; 1330 priv->p_pm_offset = -1; 1331 } 1332 1333 device_pmf_bus_register(child, priv, pci_child_suspend, 1334 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1335 1336 return true; 1337 } 1338 1339 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1340 1341 static int 1342 pci_modcmd(modcmd_t cmd, void *priv) 1343 { 1344 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1345 return 0; 1346 return ENOTTY; 1347 } 1348
Indexes created Tue Sep 30 20:09:53 GMT 2025