pci.c revision 1.159
1 /* $NetBSD: pci.c,v 1.159 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.159 2021/04/24 23:36:57 thorpej Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <net/if.h> 57 58 #include "locators.h" 59 60 static bool pci_child_register(device_t); 61 62 #ifdef PCI_CONFIG_DUMP 63 int pci_config_dump = 1; 64 #else 65 int pci_config_dump = 0; 66 #endif 67 68 int pciprint(void *, const char *); 69 70 #ifdef PCI_MACHDEP_ENUMERATE_BUS 71 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(const struct pci_attach_args *), 273 struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 278 #ifdef __HAVE_PCI_MSI_MSIX 279 pcireg_t cap; 280 int off; 281 #endif 282 int ret, pin, bus, device, function, i, width; 283 int locs[PCICF_NLOCS]; 284 285 pci_decompose_tag(pc, tag, &bus, &device, &function); 286 287 /* a driver already attached? */ 288 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 289 return 0; 290 291 id = pci_conf_read(pc, tag, PCI_ID_REG); 292 293 /* Invalid vendor ID value? */ 294 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 295 return 0; 296 /* XXX Not invalid, but we've done this ~forever. */ 297 if (PCI_VENDOR(id) == 0) 298 return 0; 299 300 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 301 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 302 return 0; 303 304 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 305 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 306 307 /* Collect memory range info */ 308 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 309 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 310 i = 0; 311 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 312 case PCI_HDRTYPE_PPB: 313 endbar = PCI_MAPREG_PPB_END; 314 break; 315 case PCI_HDRTYPE_PCB: 316 endbar = PCI_MAPREG_PCB_END; 317 break; 318 default: 319 endbar = PCI_MAPREG_END; 320 break; 321 } 322 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 323 struct pci_range *r; 324 pcireg_t type; 325 326 width = 4; 327 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 328 continue; 329 330 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 331 if (PCI_MAPREG_MEM_TYPE(type) == 332 PCI_MAPREG_MEM_TYPE_64BIT) 333 width = 8; 334 335 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 336 if (pci_mapreg_info(pc, tag, bar, type, 337 &r->r_offset, &r->r_size, &r->r_flags) != 0) 338 break; 339 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 340 && (r->r_size == 0x1000000)) { 341 struct pci_range *nr; 342 /* 343 * this has to be a mach64 344 * split things up so each half-aperture can 345 * be mapped PREFETCHABLE except the last page 346 * which may contain registers 347 */ 348 r->r_size = 0x7ff000; 349 r->r_flags = BUS_SPACE_MAP_LINEAR | 350 BUS_SPACE_MAP_PREFETCHABLE; 351 nr = &sc->PCI_SC_DEVICESC(device, 352 function).c_range[i++]; 353 nr->r_offset = r->r_offset + 0x800000; 354 nr->r_size = 0x7ff000; 355 nr->r_flags = BUS_SPACE_MAP_LINEAR | 356 BUS_SPACE_MAP_PREFETCHABLE; 357 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 358 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 359 (bar == 0x10)) { 360 r->r_flags = BUS_SPACE_MAP_LINEAR | 361 BUS_SPACE_MAP_PREFETCHABLE; 362 } 363 } 364 } 365 366 pa.pa_iot = sc->sc_iot; 367 pa.pa_memt = sc->sc_memt; 368 pa.pa_dmat = sc->sc_dmat; 369 pa.pa_dmat64 = sc->sc_dmat64; 370 pa.pa_pc = pc; 371 pa.pa_bus = bus; 372 pa.pa_device = device; 373 pa.pa_function = function; 374 pa.pa_tag = tag; 375 pa.pa_id = id; 376 pa.pa_class = pciclass; 377 378 /* 379 * Set up memory, I/O enable, and PCI command flags 380 * as appropriate. 381 */ 382 pa.pa_flags = sc->sc_flags; 383 384 /* 385 * If the cache line size is not configured, then 386 * clear the MRL/MRM/MWI command-ok flags. 387 */ 388 if (PCI_CACHELINE(bhlcr) == 0) { 389 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 390 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 391 } 392 393 if (sc->sc_bridgetag == NULL) { 394 pa.pa_intrswiz = 0; 395 pa.pa_intrtag = tag; 396 } else { 397 pa.pa_intrswiz = sc->sc_intrswiz + device; 398 pa.pa_intrtag = sc->sc_intrtag; 399 } 400 401 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 402 403 pin = PCI_INTERRUPT_PIN(intr); 404 pa.pa_rawintrpin = pin; 405 if (pin == PCI_INTERRUPT_PIN_NONE) { 406 /* no interrupt */ 407 pa.pa_intrpin = 0; 408 } else { 409 /* 410 * swizzle it based on the number of busses we're 411 * behind and our device number. 412 */ 413 pa.pa_intrpin = /* XXX */ 414 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 415 } 416 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 417 418 #ifdef __HAVE_PCI_MSI_MSIX 419 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 420 /* 421 * XXX Should we enable MSI mapping ourselves on 422 * systems that have it disabled? 423 */ 424 if (cap & PCI_HT_MSI_ENABLED) { 425 uint64_t addr; 426 if ((cap & PCI_HT_MSI_FIXED) == 0) { 427 addr = pci_conf_read(pc, tag, 428 off + PCI_HT_MSI_ADDR_LO); 429 addr |= (uint64_t)pci_conf_read(pc, tag, 430 off + PCI_HT_MSI_ADDR_HI) << 32; 431 } else 432 addr = PCI_HT_MSI_FIXED_ADDR; 433 434 /* 435 * XXX This will fail to enable MSI on systems 436 * that don't use the canonical address. 437 */ 438 if (addr == PCI_HT_MSI_FIXED_ADDR) { 439 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 440 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 441 } else 442 aprint_verbose_dev(sc->sc_dev, 443 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 444 } 445 } 446 #endif 447 448 if (match != NULL) { 449 ret = (*match)(&pa); 450 if (ret != 0 && pap != NULL) 451 *pap = pa; 452 } else { 453 struct pci_child *c; 454 locs[PCICF_DEV] = device; 455 locs[PCICF_FUNCTION] = function; 456 457 c = &sc->PCI_SC_DEVICESC(device, function); 458 pci_conf_capture(pc, tag, &c->c_conf); 459 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 460 c->c_psok = true; 461 else 462 c->c_psok = false; 463 464 c->c_dev = config_found(sc->sc_dev, &pa, pciprint, 465 CFARG_SUBMATCH, config_stdsubmatch, 466 CFARG_LOCATORS, locs, 467 CFARG_EOL); 468 469 ret = (c->c_dev != NULL); 470 } 471 472 return ret; 473 } 474 475 void 476 pcidevdetached(device_t self, device_t child) 477 { 478 struct pci_softc *sc = device_private(self); 479 int d, f; 480 pcitag_t tag; 481 struct pci_child *c; 482 483 d = device_locator(child, PCICF_DEV); 484 f = device_locator(child, PCICF_FUNCTION); 485 486 c = &sc->PCI_SC_DEVICESC(d, f); 487 488 KASSERT(c->c_dev == child); 489 490 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 491 if (c->c_psok) 492 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 493 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 494 c->c_dev = NULL; 495 } 496 497 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 498 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 499 DVF_DETACH_SHUTDOWN); 500 501 int 502 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 503 int *offset, pcireg_t *value) 504 { 505 pcireg_t reg; 506 unsigned int ofs; 507 508 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 509 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 510 return 0; 511 512 /* Determine the Capability List Pointer register to start with. */ 513 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 514 switch (PCI_HDRTYPE_TYPE(reg)) { 515 case 0: /* standard device header */ 516 case 1: /* PCI-PCI bridge header */ 517 ofs = PCI_CAPLISTPTR_REG; 518 break; 519 case 2: /* PCI-CardBus Bridge header */ 520 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 521 break; 522 default: 523 return 0; 524 } 525 526 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 527 while (ofs != 0) { 528 if ((ofs & 3) || (ofs < 0x40)) { 529 int bus, device, function; 530 531 pci_decompose_tag(pc, tag, &bus, &device, &function); 532 533 printf("Skipping broken PCI header on %d:%d:%d\n", 534 bus, device, function); 535 break; 536 } 537 reg = pci_conf_read(pc, tag, ofs); 538 if (PCI_CAPLIST_CAP(reg) == capid) { 539 if (offset) 540 *offset = ofs; 541 if (value) 542 *value = reg; 543 return 1; 544 } 545 ofs = PCI_CAPLIST_NEXT(reg); 546 } 547 548 return 0; 549 } 550 551 int 552 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 553 int *offset, pcireg_t *value) 554 { 555 pcireg_t reg; 556 unsigned int ofs; 557 558 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 559 return 0; 560 561 while (ofs != 0) { 562 #ifdef DIAGNOSTIC 563 if ((ofs & 3) || (ofs < 0x40)) 564 panic("pci_get_ht_capability"); 565 #endif 566 reg = pci_conf_read(pc, tag, ofs); 567 if (PCI_HT_CAP(reg) == capid) { 568 if (offset) 569 *offset = ofs; 570 if (value) 571 *value = reg; 572 return 1; 573 } 574 ofs = PCI_CAPLIST_NEXT(reg); 575 } 576 577 return 0; 578 } 579 580 /* 581 * return number of the devices's MSI vectors 582 * return 0 if the device does not support MSI 583 */ 584 int 585 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 586 { 587 pcireg_t reg; 588 uint32_t mmc; 589 int count, offset; 590 591 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 592 return 0; 593 594 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 595 mmc = PCI_MSI_CTL_MMC(reg); 596 count = 1 << mmc; 597 if (count > PCI_MSI_MAX_VECTORS) { 598 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 599 return 0; 600 } 601 602 return count; 603 } 604 605 /* 606 * return number of the devices's MSI-X vectors 607 * return 0 if the device does not support MSI-X 608 */ 609 int 610 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 611 { 612 pcireg_t reg; 613 int offset; 614 615 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 616 return 0; 617 618 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 619 620 return PCI_MSIX_CTL_TBLSIZE(reg); 621 } 622 623 int 624 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 625 int *offset, pcireg_t *value) 626 { 627 pcireg_t reg; 628 unsigned int ofs; 629 630 /* Only supported for PCI-express devices */ 631 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 632 return 0; 633 634 ofs = PCI_EXTCAPLIST_BASE; 635 reg = pci_conf_read(pc, tag, ofs); 636 if (reg == 0xffffffff || reg == 0) 637 return 0; 638 639 for (;;) { 640 #ifdef DIAGNOSTIC 641 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 642 panic("%s: invalid offset %u", __func__, ofs); 643 #endif 644 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 645 if (offset != NULL) 646 *offset = ofs; 647 if (value != NULL) 648 *value = reg; 649 return 1; 650 } 651 ofs = PCI_EXTCAPLIST_NEXT(reg); 652 if (ofs == 0) 653 break; 654 reg = pci_conf_read(pc, tag, ofs); 655 } 656 657 return 0; 658 } 659 660 int 661 pci_find_device(struct pci_attach_args *pa, 662 int (*match)(const struct pci_attach_args *)) 663 { 664 extern struct cfdriver pci_cd; 665 device_t pcidev; 666 int i; 667 static const int wildcard[2] = { 668 PCICF_DEV_DEFAULT, 669 PCICF_FUNCTION_DEFAULT 670 }; 671 672 for (i = 0; i < pci_cd.cd_ndevs; i++) { 673 pcidev = device_lookup(&pci_cd, i); 674 if (pcidev != NULL && 675 pci_enumerate_bus(device_private(pcidev), wildcard, 676 match, pa) != 0) 677 return 1; 678 } 679 return 0; 680 } 681 682 #ifndef PCI_MACHDEP_ENUMERATE_BUS 683 /* 684 * Generic PCI bus enumeration routine. Used unless machine-dependent 685 * code needs to provide something else. 686 */ 687 int 688 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 689 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 690 { 691 pci_chipset_tag_t pc = sc->sc_pc; 692 int device, function, nfunctions, ret; 693 const struct pci_quirkdata *qd; 694 pcireg_t id, bhlcr; 695 pcitag_t tag; 696 uint8_t devs[32]; 697 int i, n; 698 699 device_t bridgedev; 700 bool arien = false; 701 bool downstream_port = false; 702 703 /* Check PCIe ARI and port type */ 704 bridgedev = device_parent(sc->sc_dev); 705 if (device_is_a(bridgedev, "ppb")) { 706 struct ppb_softc *ppbsc = device_private(bridgedev); 707 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 708 pcitag_t ppbtag = ppbsc->sc_tag; 709 pcireg_t pciecap, capreg, reg; 710 711 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 712 &pciecap, &capreg) != 0) { 713 switch (PCIE_XCAP_TYPE(capreg)) { 714 case PCIE_XCAP_TYPE_ROOT: 715 case PCIE_XCAP_TYPE_DOWN: 716 case PCIE_XCAP_TYPE_PCI2PCIE: 717 downstream_port = true; 718 break; 719 } 720 721 reg = pci_conf_read(ppbpc, ppbtag, pciecap 722 + PCIE_DCSR2); 723 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 724 arien = true; 725 } 726 } 727 728 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 729 if (downstream_port) { 730 /* PCIe downstream ports only have a single child device */ 731 n = 1; 732 } 733 734 for (i = 0; i < n; i++) { 735 device = devs[i]; 736 737 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 738 (locators[PCICF_DEV] != device)) 739 continue; 740 741 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 742 743 id = pci_conf_read(pc, tag, PCI_ID_REG); 744 745 /* Invalid vendor ID value? */ 746 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 747 continue; 748 /* XXX Not invalid, but we've done this ~forever. */ 749 if (PCI_VENDOR(id) == 0) 750 continue; 751 752 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 753 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 754 continue; 755 756 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 757 758 if (qd != NULL && 759 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 760 nfunctions = 8; 761 else if (qd != NULL && 762 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 763 nfunctions = 1; 764 else if (arien) 765 nfunctions = 8; /* Scan all if ARI is enabled */ 766 else 767 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 768 769 #ifdef __PCI_DEV_FUNCORDER 770 char funcs[8]; 771 int j; 772 for (j = 0; j < nfunctions; j++) { 773 funcs[j] = j; 774 } 775 if (j < __arraycount(funcs)) 776 funcs[j] = -1; 777 if (nfunctions > 1) { 778 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 779 nfunctions, funcs); 780 } 781 for (j = 0; 782 j < 8 && (function = funcs[j]) < 8 && function >= 0; 783 j++) { 784 #else 785 for (function = 0; function < nfunctions; function++) { 786 #endif 787 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 788 && (locators[PCICF_FUNCTION] != function)) 789 continue; 790 791 if (qd != NULL && 792 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 793 continue; 794 tag = pci_make_tag(pc, sc->sc_bus, device, function); 795 ret = pci_probe_device(sc, tag, match, pap); 796 if (match != NULL && ret != 0) 797 return ret; 798 } 799 } 800 return 0; 801 } 802 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 803 804 805 /* 806 * Vital Product Data (PCI 2.2) 807 */ 808 809 int 810 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 811 pcireg_t *data) 812 { 813 uint32_t reg; 814 int ofs, i, j; 815 816 KASSERT(data != NULL); 817 KASSERT((offset + count) < 0x7fff); 818 819 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 820 return 1; 821 822 for (i = 0; i < count; offset += sizeof(*data), i++) { 823 reg &= 0x0000ffff; 824 reg &= ~PCI_VPD_OPFLAG; 825 reg |= PCI_VPD_ADDRESS(offset); 826 pci_conf_write(pc, tag, ofs, reg); 827 828 /* 829 * PCI 2.2 does not specify how long we should poll 830 * for completion nor whether the operation can fail. 831 */ 832 j = 0; 833 do { 834 if (j++ == 20) 835 return 1; 836 delay(4); 837 reg = pci_conf_read(pc, tag, ofs); 838 } while ((reg & PCI_VPD_OPFLAG) == 0); 839 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 840 } 841 842 return 0; 843 } 844 845 int 846 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 847 pcireg_t *data) 848 { 849 pcireg_t reg; 850 int ofs, i, j; 851 852 KASSERT(data != NULL); 853 KASSERT((offset + count) < 0x7fff); 854 855 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 856 return 1; 857 858 for (i = 0; i < count; offset += sizeof(*data), i++) { 859 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 860 861 reg &= 0x0000ffff; 862 reg |= PCI_VPD_OPFLAG; 863 reg |= PCI_VPD_ADDRESS(offset); 864 pci_conf_write(pc, tag, ofs, reg); 865 866 /* 867 * PCI 2.2 does not specify how long we should poll 868 * for completion nor whether the operation can fail. 869 */ 870 j = 0; 871 do { 872 if (j++ == 20) 873 return 1; 874 delay(1); 875 reg = pci_conf_read(pc, tag, ofs); 876 } while (reg & PCI_VPD_OPFLAG); 877 } 878 879 return 0; 880 } 881 882 int 883 pci_dma64_available(const struct pci_attach_args *pa) 884 { 885 #ifdef _PCI_HAVE_DMA64 886 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 887 return 1; 888 #endif 889 return 0; 890 } 891 892 void 893 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 894 struct pci_conf_state *pcs) 895 { 896 int off; 897 898 for (off = 0; off < 16; off++) 899 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 900 901 /* For PCI-X */ 902 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 903 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 904 905 /* For PCIe */ 906 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 907 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 908 unsigned int devtype; 909 910 devtype = PCIE_XCAP_TYPE(xcap); 911 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 912 913 if (PCIE_HAS_LINKREGS(devtype)) 914 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 915 off + PCIE_LCSR); 916 917 if ((xcap & PCIE_XCAP_SI) != 0) 918 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 919 off + PCIE_SLCSR); 920 921 if (PCIE_HAS_ROOTREGS(devtype)) 922 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 923 off + PCIE_RCR); 924 925 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 926 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 927 off + PCIE_DCSR2); 928 929 if (PCIE_HAS_LINKREGS(devtype)) 930 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 931 off + PCIE_LCSR2); 932 933 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 934 } 935 } 936 937 /* For MSI */ 938 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 939 bool bit64, pvmask; 940 941 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 942 943 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 944 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 945 946 /* Address */ 947 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 948 if (bit64) 949 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 950 off + PCI_MSI_MADDR64_HI); 951 952 /* Data */ 953 pcs->msi_mdata = pci_conf_read(pc, tag, 954 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 955 956 /* Per-vector masking */ 957 if (pvmask) 958 pcs->msi_mask = pci_conf_read(pc, tag, 959 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 960 } 961 962 /* For MSI-X */ 963 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 964 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 965 } 966 967 void 968 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 969 struct pci_conf_state *pcs) 970 { 971 int off; 972 pcireg_t val; 973 974 for (off = 15; off >= 0; off--) { 975 val = pci_conf_read(pc, tag, (off * 4)); 976 if (val != pcs->reg[off]) 977 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 978 } 979 980 /* For PCI-X */ 981 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 982 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 983 984 /* For PCIe */ 985 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 986 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 987 unsigned int devtype; 988 989 devtype = PCIE_XCAP_TYPE(xcap); 990 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 991 992 /* 993 * PCIe capability is variable sized. To not to write the next 994 * area, check the existence of each register. 995 */ 996 if (PCIE_HAS_LINKREGS(devtype)) 997 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 998 999 if ((xcap & PCIE_XCAP_SI) != 0) 1000 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 1001 1002 if (PCIE_HAS_ROOTREGS(devtype)) 1003 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1004 1005 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1006 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1007 1008 if (PCIE_HAS_LINKREGS(devtype)) 1009 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1010 pcs->e_lcr2); 1011 1012 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1013 } 1014 } 1015 1016 /* For MSI */ 1017 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1018 pcireg_t reg; 1019 bool bit64, pvmask; 1020 1021 /* First, drop Enable bit in case it's already set. */ 1022 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1023 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1024 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1025 1026 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1027 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1028 1029 /* Address */ 1030 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1031 1032 if (bit64) 1033 pci_conf_write(pc, tag, 1034 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1035 1036 /* Data */ 1037 pci_conf_write(pc, tag, 1038 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1039 pcs->msi_mdata); 1040 1041 /* Per-vector masking */ 1042 if (pvmask) 1043 pci_conf_write(pc, tag, 1044 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1045 pcs->msi_mask); 1046 1047 /* Write CTRL register in the end */ 1048 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1049 } 1050 1051 /* For MSI-X */ 1052 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1053 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1054 } 1055 1056 /* 1057 * Power Management Capability (Rev 2.2) 1058 */ 1059 static int 1060 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1061 int offset) 1062 { 1063 pcireg_t value, now; 1064 1065 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1066 now = value & PCI_PMCSR_STATE_MASK; 1067 switch (now) { 1068 case PCI_PMCSR_STATE_D0: 1069 case PCI_PMCSR_STATE_D1: 1070 case PCI_PMCSR_STATE_D2: 1071 case PCI_PMCSR_STATE_D3: 1072 *state = now; 1073 return 0; 1074 default: 1075 return EINVAL; 1076 } 1077 } 1078 1079 int 1080 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1081 { 1082 int offset; 1083 pcireg_t value; 1084 1085 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1086 return EOPNOTSUPP; 1087 1088 return pci_get_powerstate_int(pc, tag, state, offset); 1089 } 1090 1091 static int 1092 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1093 int offset, pcireg_t cap_reg) 1094 { 1095 pcireg_t value, cap, now; 1096 1097 cap = cap_reg >> PCI_PMCR_SHIFT; 1098 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1099 now = value & PCI_PMCSR_STATE_MASK; 1100 value &= ~PCI_PMCSR_STATE_MASK; 1101 1102 if (now == state) 1103 return 0; 1104 switch (state) { 1105 case PCI_PMCSR_STATE_D0: 1106 break; 1107 case PCI_PMCSR_STATE_D1: 1108 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1109 printf("invalid transition from %d to D1\n", (int)now); 1110 return EINVAL; 1111 } 1112 if (!(cap & PCI_PMCR_D1SUPP)) { 1113 printf("D1 not supported\n"); 1114 return EOPNOTSUPP; 1115 } 1116 break; 1117 case PCI_PMCSR_STATE_D2: 1118 if (now == PCI_PMCSR_STATE_D3) { 1119 printf("invalid transition from %d to D2\n", (int)now); 1120 return EINVAL; 1121 } 1122 if (!(cap & PCI_PMCR_D2SUPP)) { 1123 printf("D2 not supported\n"); 1124 return EOPNOTSUPP; 1125 } 1126 break; 1127 case PCI_PMCSR_STATE_D3: 1128 break; 1129 default: 1130 return EINVAL; 1131 } 1132 value |= state; 1133 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1134 /* delay according to pcipm1.2, ch. 5.6.1 */ 1135 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1136 DELAY(10000); 1137 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1138 DELAY(200); 1139 1140 return 0; 1141 } 1142 1143 int 1144 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1145 { 1146 int offset; 1147 pcireg_t value; 1148 1149 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1150 printf("pci_set_powerstate not supported\n"); 1151 return EOPNOTSUPP; 1152 } 1153 1154 return pci_set_powerstate_int(pc, tag, state, offset, value); 1155 } 1156 1157 int 1158 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1159 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1160 { 1161 pcireg_t pmode; 1162 int error; 1163 1164 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1165 return error; 1166 1167 switch (pmode) { 1168 case PCI_PMCSR_STATE_D0: 1169 break; 1170 case PCI_PMCSR_STATE_D3: 1171 if (wakefun == NULL) { 1172 /* 1173 * The card has lost all configuration data in 1174 * this state, so punt. 1175 */ 1176 aprint_error_dev(dev, 1177 "unable to wake up from power state D3\n"); 1178 return EOPNOTSUPP; 1179 } 1180 /*FALLTHROUGH*/ 1181 default: 1182 if (wakefun) { 1183 error = (*wakefun)(pc, tag, dev, pmode); 1184 if (error) 1185 return error; 1186 } 1187 aprint_normal_dev(dev, "waking up from power state D%d\n", 1188 pmode); 1189 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1190 return error; 1191 } 1192 return 0; 1193 } 1194 1195 int 1196 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1197 device_t dev, pcireg_t state) 1198 { 1199 return 0; 1200 } 1201 1202 struct pci_child_power { 1203 struct pci_conf_state p_pciconf; 1204 pci_chipset_tag_t p_pc; 1205 pcitag_t p_tag; 1206 bool p_has_pm; 1207 int p_pm_offset; 1208 pcireg_t p_pm_cap; 1209 pcireg_t p_class; 1210 pcireg_t p_csr; 1211 }; 1212 1213 static bool 1214 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1215 { 1216 struct pci_child_power *priv = device_pmf_bus_private(dv); 1217 pcireg_t ocsr, csr; 1218 1219 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1220 1221 if (!priv->p_has_pm) 1222 return true; /* ??? hopefully handled by ACPI */ 1223 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1224 return true; /* XXX */ 1225 1226 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1227 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1228 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1229 | PCI_COMMAND_MASTER_ENABLE); 1230 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1231 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1232 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1233 pci_conf_write(priv->p_pc, priv->p_tag, 1234 PCI_COMMAND_STATUS_REG, ocsr); 1235 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1236 return false; 1237 } 1238 return true; 1239 } 1240 1241 static void 1242 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1243 int off) 1244 { 1245 pcireg_t pmcsr; 1246 1247 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1248 1249 if (pmcsr & PCI_PMCSR_PME_STS) { 1250 /* Clear W1C bit */ 1251 pmcsr |= PCI_PMCSR_PME_STS; 1252 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1253 aprint_verbose_dev(dv, "Clear PME# now\n"); 1254 } 1255 } 1256 1257 static bool 1258 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1259 { 1260 struct pci_child_power *priv = device_pmf_bus_private(dv); 1261 1262 if (priv->p_has_pm) { 1263 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1264 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1265 aprint_error_dev(dv, 1266 "unsupported state, continuing.\n"); 1267 return false; 1268 } 1269 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1270 priv->p_pm_offset); 1271 } 1272 1273 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1274 1275 return true; 1276 } 1277 1278 static bool 1279 pci_child_shutdown(device_t dv, int how) 1280 { 1281 struct pci_child_power *priv = device_pmf_bus_private(dv); 1282 pcireg_t csr; 1283 1284 /* restore original bus-mastering state */ 1285 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1286 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1287 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1288 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1289 return true; 1290 } 1291 1292 static void 1293 pci_child_deregister(device_t dv) 1294 { 1295 struct pci_child_power *priv = device_pmf_bus_private(dv); 1296 1297 free(priv, M_DEVBUF); 1298 } 1299 1300 static bool 1301 pci_child_register(device_t child) 1302 { 1303 device_t self = device_parent(child); 1304 struct pci_softc *sc = device_private(self); 1305 struct pci_child_power *priv; 1306 int device, function, off; 1307 pcireg_t reg; 1308 1309 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1310 1311 device = device_locator(child, PCICF_DEV); 1312 function = device_locator(child, PCICF_FUNCTION); 1313 1314 priv->p_pc = sc->sc_pc; 1315 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1316 function); 1317 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1318 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1319 PCI_COMMAND_STATUS_REG); 1320 1321 if (pci_get_capability(priv->p_pc, priv->p_tag, 1322 PCI_CAP_PWRMGMT, &off, ®)) { 1323 priv->p_has_pm = true; 1324 priv->p_pm_offset = off; 1325 priv->p_pm_cap = reg; 1326 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1327 } else { 1328 priv->p_has_pm = false; 1329 priv->p_pm_offset = -1; 1330 } 1331 1332 device_pmf_bus_register(child, priv, pci_child_suspend, 1333 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1334 1335 return true; 1336 } 1337 1338 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1339 1340 static int 1341 pci_modcmd(modcmd_t cmd, void *priv) 1342 { 1343 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1344 return 0; 1345 return ENOTTY; 1346 } 1347
Indexes created Mon Sep 22 05:09:51 GMT 2025