pci.c revision 1.160.4.1
1 /* $NetBSD: pci.c,v 1.160.4.1 2021/08/04 21:27:00 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.160.4.1 2021/08/04 21:27:00 thorpej Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <net/if.h> 57 58 #include "locators.h" 59 60 static bool pci_child_register(device_t); 61 62 #ifdef PCI_CONFIG_DUMP 63 int pci_config_dump = 1; 64 #else 65 int pci_config_dump = 0; 66 #endif 67 68 int pciprint(void *, const char *); 69 70 #ifdef PCI_MACHDEP_ENUMERATE_BUS 71 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 static devhandle_t 271 pci_bus_get_child_devhandle(struct pci_softc *sc, pcitag_t tag) 272 { 273 struct pci_bus_get_child_devhandle_args args = { 274 .pc = sc->sc_pc, 275 .tag = tag, 276 }; 277 278 if (device_call(sc->sc_dev, "pci-bus-get-child-devhandle", 279 &args) != 0) { 280 /* 281 * The call is either not supported or the requested 282 * device was not found in the platform device tree. 283 * Return an invalid handle. 284 */ 285 devhandle_invalidate(&args.devhandle); 286 } 287 288 return args.devhandle; 289 } 290 291 int 292 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 293 int (*match)(const struct pci_attach_args *), 294 struct pci_attach_args *pap) 295 { 296 pci_chipset_tag_t pc = sc->sc_pc; 297 struct pci_attach_args pa; 298 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 299 #ifdef __HAVE_PCI_MSI_MSIX 300 pcireg_t cap; 301 int off; 302 #endif 303 int ret, pin, bus, device, function, i, width; 304 int locs[PCICF_NLOCS]; 305 306 pci_decompose_tag(pc, tag, &bus, &device, &function); 307 308 /* a driver already attached? */ 309 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 310 return 0; 311 312 id = pci_conf_read(pc, tag, PCI_ID_REG); 313 314 /* Invalid vendor ID value? */ 315 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 316 return 0; 317 /* XXX Not invalid, but we've done this ~forever. */ 318 if (PCI_VENDOR(id) == 0) 319 return 0; 320 321 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 322 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 323 return 0; 324 325 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 326 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 327 328 /* Collect memory range info */ 329 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 330 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 331 i = 0; 332 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 333 case PCI_HDRTYPE_PPB: 334 endbar = PCI_MAPREG_PPB_END; 335 break; 336 case PCI_HDRTYPE_PCB: 337 endbar = PCI_MAPREG_PCB_END; 338 break; 339 default: 340 endbar = PCI_MAPREG_END; 341 break; 342 } 343 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 344 struct pci_range *r; 345 pcireg_t type; 346 347 width = 4; 348 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 349 continue; 350 351 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 352 if (PCI_MAPREG_MEM_TYPE(type) == 353 PCI_MAPREG_MEM_TYPE_64BIT) 354 width = 8; 355 356 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 357 if (pci_mapreg_info(pc, tag, bar, type, 358 &r->r_offset, &r->r_size, &r->r_flags) != 0) 359 break; 360 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 361 && (r->r_size == 0x1000000)) { 362 struct pci_range *nr; 363 /* 364 * this has to be a mach64 365 * split things up so each half-aperture can 366 * be mapped PREFETCHABLE except the last page 367 * which may contain registers 368 */ 369 r->r_size = 0x7ff000; 370 r->r_flags = BUS_SPACE_MAP_LINEAR | 371 BUS_SPACE_MAP_PREFETCHABLE; 372 nr = &sc->PCI_SC_DEVICESC(device, 373 function).c_range[i++]; 374 nr->r_offset = r->r_offset + 0x800000; 375 nr->r_size = 0x7ff000; 376 nr->r_flags = BUS_SPACE_MAP_LINEAR | 377 BUS_SPACE_MAP_PREFETCHABLE; 378 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 379 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 380 (bar == 0x10)) { 381 r->r_flags = BUS_SPACE_MAP_LINEAR | 382 BUS_SPACE_MAP_PREFETCHABLE; 383 } 384 } 385 } 386 387 pa.pa_iot = sc->sc_iot; 388 pa.pa_memt = sc->sc_memt; 389 pa.pa_dmat = sc->sc_dmat; 390 pa.pa_dmat64 = sc->sc_dmat64; 391 pa.pa_pc = pc; 392 pa.pa_bus = bus; 393 pa.pa_device = device; 394 pa.pa_function = function; 395 pa.pa_tag = tag; 396 pa.pa_id = id; 397 pa.pa_class = pciclass; 398 399 /* 400 * Set up memory, I/O enable, and PCI command flags 401 * as appropriate. 402 */ 403 pa.pa_flags = sc->sc_flags; 404 405 /* 406 * If the cache line size is not configured, then 407 * clear the MRL/MRM/MWI command-ok flags. 408 */ 409 if (PCI_CACHELINE(bhlcr) == 0) { 410 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 411 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 412 } 413 414 if (sc->sc_bridgetag == NULL) { 415 pa.pa_intrswiz = 0; 416 pa.pa_intrtag = tag; 417 } else { 418 pa.pa_intrswiz = sc->sc_intrswiz + device; 419 pa.pa_intrtag = sc->sc_intrtag; 420 } 421 422 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 423 424 pin = PCI_INTERRUPT_PIN(intr); 425 pa.pa_rawintrpin = pin; 426 if (pin == PCI_INTERRUPT_PIN_NONE) { 427 /* no interrupt */ 428 pa.pa_intrpin = 0; 429 } else { 430 /* 431 * swizzle it based on the number of busses we're 432 * behind and our device number. 433 */ 434 pa.pa_intrpin = /* XXX */ 435 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 436 } 437 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 438 439 devhandle_t devhandle = pci_bus_get_child_devhandle(sc, pa.pa_tag); 440 441 #ifdef __HAVE_PCI_MSI_MSIX 442 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 443 /* 444 * XXX Should we enable MSI mapping ourselves on 445 * systems that have it disabled? 446 */ 447 if (cap & PCI_HT_MSI_ENABLED) { 448 uint64_t addr; 449 if ((cap & PCI_HT_MSI_FIXED) == 0) { 450 addr = pci_conf_read(pc, tag, 451 off + PCI_HT_MSI_ADDR_LO); 452 addr |= (uint64_t)pci_conf_read(pc, tag, 453 off + PCI_HT_MSI_ADDR_HI) << 32; 454 } else 455 addr = PCI_HT_MSI_FIXED_ADDR; 456 457 /* 458 * XXX This will fail to enable MSI on systems 459 * that don't use the canonical address. 460 */ 461 if (addr == PCI_HT_MSI_FIXED_ADDR) { 462 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 463 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 464 } else 465 aprint_verbose_dev(sc->sc_dev, 466 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 467 } 468 } 469 #endif 470 471 if (match != NULL) { 472 ret = (*match)(&pa); 473 if (ret != 0 && pap != NULL) 474 *pap = pa; 475 } else { 476 struct pci_child *c; 477 locs[PCICF_DEV] = device; 478 locs[PCICF_FUNCTION] = function; 479 480 c = &sc->PCI_SC_DEVICESC(device, function); 481 pci_conf_capture(pc, tag, &c->c_conf); 482 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 483 c->c_psok = true; 484 else 485 c->c_psok = false; 486 487 c->c_dev = config_found(sc->sc_dev, &pa, pciprint, 488 CFARGS(.submatch = config_stdsubmatch, 489 .locators = locs, 490 .devhandle = devhandle)); 491 492 ret = (c->c_dev != NULL); 493 } 494 495 return ret; 496 } 497 498 void 499 pcidevdetached(device_t self, device_t child) 500 { 501 struct pci_softc *sc = device_private(self); 502 int d, f; 503 pcitag_t tag; 504 struct pci_child *c; 505 506 d = device_locator(child, PCICF_DEV); 507 f = device_locator(child, PCICF_FUNCTION); 508 509 c = &sc->PCI_SC_DEVICESC(d, f); 510 511 KASSERT(c->c_dev == child); 512 513 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 514 if (c->c_psok) 515 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 516 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 517 c->c_dev = NULL; 518 } 519 520 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 521 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 522 DVF_DETACH_SHUTDOWN); 523 524 int 525 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 526 int *offset, pcireg_t *value) 527 { 528 pcireg_t reg; 529 unsigned int ofs; 530 531 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 532 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 533 return 0; 534 535 /* Determine the Capability List Pointer register to start with. */ 536 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 537 switch (PCI_HDRTYPE_TYPE(reg)) { 538 case 0: /* standard device header */ 539 case 1: /* PCI-PCI bridge header */ 540 ofs = PCI_CAPLISTPTR_REG; 541 break; 542 case 2: /* PCI-CardBus Bridge header */ 543 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 544 break; 545 default: 546 return 0; 547 } 548 549 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 550 while (ofs != 0) { 551 if ((ofs & 3) || (ofs < 0x40)) { 552 int bus, device, function; 553 554 pci_decompose_tag(pc, tag, &bus, &device, &function); 555 556 printf("Skipping broken PCI header on %d:%d:%d\n", 557 bus, device, function); 558 break; 559 } 560 reg = pci_conf_read(pc, tag, ofs); 561 if (PCI_CAPLIST_CAP(reg) == capid) { 562 if (offset) 563 *offset = ofs; 564 if (value) 565 *value = reg; 566 return 1; 567 } 568 ofs = PCI_CAPLIST_NEXT(reg); 569 } 570 571 return 0; 572 } 573 574 int 575 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 576 int *offset, pcireg_t *value) 577 { 578 pcireg_t reg; 579 unsigned int ofs; 580 581 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 582 return 0; 583 584 while (ofs != 0) { 585 #ifdef DIAGNOSTIC 586 if ((ofs & 3) || (ofs < 0x40)) 587 panic("pci_get_ht_capability"); 588 #endif 589 reg = pci_conf_read(pc, tag, ofs); 590 if (PCI_HT_CAP(reg) == capid) { 591 if (offset) 592 *offset = ofs; 593 if (value) 594 *value = reg; 595 return 1; 596 } 597 ofs = PCI_CAPLIST_NEXT(reg); 598 } 599 600 return 0; 601 } 602 603 /* 604 * return number of the devices's MSI vectors 605 * return 0 if the device does not support MSI 606 */ 607 int 608 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 609 { 610 pcireg_t reg; 611 uint32_t mmc; 612 int count, offset; 613 614 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 615 return 0; 616 617 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 618 mmc = PCI_MSI_CTL_MMC(reg); 619 count = 1 << mmc; 620 if (count > PCI_MSI_MAX_VECTORS) { 621 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 622 return 0; 623 } 624 625 return count; 626 } 627 628 /* 629 * return number of the devices's MSI-X vectors 630 * return 0 if the device does not support MSI-X 631 */ 632 int 633 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 634 { 635 pcireg_t reg; 636 int offset; 637 638 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 639 return 0; 640 641 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 642 643 return PCI_MSIX_CTL_TBLSIZE(reg); 644 } 645 646 int 647 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 648 int *offset, pcireg_t *value) 649 { 650 pcireg_t reg; 651 unsigned int ofs; 652 653 /* Only supported for PCI-express devices */ 654 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 655 return 0; 656 657 ofs = PCI_EXTCAPLIST_BASE; 658 reg = pci_conf_read(pc, tag, ofs); 659 if (reg == 0xffffffff || reg == 0) 660 return 0; 661 662 for (;;) { 663 #ifdef DIAGNOSTIC 664 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 665 panic("%s: invalid offset %u", __func__, ofs); 666 #endif 667 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 668 if (offset != NULL) 669 *offset = ofs; 670 if (value != NULL) 671 *value = reg; 672 return 1; 673 } 674 ofs = PCI_EXTCAPLIST_NEXT(reg); 675 if (ofs == 0) 676 break; 677 reg = pci_conf_read(pc, tag, ofs); 678 } 679 680 return 0; 681 } 682 683 int 684 pci_find_device(struct pci_attach_args *pa, 685 int (*match)(const struct pci_attach_args *)) 686 { 687 extern struct cfdriver pci_cd; 688 device_t pcidev; 689 int i; 690 static const int wildcard[2] = { 691 PCICF_DEV_DEFAULT, 692 PCICF_FUNCTION_DEFAULT 693 }; 694 695 for (i = 0; i < pci_cd.cd_ndevs; i++) { 696 pcidev = device_lookup(&pci_cd, i); 697 if (pcidev != NULL && 698 pci_enumerate_bus(device_private(pcidev), wildcard, 699 match, pa) != 0) 700 return 1; 701 } 702 return 0; 703 } 704 705 #ifndef PCI_MACHDEP_ENUMERATE_BUS 706 /* 707 * Generic PCI bus enumeration routine. Used unless machine-dependent 708 * code needs to provide something else. 709 */ 710 int 711 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 712 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 713 { 714 pci_chipset_tag_t pc = sc->sc_pc; 715 int device, function, nfunctions, ret; 716 const struct pci_quirkdata *qd; 717 pcireg_t id, bhlcr; 718 pcitag_t tag; 719 uint8_t devs[32]; 720 int i, n; 721 722 device_t bridgedev; 723 bool arien = false; 724 bool downstream_port = false; 725 726 /* Check PCIe ARI and port type */ 727 bridgedev = device_parent(sc->sc_dev); 728 if (device_is_a(bridgedev, "ppb")) { 729 struct ppb_softc *ppbsc = device_private(bridgedev); 730 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 731 pcitag_t ppbtag = ppbsc->sc_tag; 732 pcireg_t pciecap, capreg, reg; 733 734 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 735 &pciecap, &capreg) != 0) { 736 switch (PCIE_XCAP_TYPE(capreg)) { 737 case PCIE_XCAP_TYPE_ROOT: 738 case PCIE_XCAP_TYPE_DOWN: 739 case PCIE_XCAP_TYPE_PCI2PCIE: 740 downstream_port = true; 741 break; 742 } 743 744 reg = pci_conf_read(ppbpc, ppbtag, pciecap 745 + PCIE_DCSR2); 746 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 747 arien = true; 748 } 749 } 750 751 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 752 if (downstream_port) { 753 /* PCIe downstream ports only have a single child device */ 754 n = 1; 755 } 756 757 for (i = 0; i < n; i++) { 758 device = devs[i]; 759 760 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 761 (locators[PCICF_DEV] != device)) 762 continue; 763 764 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 765 766 id = pci_conf_read(pc, tag, PCI_ID_REG); 767 768 /* Invalid vendor ID value? */ 769 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 770 continue; 771 /* XXX Not invalid, but we've done this ~forever. */ 772 if (PCI_VENDOR(id) == 0) 773 continue; 774 775 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 776 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 777 continue; 778 779 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 780 781 if (qd != NULL && 782 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 783 nfunctions = 8; 784 else if (qd != NULL && 785 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 786 nfunctions = 1; 787 else if (arien) 788 nfunctions = 8; /* Scan all if ARI is enabled */ 789 else 790 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 791 792 #ifdef __PCI_DEV_FUNCORDER 793 char funcs[8]; 794 int j; 795 for (j = 0; j < nfunctions; j++) { 796 funcs[j] = j; 797 } 798 if (j < __arraycount(funcs)) 799 funcs[j] = -1; 800 if (nfunctions > 1) { 801 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 802 nfunctions, funcs); 803 } 804 for (j = 0; 805 j < 8 && (function = funcs[j]) < 8 && function >= 0; 806 j++) { 807 #else 808 for (function = 0; function < nfunctions; function++) { 809 #endif 810 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 811 && (locators[PCICF_FUNCTION] != function)) 812 continue; 813 814 if (qd != NULL && 815 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 816 continue; 817 tag = pci_make_tag(pc, sc->sc_bus, device, function); 818 ret = pci_probe_device(sc, tag, match, pap); 819 if (match != NULL && ret != 0) 820 return ret; 821 } 822 } 823 return 0; 824 } 825 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 826 827 828 /* 829 * Vital Product Data (PCI 2.2) 830 */ 831 832 int 833 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 834 pcireg_t *data) 835 { 836 uint32_t reg; 837 int ofs, i, j; 838 839 KASSERT(data != NULL); 840 KASSERT((offset + count) < 0x7fff); 841 842 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 843 return 1; 844 845 for (i = 0; i < count; offset += sizeof(*data), i++) { 846 reg &= 0x0000ffff; 847 reg &= ~PCI_VPD_OPFLAG; 848 reg |= PCI_VPD_ADDRESS(offset); 849 pci_conf_write(pc, tag, ofs, reg); 850 851 /* 852 * PCI 2.2 does not specify how long we should poll 853 * for completion nor whether the operation can fail. 854 */ 855 j = 0; 856 do { 857 if (j++ == 20) 858 return 1; 859 delay(4); 860 reg = pci_conf_read(pc, tag, ofs); 861 } while ((reg & PCI_VPD_OPFLAG) == 0); 862 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 863 } 864 865 return 0; 866 } 867 868 int 869 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 870 pcireg_t *data) 871 { 872 pcireg_t reg; 873 int ofs, i, j; 874 875 KASSERT(data != NULL); 876 KASSERT((offset + count) < 0x7fff); 877 878 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 879 return 1; 880 881 for (i = 0; i < count; offset += sizeof(*data), i++) { 882 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 883 884 reg &= 0x0000ffff; 885 reg |= PCI_VPD_OPFLAG; 886 reg |= PCI_VPD_ADDRESS(offset); 887 pci_conf_write(pc, tag, ofs, reg); 888 889 /* 890 * PCI 2.2 does not specify how long we should poll 891 * for completion nor whether the operation can fail. 892 */ 893 j = 0; 894 do { 895 if (j++ == 20) 896 return 1; 897 delay(1); 898 reg = pci_conf_read(pc, tag, ofs); 899 } while (reg & PCI_VPD_OPFLAG); 900 } 901 902 return 0; 903 } 904 905 int 906 pci_dma64_available(const struct pci_attach_args *pa) 907 { 908 #ifdef _PCI_HAVE_DMA64 909 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 910 return 1; 911 #endif 912 return 0; 913 } 914 915 void 916 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 917 struct pci_conf_state *pcs) 918 { 919 int off; 920 921 for (off = 0; off < 16; off++) 922 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 923 924 /* For PCI-X */ 925 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 926 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 927 928 /* For PCIe */ 929 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 930 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 931 unsigned int devtype; 932 933 devtype = PCIE_XCAP_TYPE(xcap); 934 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 935 936 if (PCIE_HAS_LINKREGS(devtype)) 937 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 938 off + PCIE_LCSR); 939 940 if ((xcap & PCIE_XCAP_SI) != 0) 941 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 942 off + PCIE_SLCSR); 943 944 if (PCIE_HAS_ROOTREGS(devtype)) 945 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 946 off + PCIE_RCR); 947 948 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 949 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 950 off + PCIE_DCSR2); 951 952 if (PCIE_HAS_LINKREGS(devtype)) 953 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 954 off + PCIE_LCSR2); 955 956 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 957 } 958 } 959 960 /* For MSI */ 961 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 962 bool bit64, pvmask; 963 964 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 965 966 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 967 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 968 969 /* Address */ 970 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 971 if (bit64) 972 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 973 off + PCI_MSI_MADDR64_HI); 974 975 /* Data */ 976 pcs->msi_mdata = pci_conf_read(pc, tag, 977 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 978 979 /* Per-vector masking */ 980 if (pvmask) 981 pcs->msi_mask = pci_conf_read(pc, tag, 982 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 983 } 984 985 /* For MSI-X */ 986 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 987 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 988 } 989 990 void 991 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 992 struct pci_conf_state *pcs) 993 { 994 int off; 995 pcireg_t val; 996 997 for (off = 15; off >= 0; off--) { 998 val = pci_conf_read(pc, tag, (off * 4)); 999 if (val != pcs->reg[off]) 1000 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 1001 } 1002 1003 /* For PCI-X */ 1004 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 1005 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 1006 1007 /* For PCIe */ 1008 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 1009 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 1010 unsigned int devtype; 1011 1012 devtype = PCIE_XCAP_TYPE(xcap); 1013 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 1014 1015 /* 1016 * PCIe capability is variable sized. To not to write the next 1017 * area, check the existence of each register. 1018 */ 1019 if (PCIE_HAS_LINKREGS(devtype)) 1020 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 1021 1022 if ((xcap & PCIE_XCAP_SI) != 0) 1023 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 1024 1025 if (PCIE_HAS_ROOTREGS(devtype)) 1026 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1027 1028 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1029 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1030 1031 if (PCIE_HAS_LINKREGS(devtype)) 1032 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1033 pcs->e_lcr2); 1034 1035 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1036 } 1037 } 1038 1039 /* For MSI */ 1040 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1041 pcireg_t reg; 1042 bool bit64, pvmask; 1043 1044 /* First, drop Enable bit in case it's already set. */ 1045 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1046 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1047 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1048 1049 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1050 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1051 1052 /* Address */ 1053 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1054 1055 if (bit64) 1056 pci_conf_write(pc, tag, 1057 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1058 1059 /* Data */ 1060 pci_conf_write(pc, tag, 1061 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1062 pcs->msi_mdata); 1063 1064 /* Per-vector masking */ 1065 if (pvmask) 1066 pci_conf_write(pc, tag, 1067 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1068 pcs->msi_mask); 1069 1070 /* Write CTRL register in the end */ 1071 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1072 } 1073 1074 /* For MSI-X */ 1075 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1076 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1077 } 1078 1079 /* 1080 * Power Management Capability (Rev 2.2) 1081 */ 1082 static int 1083 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1084 int offset) 1085 { 1086 pcireg_t value, now; 1087 1088 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1089 now = value & PCI_PMCSR_STATE_MASK; 1090 switch (now) { 1091 case PCI_PMCSR_STATE_D0: 1092 case PCI_PMCSR_STATE_D1: 1093 case PCI_PMCSR_STATE_D2: 1094 case PCI_PMCSR_STATE_D3: 1095 *state = now; 1096 return 0; 1097 default: 1098 return EINVAL; 1099 } 1100 } 1101 1102 int 1103 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1104 { 1105 int offset; 1106 pcireg_t value; 1107 1108 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1109 return EOPNOTSUPP; 1110 1111 return pci_get_powerstate_int(pc, tag, state, offset); 1112 } 1113 1114 static int 1115 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1116 int offset, pcireg_t cap_reg) 1117 { 1118 pcireg_t value, cap, now; 1119 1120 cap = cap_reg >> PCI_PMCR_SHIFT; 1121 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1122 now = value & PCI_PMCSR_STATE_MASK; 1123 value &= ~PCI_PMCSR_STATE_MASK; 1124 1125 if (now == state) 1126 return 0; 1127 switch (state) { 1128 case PCI_PMCSR_STATE_D0: 1129 break; 1130 case PCI_PMCSR_STATE_D1: 1131 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1132 printf("invalid transition from %d to D1\n", (int)now); 1133 return EINVAL; 1134 } 1135 if (!(cap & PCI_PMCR_D1SUPP)) { 1136 printf("D1 not supported\n"); 1137 return EOPNOTSUPP; 1138 } 1139 break; 1140 case PCI_PMCSR_STATE_D2: 1141 if (now == PCI_PMCSR_STATE_D3) { 1142 printf("invalid transition from %d to D2\n", (int)now); 1143 return EINVAL; 1144 } 1145 if (!(cap & PCI_PMCR_D2SUPP)) { 1146 printf("D2 not supported\n"); 1147 return EOPNOTSUPP; 1148 } 1149 break; 1150 case PCI_PMCSR_STATE_D3: 1151 break; 1152 default: 1153 return EINVAL; 1154 } 1155 value |= state; 1156 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1157 /* delay according to pcipm1.2, ch. 5.6.1 */ 1158 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1159 DELAY(10000); 1160 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1161 DELAY(200); 1162 1163 return 0; 1164 } 1165 1166 int 1167 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1168 { 1169 int offset; 1170 pcireg_t value; 1171 1172 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1173 printf("pci_set_powerstate not supported\n"); 1174 return EOPNOTSUPP; 1175 } 1176 1177 return pci_set_powerstate_int(pc, tag, state, offset, value); 1178 } 1179 1180 int 1181 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1182 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1183 { 1184 pcireg_t pmode; 1185 int error; 1186 1187 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1188 return error; 1189 1190 switch (pmode) { 1191 case PCI_PMCSR_STATE_D0: 1192 break; 1193 case PCI_PMCSR_STATE_D3: 1194 if (wakefun == NULL) { 1195 /* 1196 * The card has lost all configuration data in 1197 * this state, so punt. 1198 */ 1199 aprint_error_dev(dev, 1200 "unable to wake up from power state D3\n"); 1201 return EOPNOTSUPP; 1202 } 1203 /*FALLTHROUGH*/ 1204 default: 1205 if (wakefun) { 1206 error = (*wakefun)(pc, tag, dev, pmode); 1207 if (error) 1208 return error; 1209 } 1210 aprint_normal_dev(dev, "waking up from power state D%d\n", 1211 pmode); 1212 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1213 return error; 1214 } 1215 return 0; 1216 } 1217 1218 int 1219 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1220 device_t dev, pcireg_t state) 1221 { 1222 return 0; 1223 } 1224 1225 struct pci_child_power { 1226 struct pci_conf_state p_pciconf; 1227 pci_chipset_tag_t p_pc; 1228 pcitag_t p_tag; 1229 bool p_has_pm; 1230 int p_pm_offset; 1231 pcireg_t p_pm_cap; 1232 pcireg_t p_class; 1233 pcireg_t p_csr; 1234 }; 1235 1236 static bool 1237 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1238 { 1239 struct pci_child_power *priv = device_pmf_bus_private(dv); 1240 pcireg_t ocsr, csr; 1241 1242 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1243 1244 if (!priv->p_has_pm) 1245 return true; /* ??? hopefully handled by ACPI */ 1246 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1247 return true; /* XXX */ 1248 1249 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1250 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1251 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1252 | PCI_COMMAND_MASTER_ENABLE); 1253 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1254 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1255 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1256 pci_conf_write(priv->p_pc, priv->p_tag, 1257 PCI_COMMAND_STATUS_REG, ocsr); 1258 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1259 return false; 1260 } 1261 return true; 1262 } 1263 1264 static void 1265 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1266 int off) 1267 { 1268 pcireg_t pmcsr; 1269 1270 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1271 1272 if (pmcsr & PCI_PMCSR_PME_STS) { 1273 /* Clear W1C bit */ 1274 pmcsr |= PCI_PMCSR_PME_STS; 1275 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1276 aprint_verbose_dev(dv, "Clear PME# now\n"); 1277 } 1278 } 1279 1280 static bool 1281 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1282 { 1283 struct pci_child_power *priv = device_pmf_bus_private(dv); 1284 1285 if (priv->p_has_pm) { 1286 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1287 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1288 aprint_error_dev(dv, 1289 "unsupported state, continuing.\n"); 1290 return false; 1291 } 1292 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1293 priv->p_pm_offset); 1294 } 1295 1296 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1297 1298 return true; 1299 } 1300 1301 static bool 1302 pci_child_shutdown(device_t dv, int how) 1303 { 1304 struct pci_child_power *priv = device_pmf_bus_private(dv); 1305 pcireg_t csr; 1306 1307 /* restore original bus-mastering state */ 1308 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1309 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1310 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1311 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1312 return true; 1313 } 1314 1315 static void 1316 pci_child_deregister(device_t dv) 1317 { 1318 struct pci_child_power *priv = device_pmf_bus_private(dv); 1319 1320 free(priv, M_DEVBUF); 1321 } 1322 1323 static bool 1324 pci_child_register(device_t child) 1325 { 1326 device_t self = device_parent(child); 1327 struct pci_softc *sc = device_private(self); 1328 struct pci_child_power *priv; 1329 int device, function, off; 1330 pcireg_t reg; 1331 1332 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1333 1334 device = device_locator(child, PCICF_DEV); 1335 function = device_locator(child, PCICF_FUNCTION); 1336 1337 priv->p_pc = sc->sc_pc; 1338 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1339 function); 1340 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1341 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1342 PCI_COMMAND_STATUS_REG); 1343 1344 if (pci_get_capability(priv->p_pc, priv->p_tag, 1345 PCI_CAP_PWRMGMT, &off, ®)) { 1346 priv->p_has_pm = true; 1347 priv->p_pm_offset = off; 1348 priv->p_pm_cap = reg; 1349 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1350 } else { 1351 priv->p_has_pm = false; 1352 priv->p_pm_offset = -1; 1353 } 1354 1355 device_pmf_bus_register(child, priv, pci_child_suspend, 1356 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1357 1358 return true; 1359 } 1360 1361 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1362 1363 static int 1364 pci_modcmd(modcmd_t cmd, void *priv) 1365 { 1366 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1367 return 0; 1368 return ENOTTY; 1369 } 1370
Indexes created Tue Sep 30 17:09:57 GMT 2025