pci.c revision 1.25
1 /* $NetBSD: pci.c,v 1.25 1996/11/23 21:58:16 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus autoconfiguration. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 int pcimatch __P((struct device *, void *, void *)); 45 void pciattach __P((struct device *, struct device *, void *)); 46 47 struct cfattach pci_ca = { 48 sizeof(struct device), pcimatch, pciattach 49 }; 50 51 struct cfdriver pci_cd = { 52 NULL, "pci", DV_DULL 53 }; 54 55 int pciprint __P((void *, const char *)); 56 int pcisubmatch __P((struct device *, void *, void *)); 57 58 /* 59 * Callback so that ISA/EISA bridges can attach their child busses 60 * after PCI configuration is done. 61 * 62 * This works because: 63 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 64 * (2) any ISA/EISA bridges must be attached to primary PCI 65 * busses (i.e. bus zero). 66 * 67 * That boils down to: there can only be one of these outstanding 68 * at a time, it is cleared when configuring PCI bus 0 before any 69 * subdevices have been found, and it is run after all subdevices 70 * of PCI bus 0 have been found. 71 * 72 * This is needed because there are some (legacy) PCI devices which 73 * can show up as ISA/EISA devices as well (the prime example of which 74 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 75 * and the bridge is seen before the video board is, the board can show 76 * up as an ISA device, and that can (bogusly) complicate the PCI device's 77 * attach code, or make the PCI device not be properly attached at all. 78 */ 79 static void (*pci_isa_bridge_callback) __P((void *)); 80 static void *pci_isa_bridge_callback_arg; 81 82 int 83 pcimatch(parent, match, aux) 84 struct device *parent; 85 void *match, *aux; 86 { 87 struct cfdata *cf = match; 88 struct pcibus_attach_args *pba = aux; 89 90 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 91 return (0); 92 93 /* Check the locators */ 94 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 95 cf->pcibuscf_bus != pba->pba_bus) 96 return (0); 97 98 /* sanity */ 99 if (pba->pba_bus < 0 || pba->pba_bus > 255) 100 return (0); 101 102 /* 103 * XXX check other (hardware?) indicators 104 */ 105 106 return 1; 107 } 108 109 void 110 pciattach(parent, self, aux) 111 struct device *parent, *self; 112 void *aux; 113 { 114 struct pcibus_attach_args *pba = aux; 115 bus_space_tag_t iot, memt; 116 pci_chipset_tag_t pc; 117 int bus, device, maxndevs, function, nfunctions; 118 119 pci_attach_hook(parent, self, pba); 120 printf("\n"); 121 122 iot = pba->pba_iot; 123 memt = pba->pba_memt; 124 pc = pba->pba_pc; 125 bus = pba->pba_bus; 126 maxndevs = pci_bus_maxdevs(pc, bus); 127 128 if (bus == 0) 129 pci_isa_bridge_callback = NULL; 130 131 for (device = 0; device < maxndevs; device++) { 132 pcitag_t tag; 133 pcireg_t id, class, intr, bhlcr; 134 struct pci_attach_args pa; 135 int pin; 136 137 tag = pci_make_tag(pc, bus, device, 0); 138 id = pci_conf_read(pc, tag, PCI_ID_REG); 139 if (id == 0 || id == 0xffffffff) 140 continue; 141 142 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 143 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 144 145 for (function = 0; function < nfunctions; function++) { 146 tag = pci_make_tag(pc, bus, device, function); 147 id = pci_conf_read(pc, tag, PCI_ID_REG); 148 if (id == 0 || id == 0xffffffff) 149 continue; 150 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 151 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 152 153 pa.pa_iot = iot; 154 pa.pa_memt = memt; 155 pa.pa_pc = pc; 156 pa.pa_device = device; 157 pa.pa_function = function; 158 pa.pa_tag = tag; 159 pa.pa_id = id; 160 pa.pa_class = class; 161 162 if (bus == 0) { 163 pa.pa_intrswiz = 0; 164 pa.pa_intrtag = tag; 165 } else { 166 pa.pa_intrswiz = pba->pba_intrswiz + device; 167 pa.pa_intrtag = pba->pba_intrtag; 168 } 169 pin = PCI_INTERRUPT_PIN(intr); 170 if (pin == PCI_INTERRUPT_PIN_NONE) { 171 /* no interrupt */ 172 pa.pa_intrpin = 0; 173 } else { 174 /* 175 * swizzle it based on the number of 176 * busses we're behind and our device 177 * number. 178 */ 179 pa.pa_intrpin = /* XXX */ 180 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 181 } 182 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 183 184 config_found_sm(self, &pa, pciprint, pcisubmatch); 185 } 186 } 187 188 if (bus == 0 && pci_isa_bridge_callback != NULL) 189 (*pci_isa_bridge_callback)(pci_isa_bridge_callback_arg); 190 } 191 192 int 193 pciprint(aux, pnp) 194 void *aux; 195 const char *pnp; 196 { 197 register struct pci_attach_args *pa = aux; 198 char devinfo[256]; 199 200 if (pnp) { 201 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 202 printf("%s at %s", devinfo, pnp); 203 } 204 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 205 return (UNCONF); 206 } 207 208 int 209 pcisubmatch(parent, match, aux) 210 struct device *parent; 211 void *match, *aux; 212 { 213 struct cfdata *cf = match; 214 struct pci_attach_args *pa = aux; 215 216 if (cf->pcicf_dev != PCI_UNK_DEV && 217 cf->pcicf_dev != pa->pa_device) 218 return 0; 219 if (cf->pcicf_function != PCI_UNK_FUNCTION && 220 cf->pcicf_function != pa->pa_function) 221 return 0; 222 return ((*cf->cf_attach->ca_match)(parent, match, aux)); 223 } 224 225 int 226 pci_io_find(pc, pcitag, reg, iobasep, iosizep) 227 pci_chipset_tag_t pc; 228 pcitag_t pcitag; 229 int reg; 230 bus_addr_t *iobasep; 231 bus_size_t *iosizep; 232 { 233 pcireg_t addrdata, sizedata; 234 int s; 235 236 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) 237 panic("pci_io_find: bad request"); 238 239 /* XXX? 240 * Section 6.2.5.1, `Address Maps', tells us that: 241 * 242 * 1) The builtin software should have already mapped the device in a 243 * reasonable way. 244 * 245 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 246 * n bits of the address to 0. As recommended, we write all 1s and see 247 * what we get back. 248 */ 249 addrdata = pci_conf_read(pc, pcitag, reg); 250 251 s = splhigh(); 252 pci_conf_write(pc, pcitag, reg, 0xffffffff); 253 sizedata = pci_conf_read(pc, pcitag, reg); 254 pci_conf_write(pc, pcitag, reg, addrdata); 255 splx(s); 256 257 if (PCI_MAPREG_TYPE(addrdata) != PCI_MAPREG_TYPE_IO) 258 panic("pci_io_find: not an I/O region"); 259 260 if (iobasep != NULL) 261 *iobasep = PCI_MAPREG_IO_ADDR(addrdata); 262 if (iosizep != NULL) 263 *iosizep = PCI_MAPREG_IO_SIZE(sizedata); 264 265 return (0); 266 } 267 268 int 269 pci_mem_find(pc, pcitag, reg, membasep, memsizep, cacheablep) 270 pci_chipset_tag_t pc; 271 pcitag_t pcitag; 272 int reg; 273 bus_addr_t *membasep; 274 bus_size_t *memsizep; 275 int *cacheablep; 276 { 277 pcireg_t addrdata, sizedata; 278 int s; 279 280 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) 281 panic("pci_find_mem: bad request"); 282 283 /* 284 * Section 6.2.5.1, `Address Maps', tells us that: 285 * 286 * 1) The builtin software should have already mapped the device in a 287 * reasonable way. 288 * 289 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 290 * n bits of the address to 0. As recommended, we write all 1s and see 291 * what we get back. 292 */ 293 addrdata = pci_conf_read(pc, pcitag, reg); 294 295 s = splhigh(); 296 pci_conf_write(pc, pcitag, reg, 0xffffffff); 297 sizedata = pci_conf_read(pc, pcitag, reg); 298 pci_conf_write(pc, pcitag, reg, addrdata); 299 splx(s); 300 301 if (PCI_MAPREG_TYPE(addrdata) == PCI_MAPREG_TYPE_IO) 302 panic("pci_find_mem: I/O region"); 303 304 switch (PCI_MAPREG_MEM_TYPE(addrdata)) { 305 case PCI_MAPREG_MEM_TYPE_32BIT: 306 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 307 break; 308 case PCI_MAPREG_MEM_TYPE_64BIT: 309 /* XXX */ printf("pci_find_mem: 64-bit region\n"); 310 /* XXX */ return (1); 311 default: 312 printf("pci_find_mem: reserved region type\n"); 313 return (1); 314 } 315 316 if (membasep != NULL) 317 *membasep = PCI_MAPREG_MEM_ADDR(addrdata); /* PCI addr */ 318 if (memsizep != NULL) 319 *memsizep = PCI_MAPREG_MEM_SIZE(sizedata); 320 if (cacheablep != NULL) 321 *cacheablep = PCI_MAPREG_MEM_CACHEABLE(addrdata); 322 323 return 0; 324 } 325 326 void 327 set_pci_isa_bridge_callback(fn, arg) 328 void (*fn) __P((void *)); 329 void *arg; 330 { 331 332 if (pci_isa_bridge_callback != NULL) 333 panic("set_pci_isa_bridge_callback"); 334 pci_isa_bridge_callback = fn; 335 pci_isa_bridge_callback_arg = arg; 336 } 337
Indexes created Tue Sep 30 17:09:57 GMT 2025