pci.c revision 1.42.4.1
1 /* $NetBSD: pci.c,v 1.42.4.1 1999/11/15 00:41:07 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 int pcimatch __P((struct device *, struct cfdata *, void *)); 47 void pciattach __P((struct device *, struct device *, void *)); 48 49 struct pci_softc { 50 struct device sc_dev; 51 bus_space_tag_t sc_iot, sc_memt; 52 bus_dma_tag_t sc_dmat; 53 pci_chipset_tag_t sc_pc; 54 int sc_bus, sc_maxndevs; 55 u_int sc_intrswiz; 56 pcitag_t sc_intrtag; 57 int sc_flags; 58 }; 59 60 struct cfattach pci_ca = { 61 sizeof(struct pci_softc), pcimatch, pciattach 62 }; 63 64 void pci_probe_bus __P((struct device *)); 65 int pciprint __P((void *, const char *)); 66 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 67 68 /* 69 * Important note about PCI-ISA bridges: 70 * 71 * Callbacks are used to configure these devices so that ISA/EISA bridges 72 * can attach their child busses after PCI configuration is done. 73 * 74 * This works because: 75 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 76 * (2) any ISA/EISA bridges must be attached to primary PCI 77 * busses (i.e. bus zero). 78 * 79 * That boils down to: there can only be one of these outstanding 80 * at a time, it is cleared when configuring PCI bus 0 before any 81 * subdevices have been found, and it is run after all subdevices 82 * of PCI bus 0 have been found. 83 * 84 * This is needed because there are some (legacy) PCI devices which 85 * can show up as ISA/EISA devices as well (the prime example of which 86 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 87 * and the bridge is seen before the video board is, the board can show 88 * up as an ISA device, and that can (bogusly) complicate the PCI device's 89 * attach code, or make the PCI device not be properly attached at all. 90 * 91 * We use the generic config_defer() facility to achieve this. 92 */ 93 94 int 95 pcimatch(parent, cf, aux) 96 struct device *parent; 97 struct cfdata *cf; 98 void *aux; 99 { 100 struct pcibus_attach_args *pba = aux; 101 102 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 103 return (0); 104 105 /* Check the locators */ 106 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 107 cf->pcibuscf_bus != pba->pba_bus) 108 return (0); 109 110 /* sanity */ 111 if (pba->pba_bus < 0 || pba->pba_bus > 255) 112 return (0); 113 114 /* 115 * XXX check other (hardware?) indicators 116 */ 117 118 return 1; 119 } 120 121 void 122 pci_probe_bus(self) 123 struct device *self; 124 { 125 struct pci_softc *sc = (struct pci_softc *)self; 126 bus_space_tag_t iot, memt; 127 pci_chipset_tag_t pc; 128 const struct pci_quirkdata *qd; 129 int bus, device, maxndevs, function, nfunctions; 130 131 iot = sc->sc_iot; 132 memt = sc->sc_memt; 133 pc = sc->sc_pc; 134 bus = sc->sc_bus; 135 maxndevs = sc->sc_maxndevs; 136 137 for (device = 0; device < maxndevs; device++) { 138 pcitag_t tag; 139 pcireg_t id, class, intr, bhlcr, csr; 140 struct pci_attach_args pa; 141 int pin; 142 143 tag = pci_make_tag(pc, bus, device, 0); 144 id = pci_conf_read(pc, tag, PCI_ID_REG); 145 146 /* Invalid vendor ID value? */ 147 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 148 continue; 149 /* XXX Not invalid, but we've done this ~forever. */ 150 if (PCI_VENDOR(id) == 0) 151 continue; 152 153 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 154 155 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 156 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 157 (qd != NULL && 158 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 159 nfunctions = 8; 160 else 161 nfunctions = 1; 162 163 for (function = 0; function < nfunctions; function++) { 164 tag = pci_make_tag(pc, bus, device, function); 165 id = pci_conf_read(pc, tag, PCI_ID_REG); 166 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 167 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 168 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 169 170 /* Invalid vendor ID value? */ 171 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 172 continue; 173 /* XXX Not invalid, but we've done this ~forever. */ 174 if (PCI_VENDOR(id) == 0) 175 continue; 176 177 pa.pa_iot = iot; 178 pa.pa_memt = memt; 179 pa.pa_dmat = sc->sc_dmat; 180 pa.pa_pc = pc; 181 pa.pa_device = device; 182 pa.pa_function = function; 183 pa.pa_tag = tag; 184 pa.pa_id = id; 185 pa.pa_class = class; 186 187 /* 188 * Set up memory, I/O enable, and PCI command flags 189 * as appropriate. 190 */ 191 pa.pa_flags = sc->sc_flags; 192 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 193 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 194 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 195 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 196 197 if (bus == 0) { 198 pa.pa_intrswiz = 0; 199 pa.pa_intrtag = tag; 200 } else { 201 pa.pa_intrswiz = sc->sc_intrswiz + device; 202 pa.pa_intrtag = sc->sc_intrtag; 203 } 204 pin = PCI_INTERRUPT_PIN(intr); 205 if (pin == PCI_INTERRUPT_PIN_NONE) { 206 /* no interrupt */ 207 pa.pa_intrpin = 0; 208 } else { 209 /* 210 * swizzle it based on the number of 211 * busses we're behind and our device 212 * number. 213 */ 214 pa.pa_intrpin = /* XXX */ 215 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 216 } 217 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 218 219 config_found_sm(self, &pa, pciprint, pcisubmatch); 220 } 221 } 222 } 223 224 void 225 pciattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct pcibus_attach_args *pba = aux; 230 struct pci_softc *sc = (struct pci_softc *)self; 231 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 232 const char *sep = ""; 233 234 pci_attach_hook(parent, self, pba); 235 printf("\n"); 236 237 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 238 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 239 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 240 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 241 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 242 243 if (io_enabled == 0 && mem_enabled == 0) { 244 printf("%s: no spaces enabled!\n", self->dv_xname); 245 return; 246 } 247 248 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 249 250 printf("%s: ", self->dv_xname); 251 252 if (io_enabled) 253 PRINT("i/o space"); 254 if (mem_enabled) 255 PRINT("memory space"); 256 printf(" enabled"); 257 258 if (mrl_enabled || mrm_enabled || mwi_enabled) { 259 if (mrl_enabled) 260 PRINT("rd/line"); 261 if (mrm_enabled) 262 PRINT("rd/mult"); 263 if (mwi_enabled) 264 PRINT("wr/inv"); 265 printf(" ok"); 266 } 267 268 printf("\n"); 269 270 #undef PRINT 271 272 sc->sc_iot = pba->pba_iot; 273 sc->sc_memt = pba->pba_memt; 274 sc->sc_dmat = pba->pba_dmat; 275 sc->sc_pc = pba->pba_pc; 276 sc->sc_bus = pba->pba_bus; 277 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 278 sc->sc_intrswiz = pba->pba_intrswiz; 279 sc->sc_intrtag = pba->pba_intrtag; 280 sc->sc_flags = pba->pba_flags; 281 282 pci_probe_bus(self); 283 } 284 285 int 286 pciprint(aux, pnp) 287 void *aux; 288 const char *pnp; 289 { 290 register struct pci_attach_args *pa = aux; 291 char devinfo[256]; 292 #if 0 293 const struct pci_quirkdata *qd; 294 #endif 295 296 if (pnp) { 297 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 298 printf("%s at %s", devinfo, pnp); 299 } 300 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 301 #if 0 302 printf(": "); 303 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 304 if (!pnp) 305 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 306 printf("%s at %s", devinfo, pnp ? pnp : "?"); 307 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 308 #ifdef __i386__ 309 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 310 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 311 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 312 #else 313 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 314 (long)pa->pa_tag, (long)pa->pa_intrtag, (long)pa->pa_intrswiz, 315 (long)pa->pa_intrpin); 316 #endif 317 printf(", i/o %s, mem %s,", 318 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 319 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 320 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 321 PCI_PRODUCT(pa->pa_id)); 322 if (qd == NULL) { 323 printf(" no quirks"); 324 } else { 325 bitmask_snprintf(qd->quirks, 326 "\20\1multifn", devinfo, sizeof (devinfo)); 327 printf(" quirks %s", devinfo); 328 } 329 printf(")"); 330 #endif 331 return (UNCONF); 332 } 333 334 int 335 pcisubmatch(parent, cf, aux) 336 struct device *parent; 337 struct cfdata *cf; 338 void *aux; 339 { 340 struct pci_attach_args *pa = aux; 341 342 if (cf->pcicf_dev != PCI_UNK_DEV && 343 cf->pcicf_dev != pa->pa_device) 344 return 0; 345 if (cf->pcicf_function != PCI_UNK_FUNCTION && 346 cf->pcicf_function != pa->pa_function) 347 return 0; 348 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 349 } 350 351 int 352 pci_get_capability(pc, tag, capid, offset, value) 353 pci_chipset_tag_t pc; 354 pcitag_t tag; 355 int capid; 356 int *offset; 357 pcireg_t *value; 358 { 359 pcireg_t reg; 360 unsigned int ofs; 361 362 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 363 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 364 return (0); 365 366 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, PCI_CAPLISTPTR_REG)); 367 while (ofs != 0) { 368 #ifdef DIAGNOSTIC 369 if ((ofs & 3) || (ofs < 0x40)) 370 panic("pci_get_capability"); 371 #endif 372 reg = pci_conf_read(pc, tag, ofs); 373 if (PCI_CAPLIST_CAP(reg) == capid) { 374 if (offset) 375 *offset = ofs; 376 if (value) 377 *value = reg; 378 return (1); 379 } 380 ofs = PCI_CAPLIST_NEXT(reg); 381 } 382 383 return (0); 384 } 385
Indexes created Tue Sep 30 20:09:53 GMT 2025