pci.c revision 1.45
1 /* $NetBSD: pci.c,v 1.45 2000/03/22 00:47:26 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #ifdef PCI_CONFIG_DUMP 49 int pci_config_dump = 1; 50 #else 51 int pci_config_dump = 0; 52 #endif 53 54 int pcimatch __P((struct device *, struct cfdata *, void *)); 55 void pciattach __P((struct device *, struct device *, void *)); 56 57 struct pci_softc { 58 struct device sc_dev; 59 bus_space_tag_t sc_iot, sc_memt; 60 bus_dma_tag_t sc_dmat; 61 pci_chipset_tag_t sc_pc; 62 int sc_bus, sc_maxndevs; 63 u_int sc_intrswiz; 64 pcitag_t sc_intrtag; 65 int sc_flags; 66 }; 67 68 struct cfattach pci_ca = { 69 sizeof(struct pci_softc), pcimatch, pciattach 70 }; 71 72 void pci_probe_bus __P((struct device *)); 73 int pciprint __P((void *, const char *)); 74 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 75 76 /* 77 * Important note about PCI-ISA bridges: 78 * 79 * Callbacks are used to configure these devices so that ISA/EISA bridges 80 * can attach their child busses after PCI configuration is done. 81 * 82 * This works because: 83 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 84 * (2) any ISA/EISA bridges must be attached to primary PCI 85 * busses (i.e. bus zero). 86 * 87 * That boils down to: there can only be one of these outstanding 88 * at a time, it is cleared when configuring PCI bus 0 before any 89 * subdevices have been found, and it is run after all subdevices 90 * of PCI bus 0 have been found. 91 * 92 * This is needed because there are some (legacy) PCI devices which 93 * can show up as ISA/EISA devices as well (the prime example of which 94 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 95 * and the bridge is seen before the video board is, the board can show 96 * up as an ISA device, and that can (bogusly) complicate the PCI device's 97 * attach code, or make the PCI device not be properly attached at all. 98 * 99 * We use the generic config_defer() facility to achieve this. 100 */ 101 102 int 103 pcimatch(parent, cf, aux) 104 struct device *parent; 105 struct cfdata *cf; 106 void *aux; 107 { 108 struct pcibus_attach_args *pba = aux; 109 110 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 111 return (0); 112 113 /* Check the locators */ 114 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 115 cf->pcibuscf_bus != pba->pba_bus) 116 return (0); 117 118 /* sanity */ 119 if (pba->pba_bus < 0 || pba->pba_bus > 255) 120 return (0); 121 122 /* 123 * XXX check other (hardware?) indicators 124 */ 125 126 return 1; 127 } 128 129 void 130 pci_probe_bus(self) 131 struct device *self; 132 { 133 struct pci_softc *sc = (struct pci_softc *)self; 134 bus_space_tag_t iot, memt; 135 pci_chipset_tag_t pc; 136 const struct pci_quirkdata *qd; 137 int bus, device, maxndevs, function, nfunctions; 138 139 iot = sc->sc_iot; 140 memt = sc->sc_memt; 141 pc = sc->sc_pc; 142 bus = sc->sc_bus; 143 maxndevs = sc->sc_maxndevs; 144 145 for (device = 0; device < maxndevs; device++) { 146 pcitag_t tag; 147 pcireg_t id, class, intr, bhlcr, csr; 148 struct pci_attach_args pa; 149 int pin; 150 151 tag = pci_make_tag(pc, bus, device, 0); 152 id = pci_conf_read(pc, tag, PCI_ID_REG); 153 154 /* Invalid vendor ID value? */ 155 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 156 continue; 157 /* XXX Not invalid, but we've done this ~forever. */ 158 if (PCI_VENDOR(id) == 0) 159 continue; 160 161 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 162 163 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 164 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 165 (qd != NULL && 166 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 167 nfunctions = 8; 168 else 169 nfunctions = 1; 170 171 for (function = 0; function < nfunctions; function++) { 172 tag = pci_make_tag(pc, bus, device, function); 173 id = pci_conf_read(pc, tag, PCI_ID_REG); 174 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 175 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 176 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 177 178 /* Invalid vendor ID value? */ 179 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 180 continue; 181 /* XXX Not invalid, but we've done this ~forever. */ 182 if (PCI_VENDOR(id) == 0) 183 continue; 184 185 pa.pa_iot = iot; 186 pa.pa_memt = memt; 187 pa.pa_dmat = sc->sc_dmat; 188 pa.pa_pc = pc; 189 pa.pa_device = device; 190 pa.pa_function = function; 191 pa.pa_tag = tag; 192 pa.pa_id = id; 193 pa.pa_class = class; 194 195 /* 196 * Set up memory, I/O enable, and PCI command flags 197 * as appropriate. 198 */ 199 pa.pa_flags = sc->sc_flags; 200 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 201 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 202 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 203 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 204 205 if (bus == 0) { 206 pa.pa_intrswiz = 0; 207 pa.pa_intrtag = tag; 208 } else { 209 pa.pa_intrswiz = sc->sc_intrswiz + device; 210 pa.pa_intrtag = sc->sc_intrtag; 211 } 212 pin = PCI_INTERRUPT_PIN(intr); 213 if (pin == PCI_INTERRUPT_PIN_NONE) { 214 /* no interrupt */ 215 pa.pa_intrpin = 0; 216 } else { 217 /* 218 * swizzle it based on the number of 219 * busses we're behind and our device 220 * number. 221 */ 222 pa.pa_intrpin = /* XXX */ 223 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 224 } 225 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 226 227 config_found_sm(self, &pa, pciprint, pcisubmatch); 228 } 229 } 230 } 231 232 void 233 pciattach(parent, self, aux) 234 struct device *parent, *self; 235 void *aux; 236 { 237 struct pcibus_attach_args *pba = aux; 238 struct pci_softc *sc = (struct pci_softc *)self; 239 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 240 const char *sep = ""; 241 242 pci_attach_hook(parent, self, pba); 243 printf("\n"); 244 245 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 246 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 247 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 248 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 249 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 250 251 if (io_enabled == 0 && mem_enabled == 0) { 252 printf("%s: no spaces enabled!\n", self->dv_xname); 253 return; 254 } 255 256 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 257 258 printf("%s: ", self->dv_xname); 259 260 if (io_enabled) 261 PRINT("i/o space"); 262 if (mem_enabled) 263 PRINT("memory space"); 264 printf(" enabled"); 265 266 if (mrl_enabled || mrm_enabled || mwi_enabled) { 267 if (mrl_enabled) 268 PRINT("rd/line"); 269 if (mrm_enabled) 270 PRINT("rd/mult"); 271 if (mwi_enabled) 272 PRINT("wr/inv"); 273 printf(" ok"); 274 } 275 276 printf("\n"); 277 278 #undef PRINT 279 280 sc->sc_iot = pba->pba_iot; 281 sc->sc_memt = pba->pba_memt; 282 sc->sc_dmat = pba->pba_dmat; 283 sc->sc_pc = pba->pba_pc; 284 sc->sc_bus = pba->pba_bus; 285 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 286 sc->sc_intrswiz = pba->pba_intrswiz; 287 sc->sc_intrtag = pba->pba_intrtag; 288 sc->sc_flags = pba->pba_flags; 289 290 pci_probe_bus(self); 291 } 292 293 int 294 pciprint(aux, pnp) 295 void *aux; 296 const char *pnp; 297 { 298 register struct pci_attach_args *pa = aux; 299 char devinfo[256]; 300 const struct pci_quirkdata *qd; 301 302 if (pnp) { 303 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 304 printf("%s at %s", devinfo, pnp); 305 } 306 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 307 if (pci_config_dump) { 308 printf(": "); 309 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 310 if (!pnp) 311 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 312 printf("%s at %s", devinfo, pnp ? pnp : "?"); 313 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 314 #ifdef __i386__ 315 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 316 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 317 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 318 #else 319 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 320 (long)pa->pa_tag, (long)pa->pa_intrtag, (long)pa->pa_intrswiz, 321 (long)pa->pa_intrpin); 322 #endif 323 printf(", i/o %s, mem %s,", 324 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 325 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 326 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 327 PCI_PRODUCT(pa->pa_id)); 328 if (qd == NULL) { 329 printf(" no quirks"); 330 } else { 331 bitmask_snprintf(qd->quirks, 332 "\20\1multifn", devinfo, sizeof (devinfo)); 333 printf(" quirks %s", devinfo); 334 } 335 printf(")"); 336 } 337 return (UNCONF); 338 } 339 340 int 341 pcisubmatch(parent, cf, aux) 342 struct device *parent; 343 struct cfdata *cf; 344 void *aux; 345 { 346 struct pci_attach_args *pa = aux; 347 348 if (cf->pcicf_dev != PCI_UNK_DEV && 349 cf->pcicf_dev != pa->pa_device) 350 return 0; 351 if (cf->pcicf_function != PCI_UNK_FUNCTION && 352 cf->pcicf_function != pa->pa_function) 353 return 0; 354 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 355 } 356 357 int 358 pci_get_capability(pc, tag, capid, offset, value) 359 pci_chipset_tag_t pc; 360 pcitag_t tag; 361 int capid; 362 int *offset; 363 pcireg_t *value; 364 { 365 pcireg_t reg; 366 unsigned int ofs; 367 368 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 369 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 370 return (0); 371 372 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, PCI_CAPLISTPTR_REG)); 373 while (ofs != 0) { 374 #ifdef DIAGNOSTIC 375 if ((ofs & 3) || (ofs < 0x40)) 376 panic("pci_get_capability"); 377 #endif 378 reg = pci_conf_read(pc, tag, ofs); 379 if (PCI_CAPLIST_CAP(reg) == capid) { 380 if (offset) 381 *offset = ofs; 382 if (value) 383 *value = reg; 384 return (1); 385 } 386 ofs = PCI_CAPLIST_NEXT(reg); 387 } 388 389 return (0); 390 } 391
Indexes created Sun Sep 21 20:09:37 GMT 2025