pci.c revision 1.53
1 /* $NetBSD: pci.c,v 1.53 2001/05/22 16:10:44 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #ifdef PCI_CONFIG_DUMP 49 int pci_config_dump = 1; 50 #else 51 int pci_config_dump = 0; 52 #endif 53 54 int pcimatch __P((struct device *, struct cfdata *, void *)); 55 void pciattach __P((struct device *, struct device *, void *)); 56 57 struct pci_softc { 58 struct device sc_dev; 59 bus_space_tag_t sc_iot, sc_memt; 60 bus_dma_tag_t sc_dmat; 61 pci_chipset_tag_t sc_pc; 62 int sc_bus, sc_maxndevs; 63 u_int sc_intrswiz; 64 pcitag_t sc_intrtag; 65 int sc_flags; 66 }; 67 68 struct cfattach pci_ca = { 69 sizeof(struct pci_softc), pcimatch, pciattach 70 }; 71 72 void pci_probe_bus __P((struct device *)); 73 int pciprint __P((void *, const char *)); 74 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 75 76 /* 77 * Important note about PCI-ISA bridges: 78 * 79 * Callbacks are used to configure these devices so that ISA/EISA bridges 80 * can attach their child busses after PCI configuration is done. 81 * 82 * This works because: 83 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 84 * (2) any ISA/EISA bridges must be attached to primary PCI 85 * busses (i.e. bus zero). 86 * 87 * That boils down to: there can only be one of these outstanding 88 * at a time, it is cleared when configuring PCI bus 0 before any 89 * subdevices have been found, and it is run after all subdevices 90 * of PCI bus 0 have been found. 91 * 92 * This is needed because there are some (legacy) PCI devices which 93 * can show up as ISA/EISA devices as well (the prime example of which 94 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 95 * and the bridge is seen before the video board is, the board can show 96 * up as an ISA device, and that can (bogusly) complicate the PCI device's 97 * attach code, or make the PCI device not be properly attached at all. 98 * 99 * We use the generic config_defer() facility to achieve this. 100 */ 101 102 int 103 pcimatch(parent, cf, aux) 104 struct device *parent; 105 struct cfdata *cf; 106 void *aux; 107 { 108 struct pcibus_attach_args *pba = aux; 109 110 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 111 return (0); 112 113 /* Check the locators */ 114 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 115 cf->pcibuscf_bus != pba->pba_bus) 116 return (0); 117 118 /* sanity */ 119 if (pba->pba_bus < 0 || pba->pba_bus > 255) 120 return (0); 121 122 /* 123 * XXX check other (hardware?) indicators 124 */ 125 126 return 1; 127 } 128 129 /* XXX 130 * The __PCI_BUS_DEVORDER/__PCI_DEV_FUNCORDER macros should go away 131 * and be implemented with device properties when they arrive. 132 */ 133 void 134 pci_probe_bus(self) 135 struct device *self; 136 { 137 struct pci_softc *sc = (struct pci_softc *)self; 138 bus_space_tag_t iot, memt; 139 pci_chipset_tag_t pc; 140 const struct pci_quirkdata *qd; 141 int bus, device, function, nfunctions; 142 #ifdef __PCI_BUS_DEVORDER 143 char devs[32]; 144 int i; 145 #endif 146 #ifdef __PCI_DEV_FUNCORDER 147 char funcs[8]; 148 int j; 149 #endif 150 151 iot = sc->sc_iot; 152 memt = sc->sc_memt; 153 pc = sc->sc_pc; 154 bus = sc->sc_bus; 155 #ifdef __PCI_BUS_DEVORDER 156 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 157 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 158 #else 159 for (device = 0; device < sc->sc_maxndevs; device++) 160 #endif 161 { 162 pcitag_t tag; 163 pcireg_t id, class, intr, bhlcr, csr; 164 struct pci_attach_args pa; 165 int pin; 166 167 tag = pci_make_tag(pc, bus, device, 0); 168 id = pci_conf_read(pc, tag, PCI_ID_REG); 169 170 /* Invalid vendor ID value? */ 171 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 172 continue; 173 /* XXX Not invalid, but we've done this ~forever. */ 174 if (PCI_VENDOR(id) == 0) 175 continue; 176 177 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 178 179 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 180 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 181 (qd != NULL && 182 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 183 nfunctions = 8; 184 else 185 nfunctions = 1; 186 187 #ifdef __PCI_DEV_FUNCORDER 188 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, funcs); 189 for (j = 0; (function = funcs[j]) < nfunctions && 190 function >= 0; j++) 191 #else 192 for (function = 0; function < nfunctions; function++) 193 #endif 194 { 195 tag = pci_make_tag(pc, bus, device, function); 196 id = pci_conf_read(pc, tag, PCI_ID_REG); 197 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 198 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 199 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 200 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 201 202 /* Invalid vendor ID value? */ 203 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 204 continue; 205 /* XXX Not invalid, but we've done this ~forever. */ 206 if (PCI_VENDOR(id) == 0) 207 continue; 208 209 pa.pa_iot = iot; 210 pa.pa_memt = memt; 211 pa.pa_dmat = sc->sc_dmat; 212 pa.pa_pc = pc; 213 pa.pa_bus = bus; 214 pa.pa_device = device; 215 pa.pa_function = function; 216 pa.pa_tag = tag; 217 pa.pa_id = id; 218 pa.pa_class = class; 219 220 /* 221 * Set up memory, I/O enable, and PCI command flags 222 * as appropriate. 223 */ 224 pa.pa_flags = sc->sc_flags; 225 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 226 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 227 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 228 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 229 230 /* 231 * If the cache line size is not configured, then 232 * clear the MRL/MRM/MWI command-ok flags. 233 */ 234 if (PCI_CACHELINE(bhlcr) == 0) 235 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 236 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 237 238 if (bus == 0) { 239 pa.pa_intrswiz = 0; 240 pa.pa_intrtag = tag; 241 } else { 242 pa.pa_intrswiz = sc->sc_intrswiz + device; 243 pa.pa_intrtag = sc->sc_intrtag; 244 } 245 pin = PCI_INTERRUPT_PIN(intr); 246 if (pin == PCI_INTERRUPT_PIN_NONE) { 247 /* no interrupt */ 248 pa.pa_intrpin = 0; 249 } else { 250 /* 251 * swizzle it based on the number of 252 * busses we're behind and our device 253 * number. 254 */ 255 pa.pa_intrpin = /* XXX */ 256 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 257 } 258 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 259 260 config_found_sm(self, &pa, pciprint, pcisubmatch); 261 } 262 } 263 } 264 265 void 266 pciattach(parent, self, aux) 267 struct device *parent, *self; 268 void *aux; 269 { 270 struct pcibus_attach_args *pba = aux; 271 struct pci_softc *sc = (struct pci_softc *)self; 272 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 273 const char *sep = ""; 274 275 pci_attach_hook(parent, self, pba); 276 printf("\n"); 277 278 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 279 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 280 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 281 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 282 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 283 284 if (io_enabled == 0 && mem_enabled == 0) { 285 printf("%s: no spaces enabled!\n", self->dv_xname); 286 return; 287 } 288 289 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 290 291 printf("%s: ", self->dv_xname); 292 293 if (io_enabled) 294 PRINT("i/o space"); 295 if (mem_enabled) 296 PRINT("memory space"); 297 printf(" enabled"); 298 299 if (mrl_enabled || mrm_enabled || mwi_enabled) { 300 if (mrl_enabled) 301 PRINT("rd/line"); 302 if (mrm_enabled) 303 PRINT("rd/mult"); 304 if (mwi_enabled) 305 PRINT("wr/inv"); 306 printf(" ok"); 307 } 308 309 printf("\n"); 310 311 #undef PRINT 312 313 sc->sc_iot = pba->pba_iot; 314 sc->sc_memt = pba->pba_memt; 315 sc->sc_dmat = pba->pba_dmat; 316 sc->sc_pc = pba->pba_pc; 317 sc->sc_bus = pba->pba_bus; 318 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 319 sc->sc_intrswiz = pba->pba_intrswiz; 320 sc->sc_intrtag = pba->pba_intrtag; 321 sc->sc_flags = pba->pba_flags; 322 pci_probe_bus(self); 323 } 324 325 int 326 pciprint(aux, pnp) 327 void *aux; 328 const char *pnp; 329 { 330 struct pci_attach_args *pa = aux; 331 char devinfo[256]; 332 const struct pci_quirkdata *qd; 333 334 if (pnp) { 335 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 336 printf("%s at %s", devinfo, pnp); 337 } 338 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 339 if (pci_config_dump) { 340 printf(": "); 341 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 342 if (!pnp) 343 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 344 printf("%s at %s", devinfo, pnp ? pnp : "?"); 345 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 346 #ifdef __i386__ 347 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 348 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 349 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 350 #else 351 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 352 (long)pa->pa_tag, (long)pa->pa_intrtag, (long)pa->pa_intrswiz, 353 (long)pa->pa_intrpin); 354 #endif 355 printf(", i/o %s, mem %s,", 356 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 357 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 358 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 359 PCI_PRODUCT(pa->pa_id)); 360 if (qd == NULL) { 361 printf(" no quirks"); 362 } else { 363 bitmask_snprintf(qd->quirks, 364 "\20\1multifn", devinfo, sizeof (devinfo)); 365 printf(" quirks %s", devinfo); 366 } 367 printf(")"); 368 } 369 return (UNCONF); 370 } 371 372 int 373 pcisubmatch(parent, cf, aux) 374 struct device *parent; 375 struct cfdata *cf; 376 void *aux; 377 { 378 struct pci_attach_args *pa = aux; 379 380 if (cf->pcicf_dev != PCI_UNK_DEV && 381 cf->pcicf_dev != pa->pa_device) 382 return 0; 383 if (cf->pcicf_function != PCI_UNK_FUNCTION && 384 cf->pcicf_function != pa->pa_function) 385 return 0; 386 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 387 } 388 389 int 390 pci_get_capability(pc, tag, capid, offset, value) 391 pci_chipset_tag_t pc; 392 pcitag_t tag; 393 int capid; 394 int *offset; 395 pcireg_t *value; 396 { 397 pcireg_t reg; 398 unsigned int ofs; 399 400 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 401 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 402 return (0); 403 404 /* Determine the Capability List Pointer register to start with. */ 405 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 406 switch (PCI_HDRTYPE_TYPE(reg)) { 407 case 0: /* standard device header */ 408 ofs = PCI_CAPLISTPTR_REG; 409 break; 410 case 2: /* PCI-CardBus Bridge header */ 411 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 412 break; 413 default: 414 return (0); 415 } 416 417 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 418 while (ofs != 0) { 419 #ifdef DIAGNOSTIC 420 if ((ofs & 3) || (ofs < 0x40)) 421 panic("pci_get_capability"); 422 #endif 423 reg = pci_conf_read(pc, tag, ofs); 424 if (PCI_CAPLIST_CAP(reg) == capid) { 425 if (offset) 426 *offset = ofs; 427 if (value) 428 *value = reg; 429 return (1); 430 } 431 ofs = PCI_CAPLIST_NEXT(reg); 432 } 433 434 return (0); 435 } 436
Indexes created Mon Sep 22 21:09:42 GMT 2025