pci.c revision 1.54.2.1
1 /* $NetBSD: pci.c,v 1.54.2.1 2001/10/01 12:45:57 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #ifdef PCI_CONFIG_DUMP 49 int pci_config_dump = 1; 50 #else 51 int pci_config_dump = 0; 52 #endif 53 54 int pcimatch __P((struct device *, struct cfdata *, void *)); 55 void pciattach __P((struct device *, struct device *, void *)); 56 57 struct cfattach pci_ca = { 58 sizeof(struct pci_softc), pcimatch, pciattach 59 }; 60 61 int pci_probe_bus(struct device *, int (*match)(struct pci_attach_args *), 62 struct pci_attach_args *); 63 int pciprint __P((void *, const char *)); 64 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 65 66 /* 67 * Important note about PCI-ISA bridges: 68 * 69 * Callbacks are used to configure these devices so that ISA/EISA bridges 70 * can attach their child busses after PCI configuration is done. 71 * 72 * This works because: 73 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 74 * (2) any ISA/EISA bridges must be attached to primary PCI 75 * busses (i.e. bus zero). 76 * 77 * That boils down to: there can only be one of these outstanding 78 * at a time, it is cleared when configuring PCI bus 0 before any 79 * subdevices have been found, and it is run after all subdevices 80 * of PCI bus 0 have been found. 81 * 82 * This is needed because there are some (legacy) PCI devices which 83 * can show up as ISA/EISA devices as well (the prime example of which 84 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 85 * and the bridge is seen before the video board is, the board can show 86 * up as an ISA device, and that can (bogusly) complicate the PCI device's 87 * attach code, or make the PCI device not be properly attached at all. 88 * 89 * We use the generic config_defer() facility to achieve this. 90 */ 91 92 int 93 pcimatch(parent, cf, aux) 94 struct device *parent; 95 struct cfdata *cf; 96 void *aux; 97 { 98 struct pcibus_attach_args *pba = aux; 99 100 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 101 return (0); 102 103 /* Check the locators */ 104 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 105 cf->pcibuscf_bus != pba->pba_bus) 106 return (0); 107 108 /* sanity */ 109 if (pba->pba_bus < 0 || pba->pba_bus > 255) 110 return (0); 111 112 /* 113 * XXX check other (hardware?) indicators 114 */ 115 116 return 1; 117 } 118 119 /* XXX 120 * The __PCI_BUS_DEVORDER/__PCI_DEV_FUNCORDER macros should go away 121 * and be implemented with device properties when they arrive. 122 */ 123 int 124 pci_probe_bus(struct device *self, int (*match)(struct pci_attach_args *), 125 struct pci_attach_args *pap) 126 { 127 struct pci_softc *sc = (struct pci_softc *)self; 128 bus_space_tag_t iot, memt; 129 pci_chipset_tag_t pc; 130 const struct pci_quirkdata *qd; 131 int bus, device, function, nfunctions, ret; 132 #ifdef __PCI_BUS_DEVORDER 133 char devs[32]; 134 int i; 135 #endif 136 #ifdef __PCI_DEV_FUNCORDER 137 char funcs[8]; 138 int j; 139 #endif 140 141 iot = sc->sc_iot; 142 memt = sc->sc_memt; 143 pc = sc->sc_pc; 144 bus = sc->sc_bus; 145 #ifdef __PCI_BUS_DEVORDER 146 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 147 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 148 #else 149 for (device = 0; device < sc->sc_maxndevs; device++) 150 #endif 151 { 152 pcitag_t tag; 153 pcireg_t id, class, intr, bhlcr, csr; 154 struct pci_attach_args pa; 155 int pin; 156 157 tag = pci_make_tag(pc, bus, device, 0); 158 id = pci_conf_read(pc, tag, PCI_ID_REG); 159 160 /* Invalid vendor ID value? */ 161 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 162 continue; 163 /* XXX Not invalid, but we've done this ~forever. */ 164 if (PCI_VENDOR(id) == 0) 165 continue; 166 167 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 168 169 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 170 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 171 (qd != NULL && 172 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 173 nfunctions = 8; 174 else 175 nfunctions = 1; 176 177 #ifdef __PCI_DEV_FUNCORDER 178 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, funcs); 179 for (j = 0; (function = funcs[j]) < nfunctions && 180 function >= 0; j++) 181 #else 182 for (function = 0; function < nfunctions; function++) 183 #endif 184 { 185 tag = pci_make_tag(pc, bus, device, function); 186 id = pci_conf_read(pc, tag, PCI_ID_REG); 187 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 188 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 189 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 190 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 191 192 /* Invalid vendor ID value? */ 193 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 194 continue; 195 /* XXX Not invalid, but we've done this ~forever. */ 196 if (PCI_VENDOR(id) == 0) 197 continue; 198 199 pa.pa_iot = iot; 200 pa.pa_memt = memt; 201 pa.pa_dmat = sc->sc_dmat; 202 pa.pa_pc = pc; 203 pa.pa_bus = bus; 204 pa.pa_device = device; 205 pa.pa_function = function; 206 pa.pa_tag = tag; 207 pa.pa_id = id; 208 pa.pa_class = class; 209 210 /* 211 * Set up memory, I/O enable, and PCI command flags 212 * as appropriate. 213 */ 214 pa.pa_flags = sc->sc_flags; 215 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 216 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 217 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 218 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 219 220 /* 221 * If the cache line size is not configured, then 222 * clear the MRL/MRM/MWI command-ok flags. 223 */ 224 if (PCI_CACHELINE(bhlcr) == 0) 225 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 226 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 227 228 if (bus == 0) { 229 pa.pa_intrswiz = 0; 230 pa.pa_intrtag = tag; 231 } else { 232 pa.pa_intrswiz = sc->sc_intrswiz + device; 233 pa.pa_intrtag = sc->sc_intrtag; 234 } 235 pin = PCI_INTERRUPT_PIN(intr); 236 if (pin == PCI_INTERRUPT_PIN_NONE) { 237 /* no interrupt */ 238 pa.pa_intrpin = 0; 239 } else { 240 /* 241 * swizzle it based on the number of 242 * busses we're behind and our device 243 * number. 244 */ 245 pa.pa_intrpin = /* XXX */ 246 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 247 } 248 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 249 250 if (match != NULL) { 251 ret = match(&pa); 252 if (ret != 0) { 253 if (pap != NULL) 254 *pap = pa; 255 return ret; 256 } 257 } else { 258 config_found_sm(self, &pa, pciprint, 259 pcisubmatch); 260 } 261 } 262 } 263 return 0; 264 } 265 266 void 267 pciattach(parent, self, aux) 268 struct device *parent, *self; 269 void *aux; 270 { 271 struct pcibus_attach_args *pba = aux; 272 struct pci_softc *sc = (struct pci_softc *)self; 273 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 274 const char *sep = ""; 275 276 pci_attach_hook(parent, self, pba); 277 printf("\n"); 278 279 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 280 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 281 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 282 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 283 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 284 285 if (io_enabled == 0 && mem_enabled == 0) { 286 printf("%s: no spaces enabled!\n", self->dv_xname); 287 return; 288 } 289 290 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 291 292 printf("%s: ", self->dv_xname); 293 294 if (io_enabled) 295 PRINT("i/o space"); 296 if (mem_enabled) 297 PRINT("memory space"); 298 printf(" enabled"); 299 300 if (mrl_enabled || mrm_enabled || mwi_enabled) { 301 if (mrl_enabled) 302 PRINT("rd/line"); 303 if (mrm_enabled) 304 PRINT("rd/mult"); 305 if (mwi_enabled) 306 PRINT("wr/inv"); 307 printf(" ok"); 308 } 309 310 printf("\n"); 311 312 #undef PRINT 313 314 sc->sc_iot = pba->pba_iot; 315 sc->sc_memt = pba->pba_memt; 316 sc->sc_dmat = pba->pba_dmat; 317 sc->sc_pc = pba->pba_pc; 318 sc->sc_bus = pba->pba_bus; 319 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 320 sc->sc_intrswiz = pba->pba_intrswiz; 321 sc->sc_intrtag = pba->pba_intrtag; 322 sc->sc_flags = pba->pba_flags; 323 pci_probe_bus(self, NULL, NULL); 324 } 325 326 int 327 pciprint(aux, pnp) 328 void *aux; 329 const char *pnp; 330 { 331 struct pci_attach_args *pa = aux; 332 char devinfo[256]; 333 const struct pci_quirkdata *qd; 334 335 if (pnp) { 336 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 337 printf("%s at %s", devinfo, pnp); 338 } 339 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 340 if (pci_config_dump) { 341 printf(": "); 342 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 343 if (!pnp) 344 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 345 printf("%s at %s", devinfo, pnp ? pnp : "?"); 346 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 347 #ifdef __i386__ 348 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 349 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 350 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 351 #else 352 printf("intrswiz %#lx, intrpin %#lx", 353 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 354 #endif 355 printf(", i/o %s, mem %s,", 356 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 357 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 358 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 359 PCI_PRODUCT(pa->pa_id)); 360 if (qd == NULL) { 361 printf(" no quirks"); 362 } else { 363 bitmask_snprintf(qd->quirks, 364 "\20\1multifn", devinfo, sizeof (devinfo)); 365 printf(" quirks %s", devinfo); 366 } 367 printf(")"); 368 } 369 return (UNCONF); 370 } 371 372 int 373 pcisubmatch(parent, cf, aux) 374 struct device *parent; 375 struct cfdata *cf; 376 void *aux; 377 { 378 struct pci_attach_args *pa = aux; 379 380 if (cf->pcicf_dev != PCI_UNK_DEV && 381 cf->pcicf_dev != pa->pa_device) 382 return 0; 383 if (cf->pcicf_function != PCI_UNK_FUNCTION && 384 cf->pcicf_function != pa->pa_function) 385 return 0; 386 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 387 } 388 389 int 390 pci_get_capability(pc, tag, capid, offset, value) 391 pci_chipset_tag_t pc; 392 pcitag_t tag; 393 int capid; 394 int *offset; 395 pcireg_t *value; 396 { 397 pcireg_t reg; 398 unsigned int ofs; 399 400 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 401 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 402 return (0); 403 404 /* Determine the Capability List Pointer register to start with. */ 405 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 406 switch (PCI_HDRTYPE_TYPE(reg)) { 407 case 0: /* standard device header */ 408 ofs = PCI_CAPLISTPTR_REG; 409 break; 410 case 2: /* PCI-CardBus Bridge header */ 411 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 412 break; 413 default: 414 return (0); 415 } 416 417 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 418 while (ofs != 0) { 419 #ifdef DIAGNOSTIC 420 if ((ofs & 3) || (ofs < 0x40)) 421 panic("pci_get_capability"); 422 #endif 423 reg = pci_conf_read(pc, tag, ofs); 424 if (PCI_CAPLIST_CAP(reg) == capid) { 425 if (offset) 426 *offset = ofs; 427 if (value) 428 *value = reg; 429 return (1); 430 } 431 ofs = PCI_CAPLIST_NEXT(reg); 432 } 433 434 return (0); 435 } 436 437 int 438 pci_find_device(struct pci_attach_args *pa, 439 int (*match)(struct pci_attach_args *)) 440 { 441 int i; 442 struct device *pcidev; 443 extern struct cfdriver pci_cd; 444 445 for (i = 0; i < pci_cd.cd_ndevs; i++) { 446 pcidev = pci_cd.cd_devs[i]; 447 if (pcidev != NULL && pci_probe_bus(pcidev, match, pa) != 0) 448 return 1; 449 } 450 return 0; 451 } 452
Indexes created Tue Sep 30 17:09:57 GMT 2025