pci.c revision 1.55
1 /* $NetBSD: pci.c,v 1.55 2001/09/10 10:04:49 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #ifdef PCI_CONFIG_DUMP 49 int pci_config_dump = 1; 50 #else 51 int pci_config_dump = 0; 52 #endif 53 54 int pcimatch __P((struct device *, struct cfdata *, void *)); 55 void pciattach __P((struct device *, struct device *, void *)); 56 57 struct pci_softc { 58 struct device sc_dev; 59 bus_space_tag_t sc_iot, sc_memt; 60 bus_dma_tag_t sc_dmat; 61 pci_chipset_tag_t sc_pc; 62 int sc_bus, sc_maxndevs; 63 u_int sc_intrswiz; 64 pcitag_t sc_intrtag; 65 int sc_flags; 66 }; 67 68 struct cfattach pci_ca = { 69 sizeof(struct pci_softc), pcimatch, pciattach 70 }; 71 72 int pci_probe_bus(struct device *, int (*match)(struct pci_attach_args *), 73 struct pci_attach_args *); 74 int pciprint __P((void *, const char *)); 75 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 76 77 /* 78 * Important note about PCI-ISA bridges: 79 * 80 * Callbacks are used to configure these devices so that ISA/EISA bridges 81 * can attach their child busses after PCI configuration is done. 82 * 83 * This works because: 84 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 85 * (2) any ISA/EISA bridges must be attached to primary PCI 86 * busses (i.e. bus zero). 87 * 88 * That boils down to: there can only be one of these outstanding 89 * at a time, it is cleared when configuring PCI bus 0 before any 90 * subdevices have been found, and it is run after all subdevices 91 * of PCI bus 0 have been found. 92 * 93 * This is needed because there are some (legacy) PCI devices which 94 * can show up as ISA/EISA devices as well (the prime example of which 95 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 96 * and the bridge is seen before the video board is, the board can show 97 * up as an ISA device, and that can (bogusly) complicate the PCI device's 98 * attach code, or make the PCI device not be properly attached at all. 99 * 100 * We use the generic config_defer() facility to achieve this. 101 */ 102 103 int 104 pcimatch(parent, cf, aux) 105 struct device *parent; 106 struct cfdata *cf; 107 void *aux; 108 { 109 struct pcibus_attach_args *pba = aux; 110 111 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 112 return (0); 113 114 /* Check the locators */ 115 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 116 cf->pcibuscf_bus != pba->pba_bus) 117 return (0); 118 119 /* sanity */ 120 if (pba->pba_bus < 0 || pba->pba_bus > 255) 121 return (0); 122 123 /* 124 * XXX check other (hardware?) indicators 125 */ 126 127 return 1; 128 } 129 130 /* XXX 131 * The __PCI_BUS_DEVORDER/__PCI_DEV_FUNCORDER macros should go away 132 * and be implemented with device properties when they arrive. 133 */ 134 int 135 pci_probe_bus(struct device *self, int (*match)(struct pci_attach_args *), 136 struct pci_attach_args *pap) 137 { 138 struct pci_softc *sc = (struct pci_softc *)self; 139 bus_space_tag_t iot, memt; 140 pci_chipset_tag_t pc; 141 const struct pci_quirkdata *qd; 142 int bus, device, function, nfunctions, ret; 143 #ifdef __PCI_BUS_DEVORDER 144 char devs[32]; 145 int i; 146 #endif 147 #ifdef __PCI_DEV_FUNCORDER 148 char funcs[8]; 149 int j; 150 #endif 151 152 iot = sc->sc_iot; 153 memt = sc->sc_memt; 154 pc = sc->sc_pc; 155 bus = sc->sc_bus; 156 #ifdef __PCI_BUS_DEVORDER 157 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 158 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 159 #else 160 for (device = 0; device < sc->sc_maxndevs; device++) 161 #endif 162 { 163 pcitag_t tag; 164 pcireg_t id, class, intr, bhlcr, csr; 165 struct pci_attach_args pa; 166 int pin; 167 168 tag = pci_make_tag(pc, bus, device, 0); 169 id = pci_conf_read(pc, tag, PCI_ID_REG); 170 171 /* Invalid vendor ID value? */ 172 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 173 continue; 174 /* XXX Not invalid, but we've done this ~forever. */ 175 if (PCI_VENDOR(id) == 0) 176 continue; 177 178 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 179 180 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 181 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 182 (qd != NULL && 183 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 184 nfunctions = 8; 185 else 186 nfunctions = 1; 187 188 #ifdef __PCI_DEV_FUNCORDER 189 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, funcs); 190 for (j = 0; (function = funcs[j]) < nfunctions && 191 function >= 0; j++) 192 #else 193 for (function = 0; function < nfunctions; function++) 194 #endif 195 { 196 tag = pci_make_tag(pc, bus, device, function); 197 id = pci_conf_read(pc, tag, PCI_ID_REG); 198 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 199 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 200 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 201 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 202 203 /* Invalid vendor ID value? */ 204 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 205 continue; 206 /* XXX Not invalid, but we've done this ~forever. */ 207 if (PCI_VENDOR(id) == 0) 208 continue; 209 210 pa.pa_iot = iot; 211 pa.pa_memt = memt; 212 pa.pa_dmat = sc->sc_dmat; 213 pa.pa_pc = pc; 214 pa.pa_bus = bus; 215 pa.pa_device = device; 216 pa.pa_function = function; 217 pa.pa_tag = tag; 218 pa.pa_id = id; 219 pa.pa_class = class; 220 221 /* 222 * Set up memory, I/O enable, and PCI command flags 223 * as appropriate. 224 */ 225 pa.pa_flags = sc->sc_flags; 226 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 227 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 228 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 229 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 230 231 /* 232 * If the cache line size is not configured, then 233 * clear the MRL/MRM/MWI command-ok flags. 234 */ 235 if (PCI_CACHELINE(bhlcr) == 0) 236 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 237 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 238 239 if (bus == 0) { 240 pa.pa_intrswiz = 0; 241 pa.pa_intrtag = tag; 242 } else { 243 pa.pa_intrswiz = sc->sc_intrswiz + device; 244 pa.pa_intrtag = sc->sc_intrtag; 245 } 246 pin = PCI_INTERRUPT_PIN(intr); 247 if (pin == PCI_INTERRUPT_PIN_NONE) { 248 /* no interrupt */ 249 pa.pa_intrpin = 0; 250 } else { 251 /* 252 * swizzle it based on the number of 253 * busses we're behind and our device 254 * number. 255 */ 256 pa.pa_intrpin = /* XXX */ 257 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 258 } 259 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 260 261 if (match != NULL) { 262 ret = match(&pa); 263 if (ret != 0) { 264 if (pap != NULL) 265 *pap = pa; 266 return ret; 267 } 268 } else { 269 config_found_sm(self, &pa, pciprint, 270 pcisubmatch); 271 } 272 } 273 } 274 return 0; 275 } 276 277 void 278 pciattach(parent, self, aux) 279 struct device *parent, *self; 280 void *aux; 281 { 282 struct pcibus_attach_args *pba = aux; 283 struct pci_softc *sc = (struct pci_softc *)self; 284 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 285 const char *sep = ""; 286 287 pci_attach_hook(parent, self, pba); 288 printf("\n"); 289 290 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 291 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 292 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 293 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 294 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 295 296 if (io_enabled == 0 && mem_enabled == 0) { 297 printf("%s: no spaces enabled!\n", self->dv_xname); 298 return; 299 } 300 301 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 302 303 printf("%s: ", self->dv_xname); 304 305 if (io_enabled) 306 PRINT("i/o space"); 307 if (mem_enabled) 308 PRINT("memory space"); 309 printf(" enabled"); 310 311 if (mrl_enabled || mrm_enabled || mwi_enabled) { 312 if (mrl_enabled) 313 PRINT("rd/line"); 314 if (mrm_enabled) 315 PRINT("rd/mult"); 316 if (mwi_enabled) 317 PRINT("wr/inv"); 318 printf(" ok"); 319 } 320 321 printf("\n"); 322 323 #undef PRINT 324 325 sc->sc_iot = pba->pba_iot; 326 sc->sc_memt = pba->pba_memt; 327 sc->sc_dmat = pba->pba_dmat; 328 sc->sc_pc = pba->pba_pc; 329 sc->sc_bus = pba->pba_bus; 330 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 331 sc->sc_intrswiz = pba->pba_intrswiz; 332 sc->sc_intrtag = pba->pba_intrtag; 333 sc->sc_flags = pba->pba_flags; 334 pci_probe_bus(self, NULL, NULL); 335 } 336 337 int 338 pciprint(aux, pnp) 339 void *aux; 340 const char *pnp; 341 { 342 struct pci_attach_args *pa = aux; 343 char devinfo[256]; 344 const struct pci_quirkdata *qd; 345 346 if (pnp) { 347 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 348 printf("%s at %s", devinfo, pnp); 349 } 350 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 351 if (pci_config_dump) { 352 printf(": "); 353 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 354 if (!pnp) 355 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 356 printf("%s at %s", devinfo, pnp ? pnp : "?"); 357 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 358 #ifdef __i386__ 359 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 360 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 361 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 362 #else 363 printf("intrswiz %#lx, intrpin %#lx", 364 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 365 #endif 366 printf(", i/o %s, mem %s,", 367 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 368 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 369 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 370 PCI_PRODUCT(pa->pa_id)); 371 if (qd == NULL) { 372 printf(" no quirks"); 373 } else { 374 bitmask_snprintf(qd->quirks, 375 "\20\1multifn", devinfo, sizeof (devinfo)); 376 printf(" quirks %s", devinfo); 377 } 378 printf(")"); 379 } 380 return (UNCONF); 381 } 382 383 int 384 pcisubmatch(parent, cf, aux) 385 struct device *parent; 386 struct cfdata *cf; 387 void *aux; 388 { 389 struct pci_attach_args *pa = aux; 390 391 if (cf->pcicf_dev != PCI_UNK_DEV && 392 cf->pcicf_dev != pa->pa_device) 393 return 0; 394 if (cf->pcicf_function != PCI_UNK_FUNCTION && 395 cf->pcicf_function != pa->pa_function) 396 return 0; 397 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 398 } 399 400 int 401 pci_get_capability(pc, tag, capid, offset, value) 402 pci_chipset_tag_t pc; 403 pcitag_t tag; 404 int capid; 405 int *offset; 406 pcireg_t *value; 407 { 408 pcireg_t reg; 409 unsigned int ofs; 410 411 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 412 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 413 return (0); 414 415 /* Determine the Capability List Pointer register to start with. */ 416 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 417 switch (PCI_HDRTYPE_TYPE(reg)) { 418 case 0: /* standard device header */ 419 ofs = PCI_CAPLISTPTR_REG; 420 break; 421 case 2: /* PCI-CardBus Bridge header */ 422 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 423 break; 424 default: 425 return (0); 426 } 427 428 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 429 while (ofs != 0) { 430 #ifdef DIAGNOSTIC 431 if ((ofs & 3) || (ofs < 0x40)) 432 panic("pci_get_capability"); 433 #endif 434 reg = pci_conf_read(pc, tag, ofs); 435 if (PCI_CAPLIST_CAP(reg) == capid) { 436 if (offset) 437 *offset = ofs; 438 if (value) 439 *value = reg; 440 return (1); 441 } 442 ofs = PCI_CAPLIST_NEXT(reg); 443 } 444 445 return (0); 446 } 447 448 int 449 pci_find_device(struct pci_attach_args *pa, 450 int (*match)(struct pci_attach_args *)) 451 { 452 int i; 453 struct device *pcidev; 454 extern struct cfdriver pci_cd; 455 456 for (i = 0; i < pci_cd.cd_ndevs; i++) { 457 pcidev = pci_cd.cd_devs[i]; 458 if (pcidev != NULL && pci_probe_bus(pcidev, match, pa) != 0) 459 return 1; 460 } 461 return 0; 462 } 463
Indexes created Sun Sep 21 20:09:37 GMT 2025