pci.c revision 1.58
1 /* $NetBSD: pci.c,v 1.58 2001/11/13 07:48:47 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.58 2001/11/13 07:48:47 lukem Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #ifdef PCI_CONFIG_DUMP 52 int pci_config_dump = 1; 53 #else 54 int pci_config_dump = 0; 55 #endif 56 57 int pcimatch __P((struct device *, struct cfdata *, void *)); 58 void pciattach __P((struct device *, struct device *, void *)); 59 60 struct cfattach pci_ca = { 61 sizeof(struct pci_softc), pcimatch, pciattach 62 }; 63 64 int pci_probe_bus(struct device *, int (*match)(struct pci_attach_args *), 65 struct pci_attach_args *); 66 int pciprint __P((void *, const char *)); 67 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 68 69 /* 70 * Important note about PCI-ISA bridges: 71 * 72 * Callbacks are used to configure these devices so that ISA/EISA bridges 73 * can attach their child busses after PCI configuration is done. 74 * 75 * This works because: 76 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 77 * (2) any ISA/EISA bridges must be attached to primary PCI 78 * busses (i.e. bus zero). 79 * 80 * That boils down to: there can only be one of these outstanding 81 * at a time, it is cleared when configuring PCI bus 0 before any 82 * subdevices have been found, and it is run after all subdevices 83 * of PCI bus 0 have been found. 84 * 85 * This is needed because there are some (legacy) PCI devices which 86 * can show up as ISA/EISA devices as well (the prime example of which 87 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 88 * and the bridge is seen before the video board is, the board can show 89 * up as an ISA device, and that can (bogusly) complicate the PCI device's 90 * attach code, or make the PCI device not be properly attached at all. 91 * 92 * We use the generic config_defer() facility to achieve this. 93 */ 94 95 int 96 pcimatch(parent, cf, aux) 97 struct device *parent; 98 struct cfdata *cf; 99 void *aux; 100 { 101 struct pcibus_attach_args *pba = aux; 102 103 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 104 return (0); 105 106 /* Check the locators */ 107 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 108 cf->pcibuscf_bus != pba->pba_bus) 109 return (0); 110 111 /* sanity */ 112 if (pba->pba_bus < 0 || pba->pba_bus > 255) 113 return (0); 114 115 /* 116 * XXX check other (hardware?) indicators 117 */ 118 119 return 1; 120 } 121 122 /* XXX 123 * The __PCI_BUS_DEVORDER/__PCI_DEV_FUNCORDER macros should go away 124 * and be implemented with device properties when they arrive. 125 */ 126 int 127 pci_probe_bus(struct device *self, int (*match)(struct pci_attach_args *), 128 struct pci_attach_args *pap) 129 { 130 struct pci_softc *sc = (struct pci_softc *)self; 131 bus_space_tag_t iot, memt; 132 pci_chipset_tag_t pc; 133 int bus, device, function, nfunctions, ret; 134 #ifdef __PCI_BUS_DEVORDER 135 char devs[32]; 136 int i; 137 #endif 138 #ifdef __PCI_DEV_FUNCORDER 139 char funcs[8]; 140 int j; 141 #else 142 const struct pci_quirkdata *qd; 143 #endif 144 145 iot = sc->sc_iot; 146 memt = sc->sc_memt; 147 pc = sc->sc_pc; 148 bus = sc->sc_bus; 149 #ifdef __PCI_BUS_DEVORDER 150 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 151 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 152 #else 153 for (device = 0; device < sc->sc_maxndevs; device++) 154 #endif 155 { 156 pcitag_t tag; 157 pcireg_t id, class, intr, bhlcr, csr; 158 struct pci_attach_args pa; 159 int pin; 160 161 #ifdef __PCI_DEV_FUNCORDER 162 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, funcs); 163 nfunctions = 8; 164 #else 165 tag = pci_make_tag(pc, bus, device, 0); 166 id = pci_conf_read(pc, tag, PCI_ID_REG); 167 168 /* Invalid vendor ID value? */ 169 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 170 continue; 171 /* XXX Not invalid, but we've done this ~forever. */ 172 if (PCI_VENDOR(id) == 0) 173 continue; 174 175 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 176 177 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 178 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 179 (qd != NULL && 180 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 181 nfunctions = 8; 182 else 183 nfunctions = 1; 184 #endif /* __PCI_DEV_FUNCORDER */ 185 186 #ifdef __PCI_DEV_FUNCORDER 187 for (j = 0; (function = funcs[j]) < nfunctions && 188 function >= 0; j++) 189 #else 190 for (function = 0; function < nfunctions; function++) 191 #endif 192 { 193 tag = pci_make_tag(pc, bus, device, function); 194 id = pci_conf_read(pc, tag, PCI_ID_REG); 195 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 196 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 197 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 198 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 199 200 /* Invalid vendor ID value? */ 201 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 202 continue; 203 /* XXX Not invalid, but we've done this ~forever. */ 204 if (PCI_VENDOR(id) == 0) 205 continue; 206 207 pa.pa_iot = iot; 208 pa.pa_memt = memt; 209 pa.pa_dmat = sc->sc_dmat; 210 pa.pa_pc = pc; 211 pa.pa_bus = bus; 212 pa.pa_device = device; 213 pa.pa_function = function; 214 pa.pa_tag = tag; 215 pa.pa_id = id; 216 pa.pa_class = class; 217 218 /* 219 * Set up memory, I/O enable, and PCI command flags 220 * as appropriate. 221 */ 222 pa.pa_flags = sc->sc_flags; 223 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 224 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 225 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 226 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 227 228 /* 229 * If the cache line size is not configured, then 230 * clear the MRL/MRM/MWI command-ok flags. 231 */ 232 if (PCI_CACHELINE(bhlcr) == 0) 233 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 234 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 235 236 if (bus == 0) { 237 pa.pa_intrswiz = 0; 238 pa.pa_intrtag = tag; 239 } else { 240 pa.pa_intrswiz = sc->sc_intrswiz + device; 241 pa.pa_intrtag = sc->sc_intrtag; 242 } 243 pin = PCI_INTERRUPT_PIN(intr); 244 if (pin == PCI_INTERRUPT_PIN_NONE) { 245 /* no interrupt */ 246 pa.pa_intrpin = 0; 247 } else { 248 /* 249 * swizzle it based on the number of 250 * busses we're behind and our device 251 * number. 252 */ 253 pa.pa_intrpin = /* XXX */ 254 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 255 } 256 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 257 258 if (match != NULL) { 259 ret = match(&pa); 260 if (ret != 0) { 261 if (pap != NULL) 262 *pap = pa; 263 return ret; 264 } 265 } else { 266 config_found_sm(self, &pa, pciprint, 267 pcisubmatch); 268 } 269 } 270 } 271 return 0; 272 } 273 274 void 275 pciattach(parent, self, aux) 276 struct device *parent, *self; 277 void *aux; 278 { 279 struct pcibus_attach_args *pba = aux; 280 struct pci_softc *sc = (struct pci_softc *)self; 281 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 282 const char *sep = ""; 283 284 pci_attach_hook(parent, self, pba); 285 printf("\n"); 286 287 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 288 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 289 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 290 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 291 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 292 293 if (io_enabled == 0 && mem_enabled == 0) { 294 printf("%s: no spaces enabled!\n", self->dv_xname); 295 return; 296 } 297 298 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 299 300 printf("%s: ", self->dv_xname); 301 302 if (io_enabled) 303 PRINT("i/o space"); 304 if (mem_enabled) 305 PRINT("memory space"); 306 printf(" enabled"); 307 308 if (mrl_enabled || mrm_enabled || mwi_enabled) { 309 if (mrl_enabled) 310 PRINT("rd/line"); 311 if (mrm_enabled) 312 PRINT("rd/mult"); 313 if (mwi_enabled) 314 PRINT("wr/inv"); 315 printf(" ok"); 316 } 317 318 printf("\n"); 319 320 #undef PRINT 321 322 sc->sc_iot = pba->pba_iot; 323 sc->sc_memt = pba->pba_memt; 324 sc->sc_dmat = pba->pba_dmat; 325 sc->sc_pc = pba->pba_pc; 326 sc->sc_bus = pba->pba_bus; 327 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 328 sc->sc_intrswiz = pba->pba_intrswiz; 329 sc->sc_intrtag = pba->pba_intrtag; 330 sc->sc_flags = pba->pba_flags; 331 pci_probe_bus(self, NULL, NULL); 332 } 333 334 int 335 pciprint(aux, pnp) 336 void *aux; 337 const char *pnp; 338 { 339 struct pci_attach_args *pa = aux; 340 char devinfo[256]; 341 const struct pci_quirkdata *qd; 342 343 if (pnp) { 344 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 345 printf("%s at %s", devinfo, pnp); 346 } 347 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 348 if (pci_config_dump) { 349 printf(": "); 350 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 351 if (!pnp) 352 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 353 printf("%s at %s", devinfo, pnp ? pnp : "?"); 354 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 355 #ifdef __i386__ 356 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 357 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 358 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 359 #else 360 printf("intrswiz %#lx, intrpin %#lx", 361 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 362 #endif 363 printf(", i/o %s, mem %s,", 364 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 365 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 366 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 367 PCI_PRODUCT(pa->pa_id)); 368 if (qd == NULL) { 369 printf(" no quirks"); 370 } else { 371 bitmask_snprintf(qd->quirks, 372 "\20\1multifn", devinfo, sizeof (devinfo)); 373 printf(" quirks %s", devinfo); 374 } 375 printf(")"); 376 } 377 return (UNCONF); 378 } 379 380 int 381 pcisubmatch(parent, cf, aux) 382 struct device *parent; 383 struct cfdata *cf; 384 void *aux; 385 { 386 struct pci_attach_args *pa = aux; 387 388 if (cf->pcicf_dev != PCI_UNK_DEV && 389 cf->pcicf_dev != pa->pa_device) 390 return 0; 391 if (cf->pcicf_function != PCI_UNK_FUNCTION && 392 cf->pcicf_function != pa->pa_function) 393 return 0; 394 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 395 } 396 397 int 398 pci_get_capability(pc, tag, capid, offset, value) 399 pci_chipset_tag_t pc; 400 pcitag_t tag; 401 int capid; 402 int *offset; 403 pcireg_t *value; 404 { 405 pcireg_t reg; 406 unsigned int ofs; 407 408 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 409 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 410 return (0); 411 412 /* Determine the Capability List Pointer register to start with. */ 413 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 414 switch (PCI_HDRTYPE_TYPE(reg)) { 415 case 0: /* standard device header */ 416 ofs = PCI_CAPLISTPTR_REG; 417 break; 418 case 2: /* PCI-CardBus Bridge header */ 419 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 420 break; 421 default: 422 return (0); 423 } 424 425 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 426 while (ofs != 0) { 427 #ifdef DIAGNOSTIC 428 if ((ofs & 3) || (ofs < 0x40)) 429 panic("pci_get_capability"); 430 #endif 431 reg = pci_conf_read(pc, tag, ofs); 432 if (PCI_CAPLIST_CAP(reg) == capid) { 433 if (offset) 434 *offset = ofs; 435 if (value) 436 *value = reg; 437 return (1); 438 } 439 ofs = PCI_CAPLIST_NEXT(reg); 440 } 441 442 return (0); 443 } 444 445 int 446 pci_find_device(struct pci_attach_args *pa, 447 int (*match)(struct pci_attach_args *)) 448 { 449 int i; 450 struct device *pcidev; 451 extern struct cfdriver pci_cd; 452 453 for (i = 0; i < pci_cd.cd_ndevs; i++) { 454 pcidev = pci_cd.cd_devs[i]; 455 if (pcidev != NULL && pci_probe_bus(pcidev, match, pa) != 0) 456 return 1; 457 } 458 return 0; 459 } 460
Indexes created Tue Sep 30 17:09:57 GMT 2025