pci.c revision 1.77
1 /* $NetBSD: pci.c,v 1.77 2003/03/25 21:56:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.77 2003/03/25 21:56:20 thorpej Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include "locators.h" 52 53 #ifdef PCI_CONFIG_DUMP 54 int pci_config_dump = 1; 55 #else 56 int pci_config_dump = 0; 57 #endif 58 59 int pcimatch __P((struct device *, struct cfdata *, void *)); 60 void pciattach __P((struct device *, struct device *, void *)); 61 62 CFATTACH_DECL(pci, sizeof(struct pci_softc), 63 pcimatch, pciattach, NULL, NULL); 64 65 int pciprint __P((void *, const char *)); 66 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 67 68 /* 69 * Important note about PCI-ISA bridges: 70 * 71 * Callbacks are used to configure these devices so that ISA/EISA bridges 72 * can attach their child busses after PCI configuration is done. 73 * 74 * This works because: 75 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 76 * (2) any ISA/EISA bridges must be attached to primary PCI 77 * busses (i.e. bus zero). 78 * 79 * That boils down to: there can only be one of these outstanding 80 * at a time, it is cleared when configuring PCI bus 0 before any 81 * subdevices have been found, and it is run after all subdevices 82 * of PCI bus 0 have been found. 83 * 84 * This is needed because there are some (legacy) PCI devices which 85 * can show up as ISA/EISA devices as well (the prime example of which 86 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 87 * and the bridge is seen before the video board is, the board can show 88 * up as an ISA device, and that can (bogusly) complicate the PCI device's 89 * attach code, or make the PCI device not be properly attached at all. 90 * 91 * We use the generic config_defer() facility to achieve this. 92 */ 93 94 int 95 pcimatch(parent, cf, aux) 96 struct device *parent; 97 struct cfdata *cf; 98 void *aux; 99 { 100 struct pcibus_attach_args *pba = aux; 101 102 if (strcmp(pba->pba_busname, cf->cf_name)) 103 return (0); 104 105 /* Check the locators */ 106 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 107 cf->pcibuscf_bus != pba->pba_bus) 108 return (0); 109 110 /* sanity */ 111 if (pba->pba_bus < 0 || pba->pba_bus > 255) 112 return (0); 113 114 /* 115 * XXX check other (hardware?) indicators 116 */ 117 118 return (1); 119 } 120 121 void 122 pciattach(parent, self, aux) 123 struct device *parent, *self; 124 void *aux; 125 { 126 struct pcibus_attach_args *pba = aux; 127 struct pci_softc *sc = (struct pci_softc *)self; 128 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 129 const char *sep = ""; 130 131 pci_attach_hook(parent, self, pba); 132 printf("\n"); 133 134 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 135 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 136 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 137 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 138 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 139 140 if (io_enabled == 0 && mem_enabled == 0) { 141 printf("%s: no spaces enabled!\n", self->dv_xname); 142 return; 143 } 144 145 #define PRINT(str) do { printf("%s%s", sep, str); sep = ", "; } while (0) 146 147 printf("%s: ", self->dv_xname); 148 149 if (io_enabled) 150 PRINT("i/o space"); 151 if (mem_enabled) 152 PRINT("memory space"); 153 printf(" enabled"); 154 155 if (mrl_enabled || mrm_enabled || mwi_enabled) { 156 if (mrl_enabled) 157 PRINT("rd/line"); 158 if (mrm_enabled) 159 PRINT("rd/mult"); 160 if (mwi_enabled) 161 PRINT("wr/inv"); 162 printf(" ok"); 163 } 164 165 printf("\n"); 166 167 #undef PRINT 168 169 sc->sc_iot = pba->pba_iot; 170 sc->sc_memt = pba->pba_memt; 171 sc->sc_dmat = pba->pba_dmat; 172 sc->sc_pc = pba->pba_pc; 173 sc->sc_bus = pba->pba_bus; 174 sc->sc_bridgetag = pba->pba_bridgetag; 175 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 176 sc->sc_intrswiz = pba->pba_intrswiz; 177 sc->sc_intrtag = pba->pba_intrtag; 178 sc->sc_flags = pba->pba_flags; 179 pci_enumerate_bus(sc, NULL, NULL); 180 } 181 182 int 183 pciprint(aux, pnp) 184 void *aux; 185 const char *pnp; 186 { 187 struct pci_attach_args *pa = aux; 188 char devinfo[256]; 189 const struct pci_quirkdata *qd; 190 191 if (pnp) { 192 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 193 aprint_normal("%s at %s", devinfo, pnp); 194 } 195 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 196 if (pci_config_dump) { 197 printf(": "); 198 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 199 if (!pnp) 200 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 201 printf("%s at %s", devinfo, pnp ? pnp : "?"); 202 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 203 #ifdef __i386__ 204 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 205 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 206 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 207 #else 208 printf("intrswiz %#lx, intrpin %#lx", 209 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 210 #endif 211 printf(", i/o %s, mem %s,", 212 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 213 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 214 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 215 PCI_PRODUCT(pa->pa_id)); 216 if (qd == NULL) { 217 printf(" no quirks"); 218 } else { 219 bitmask_snprintf(qd->quirks, 220 "\20\1multifn", devinfo, sizeof (devinfo)); 221 printf(" quirks %s", devinfo); 222 } 223 printf(")"); 224 } 225 return (UNCONF); 226 } 227 228 int 229 pcisubmatch(parent, cf, aux) 230 struct device *parent; 231 struct cfdata *cf; 232 void *aux; 233 { 234 struct pci_attach_args *pa = aux; 235 236 if (cf->pcicf_dev != PCI_UNK_DEV && 237 cf->pcicf_dev != pa->pa_device) 238 return (0); 239 if (cf->pcicf_function != PCI_UNK_FUNCTION && 240 cf->pcicf_function != pa->pa_function) 241 return (0); 242 return (config_match(parent, cf, aux)); 243 } 244 245 int 246 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 247 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 248 { 249 pci_chipset_tag_t pc = sc->sc_pc; 250 struct pci_attach_args pa; 251 pcireg_t id, csr, class, intr, bhlcr; 252 int ret, pin, bus, device, function; 253 254 pci_decompose_tag(pc, tag, &bus, &device, &function); 255 256 id = pci_conf_read(pc, tag, PCI_ID_REG); 257 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 258 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 259 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 260 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 261 262 /* Invalid vendor ID value? */ 263 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 264 return (0); 265 /* XXX Not invalid, but we've done this ~forever. */ 266 if (PCI_VENDOR(id) == 0) 267 return (0); 268 269 pa.pa_iot = sc->sc_iot; 270 pa.pa_memt = sc->sc_memt; 271 pa.pa_dmat = sc->sc_dmat; 272 pa.pa_pc = pc; 273 pa.pa_bus = bus; 274 pa.pa_device = device; 275 pa.pa_function = function; 276 pa.pa_tag = tag; 277 pa.pa_id = id; 278 pa.pa_class = class; 279 280 /* 281 * Set up memory, I/O enable, and PCI command flags 282 * as appropriate. 283 */ 284 pa.pa_flags = sc->sc_flags; 285 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 286 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 287 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 288 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 289 290 /* 291 * If the cache line size is not configured, then 292 * clear the MRL/MRM/MWI command-ok flags. 293 */ 294 if (PCI_CACHELINE(bhlcr) == 0) 295 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 296 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 297 298 if (sc->sc_bridgetag == NULL) { 299 pa.pa_intrswiz = 0; 300 pa.pa_intrtag = tag; 301 } else { 302 pa.pa_intrswiz = sc->sc_intrswiz + device; 303 pa.pa_intrtag = sc->sc_intrtag; 304 } 305 pin = PCI_INTERRUPT_PIN(intr); 306 pa.pa_rawintrpin = pin; 307 if (pin == PCI_INTERRUPT_PIN_NONE) { 308 /* no interrupt */ 309 pa.pa_intrpin = 0; 310 } else { 311 /* 312 * swizzle it based on the number of busses we're 313 * behind and our device number. 314 */ 315 pa.pa_intrpin = /* XXX */ 316 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 317 } 318 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 319 320 if (match != NULL) { 321 ret = (*match)(&pa); 322 if (ret != 0 && pap != NULL) 323 *pap = pa; 324 } else { 325 ret = config_found_sm(&sc->sc_dev, &pa, pciprint, 326 pcisubmatch) != NULL; 327 } 328 329 return (ret); 330 } 331 332 int 333 pci_get_capability(pc, tag, capid, offset, value) 334 pci_chipset_tag_t pc; 335 pcitag_t tag; 336 int capid; 337 int *offset; 338 pcireg_t *value; 339 { 340 pcireg_t reg; 341 unsigned int ofs; 342 343 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 344 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 345 return (0); 346 347 /* Determine the Capability List Pointer register to start with. */ 348 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 349 switch (PCI_HDRTYPE_TYPE(reg)) { 350 case 0: /* standard device header */ 351 ofs = PCI_CAPLISTPTR_REG; 352 break; 353 case 2: /* PCI-CardBus Bridge header */ 354 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 355 break; 356 default: 357 return (0); 358 } 359 360 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 361 while (ofs != 0) { 362 #ifdef DIAGNOSTIC 363 if ((ofs & 3) || (ofs < 0x40)) 364 panic("pci_get_capability"); 365 #endif 366 reg = pci_conf_read(pc, tag, ofs); 367 if (PCI_CAPLIST_CAP(reg) == capid) { 368 if (offset) 369 *offset = ofs; 370 if (value) 371 *value = reg; 372 return (1); 373 } 374 ofs = PCI_CAPLIST_NEXT(reg); 375 } 376 377 return (0); 378 } 379 380 int 381 pci_find_device(struct pci_attach_args *pa, 382 int (*match)(struct pci_attach_args *)) 383 { 384 extern struct cfdriver pci_cd; 385 struct device *pcidev; 386 int i; 387 388 for (i = 0; i < pci_cd.cd_ndevs; i++) { 389 pcidev = pci_cd.cd_devs[i]; 390 if (pcidev != NULL && 391 pci_enumerate_bus((struct pci_softc *) pcidev, 392 match, pa) != 0) 393 return (1); 394 } 395 return (0); 396 } 397 398 /* 399 * Generic PCI bus enumeration routine. Used unless machine-dependent 400 * code needs to provide something else. 401 */ 402 int 403 pci_enumerate_bus_generic(struct pci_softc *sc, 404 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 405 { 406 pci_chipset_tag_t pc = sc->sc_pc; 407 int device, function, nfunctions, ret; 408 const struct pci_quirkdata *qd; 409 pcireg_t id, bhlcr; 410 pcitag_t tag; 411 #ifdef __PCI_BUS_DEVORDER 412 char devs[32]; 413 int i; 414 #endif 415 416 #ifdef __PCI_BUS_DEVORDER 417 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 418 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 419 #else 420 for (device = 0; device < sc->sc_maxndevs; device++) 421 #endif 422 { 423 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 424 id = pci_conf_read(pc, tag, PCI_ID_REG); 425 426 /* Invalid vendor ID value? */ 427 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 428 continue; 429 /* XXX Not invalid, but we've done this ~forever. */ 430 if (PCI_VENDOR(id) == 0) 431 continue; 432 433 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 434 435 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 436 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 437 (qd != NULL && 438 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 439 nfunctions = 8; 440 else 441 nfunctions = 1; 442 443 for (function = 0; function < nfunctions; function++) { 444 tag = pci_make_tag(pc, sc->sc_bus, device, function); 445 ret = pci_probe_device(sc, tag, match, pap); 446 if (match != NULL && ret != 0) 447 return (ret); 448 } 449 } 450 return (0); 451 } 452 453 /* 454 * Power Management Capability (Rev 2.2) 455 */ 456 457 int 458 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, int newstate) 459 { 460 int offset; 461 pcireg_t value, cap, now; 462 463 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 464 return (EOPNOTSUPP); 465 466 cap = value >> 16; 467 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 468 now = value & PCI_PMCSR_STATE_MASK; 469 value &= ~PCI_PMCSR_STATE_MASK; 470 switch (newstate) { 471 case PCI_PWR_D0: 472 if (now == PCI_PMCSR_STATE_D0) 473 return (0); 474 value |= PCI_PMCSR_STATE_D0; 475 break; 476 case PCI_PWR_D1: 477 if (now == PCI_PMCSR_STATE_D1) 478 return (0); 479 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 480 return (EINVAL); 481 if (!(cap & PCI_PMCR_D1SUPP)) 482 return (EOPNOTSUPP); 483 value |= PCI_PMCSR_STATE_D1; 484 break; 485 case PCI_PWR_D2: 486 if (now == PCI_PMCSR_STATE_D2) 487 return (0); 488 if (now == PCI_PMCSR_STATE_D3) 489 return (EINVAL); 490 if (!(cap & PCI_PMCR_D2SUPP)) 491 return (EOPNOTSUPP); 492 value |= PCI_PMCSR_STATE_D2; 493 break; 494 case PCI_PWR_D3: 495 if (now == PCI_PMCSR_STATE_D3) 496 return (0); 497 value |= PCI_PMCSR_STATE_D3; 498 break; 499 default: 500 return (EINVAL); 501 } 502 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 503 DELAY(1000); 504 505 return (0); 506 } 507 508 int 509 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 510 { 511 int offset; 512 pcireg_t value; 513 514 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 515 return (PCI_PWR_D0); 516 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 517 value &= PCI_PMCSR_STATE_MASK; 518 switch (value) { 519 case PCI_PMCSR_STATE_D0: 520 return (PCI_PWR_D0); 521 case PCI_PMCSR_STATE_D1: 522 return (PCI_PWR_D1); 523 case PCI_PMCSR_STATE_D2: 524 return (PCI_PWR_D2); 525 case PCI_PMCSR_STATE_D3: 526 return (PCI_PWR_D3); 527 } 528 529 return (PCI_PWR_D0); 530 } 531 532 /* 533 * Vital Product Data (PCI 2.2) 534 */ 535 536 int 537 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 538 pcireg_t *data) 539 { 540 uint32_t reg; 541 int ofs, i, j; 542 543 KASSERT(data != NULL); 544 KASSERT((offset + count) < 0x7fff); 545 546 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 547 return (1); 548 549 for (i = 0; i < count; offset += sizeof(*data), i++) { 550 reg &= 0x0000ffff; 551 reg &= ~PCI_VPD_OPFLAG; 552 reg |= PCI_VPD_ADDRESS(offset); 553 pci_conf_write(pc, tag, ofs, reg); 554 555 /* 556 * PCI 2.2 does not specify how long we should poll 557 * for completion nor whether the operation can fail. 558 */ 559 j = 0; 560 do { 561 if (j++ == 20) 562 return (1); 563 delay(4); 564 reg = pci_conf_read(pc, tag, ofs); 565 } while ((reg & PCI_VPD_OPFLAG) == 0); 566 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 567 } 568 569 return (0); 570 } 571 572 int 573 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 574 pcireg_t *data) 575 { 576 pcireg_t reg; 577 int ofs, i, j; 578 579 KASSERT(data != NULL); 580 KASSERT((offset + count) < 0x7fff); 581 582 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 583 return (1); 584 585 for (i = 0; i < count; offset += sizeof(*data), i++) { 586 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 587 588 reg &= 0x0000ffff; 589 reg &= ~PCI_VPD_OPFLAG; 590 reg |= PCI_VPD_ADDRESS(offset); 591 pci_conf_write(pc, tag, ofs, reg); 592 593 /* 594 * PCI 2.2 does not specify how long we should poll 595 * for completion nor whether the operation can fail. 596 */ 597 j = 0; 598 do { 599 if (j++ == 20) 600 return (1); 601 delay(1); 602 reg = pci_conf_read(pc, tag, ofs); 603 } while ((reg & PCI_VPD_OPFLAG) == 0); 604 } 605 606 return (0); 607 } 608
Indexes created Tue Sep 30 20:09:53 GMT 2025