pci.c revision 1.80.2.8
1 /* $NetBSD: pci.c,v 1.80.2.8 2005/11/10 14:06:02 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.80.2.8 2005/11/10 14:06:02 skrll Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include "locators.h" 54 55 #ifdef PCI_CONFIG_DUMP 56 int pci_config_dump = 1; 57 #else 58 int pci_config_dump = 0; 59 #endif 60 61 int pciprint(void *, const char *); 62 63 #ifdef PCI_MACHDEP_ENUMERATE_BUS 64 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 65 #else 66 int pci_enumerate_bus(struct pci_softc *, const int *, 67 int (*)(struct pci_attach_args *), struct pci_attach_args *); 68 #endif 69 70 /* 71 * Important note about PCI-ISA bridges: 72 * 73 * Callbacks are used to configure these devices so that ISA/EISA bridges 74 * can attach their child busses after PCI configuration is done. 75 * 76 * This works because: 77 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 78 * (2) any ISA/EISA bridges must be attached to primary PCI 79 * busses (i.e. bus zero). 80 * 81 * That boils down to: there can only be one of these outstanding 82 * at a time, it is cleared when configuring PCI bus 0 before any 83 * subdevices have been found, and it is run after all subdevices 84 * of PCI bus 0 have been found. 85 * 86 * This is needed because there are some (legacy) PCI devices which 87 * can show up as ISA/EISA devices as well (the prime example of which 88 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 89 * and the bridge is seen before the video board is, the board can show 90 * up as an ISA device, and that can (bogusly) complicate the PCI device's 91 * attach code, or make the PCI device not be properly attached at all. 92 * 93 * We use the generic config_defer() facility to achieve this. 94 */ 95 96 static int 97 pcirescan(struct device *sc, const char *ifattr, const int *locators) 98 { 99 100 KASSERT(ifattr && !strcmp(ifattr, "pci")); 101 KASSERT(locators); 102 103 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 104 return (0); 105 } 106 107 static int 108 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 109 { 110 struct pcibus_attach_args *pba = aux; 111 112 /* Check the locators */ 113 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 114 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 115 return (0); 116 117 /* sanity */ 118 if (pba->pba_bus < 0 || pba->pba_bus > 255) 119 return (0); 120 121 /* 122 * XXX check other (hardware?) indicators 123 */ 124 125 return (1); 126 } 127 128 static void 129 pciattach(struct device *parent, struct device *self, void *aux) 130 { 131 struct pcibus_attach_args *pba = aux; 132 struct pci_softc *sc = (struct pci_softc *)self; 133 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 134 const char *sep = ""; 135 static const int wildcard[PCICF_NLOCS] = { 136 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 137 }; 138 139 pci_attach_hook(parent, self, pba); 140 141 aprint_naive("\n"); 142 aprint_normal("\n"); 143 144 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 145 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 146 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 147 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 148 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 149 150 if (io_enabled == 0 && mem_enabled == 0) { 151 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 152 return; 153 } 154 155 #define PRINT(str) \ 156 do { \ 157 aprint_normal("%s%s", sep, str); \ 158 sep = ", "; \ 159 } while (/*CONSTCOND*/0) 160 161 aprint_normal("%s: ", self->dv_xname); 162 163 if (io_enabled) 164 PRINT("i/o space"); 165 if (mem_enabled) 166 PRINT("memory space"); 167 aprint_normal(" enabled"); 168 169 if (mrl_enabled || mrm_enabled || mwi_enabled) { 170 if (mrl_enabled) 171 PRINT("rd/line"); 172 if (mrm_enabled) 173 PRINT("rd/mult"); 174 if (mwi_enabled) 175 PRINT("wr/inv"); 176 aprint_normal(" ok"); 177 } 178 179 aprint_normal("\n"); 180 181 #undef PRINT 182 183 sc->sc_iot = pba->pba_iot; 184 sc->sc_memt = pba->pba_memt; 185 sc->sc_dmat = pba->pba_dmat; 186 sc->sc_dmat64 = pba->pba_dmat64; 187 sc->sc_pc = pba->pba_pc; 188 sc->sc_bus = pba->pba_bus; 189 sc->sc_bridgetag = pba->pba_bridgetag; 190 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 191 sc->sc_intrswiz = pba->pba_intrswiz; 192 sc->sc_intrtag = pba->pba_intrtag; 193 sc->sc_flags = pba->pba_flags; 194 pcirescan(&sc->sc_dev, "pci", wildcard); 195 } 196 197 int 198 pciprint(void *aux, const char *pnp) 199 { 200 struct pci_attach_args *pa = aux; 201 char devinfo[256]; 202 const struct pci_quirkdata *qd; 203 204 if (pnp) { 205 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 206 aprint_normal("%s at %s", devinfo, pnp); 207 } 208 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 209 if (pci_config_dump) { 210 printf(": "); 211 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 212 if (!pnp) 213 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 214 printf("%s at %s", devinfo, pnp ? pnp : "?"); 215 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 216 #ifdef __i386__ 217 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 218 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 219 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 220 #else 221 printf("intrswiz %#lx, intrpin %#lx", 222 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 223 #endif 224 printf(", i/o %s, mem %s,", 225 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 226 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 227 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 228 PCI_PRODUCT(pa->pa_id)); 229 if (qd == NULL) { 230 printf(" no quirks"); 231 } else { 232 bitmask_snprintf(qd->quirks, 233 "\002\001multifn\002singlefn\003skipfunc0" 234 "\004skipfunc1\005skipfunc2\006skipfunc3" 235 "\007skipfunc4\010skipfunc5\011skipfunc6" 236 "\012skipfunc7", 237 devinfo, sizeof (devinfo)); 238 printf(" quirks %s", devinfo); 239 } 240 printf(")"); 241 } 242 return (UNCONF); 243 } 244 245 int 246 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 247 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 248 { 249 pci_chipset_tag_t pc = sc->sc_pc; 250 struct pci_attach_args pa; 251 pcireg_t id, csr, class, intr, bhlcr; 252 int ret, pin, bus, device, function; 253 int locs[PCICF_NLOCS]; 254 struct device *subdev; 255 256 pci_decompose_tag(pc, tag, &bus, &device, &function); 257 258 /* a driver already attached? */ 259 if (sc->PCI_SC_DEVICESC(device, function) && !match) 260 return (0); 261 262 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 263 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 264 return (0); 265 266 id = pci_conf_read(pc, tag, PCI_ID_REG); 267 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 268 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 269 270 /* Invalid vendor ID value? */ 271 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 272 return (0); 273 /* XXX Not invalid, but we've done this ~forever. */ 274 if (PCI_VENDOR(id) == 0) 275 return (0); 276 277 pa.pa_iot = sc->sc_iot; 278 pa.pa_memt = sc->sc_memt; 279 pa.pa_dmat = sc->sc_dmat; 280 pa.pa_dmat64 = sc->sc_dmat64; 281 pa.pa_pc = pc; 282 pa.pa_bus = bus; 283 pa.pa_device = device; 284 pa.pa_function = function; 285 pa.pa_tag = tag; 286 pa.pa_id = id; 287 pa.pa_class = class; 288 289 /* 290 * Set up memory, I/O enable, and PCI command flags 291 * as appropriate. 292 */ 293 pa.pa_flags = sc->sc_flags; 294 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 295 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 296 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 297 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 298 299 /* 300 * If the cache line size is not configured, then 301 * clear the MRL/MRM/MWI command-ok flags. 302 */ 303 if (PCI_CACHELINE(bhlcr) == 0) 304 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 305 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 306 307 if (sc->sc_bridgetag == NULL) { 308 pa.pa_intrswiz = 0; 309 pa.pa_intrtag = tag; 310 } else { 311 pa.pa_intrswiz = sc->sc_intrswiz + device; 312 pa.pa_intrtag = sc->sc_intrtag; 313 } 314 315 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 316 317 pin = PCI_INTERRUPT_PIN(intr); 318 pa.pa_rawintrpin = pin; 319 if (pin == PCI_INTERRUPT_PIN_NONE) { 320 /* no interrupt */ 321 pa.pa_intrpin = 0; 322 } else { 323 /* 324 * swizzle it based on the number of busses we're 325 * behind and our device number. 326 */ 327 pa.pa_intrpin = /* XXX */ 328 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 329 } 330 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 331 332 if (match != NULL) { 333 ret = (*match)(&pa); 334 if (ret != 0 && pap != NULL) 335 *pap = pa; 336 } else { 337 locs[PCICF_DEV] = device; 338 locs[PCICF_FUNCTION] = function; 339 340 subdev = config_found_sm_loc(&sc->sc_dev, "pci", locs, &pa, 341 pciprint, config_stdsubmatch); 342 sc->PCI_SC_DEVICESC(device, function) = subdev; 343 ret = (subdev != NULL); 344 } 345 346 return (ret); 347 } 348 349 static void 350 pcidevdetached(struct device *sc, struct device *dev) 351 { 352 struct pci_softc *psc = (struct pci_softc *)sc; 353 int d, f; 354 355 KASSERT(dev->dv_locators); 356 d = dev->dv_locators[PCICF_DEV]; 357 f = dev->dv_locators[PCICF_FUNCTION]; 358 359 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 360 361 psc->PCI_SC_DEVICESC(d, f) = 0; 362 } 363 364 int 365 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 366 int *offset, pcireg_t *value) 367 { 368 pcireg_t reg; 369 unsigned int ofs; 370 371 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 372 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 373 return (0); 374 375 /* Determine the Capability List Pointer register to start with. */ 376 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 377 switch (PCI_HDRTYPE_TYPE(reg)) { 378 case 0: /* standard device header */ 379 ofs = PCI_CAPLISTPTR_REG; 380 break; 381 case 2: /* PCI-CardBus Bridge header */ 382 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 383 break; 384 default: 385 return (0); 386 } 387 388 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 389 while (ofs != 0) { 390 #ifdef DIAGNOSTIC 391 if ((ofs & 3) || (ofs < 0x40)) 392 panic("pci_get_capability"); 393 #endif 394 reg = pci_conf_read(pc, tag, ofs); 395 if (PCI_CAPLIST_CAP(reg) == capid) { 396 if (offset) 397 *offset = ofs; 398 if (value) 399 *value = reg; 400 return (1); 401 } 402 ofs = PCI_CAPLIST_NEXT(reg); 403 } 404 405 return (0); 406 } 407 408 int 409 pci_find_device(struct pci_attach_args *pa, 410 int (*match)(struct pci_attach_args *)) 411 { 412 extern struct cfdriver pci_cd; 413 struct device *pcidev; 414 int i; 415 static const int wildcard[2] = { 416 PCICF_DEV_DEFAULT, 417 PCICF_FUNCTION_DEFAULT 418 }; 419 420 for (i = 0; i < pci_cd.cd_ndevs; i++) { 421 pcidev = pci_cd.cd_devs[i]; 422 if (pcidev != NULL && 423 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 424 match, pa) != 0) 425 return (1); 426 } 427 return (0); 428 } 429 430 #ifndef PCI_MACHDEP_ENUMERATE_BUS 431 /* 432 * Generic PCI bus enumeration routine. Used unless machine-dependent 433 * code needs to provide something else. 434 */ 435 int 436 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 437 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 438 { 439 pci_chipset_tag_t pc = sc->sc_pc; 440 int device, function, nfunctions, ret; 441 const struct pci_quirkdata *qd; 442 pcireg_t id, bhlcr; 443 pcitag_t tag; 444 #ifdef __PCI_BUS_DEVORDER 445 char devs[32]; 446 int i; 447 #endif 448 449 #ifdef __PCI_BUS_DEVORDER 450 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 451 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 452 #else 453 for (device = 0; device < sc->sc_maxndevs; device++) 454 #endif 455 { 456 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 457 (locators[PCICF_DEV] != device)) 458 continue; 459 460 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 461 462 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 463 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 464 continue; 465 466 id = pci_conf_read(pc, tag, PCI_ID_REG); 467 468 /* Invalid vendor ID value? */ 469 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 470 continue; 471 /* XXX Not invalid, but we've done this ~forever. */ 472 if (PCI_VENDOR(id) == 0) 473 continue; 474 475 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 476 477 if (qd != NULL && 478 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 479 nfunctions = 8; 480 else if (qd != NULL && 481 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 482 nfunctions = 1; 483 else 484 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 485 486 for (function = 0; function < nfunctions; function++) { 487 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 488 && (locators[PCICF_FUNCTION] != function)) 489 continue; 490 491 if (qd != NULL && 492 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 493 continue; 494 tag = pci_make_tag(pc, sc->sc_bus, device, function); 495 ret = pci_probe_device(sc, tag, match, pap); 496 if (match != NULL && ret != 0) 497 return (ret); 498 } 499 } 500 return (0); 501 } 502 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 503 504 /* 505 * Power Management Capability (Rev 2.2) 506 */ 507 508 int 509 pci_powerstate(pci_chipset_tag_t pc, pcitag_t tag, const int *newstate, 510 int *oldstate) 511 { 512 int offset; 513 pcireg_t value, cap, now; 514 515 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 516 return EOPNOTSUPP; 517 518 cap = value >> 16; 519 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 520 now = value & PCI_PMCSR_STATE_MASK; 521 value &= ~PCI_PMCSR_STATE_MASK; 522 if (oldstate) { 523 switch (now) { 524 case PCI_PMCSR_STATE_D0: 525 *oldstate = PCI_PWR_D0; 526 break; 527 case PCI_PMCSR_STATE_D1: 528 *oldstate = PCI_PWR_D1; 529 break; 530 case PCI_PMCSR_STATE_D2: 531 *oldstate = PCI_PWR_D2; 532 break; 533 case PCI_PMCSR_STATE_D3: 534 *oldstate = PCI_PWR_D3; 535 break; 536 default: 537 return EINVAL; 538 } 539 } 540 if (newstate == NULL) 541 return 0; 542 switch (*newstate) { 543 case PCI_PWR_D0: 544 if (now == PCI_PMCSR_STATE_D0) 545 return 0; 546 value |= PCI_PMCSR_STATE_D0; 547 break; 548 case PCI_PWR_D1: 549 if (now == PCI_PMCSR_STATE_D1) 550 return 0; 551 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 552 return EINVAL; 553 if (!(cap & PCI_PMCR_D1SUPP)) 554 return EOPNOTSUPP; 555 value |= PCI_PMCSR_STATE_D1; 556 break; 557 case PCI_PWR_D2: 558 if (now == PCI_PMCSR_STATE_D2) 559 return 0; 560 if (now == PCI_PMCSR_STATE_D3) 561 return EINVAL; 562 if (!(cap & PCI_PMCR_D2SUPP)) 563 return EOPNOTSUPP; 564 value |= PCI_PMCSR_STATE_D2; 565 break; 566 case PCI_PWR_D3: 567 if (now == PCI_PMCSR_STATE_D3) 568 return 0; 569 value |= PCI_PMCSR_STATE_D3; 570 break; 571 default: 572 return EINVAL; 573 } 574 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 575 DELAY(1000); 576 577 return 0; 578 } 579 580 /* 581 * Vital Product Data (PCI 2.2) 582 */ 583 584 int 585 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 586 pcireg_t *data) 587 { 588 uint32_t reg; 589 int ofs, i, j; 590 591 KASSERT(data != NULL); 592 KASSERT((offset + count) < 0x7fff); 593 594 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 595 return (1); 596 597 for (i = 0; i < count; offset += sizeof(*data), i++) { 598 reg &= 0x0000ffff; 599 reg &= ~PCI_VPD_OPFLAG; 600 reg |= PCI_VPD_ADDRESS(offset); 601 pci_conf_write(pc, tag, ofs, reg); 602 603 /* 604 * PCI 2.2 does not specify how long we should poll 605 * for completion nor whether the operation can fail. 606 */ 607 j = 0; 608 do { 609 if (j++ == 20) 610 return (1); 611 delay(4); 612 reg = pci_conf_read(pc, tag, ofs); 613 } while ((reg & PCI_VPD_OPFLAG) == 0); 614 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 615 } 616 617 return (0); 618 } 619 620 int 621 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 622 pcireg_t *data) 623 { 624 pcireg_t reg; 625 int ofs, i, j; 626 627 KASSERT(data != NULL); 628 KASSERT((offset + count) < 0x7fff); 629 630 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 631 return (1); 632 633 for (i = 0; i < count; offset += sizeof(*data), i++) { 634 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 635 636 reg &= 0x0000ffff; 637 reg |= PCI_VPD_OPFLAG; 638 reg |= PCI_VPD_ADDRESS(offset); 639 pci_conf_write(pc, tag, ofs, reg); 640 641 /* 642 * PCI 2.2 does not specify how long we should poll 643 * for completion nor whether the operation can fail. 644 */ 645 j = 0; 646 do { 647 if (j++ == 20) 648 return (1); 649 delay(1); 650 reg = pci_conf_read(pc, tag, ofs); 651 } while (reg & PCI_VPD_OPFLAG); 652 } 653 654 return (0); 655 } 656 657 int 658 pci_dma64_available(struct pci_attach_args *pa) 659 { 660 #ifdef _PCI_HAVE_DMA64 661 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 662 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 663 return 1; 664 #endif 665 return 0; 666 } 667 668 void 669 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 670 struct pci_conf_state *pcs) 671 { 672 int off; 673 674 for (off = 0; off < 16; off++) 675 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 676 677 return; 678 } 679 680 void 681 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 682 struct pci_conf_state *pcs) 683 { 684 int off; 685 686 for (off = 0; off < 16; off++) 687 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 688 689 return; 690 } 691 692 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 693 pcimatch, pciattach, NULL, NULL, pcirescan, pcidevdetached); 694
Indexes created Tue Sep 30 20:09:53 GMT 2025