pci.c revision 1.87
1 /* $NetBSD: pci.c,v 1.87 2004/08/17 23:20:10 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.87 2004/08/17 23:20:10 drochner Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include "locators.h" 54 55 #ifdef PCI_CONFIG_DUMP 56 int pci_config_dump = 1; 57 #else 58 int pci_config_dump = 0; 59 #endif 60 61 int pcimatch __P((struct device *, struct cfdata *, void *)); 62 void pciattach __P((struct device *, struct device *, void *)); 63 int pcirescan(struct device *, const char *, const int *); 64 void pcidevdetached(struct device *, struct device *); 65 66 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 67 pcimatch, pciattach, NULL, NULL, pcirescan, pcidevdetached); 68 69 int pciprint __P((void *, const char *)); 70 int pcisubmatch __P((struct device *, struct cfdata *, 71 const locdesc_t *, void *)); 72 73 #ifdef PCI_MACHDEP_ENUMERATE_BUS 74 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 75 #else 76 int pci_enumerate_bus(struct pci_softc *, const int *, 77 int (*)(struct pci_attach_args *), struct pci_attach_args *); 78 #endif 79 80 /* 81 * Important note about PCI-ISA bridges: 82 * 83 * Callbacks are used to configure these devices so that ISA/EISA bridges 84 * can attach their child busses after PCI configuration is done. 85 * 86 * This works because: 87 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 88 * (2) any ISA/EISA bridges must be attached to primary PCI 89 * busses (i.e. bus zero). 90 * 91 * That boils down to: there can only be one of these outstanding 92 * at a time, it is cleared when configuring PCI bus 0 before any 93 * subdevices have been found, and it is run after all subdevices 94 * of PCI bus 0 have been found. 95 * 96 * This is needed because there are some (legacy) PCI devices which 97 * can show up as ISA/EISA devices as well (the prime example of which 98 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 99 * and the bridge is seen before the video board is, the board can show 100 * up as an ISA device, and that can (bogusly) complicate the PCI device's 101 * attach code, or make the PCI device not be properly attached at all. 102 * 103 * We use the generic config_defer() facility to achieve this. 104 */ 105 106 int 107 pcimatch(parent, cf, aux) 108 struct device *parent; 109 struct cfdata *cf; 110 void *aux; 111 { 112 struct pcibus_attach_args *pba = aux; 113 114 if (strcmp(pba->pba_busname, cf->cf_name)) 115 return (0); 116 117 /* Check the locators */ 118 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 119 cf->pcibuscf_bus != pba->pba_bus) 120 return (0); 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return (0); 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return (1); 131 } 132 133 void 134 pciattach(parent, self, aux) 135 struct device *parent, *self; 136 void *aux; 137 { 138 struct pcibus_attach_args *pba = aux; 139 struct pci_softc *sc = (struct pci_softc *)self; 140 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 141 const char *sep = ""; 142 static const int wildcard[2] = { PCICF_DEV_DEFAULT, 143 PCICF_FUNCTION_DEFAULT }; 144 145 pci_attach_hook(parent, self, pba); 146 147 aprint_naive("\n"); 148 aprint_normal("\n"); 149 150 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 151 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 152 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 153 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 154 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 155 156 if (io_enabled == 0 && mem_enabled == 0) { 157 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 158 return; 159 } 160 161 #define PRINT(str) \ 162 do { \ 163 aprint_normal("%s%s", sep, str); \ 164 sep = ", "; \ 165 } while (/*CONSTCOND*/0) 166 167 aprint_normal("%s: ", self->dv_xname); 168 169 if (io_enabled) 170 PRINT("i/o space"); 171 if (mem_enabled) 172 PRINT("memory space"); 173 aprint_normal(" enabled"); 174 175 if (mrl_enabled || mrm_enabled || mwi_enabled) { 176 if (mrl_enabled) 177 PRINT("rd/line"); 178 if (mrm_enabled) 179 PRINT("rd/mult"); 180 if (mwi_enabled) 181 PRINT("wr/inv"); 182 aprint_normal(" ok"); 183 } 184 185 aprint_normal("\n"); 186 187 #undef PRINT 188 189 sc->sc_iot = pba->pba_iot; 190 sc->sc_memt = pba->pba_memt; 191 sc->sc_dmat = pba->pba_dmat; 192 sc->sc_dmat64 = pba->pba_dmat64; 193 sc->sc_pc = pba->pba_pc; 194 sc->sc_bus = pba->pba_bus; 195 sc->sc_bridgetag = pba->pba_bridgetag; 196 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 197 sc->sc_intrswiz = pba->pba_intrswiz; 198 sc->sc_intrtag = pba->pba_intrtag; 199 sc->sc_flags = pba->pba_flags; 200 pcirescan(&sc->sc_dev, "pci", wildcard); 201 } 202 203 int 204 pcirescan(struct device *sc, const char *ifattr, const int *locators) 205 { 206 207 KASSERT(ifattr && !strcmp(ifattr, "pci")); 208 KASSERT(locators); 209 210 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 211 return (0); 212 } 213 214 int 215 pciprint(aux, pnp) 216 void *aux; 217 const char *pnp; 218 { 219 struct pci_attach_args *pa = aux; 220 char devinfo[256]; 221 const struct pci_quirkdata *qd; 222 223 if (pnp) { 224 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 225 aprint_normal("%s at %s", devinfo, pnp); 226 } 227 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 228 if (pci_config_dump) { 229 printf(": "); 230 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 231 if (!pnp) 232 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 233 printf("%s at %s", devinfo, pnp ? pnp : "?"); 234 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 235 #ifdef __i386__ 236 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 237 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 238 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 239 #else 240 printf("intrswiz %#lx, intrpin %#lx", 241 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 242 #endif 243 printf(", i/o %s, mem %s,", 244 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 245 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 246 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 247 PCI_PRODUCT(pa->pa_id)); 248 if (qd == NULL) { 249 printf(" no quirks"); 250 } else { 251 bitmask_snprintf(qd->quirks, 252 "\002\001multifn\002singlefn\003skipfunc0" 253 "\004skipfunc1\005skipfunc2\006skipfunc3" 254 "\007skipfunc4\010skipfunc5\011skipfunc6" 255 "\012skipfunc7", 256 devinfo, sizeof (devinfo)); 257 printf(" quirks %s", devinfo); 258 } 259 printf(")"); 260 } 261 return (UNCONF); 262 } 263 264 int 265 pcisubmatch(struct device *parent, struct cfdata *cf, 266 const locdesc_t *ldesc, void *aux) 267 { 268 269 if (cf->pcicf_dev != PCI_UNK_DEV && 270 cf->pcicf_dev != ldesc->locs[PCICF_DEV]) 271 return (0); 272 if (cf->pcicf_function != PCI_UNK_FUNCTION && 273 cf->pcicf_function != ldesc->locs[PCICF_FUNCTION]) 274 return (0); 275 return (config_match(parent, cf, aux)); 276 } 277 278 int 279 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 280 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 281 { 282 pci_chipset_tag_t pc = sc->sc_pc; 283 struct pci_attach_args pa; 284 pcireg_t id, csr, class, intr, bhlcr; 285 int ret, pin, bus, device, function; 286 int help[3]; 287 locdesc_t *ldp = (void *)&help; /* XXX XXX */ 288 struct device *subdev; 289 290 pci_decompose_tag(pc, tag, &bus, &device, &function); 291 292 /* a driver already attached? */ 293 if (sc->PCI_SC_DEVICESC(device, function) && !match) 294 return (0); 295 296 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 297 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 298 return (0); 299 300 id = pci_conf_read(pc, tag, PCI_ID_REG); 301 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 302 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 303 304 /* Invalid vendor ID value? */ 305 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 306 return (0); 307 /* XXX Not invalid, but we've done this ~forever. */ 308 if (PCI_VENDOR(id) == 0) 309 return (0); 310 311 pa.pa_iot = sc->sc_iot; 312 pa.pa_memt = sc->sc_memt; 313 pa.pa_dmat = sc->sc_dmat; 314 pa.pa_dmat64 = sc->sc_dmat64; 315 pa.pa_pc = pc; 316 pa.pa_bus = bus; 317 pa.pa_device = device; 318 pa.pa_function = function; 319 pa.pa_tag = tag; 320 pa.pa_id = id; 321 pa.pa_class = class; 322 323 /* 324 * Set up memory, I/O enable, and PCI command flags 325 * as appropriate. 326 */ 327 pa.pa_flags = sc->sc_flags; 328 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 329 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 330 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 331 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 332 333 /* 334 * If the cache line size is not configured, then 335 * clear the MRL/MRM/MWI command-ok flags. 336 */ 337 if (PCI_CACHELINE(bhlcr) == 0) 338 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 339 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 340 341 if (sc->sc_bridgetag == NULL) { 342 pa.pa_intrswiz = 0; 343 pa.pa_intrtag = tag; 344 } else { 345 pa.pa_intrswiz = sc->sc_intrswiz + device; 346 pa.pa_intrtag = sc->sc_intrtag; 347 } 348 349 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 350 351 pin = PCI_INTERRUPT_PIN(intr); 352 pa.pa_rawintrpin = pin; 353 if (pin == PCI_INTERRUPT_PIN_NONE) { 354 /* no interrupt */ 355 pa.pa_intrpin = 0; 356 } else { 357 /* 358 * swizzle it based on the number of busses we're 359 * behind and our device number. 360 */ 361 pa.pa_intrpin = /* XXX */ 362 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 363 } 364 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 365 366 if (match != NULL) { 367 ret = (*match)(&pa); 368 if (ret != 0 && pap != NULL) 369 *pap = pa; 370 } else { 371 ldp->len = 2; 372 ldp->locs[PCICF_DEV] = device; 373 ldp->locs[PCICF_FUNCTION] = function; 374 375 subdev = config_found_sm_loc(&sc->sc_dev, "pci", ldp, &pa, 376 pciprint, pcisubmatch); 377 sc->PCI_SC_DEVICESC(device, function) = subdev; 378 ret = (subdev != NULL); 379 } 380 381 return (ret); 382 } 383 384 void 385 pcidevdetached(struct device *sc, struct device *dev) 386 { 387 struct pci_softc *psc = (struct pci_softc *)sc; 388 int d, f; 389 390 KASSERT(dev->dv_locators); 391 d = dev->dv_locators[PCICF_DEV]; 392 f = dev->dv_locators[PCICF_FUNCTION]; 393 394 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 395 396 psc->PCI_SC_DEVICESC(d, f) = 0; 397 } 398 399 int 400 pci_get_capability(pc, tag, capid, offset, value) 401 pci_chipset_tag_t pc; 402 pcitag_t tag; 403 int capid; 404 int *offset; 405 pcireg_t *value; 406 { 407 pcireg_t reg; 408 unsigned int ofs; 409 410 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 411 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 412 return (0); 413 414 /* Determine the Capability List Pointer register to start with. */ 415 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 416 switch (PCI_HDRTYPE_TYPE(reg)) { 417 case 0: /* standard device header */ 418 ofs = PCI_CAPLISTPTR_REG; 419 break; 420 case 2: /* PCI-CardBus Bridge header */ 421 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 422 break; 423 default: 424 return (0); 425 } 426 427 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 428 while (ofs != 0) { 429 #ifdef DIAGNOSTIC 430 if ((ofs & 3) || (ofs < 0x40)) 431 panic("pci_get_capability"); 432 #endif 433 reg = pci_conf_read(pc, tag, ofs); 434 if (PCI_CAPLIST_CAP(reg) == capid) { 435 if (offset) 436 *offset = ofs; 437 if (value) 438 *value = reg; 439 return (1); 440 } 441 ofs = PCI_CAPLIST_NEXT(reg); 442 } 443 444 return (0); 445 } 446 447 int 448 pci_find_device(struct pci_attach_args *pa, 449 int (*match)(struct pci_attach_args *)) 450 { 451 extern struct cfdriver pci_cd; 452 struct device *pcidev; 453 int i; 454 static const int wildcard[2] = { 455 PCICF_DEV_DEFAULT, 456 PCICF_FUNCTION_DEFAULT 457 }; 458 459 for (i = 0; i < pci_cd.cd_ndevs; i++) { 460 pcidev = pci_cd.cd_devs[i]; 461 if (pcidev != NULL && 462 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 463 match, pa) != 0) 464 return (1); 465 } 466 return (0); 467 } 468 469 #ifndef PCI_MACHDEP_ENUMERATE_BUS 470 /* 471 * Generic PCI bus enumeration routine. Used unless machine-dependent 472 * code needs to provide something else. 473 */ 474 int 475 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 476 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 477 { 478 pci_chipset_tag_t pc = sc->sc_pc; 479 int device, function, nfunctions, ret; 480 const struct pci_quirkdata *qd; 481 pcireg_t id, bhlcr; 482 pcitag_t tag; 483 #ifdef __PCI_BUS_DEVORDER 484 char devs[32]; 485 int i; 486 #endif 487 488 #ifdef __PCI_BUS_DEVORDER 489 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 490 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 491 #else 492 for (device = 0; device < sc->sc_maxndevs; device++) 493 #endif 494 { 495 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 496 (locators[PCICF_DEV] != device)) 497 continue; 498 499 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 500 501 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 502 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 503 continue; 504 505 id = pci_conf_read(pc, tag, PCI_ID_REG); 506 507 /* Invalid vendor ID value? */ 508 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 509 continue; 510 /* XXX Not invalid, but we've done this ~forever. */ 511 if (PCI_VENDOR(id) == 0) 512 continue; 513 514 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 515 516 if (qd != NULL && 517 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 518 nfunctions = 8; 519 else if (qd != NULL && 520 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 521 nfunctions = 1; 522 else 523 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 524 525 for (function = 0; function < nfunctions; function++) { 526 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 527 && (locators[PCICF_FUNCTION] != function)) 528 continue; 529 530 if (qd != NULL && 531 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 532 continue; 533 tag = pci_make_tag(pc, sc->sc_bus, device, function); 534 ret = pci_probe_device(sc, tag, match, pap); 535 if (match != NULL && ret != 0) 536 return (ret); 537 } 538 } 539 return (0); 540 } 541 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 542 543 /* 544 * Power Management Capability (Rev 2.2) 545 */ 546 547 int 548 pci_powerstate(pci_chipset_tag_t pc, pcitag_t tag, const int *newstate, 549 int *oldstate) 550 { 551 int offset; 552 pcireg_t value, cap, now; 553 554 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 555 return EOPNOTSUPP; 556 557 cap = value >> 16; 558 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 559 now = value & PCI_PMCSR_STATE_MASK; 560 value &= ~PCI_PMCSR_STATE_MASK; 561 if (oldstate) { 562 switch (now) { 563 case PCI_PMCSR_STATE_D0: 564 *oldstate = PCI_PWR_D0; 565 break; 566 case PCI_PMCSR_STATE_D1: 567 *oldstate = PCI_PWR_D1; 568 break; 569 case PCI_PMCSR_STATE_D2: 570 *oldstate = PCI_PWR_D2; 571 break; 572 case PCI_PMCSR_STATE_D3: 573 *oldstate = PCI_PWR_D3; 574 break; 575 default: 576 return EINVAL; 577 } 578 } 579 if (newstate == NULL) 580 return 0; 581 switch (*newstate) { 582 case PCI_PWR_D0: 583 if (now == PCI_PMCSR_STATE_D0) 584 return 0; 585 value |= PCI_PMCSR_STATE_D0; 586 break; 587 case PCI_PWR_D1: 588 if (now == PCI_PMCSR_STATE_D1) 589 return 0; 590 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 591 return EINVAL; 592 if (!(cap & PCI_PMCR_D1SUPP)) 593 return EOPNOTSUPP; 594 value |= PCI_PMCSR_STATE_D1; 595 break; 596 case PCI_PWR_D2: 597 if (now == PCI_PMCSR_STATE_D2) 598 return 0; 599 if (now == PCI_PMCSR_STATE_D3) 600 return EINVAL; 601 if (!(cap & PCI_PMCR_D2SUPP)) 602 return EOPNOTSUPP; 603 value |= PCI_PMCSR_STATE_D2; 604 break; 605 case PCI_PWR_D3: 606 if (now == PCI_PMCSR_STATE_D3) 607 return 0; 608 value |= PCI_PMCSR_STATE_D3; 609 break; 610 default: 611 return EINVAL; 612 } 613 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 614 DELAY(1000); 615 616 return 0; 617 } 618 619 /* 620 * Vital Product Data (PCI 2.2) 621 */ 622 623 int 624 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 625 pcireg_t *data) 626 { 627 uint32_t reg; 628 int ofs, i, j; 629 630 KASSERT(data != NULL); 631 KASSERT((offset + count) < 0x7fff); 632 633 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 634 return (1); 635 636 for (i = 0; i < count; offset += sizeof(*data), i++) { 637 reg &= 0x0000ffff; 638 reg &= ~PCI_VPD_OPFLAG; 639 reg |= PCI_VPD_ADDRESS(offset); 640 pci_conf_write(pc, tag, ofs, reg); 641 642 /* 643 * PCI 2.2 does not specify how long we should poll 644 * for completion nor whether the operation can fail. 645 */ 646 j = 0; 647 do { 648 if (j++ == 20) 649 return (1); 650 delay(4); 651 reg = pci_conf_read(pc, tag, ofs); 652 } while ((reg & PCI_VPD_OPFLAG) == 0); 653 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 654 } 655 656 return (0); 657 } 658 659 int 660 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 661 pcireg_t *data) 662 { 663 pcireg_t reg; 664 int ofs, i, j; 665 666 KASSERT(data != NULL); 667 KASSERT((offset + count) < 0x7fff); 668 669 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 670 return (1); 671 672 for (i = 0; i < count; offset += sizeof(*data), i++) { 673 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 674 675 reg &= 0x0000ffff; 676 reg |= PCI_VPD_OPFLAG; 677 reg |= PCI_VPD_ADDRESS(offset); 678 pci_conf_write(pc, tag, ofs, reg); 679 680 /* 681 * PCI 2.2 does not specify how long we should poll 682 * for completion nor whether the operation can fail. 683 */ 684 j = 0; 685 do { 686 if (j++ == 20) 687 return (1); 688 delay(1); 689 reg = pci_conf_read(pc, tag, ofs); 690 } while (reg & PCI_VPD_OPFLAG); 691 } 692 693 return (0); 694 } 695 696 int 697 pci_dma64_available(struct pci_attach_args *pa) 698 { 699 #ifdef _PCI_HAVE_DMA64 700 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 701 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 702 return 1; 703 #endif 704 return 0; 705 } 706
Indexes created Sun Sep 21 20:09:37 GMT 2025