pci.c revision 1.94
1 /* $NetBSD: pci.c,v 1.94 2005/08/25 18:35:39 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.94 2005/08/25 18:35:39 drochner Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include "locators.h" 54 55 #ifdef PCI_CONFIG_DUMP 56 int pci_config_dump = 1; 57 #else 58 int pci_config_dump = 0; 59 #endif 60 61 int pciprint(void *, const char *); 62 int pcisubmatch(struct device *, struct cfdata *, 63 const locdesc_t *, void *); 64 65 #ifdef PCI_MACHDEP_ENUMERATE_BUS 66 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 67 #else 68 int pci_enumerate_bus(struct pci_softc *, const int *, 69 int (*)(struct pci_attach_args *), struct pci_attach_args *); 70 #endif 71 72 /* 73 * Important note about PCI-ISA bridges: 74 * 75 * Callbacks are used to configure these devices so that ISA/EISA bridges 76 * can attach their child busses after PCI configuration is done. 77 * 78 * This works because: 79 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 80 * (2) any ISA/EISA bridges must be attached to primary PCI 81 * busses (i.e. bus zero). 82 * 83 * That boils down to: there can only be one of these outstanding 84 * at a time, it is cleared when configuring PCI bus 0 before any 85 * subdevices have been found, and it is run after all subdevices 86 * of PCI bus 0 have been found. 87 * 88 * This is needed because there are some (legacy) PCI devices which 89 * can show up as ISA/EISA devices as well (the prime example of which 90 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 91 * and the bridge is seen before the video board is, the board can show 92 * up as an ISA device, and that can (bogusly) complicate the PCI device's 93 * attach code, or make the PCI device not be properly attached at all. 94 * 95 * We use the generic config_defer() facility to achieve this. 96 */ 97 98 static int 99 pcirescan(struct device *sc, const char *ifattr, const int *locators) 100 { 101 102 KASSERT(ifattr && !strcmp(ifattr, "pci")); 103 KASSERT(locators); 104 105 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 106 return (0); 107 } 108 109 static int 110 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 struct pcibus_attach_args *pba = aux; 113 114 /* Check the locators */ 115 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 116 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 117 return (0); 118 119 /* sanity */ 120 if (pba->pba_bus < 0 || pba->pba_bus > 255) 121 return (0); 122 123 /* 124 * XXX check other (hardware?) indicators 125 */ 126 127 return (1); 128 } 129 130 static void 131 pciattach(struct device *parent, struct device *self, void *aux) 132 { 133 struct pcibus_attach_args *pba = aux; 134 struct pci_softc *sc = (struct pci_softc *)self; 135 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 136 const char *sep = ""; 137 static const int wildcard[2] = { PCICF_DEV_DEFAULT, 138 PCICF_FUNCTION_DEFAULT }; 139 140 pci_attach_hook(parent, self, pba); 141 142 aprint_naive("\n"); 143 aprint_normal("\n"); 144 145 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 146 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 147 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 148 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 149 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 150 151 if (io_enabled == 0 && mem_enabled == 0) { 152 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 153 return; 154 } 155 156 #define PRINT(str) \ 157 do { \ 158 aprint_normal("%s%s", sep, str); \ 159 sep = ", "; \ 160 } while (/*CONSTCOND*/0) 161 162 aprint_normal("%s: ", self->dv_xname); 163 164 if (io_enabled) 165 PRINT("i/o space"); 166 if (mem_enabled) 167 PRINT("memory space"); 168 aprint_normal(" enabled"); 169 170 if (mrl_enabled || mrm_enabled || mwi_enabled) { 171 if (mrl_enabled) 172 PRINT("rd/line"); 173 if (mrm_enabled) 174 PRINT("rd/mult"); 175 if (mwi_enabled) 176 PRINT("wr/inv"); 177 aprint_normal(" ok"); 178 } 179 180 aprint_normal("\n"); 181 182 #undef PRINT 183 184 sc->sc_iot = pba->pba_iot; 185 sc->sc_memt = pba->pba_memt; 186 sc->sc_dmat = pba->pba_dmat; 187 sc->sc_dmat64 = pba->pba_dmat64; 188 sc->sc_pc = pba->pba_pc; 189 sc->sc_bus = pba->pba_bus; 190 sc->sc_bridgetag = pba->pba_bridgetag; 191 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 192 sc->sc_intrswiz = pba->pba_intrswiz; 193 sc->sc_intrtag = pba->pba_intrtag; 194 sc->sc_flags = pba->pba_flags; 195 pcirescan(&sc->sc_dev, "pci", wildcard); 196 } 197 198 int 199 pciprint(void *aux, const char *pnp) 200 { 201 struct pci_attach_args *pa = aux; 202 char devinfo[256]; 203 const struct pci_quirkdata *qd; 204 205 if (pnp) { 206 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 207 aprint_normal("%s at %s", devinfo, pnp); 208 } 209 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 210 if (pci_config_dump) { 211 printf(": "); 212 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 213 if (!pnp) 214 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 215 printf("%s at %s", devinfo, pnp ? pnp : "?"); 216 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 217 #ifdef __i386__ 218 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 219 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 220 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 221 #else 222 printf("intrswiz %#lx, intrpin %#lx", 223 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 224 #endif 225 printf(", i/o %s, mem %s,", 226 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 227 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 228 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 229 PCI_PRODUCT(pa->pa_id)); 230 if (qd == NULL) { 231 printf(" no quirks"); 232 } else { 233 bitmask_snprintf(qd->quirks, 234 "\002\001multifn\002singlefn\003skipfunc0" 235 "\004skipfunc1\005skipfunc2\006skipfunc3" 236 "\007skipfunc4\010skipfunc5\011skipfunc6" 237 "\012skipfunc7", 238 devinfo, sizeof (devinfo)); 239 printf(" quirks %s", devinfo); 240 } 241 printf(")"); 242 } 243 return (UNCONF); 244 } 245 246 int 247 pcisubmatch(struct device *parent, struct cfdata *cf, 248 const locdesc_t *locs, void *aux) 249 { 250 251 if (cf->cf_loc[PCICF_DEV] != PCICF_DEV_DEFAULT && 252 cf->cf_loc[PCICF_DEV] != locs[PCICF_DEV]) 253 return (0); 254 if (cf->cf_loc[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT && 255 cf->cf_loc[PCICF_FUNCTION] != locs[PCICF_FUNCTION]) 256 return (0); 257 return (config_match(parent, cf, aux)); 258 } 259 260 int 261 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 262 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 263 { 264 pci_chipset_tag_t pc = sc->sc_pc; 265 struct pci_attach_args pa; 266 pcireg_t id, csr, class, intr, bhlcr; 267 int ret, pin, bus, device, function; 268 int locs[PCICF_NLOCS]; 269 struct device *subdev; 270 271 pci_decompose_tag(pc, tag, &bus, &device, &function); 272 273 /* a driver already attached? */ 274 if (sc->PCI_SC_DEVICESC(device, function) && !match) 275 return (0); 276 277 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 278 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 279 return (0); 280 281 id = pci_conf_read(pc, tag, PCI_ID_REG); 282 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 283 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 284 285 /* Invalid vendor ID value? */ 286 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 287 return (0); 288 /* XXX Not invalid, but we've done this ~forever. */ 289 if (PCI_VENDOR(id) == 0) 290 return (0); 291 292 pa.pa_iot = sc->sc_iot; 293 pa.pa_memt = sc->sc_memt; 294 pa.pa_dmat = sc->sc_dmat; 295 pa.pa_dmat64 = sc->sc_dmat64; 296 pa.pa_pc = pc; 297 pa.pa_bus = bus; 298 pa.pa_device = device; 299 pa.pa_function = function; 300 pa.pa_tag = tag; 301 pa.pa_id = id; 302 pa.pa_class = class; 303 304 /* 305 * Set up memory, I/O enable, and PCI command flags 306 * as appropriate. 307 */ 308 pa.pa_flags = sc->sc_flags; 309 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 310 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 311 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 312 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 313 314 /* 315 * If the cache line size is not configured, then 316 * clear the MRL/MRM/MWI command-ok flags. 317 */ 318 if (PCI_CACHELINE(bhlcr) == 0) 319 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 320 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 321 322 if (sc->sc_bridgetag == NULL) { 323 pa.pa_intrswiz = 0; 324 pa.pa_intrtag = tag; 325 } else { 326 pa.pa_intrswiz = sc->sc_intrswiz + device; 327 pa.pa_intrtag = sc->sc_intrtag; 328 } 329 330 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 331 332 pin = PCI_INTERRUPT_PIN(intr); 333 pa.pa_rawintrpin = pin; 334 if (pin == PCI_INTERRUPT_PIN_NONE) { 335 /* no interrupt */ 336 pa.pa_intrpin = 0; 337 } else { 338 /* 339 * swizzle it based on the number of busses we're 340 * behind and our device number. 341 */ 342 pa.pa_intrpin = /* XXX */ 343 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 344 } 345 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 346 347 if (match != NULL) { 348 ret = (*match)(&pa); 349 if (ret != 0 && pap != NULL) 350 *pap = pa; 351 } else { 352 locs[PCICF_DEV] = device; 353 locs[PCICF_FUNCTION] = function; 354 355 subdev = config_found_sm_loc(&sc->sc_dev, "pci", locs, &pa, 356 pciprint, pcisubmatch); 357 sc->PCI_SC_DEVICESC(device, function) = subdev; 358 ret = (subdev != NULL); 359 } 360 361 return (ret); 362 } 363 364 static void 365 pcidevdetached(struct device *sc, struct device *dev) 366 { 367 struct pci_softc *psc = (struct pci_softc *)sc; 368 int d, f; 369 370 KASSERT(dev->dv_locators); 371 d = dev->dv_locators[PCICF_DEV]; 372 f = dev->dv_locators[PCICF_FUNCTION]; 373 374 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 375 376 psc->PCI_SC_DEVICESC(d, f) = 0; 377 } 378 379 int 380 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 381 int *offset, pcireg_t *value) 382 { 383 pcireg_t reg; 384 unsigned int ofs; 385 386 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 387 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 388 return (0); 389 390 /* Determine the Capability List Pointer register to start with. */ 391 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 392 switch (PCI_HDRTYPE_TYPE(reg)) { 393 case 0: /* standard device header */ 394 ofs = PCI_CAPLISTPTR_REG; 395 break; 396 case 2: /* PCI-CardBus Bridge header */ 397 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 398 break; 399 default: 400 return (0); 401 } 402 403 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 404 while (ofs != 0) { 405 #ifdef DIAGNOSTIC 406 if ((ofs & 3) || (ofs < 0x40)) 407 panic("pci_get_capability"); 408 #endif 409 reg = pci_conf_read(pc, tag, ofs); 410 if (PCI_CAPLIST_CAP(reg) == capid) { 411 if (offset) 412 *offset = ofs; 413 if (value) 414 *value = reg; 415 return (1); 416 } 417 ofs = PCI_CAPLIST_NEXT(reg); 418 } 419 420 return (0); 421 } 422 423 int 424 pci_find_device(struct pci_attach_args *pa, 425 int (*match)(struct pci_attach_args *)) 426 { 427 extern struct cfdriver pci_cd; 428 struct device *pcidev; 429 int i; 430 static const int wildcard[2] = { 431 PCICF_DEV_DEFAULT, 432 PCICF_FUNCTION_DEFAULT 433 }; 434 435 for (i = 0; i < pci_cd.cd_ndevs; i++) { 436 pcidev = pci_cd.cd_devs[i]; 437 if (pcidev != NULL && 438 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 439 match, pa) != 0) 440 return (1); 441 } 442 return (0); 443 } 444 445 #ifndef PCI_MACHDEP_ENUMERATE_BUS 446 /* 447 * Generic PCI bus enumeration routine. Used unless machine-dependent 448 * code needs to provide something else. 449 */ 450 int 451 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 452 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 453 { 454 pci_chipset_tag_t pc = sc->sc_pc; 455 int device, function, nfunctions, ret; 456 const struct pci_quirkdata *qd; 457 pcireg_t id, bhlcr; 458 pcitag_t tag; 459 #ifdef __PCI_BUS_DEVORDER 460 char devs[32]; 461 int i; 462 #endif 463 464 #ifdef __PCI_BUS_DEVORDER 465 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 466 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 467 #else 468 for (device = 0; device < sc->sc_maxndevs; device++) 469 #endif 470 { 471 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 472 (locators[PCICF_DEV] != device)) 473 continue; 474 475 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 476 477 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 478 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 479 continue; 480 481 id = pci_conf_read(pc, tag, PCI_ID_REG); 482 483 /* Invalid vendor ID value? */ 484 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 485 continue; 486 /* XXX Not invalid, but we've done this ~forever. */ 487 if (PCI_VENDOR(id) == 0) 488 continue; 489 490 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 491 492 if (qd != NULL && 493 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 494 nfunctions = 8; 495 else if (qd != NULL && 496 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 497 nfunctions = 1; 498 else 499 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 500 501 for (function = 0; function < nfunctions; function++) { 502 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 503 && (locators[PCICF_FUNCTION] != function)) 504 continue; 505 506 if (qd != NULL && 507 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 508 continue; 509 tag = pci_make_tag(pc, sc->sc_bus, device, function); 510 ret = pci_probe_device(sc, tag, match, pap); 511 if (match != NULL && ret != 0) 512 return (ret); 513 } 514 } 515 return (0); 516 } 517 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 518 519 /* 520 * Power Management Capability (Rev 2.2) 521 */ 522 523 int 524 pci_powerstate(pci_chipset_tag_t pc, pcitag_t tag, const int *newstate, 525 int *oldstate) 526 { 527 int offset; 528 pcireg_t value, cap, now; 529 530 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 531 return EOPNOTSUPP; 532 533 cap = value >> 16; 534 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 535 now = value & PCI_PMCSR_STATE_MASK; 536 value &= ~PCI_PMCSR_STATE_MASK; 537 if (oldstate) { 538 switch (now) { 539 case PCI_PMCSR_STATE_D0: 540 *oldstate = PCI_PWR_D0; 541 break; 542 case PCI_PMCSR_STATE_D1: 543 *oldstate = PCI_PWR_D1; 544 break; 545 case PCI_PMCSR_STATE_D2: 546 *oldstate = PCI_PWR_D2; 547 break; 548 case PCI_PMCSR_STATE_D3: 549 *oldstate = PCI_PWR_D3; 550 break; 551 default: 552 return EINVAL; 553 } 554 } 555 if (newstate == NULL) 556 return 0; 557 switch (*newstate) { 558 case PCI_PWR_D0: 559 if (now == PCI_PMCSR_STATE_D0) 560 return 0; 561 value |= PCI_PMCSR_STATE_D0; 562 break; 563 case PCI_PWR_D1: 564 if (now == PCI_PMCSR_STATE_D1) 565 return 0; 566 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 567 return EINVAL; 568 if (!(cap & PCI_PMCR_D1SUPP)) 569 return EOPNOTSUPP; 570 value |= PCI_PMCSR_STATE_D1; 571 break; 572 case PCI_PWR_D2: 573 if (now == PCI_PMCSR_STATE_D2) 574 return 0; 575 if (now == PCI_PMCSR_STATE_D3) 576 return EINVAL; 577 if (!(cap & PCI_PMCR_D2SUPP)) 578 return EOPNOTSUPP; 579 value |= PCI_PMCSR_STATE_D2; 580 break; 581 case PCI_PWR_D3: 582 if (now == PCI_PMCSR_STATE_D3) 583 return 0; 584 value |= PCI_PMCSR_STATE_D3; 585 break; 586 default: 587 return EINVAL; 588 } 589 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 590 DELAY(1000); 591 592 return 0; 593 } 594 595 /* 596 * Vital Product Data (PCI 2.2) 597 */ 598 599 int 600 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 601 pcireg_t *data) 602 { 603 uint32_t reg; 604 int ofs, i, j; 605 606 KASSERT(data != NULL); 607 KASSERT((offset + count) < 0x7fff); 608 609 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 610 return (1); 611 612 for (i = 0; i < count; offset += sizeof(*data), i++) { 613 reg &= 0x0000ffff; 614 reg &= ~PCI_VPD_OPFLAG; 615 reg |= PCI_VPD_ADDRESS(offset); 616 pci_conf_write(pc, tag, ofs, reg); 617 618 /* 619 * PCI 2.2 does not specify how long we should poll 620 * for completion nor whether the operation can fail. 621 */ 622 j = 0; 623 do { 624 if (j++ == 20) 625 return (1); 626 delay(4); 627 reg = pci_conf_read(pc, tag, ofs); 628 } while ((reg & PCI_VPD_OPFLAG) == 0); 629 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 630 } 631 632 return (0); 633 } 634 635 int 636 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 637 pcireg_t *data) 638 { 639 pcireg_t reg; 640 int ofs, i, j; 641 642 KASSERT(data != NULL); 643 KASSERT((offset + count) < 0x7fff); 644 645 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 646 return (1); 647 648 for (i = 0; i < count; offset += sizeof(*data), i++) { 649 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 650 651 reg &= 0x0000ffff; 652 reg |= PCI_VPD_OPFLAG; 653 reg |= PCI_VPD_ADDRESS(offset); 654 pci_conf_write(pc, tag, ofs, reg); 655 656 /* 657 * PCI 2.2 does not specify how long we should poll 658 * for completion nor whether the operation can fail. 659 */ 660 j = 0; 661 do { 662 if (j++ == 20) 663 return (1); 664 delay(1); 665 reg = pci_conf_read(pc, tag, ofs); 666 } while (reg & PCI_VPD_OPFLAG); 667 } 668 669 return (0); 670 } 671 672 int 673 pci_dma64_available(struct pci_attach_args *pa) 674 { 675 #ifdef _PCI_HAVE_DMA64 676 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 677 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 678 return 1; 679 #endif 680 return 0; 681 } 682 683 void 684 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 685 struct pci_conf_state *pcs) 686 { 687 int off; 688 689 for (off = 0; off < 16; off++) 690 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 691 692 return; 693 } 694 695 void 696 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 697 struct pci_conf_state *pcs) 698 { 699 int off; 700 701 for (off = 0; off < 16; off++) 702 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 703 704 return; 705 } 706 707 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 708 pcimatch, pciattach, NULL, NULL, pcirescan, pcidevdetached); 709
Indexes created Mon Sep 22 05:09:51 GMT 2025