pciide.c revision 1.102
1 /* $NetBSD: pciide.c,v 1.102 2001/01/05 15:29:39 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/cy82c693var.h> 119 120 #include "opt_pciide.h" 121 122 /* inlines for reading/writing 8-bit PCI registers */ 123 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 124 int)); 125 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 126 int, u_int8_t)); 127 128 static __inline u_int8_t 129 pciide_pci_read(pc, pa, reg) 130 pci_chipset_tag_t pc; 131 pcitag_t pa; 132 int reg; 133 { 134 135 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 136 ((reg & 0x03) * 8) & 0xff); 137 } 138 139 static __inline void 140 pciide_pci_write(pc, pa, reg, val) 141 pci_chipset_tag_t pc; 142 pcitag_t pa; 143 int reg; 144 u_int8_t val; 145 { 146 pcireg_t pcival; 147 148 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 149 pcival &= ~(0xff << ((reg & 0x03) * 8)); 150 pcival |= (val << ((reg & 0x03) * 8)); 151 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 152 } 153 154 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 156 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 void piix_setup_channel __P((struct channel_softc*)); 158 void piix3_4_setup_channel __P((struct channel_softc*)); 159 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 161 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 163 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void amd756_setup_channel __P((struct channel_softc*)); 165 166 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void apollo_setup_channel __P((struct channel_softc*)); 168 169 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_setup_channel __P((struct channel_softc*)); 172 void cmd_channel_map __P((struct pci_attach_args *, 173 struct pciide_softc *, int)); 174 int cmd_pci_intr __P((void *)); 175 void cmd646_9_irqack __P((struct channel_softc *)); 176 177 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cy693_setup_channel __P((struct channel_softc*)); 179 180 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sis_setup_channel __P((struct channel_softc*)); 182 183 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void acer_setup_channel __P((struct channel_softc*)); 185 int acer_pci_intr __P((void *)); 186 187 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void pdc202xx_setup_channel __P((struct channel_softc*)); 189 int pdc202xx_pci_intr __P((void *)); 190 191 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 192 void opti_setup_channel __P((struct channel_softc*)); 193 194 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void hpt_setup_channel __P((struct channel_softc*)); 196 int hpt_pci_intr __P((void *)); 197 198 void pciide_channel_dma_setup __P((struct pciide_channel *)); 199 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 200 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 201 void pciide_dma_start __P((void*, int, int)); 202 int pciide_dma_finish __P((void*, int, int, int)); 203 void pciide_irqack __P((struct channel_softc *)); 204 void pciide_print_modes __P((struct pciide_channel *)); 205 206 struct pciide_product_desc { 207 u_int32_t ide_product; 208 int ide_flags; 209 const char *ide_name; 210 /* map and setup chip, probe drives */ 211 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 212 }; 213 214 /* Flags for ide_flags */ 215 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 216 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 217 218 /* Default product description for devices not known from this controller */ 219 const struct pciide_product_desc default_product_desc = { 220 0, 221 0, 222 "Generic PCI IDE controller", 223 default_chip_map, 224 }; 225 226 const struct pciide_product_desc pciide_intel_products[] = { 227 { PCI_PRODUCT_INTEL_82092AA, 228 0, 229 "Intel 82092AA IDE controller", 230 default_chip_map, 231 }, 232 { PCI_PRODUCT_INTEL_82371FB_IDE, 233 0, 234 "Intel 82371FB IDE controller (PIIX)", 235 piix_chip_map, 236 }, 237 { PCI_PRODUCT_INTEL_82371SB_IDE, 238 0, 239 "Intel 82371SB IDE Interface (PIIX3)", 240 piix_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82371AB_IDE, 243 0, 244 "Intel 82371AB IDE controller (PIIX4)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82440MX_IDE, 248 0, 249 "Intel 82440MX IDE controller", 250 piix_chip_map 251 }, 252 { PCI_PRODUCT_INTEL_82801AA_IDE, 253 0, 254 "Intel 82801AA IDE Controller (ICH)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82801AB_IDE, 258 0, 259 "Intel 82801AB IDE Controller (ICH0)", 260 piix_chip_map, 261 }, 262 { PCI_PRODUCT_INTEL_82801BA_IDE, 263 0, 264 "Intel 82801BA IDE Controller (ICH2)", 265 piix_chip_map, 266 }, 267 { 0, 268 0, 269 NULL, 270 } 271 }; 272 273 const struct pciide_product_desc pciide_amd_products[] = { 274 { PCI_PRODUCT_AMD_PBC756_IDE, 275 0, 276 "Advanced Micro Devices AMD756 IDE Controller", 277 amd756_chip_map 278 }, 279 { 0, 280 0, 281 NULL, 282 } 283 }; 284 285 const struct pciide_product_desc pciide_cmd_products[] = { 286 { PCI_PRODUCT_CMDTECH_640, 287 0, 288 "CMD Technology PCI0640", 289 cmd_chip_map 290 }, 291 { PCI_PRODUCT_CMDTECH_643, 292 0, 293 "CMD Technology PCI0643", 294 cmd0643_9_chip_map, 295 }, 296 { PCI_PRODUCT_CMDTECH_646, 297 0, 298 "CMD Technology PCI0646", 299 cmd0643_9_chip_map, 300 }, 301 { PCI_PRODUCT_CMDTECH_648, 302 IDE_PCI_CLASS_OVERRIDE, 303 "CMD Technology PCI0648", 304 cmd0643_9_chip_map, 305 }, 306 { PCI_PRODUCT_CMDTECH_649, 307 IDE_PCI_CLASS_OVERRIDE, 308 "CMD Technology PCI0649", 309 cmd0643_9_chip_map, 310 }, 311 { 0, 312 0, 313 NULL, 314 } 315 }; 316 317 const struct pciide_product_desc pciide_via_products[] = { 318 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 319 0, 320 "VIA Tech VT82C586 IDE Controller", 321 apollo_chip_map, 322 }, 323 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 324 0, 325 "VIA Tech VT82C586A IDE Controller", 326 apollo_chip_map, 327 }, 328 { 0, 329 0, 330 NULL, 331 } 332 }; 333 334 const struct pciide_product_desc pciide_cypress_products[] = { 335 { PCI_PRODUCT_CONTAQ_82C693, 336 IDE_16BIT_IOSPACE, 337 "Cypress 82C693 IDE Controller", 338 cy693_chip_map, 339 }, 340 { 0, 341 0, 342 NULL, 343 } 344 }; 345 346 const struct pciide_product_desc pciide_sis_products[] = { 347 { PCI_PRODUCT_SIS_5597_IDE, 348 0, 349 "Silicon Integrated System 5597/5598 IDE controller", 350 sis_chip_map, 351 }, 352 { 0, 353 0, 354 NULL, 355 } 356 }; 357 358 const struct pciide_product_desc pciide_acer_products[] = { 359 { PCI_PRODUCT_ALI_M5229, 360 0, 361 "Acer Labs M5229 UDMA IDE Controller", 362 acer_chip_map, 363 }, 364 { 0, 365 0, 366 NULL, 367 } 368 }; 369 370 const struct pciide_product_desc pciide_promise_products[] = { 371 { PCI_PRODUCT_PROMISE_ULTRA33, 372 IDE_PCI_CLASS_OVERRIDE, 373 "Promise Ultra33/ATA Bus Master IDE Accelerator", 374 pdc202xx_chip_map, 375 }, 376 { PCI_PRODUCT_PROMISE_ULTRA66, 377 IDE_PCI_CLASS_OVERRIDE, 378 "Promise Ultra66/ATA Bus Master IDE Accelerator", 379 pdc202xx_chip_map, 380 }, 381 { PCI_PRODUCT_PROMISE_ULTRA100, 382 IDE_PCI_CLASS_OVERRIDE, 383 "Promise Ultra100/ATA Bus Master IDE Accelerator", 384 pdc202xx_chip_map, 385 }, 386 { PCI_PRODUCT_PROMISE_ULTRA100X, 387 IDE_PCI_CLASS_OVERRIDE, 388 "Promise Ultra100/ATA Bus Master IDE Accelerator", 389 pdc202xx_chip_map, 390 }, 391 { 0, 392 0, 393 NULL, 394 } 395 }; 396 397 const struct pciide_product_desc pciide_opti_products[] = { 398 { PCI_PRODUCT_OPTI_82C621, 399 0, 400 "OPTi 82c621 PCI IDE controller", 401 opti_chip_map, 402 }, 403 { PCI_PRODUCT_OPTI_82C568, 404 0, 405 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 406 opti_chip_map, 407 }, 408 { PCI_PRODUCT_OPTI_82D568, 409 0, 410 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 411 opti_chip_map, 412 }, 413 { 0, 414 0, 415 NULL, 416 } 417 }; 418 419 const struct pciide_product_desc pciide_triones_products[] = { 420 { PCI_PRODUCT_TRIONES_HPT366, 421 IDE_PCI_CLASS_OVERRIDE, 422 "Triones/Highpoint HPT366/370 IDE Controller", 423 hpt_chip_map, 424 }, 425 { 0, 426 0, 427 NULL, 428 } 429 }; 430 431 struct pciide_vendor_desc { 432 u_int32_t ide_vendor; 433 const struct pciide_product_desc *ide_products; 434 }; 435 436 const struct pciide_vendor_desc pciide_vendors[] = { 437 { PCI_VENDOR_INTEL, pciide_intel_products }, 438 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 439 { PCI_VENDOR_VIATECH, pciide_via_products }, 440 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 441 { PCI_VENDOR_SIS, pciide_sis_products }, 442 { PCI_VENDOR_ALI, pciide_acer_products }, 443 { PCI_VENDOR_PROMISE, pciide_promise_products }, 444 { PCI_VENDOR_AMD, pciide_amd_products }, 445 { PCI_VENDOR_OPTI, pciide_opti_products }, 446 { PCI_VENDOR_TRIONES, pciide_triones_products }, 447 { 0, NULL } 448 }; 449 450 /* options passed via the 'flags' config keyword */ 451 #define PCIIDE_OPTIONS_DMA 0x01 452 453 int pciide_match __P((struct device *, struct cfdata *, void *)); 454 void pciide_attach __P((struct device *, struct device *, void *)); 455 456 struct cfattach pciide_ca = { 457 sizeof(struct pciide_softc), pciide_match, pciide_attach 458 }; 459 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 460 int pciide_mapregs_compat __P(( struct pci_attach_args *, 461 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 462 int pciide_mapregs_native __P((struct pci_attach_args *, 463 struct pciide_channel *, bus_size_t *, bus_size_t *, 464 int (*pci_intr) __P((void *)))); 465 void pciide_mapreg_dma __P((struct pciide_softc *, 466 struct pci_attach_args *)); 467 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 468 void pciide_mapchan __P((struct pci_attach_args *, 469 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 470 int (*pci_intr) __P((void *)))); 471 int pciide_chan_candisable __P((struct pciide_channel *)); 472 void pciide_map_compat_intr __P(( struct pci_attach_args *, 473 struct pciide_channel *, int, int)); 474 int pciide_print __P((void *, const char *pnp)); 475 int pciide_compat_intr __P((void *)); 476 int pciide_pci_intr __P((void *)); 477 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 478 479 const struct pciide_product_desc * 480 pciide_lookup_product(id) 481 u_int32_t id; 482 { 483 const struct pciide_product_desc *pp; 484 const struct pciide_vendor_desc *vp; 485 486 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 487 if (PCI_VENDOR(id) == vp->ide_vendor) 488 break; 489 490 if ((pp = vp->ide_products) == NULL) 491 return NULL; 492 493 for (; pp->ide_name != NULL; pp++) 494 if (PCI_PRODUCT(id) == pp->ide_product) 495 break; 496 497 if (pp->ide_name == NULL) 498 return NULL; 499 return pp; 500 } 501 502 int 503 pciide_match(parent, match, aux) 504 struct device *parent; 505 struct cfdata *match; 506 void *aux; 507 { 508 struct pci_attach_args *pa = aux; 509 const struct pciide_product_desc *pp; 510 511 /* 512 * Check the ID register to see that it's a PCI IDE controller. 513 * If it is, we assume that we can deal with it; it _should_ 514 * work in a standardized way... 515 */ 516 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 517 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 518 return (1); 519 } 520 521 /* 522 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 523 * controllers. Let see if we can deal with it anyway. 524 */ 525 pp = pciide_lookup_product(pa->pa_id); 526 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 527 return (1); 528 } 529 530 return (0); 531 } 532 533 void 534 pciide_attach(parent, self, aux) 535 struct device *parent, *self; 536 void *aux; 537 { 538 struct pci_attach_args *pa = aux; 539 pci_chipset_tag_t pc = pa->pa_pc; 540 pcitag_t tag = pa->pa_tag; 541 struct pciide_softc *sc = (struct pciide_softc *)self; 542 pcireg_t csr; 543 char devinfo[256]; 544 const char *displaydev; 545 546 sc->sc_pp = pciide_lookup_product(pa->pa_id); 547 if (sc->sc_pp == NULL) { 548 sc->sc_pp = &default_product_desc; 549 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 550 displaydev = devinfo; 551 } else 552 displaydev = sc->sc_pp->ide_name; 553 554 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 555 556 sc->sc_pc = pa->pa_pc; 557 sc->sc_tag = pa->pa_tag; 558 #ifdef WDCDEBUG 559 if (wdcdebug_pciide_mask & DEBUG_PROBE) 560 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 561 #endif 562 sc->sc_pp->chip_map(sc, pa); 563 564 if (sc->sc_dma_ok) { 565 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 566 csr |= PCI_COMMAND_MASTER_ENABLE; 567 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 568 } 569 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 570 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 571 } 572 573 /* tell wether the chip is enabled or not */ 574 int 575 pciide_chipen(sc, pa) 576 struct pciide_softc *sc; 577 struct pci_attach_args *pa; 578 { 579 pcireg_t csr; 580 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 581 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 582 PCI_COMMAND_STATUS_REG); 583 printf("%s: device disabled (at %s)\n", 584 sc->sc_wdcdev.sc_dev.dv_xname, 585 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 586 "device" : "bridge"); 587 return 0; 588 } 589 return 1; 590 } 591 592 int 593 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 594 struct pci_attach_args *pa; 595 struct pciide_channel *cp; 596 int compatchan; 597 bus_size_t *cmdsizep, *ctlsizep; 598 { 599 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 600 struct channel_softc *wdc_cp = &cp->wdc_channel; 601 602 cp->compat = 1; 603 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 604 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 605 606 wdc_cp->cmd_iot = pa->pa_iot; 607 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 608 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 609 printf("%s: couldn't map %s channel cmd regs\n", 610 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 611 return (0); 612 } 613 614 wdc_cp->ctl_iot = pa->pa_iot; 615 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 616 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 617 printf("%s: couldn't map %s channel ctl regs\n", 618 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 619 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 620 PCIIDE_COMPAT_CMD_SIZE); 621 return (0); 622 } 623 624 return (1); 625 } 626 627 int 628 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 629 struct pci_attach_args * pa; 630 struct pciide_channel *cp; 631 bus_size_t *cmdsizep, *ctlsizep; 632 int (*pci_intr) __P((void *)); 633 { 634 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 635 struct channel_softc *wdc_cp = &cp->wdc_channel; 636 const char *intrstr; 637 pci_intr_handle_t intrhandle; 638 639 cp->compat = 0; 640 641 if (sc->sc_pci_ih == NULL) { 642 if (pci_intr_map(pa, &intrhandle) != 0) { 643 printf("%s: couldn't map native-PCI interrupt\n", 644 sc->sc_wdcdev.sc_dev.dv_xname); 645 return 0; 646 } 647 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 648 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 649 intrhandle, IPL_BIO, pci_intr, sc); 650 if (sc->sc_pci_ih != NULL) { 651 printf("%s: using %s for native-PCI interrupt\n", 652 sc->sc_wdcdev.sc_dev.dv_xname, 653 intrstr ? intrstr : "unknown interrupt"); 654 } else { 655 printf("%s: couldn't establish native-PCI interrupt", 656 sc->sc_wdcdev.sc_dev.dv_xname); 657 if (intrstr != NULL) 658 printf(" at %s", intrstr); 659 printf("\n"); 660 return 0; 661 } 662 } 663 cp->ih = sc->sc_pci_ih; 664 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 665 PCI_MAPREG_TYPE_IO, 0, 666 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 667 printf("%s: couldn't map %s channel cmd regs\n", 668 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 669 return 0; 670 } 671 672 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 673 PCI_MAPREG_TYPE_IO, 0, 674 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 675 printf("%s: couldn't map %s channel ctl regs\n", 676 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 677 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 678 return 0; 679 } 680 return (1); 681 } 682 683 void 684 pciide_mapreg_dma(sc, pa) 685 struct pciide_softc *sc; 686 struct pci_attach_args *pa; 687 { 688 pcireg_t maptype; 689 bus_addr_t addr; 690 691 /* 692 * Map DMA registers 693 * 694 * Note that sc_dma_ok is the right variable to test to see if 695 * DMA can be done. If the interface doesn't support DMA, 696 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 697 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 698 * non-zero if the interface supports DMA and the registers 699 * could be mapped. 700 * 701 * XXX Note that despite the fact that the Bus Master IDE specs 702 * XXX say that "The bus master IDE function uses 16 bytes of IO 703 * XXX space," some controllers (at least the United 704 * XXX Microelectronics UM8886BF) place it in memory space. 705 */ 706 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 707 PCIIDE_REG_BUS_MASTER_DMA); 708 709 switch (maptype) { 710 case PCI_MAPREG_TYPE_IO: 711 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 712 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 713 &addr, NULL, NULL) == 0); 714 if (sc->sc_dma_ok == 0) { 715 printf(", but unused (couldn't query registers)"); 716 break; 717 } 718 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 719 && addr >= 0x10000) { 720 sc->sc_dma_ok = 0; 721 printf(", but unused (registers at unsafe address %#lx)", (unsigned long)addr); 722 break; 723 } 724 /* FALLTHROUGH */ 725 726 case PCI_MAPREG_MEM_TYPE_32BIT: 727 sc->sc_dma_ok = (pci_mapreg_map(pa, 728 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 729 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 730 sc->sc_dmat = pa->pa_dmat; 731 if (sc->sc_dma_ok == 0) { 732 printf(", but unused (couldn't map registers)"); 733 } else { 734 sc->sc_wdcdev.dma_arg = sc; 735 sc->sc_wdcdev.dma_init = pciide_dma_init; 736 sc->sc_wdcdev.dma_start = pciide_dma_start; 737 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 738 } 739 break; 740 741 default: 742 sc->sc_dma_ok = 0; 743 printf(", but unsupported register maptype (0x%x)", maptype); 744 } 745 } 746 747 int 748 pciide_compat_intr(arg) 749 void *arg; 750 { 751 struct pciide_channel *cp = arg; 752 753 #ifdef DIAGNOSTIC 754 /* should only be called for a compat channel */ 755 if (cp->compat == 0) 756 panic("pciide compat intr called for non-compat chan %p\n", cp); 757 #endif 758 return (wdcintr(&cp->wdc_channel)); 759 } 760 761 int 762 pciide_pci_intr(arg) 763 void *arg; 764 { 765 struct pciide_softc *sc = arg; 766 struct pciide_channel *cp; 767 struct channel_softc *wdc_cp; 768 int i, rv, crv; 769 770 rv = 0; 771 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 772 cp = &sc->pciide_channels[i]; 773 wdc_cp = &cp->wdc_channel; 774 775 /* If a compat channel skip. */ 776 if (cp->compat) 777 continue; 778 /* if this channel not waiting for intr, skip */ 779 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 780 continue; 781 782 crv = wdcintr(wdc_cp); 783 if (crv == 0) 784 ; /* leave rv alone */ 785 else if (crv == 1) 786 rv = 1; /* claim the intr */ 787 else if (rv == 0) /* crv should be -1 in this case */ 788 rv = crv; /* if we've done no better, take it */ 789 } 790 return (rv); 791 } 792 793 void 794 pciide_channel_dma_setup(cp) 795 struct pciide_channel *cp; 796 { 797 int drive; 798 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 799 struct ata_drive_datas *drvp; 800 801 for (drive = 0; drive < 2; drive++) { 802 drvp = &cp->wdc_channel.ch_drive[drive]; 803 /* If no drive, skip */ 804 if ((drvp->drive_flags & DRIVE) == 0) 805 continue; 806 /* setup DMA if needed */ 807 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 808 (drvp->drive_flags & DRIVE_UDMA) == 0) || 809 sc->sc_dma_ok == 0) { 810 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 811 continue; 812 } 813 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 814 != 0) { 815 /* Abort DMA setup */ 816 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 817 continue; 818 } 819 } 820 } 821 822 int 823 pciide_dma_table_setup(sc, channel, drive) 824 struct pciide_softc *sc; 825 int channel, drive; 826 { 827 bus_dma_segment_t seg; 828 int error, rseg; 829 const bus_size_t dma_table_size = 830 sizeof(struct idedma_table) * NIDEDMA_TABLES; 831 struct pciide_dma_maps *dma_maps = 832 &sc->pciide_channels[channel].dma_maps[drive]; 833 834 /* If table was already allocated, just return */ 835 if (dma_maps->dma_table) 836 return 0; 837 838 /* Allocate memory for the DMA tables and map it */ 839 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 840 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 841 BUS_DMA_NOWAIT)) != 0) { 842 printf("%s:%d: unable to allocate table DMA for " 843 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 844 channel, drive, error); 845 return error; 846 } 847 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 848 dma_table_size, 849 (caddr_t *)&dma_maps->dma_table, 850 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 851 printf("%s:%d: unable to map table DMA for" 852 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 853 channel, drive, error); 854 return error; 855 } 856 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 857 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 858 (unsigned long)seg.ds_addr), DEBUG_PROBE); 859 860 /* Create and load table DMA map for this disk */ 861 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 862 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 863 &dma_maps->dmamap_table)) != 0) { 864 printf("%s:%d: unable to create table DMA map for " 865 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 866 channel, drive, error); 867 return error; 868 } 869 if ((error = bus_dmamap_load(sc->sc_dmat, 870 dma_maps->dmamap_table, 871 dma_maps->dma_table, 872 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 873 printf("%s:%d: unable to load table DMA map for " 874 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 875 channel, drive, error); 876 return error; 877 } 878 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 879 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 880 DEBUG_PROBE); 881 /* Create a xfer DMA map for this drive */ 882 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 883 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 884 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 885 &dma_maps->dmamap_xfer)) != 0) { 886 printf("%s:%d: unable to create xfer DMA map for " 887 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 888 channel, drive, error); 889 return error; 890 } 891 return 0; 892 } 893 894 int 895 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 896 void *v; 897 int channel, drive; 898 void *databuf; 899 size_t datalen; 900 int flags; 901 { 902 struct pciide_softc *sc = v; 903 int error, seg; 904 struct pciide_dma_maps *dma_maps = 905 &sc->pciide_channels[channel].dma_maps[drive]; 906 907 error = bus_dmamap_load(sc->sc_dmat, 908 dma_maps->dmamap_xfer, 909 databuf, datalen, NULL, BUS_DMA_NOWAIT); 910 if (error) { 911 printf("%s:%d: unable to load xfer DMA map for" 912 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 913 channel, drive, error); 914 return error; 915 } 916 917 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 918 dma_maps->dmamap_xfer->dm_mapsize, 919 (flags & WDC_DMA_READ) ? 920 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 921 922 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 923 #ifdef DIAGNOSTIC 924 /* A segment must not cross a 64k boundary */ 925 { 926 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 927 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 928 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 929 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 930 printf("pciide_dma: segment %d physical addr 0x%lx" 931 " len 0x%lx not properly aligned\n", 932 seg, phys, len); 933 panic("pciide_dma: buf align"); 934 } 935 } 936 #endif 937 dma_maps->dma_table[seg].base_addr = 938 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 939 dma_maps->dma_table[seg].byte_count = 940 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 941 IDEDMA_BYTE_COUNT_MASK); 942 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 943 seg, le32toh(dma_maps->dma_table[seg].byte_count), 944 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 945 946 } 947 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 948 htole32(IDEDMA_BYTE_COUNT_EOT); 949 950 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 951 dma_maps->dmamap_table->dm_mapsize, 952 BUS_DMASYNC_PREWRITE); 953 954 /* Maps are ready. Start DMA function */ 955 #ifdef DIAGNOSTIC 956 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 957 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 958 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 959 panic("pciide_dma_init: table align"); 960 } 961 #endif 962 963 /* Clear status bits */ 964 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 965 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 966 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 967 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 968 /* Write table addr */ 969 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 970 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 971 dma_maps->dmamap_table->dm_segs[0].ds_addr); 972 /* set read/write */ 973 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 974 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 975 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 976 /* remember flags */ 977 dma_maps->dma_flags = flags; 978 return 0; 979 } 980 981 void 982 pciide_dma_start(v, channel, drive) 983 void *v; 984 int channel, drive; 985 { 986 struct pciide_softc *sc = v; 987 988 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 989 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 990 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 991 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 992 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 993 } 994 995 int 996 pciide_dma_finish(v, channel, drive, force) 997 void *v; 998 int channel, drive; 999 int force; 1000 { 1001 struct pciide_softc *sc = v; 1002 u_int8_t status; 1003 int error = 0; 1004 struct pciide_dma_maps *dma_maps = 1005 &sc->pciide_channels[channel].dma_maps[drive]; 1006 1007 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1008 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1009 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1010 DEBUG_XFERS); 1011 1012 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1013 return WDC_DMAST_NOIRQ; 1014 1015 /* stop DMA channel */ 1016 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1017 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1018 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1019 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1020 1021 /* Unload the map of the data buffer */ 1022 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1023 dma_maps->dmamap_xfer->dm_mapsize, 1024 (dma_maps->dma_flags & WDC_DMA_READ) ? 1025 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1026 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1027 1028 if ((status & IDEDMA_CTL_ERR) != 0) { 1029 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1030 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1031 error |= WDC_DMAST_ERR; 1032 } 1033 1034 if ((status & IDEDMA_CTL_INTR) == 0) { 1035 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1036 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1037 drive, status); 1038 error |= WDC_DMAST_NOIRQ; 1039 } 1040 1041 if ((status & IDEDMA_CTL_ACT) != 0) { 1042 /* data underrun, may be a valid condition for ATAPI */ 1043 error |= WDC_DMAST_UNDER; 1044 } 1045 return error; 1046 } 1047 1048 void 1049 pciide_irqack(chp) 1050 struct channel_softc *chp; 1051 { 1052 struct pciide_channel *cp = (struct pciide_channel*)chp; 1053 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1054 1055 /* clear status bits in IDE DMA registers */ 1056 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1057 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1058 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1059 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1060 } 1061 1062 /* some common code used by several chip_map */ 1063 int 1064 pciide_chansetup(sc, channel, interface) 1065 struct pciide_softc *sc; 1066 int channel; 1067 pcireg_t interface; 1068 { 1069 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1070 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1071 cp->name = PCIIDE_CHANNEL_NAME(channel); 1072 cp->wdc_channel.channel = channel; 1073 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1074 cp->wdc_channel.ch_queue = 1075 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1076 if (cp->wdc_channel.ch_queue == NULL) { 1077 printf("%s %s channel: " 1078 "can't allocate memory for command queue", 1079 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1080 return 0; 1081 } 1082 printf("%s: %s channel %s to %s mode\n", 1083 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1084 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1085 "configured" : "wired", 1086 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1087 "native-PCI" : "compatibility"); 1088 return 1; 1089 } 1090 1091 /* some common code used by several chip channel_map */ 1092 void 1093 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1094 struct pci_attach_args *pa; 1095 struct pciide_channel *cp; 1096 pcireg_t interface; 1097 bus_size_t *cmdsizep, *ctlsizep; 1098 int (*pci_intr) __P((void *)); 1099 { 1100 struct channel_softc *wdc_cp = &cp->wdc_channel; 1101 1102 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1103 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1104 pci_intr); 1105 else 1106 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1107 wdc_cp->channel, cmdsizep, ctlsizep); 1108 1109 if (cp->hw_ok == 0) 1110 return; 1111 wdc_cp->data32iot = wdc_cp->cmd_iot; 1112 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1113 wdcattach(wdc_cp); 1114 } 1115 1116 /* 1117 * Generic code to call to know if a channel can be disabled. Return 1 1118 * if channel can be disabled, 0 if not 1119 */ 1120 int 1121 pciide_chan_candisable(cp) 1122 struct pciide_channel *cp; 1123 { 1124 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1125 struct channel_softc *wdc_cp = &cp->wdc_channel; 1126 1127 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1128 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1129 printf("%s: disabling %s channel (no drives)\n", 1130 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1131 cp->hw_ok = 0; 1132 return 1; 1133 } 1134 return 0; 1135 } 1136 1137 /* 1138 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1139 * Set hw_ok=0 on failure 1140 */ 1141 void 1142 pciide_map_compat_intr(pa, cp, compatchan, interface) 1143 struct pci_attach_args *pa; 1144 struct pciide_channel *cp; 1145 int compatchan, interface; 1146 { 1147 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1148 struct channel_softc *wdc_cp = &cp->wdc_channel; 1149 1150 if (cp->hw_ok == 0) 1151 return; 1152 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1153 return; 1154 1155 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1156 pa, compatchan, pciide_compat_intr, cp); 1157 if (cp->ih == NULL) { 1158 printf("%s: no compatibility interrupt for use by %s " 1159 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1160 cp->hw_ok = 0; 1161 } 1162 } 1163 1164 void 1165 pciide_print_modes(cp) 1166 struct pciide_channel *cp; 1167 { 1168 wdc_print_modes(&cp->wdc_channel); 1169 } 1170 1171 void 1172 default_chip_map(sc, pa) 1173 struct pciide_softc *sc; 1174 struct pci_attach_args *pa; 1175 { 1176 struct pciide_channel *cp; 1177 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1178 pcireg_t csr; 1179 int channel, drive; 1180 struct ata_drive_datas *drvp; 1181 u_int8_t idedma_ctl; 1182 bus_size_t cmdsize, ctlsize; 1183 char *failreason; 1184 1185 if (pciide_chipen(sc, pa) == 0) 1186 return; 1187 1188 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1189 printf("%s: bus-master DMA support present", 1190 sc->sc_wdcdev.sc_dev.dv_xname); 1191 if (sc->sc_pp == &default_product_desc && 1192 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1193 PCIIDE_OPTIONS_DMA) == 0) { 1194 printf(", but unused (no driver support)"); 1195 sc->sc_dma_ok = 0; 1196 } else { 1197 pciide_mapreg_dma(sc, pa); 1198 if (sc->sc_dma_ok != 0) 1199 printf(", used without full driver " 1200 "support"); 1201 } 1202 } else { 1203 printf("%s: hardware does not support DMA", 1204 sc->sc_wdcdev.sc_dev.dv_xname); 1205 sc->sc_dma_ok = 0; 1206 } 1207 printf("\n"); 1208 if (sc->sc_dma_ok) { 1209 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1210 sc->sc_wdcdev.irqack = pciide_irqack; 1211 } 1212 sc->sc_wdcdev.PIO_cap = 0; 1213 sc->sc_wdcdev.DMA_cap = 0; 1214 1215 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1216 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1217 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1218 1219 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1220 cp = &sc->pciide_channels[channel]; 1221 if (pciide_chansetup(sc, channel, interface) == 0) 1222 continue; 1223 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1224 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1225 &ctlsize, pciide_pci_intr); 1226 } else { 1227 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1228 channel, &cmdsize, &ctlsize); 1229 } 1230 if (cp->hw_ok == 0) 1231 continue; 1232 /* 1233 * Check to see if something appears to be there. 1234 */ 1235 failreason = NULL; 1236 if (!wdcprobe(&cp->wdc_channel)) { 1237 failreason = "not responding; disabled or no drives?"; 1238 goto next; 1239 } 1240 /* 1241 * Now, make sure it's actually attributable to this PCI IDE 1242 * channel by trying to access the channel again while the 1243 * PCI IDE controller's I/O space is disabled. (If the 1244 * channel no longer appears to be there, it belongs to 1245 * this controller.) YUCK! 1246 */ 1247 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1248 PCI_COMMAND_STATUS_REG); 1249 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1250 csr & ~PCI_COMMAND_IO_ENABLE); 1251 if (wdcprobe(&cp->wdc_channel)) 1252 failreason = "other hardware responding at addresses"; 1253 pci_conf_write(sc->sc_pc, sc->sc_tag, 1254 PCI_COMMAND_STATUS_REG, csr); 1255 next: 1256 if (failreason) { 1257 printf("%s: %s channel ignored (%s)\n", 1258 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1259 failreason); 1260 cp->hw_ok = 0; 1261 bus_space_unmap(cp->wdc_channel.cmd_iot, 1262 cp->wdc_channel.cmd_ioh, cmdsize); 1263 bus_space_unmap(cp->wdc_channel.ctl_iot, 1264 cp->wdc_channel.ctl_ioh, ctlsize); 1265 } else { 1266 pciide_map_compat_intr(pa, cp, channel, interface); 1267 } 1268 if (cp->hw_ok) { 1269 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1270 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1271 wdcattach(&cp->wdc_channel); 1272 } 1273 } 1274 1275 if (sc->sc_dma_ok == 0) 1276 return; 1277 1278 /* Allocate DMA maps */ 1279 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1280 idedma_ctl = 0; 1281 cp = &sc->pciide_channels[channel]; 1282 for (drive = 0; drive < 2; drive++) { 1283 drvp = &cp->wdc_channel.ch_drive[drive]; 1284 /* If no drive, skip */ 1285 if ((drvp->drive_flags & DRIVE) == 0) 1286 continue; 1287 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1288 continue; 1289 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1290 /* Abort DMA setup */ 1291 printf("%s:%d:%d: can't allocate DMA maps, " 1292 "using PIO transfers\n", 1293 sc->sc_wdcdev.sc_dev.dv_xname, 1294 channel, drive); 1295 drvp->drive_flags &= ~DRIVE_DMA; 1296 } 1297 printf("%s:%d:%d: using DMA data transfers\n", 1298 sc->sc_wdcdev.sc_dev.dv_xname, 1299 channel, drive); 1300 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1301 } 1302 if (idedma_ctl != 0) { 1303 /* Add software bits in status register */ 1304 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1305 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1306 idedma_ctl); 1307 } 1308 } 1309 } 1310 1311 void 1312 piix_chip_map(sc, pa) 1313 struct pciide_softc *sc; 1314 struct pci_attach_args *pa; 1315 { 1316 struct pciide_channel *cp; 1317 int channel; 1318 u_int32_t idetim; 1319 bus_size_t cmdsize, ctlsize; 1320 1321 if (pciide_chipen(sc, pa) == 0) 1322 return; 1323 1324 printf("%s: bus-master DMA support present", 1325 sc->sc_wdcdev.sc_dev.dv_xname); 1326 pciide_mapreg_dma(sc, pa); 1327 printf("\n"); 1328 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1329 WDC_CAPABILITY_MODE; 1330 if (sc->sc_dma_ok) { 1331 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1332 sc->sc_wdcdev.irqack = pciide_irqack; 1333 switch(sc->sc_pp->ide_product) { 1334 case PCI_PRODUCT_INTEL_82371AB_IDE: 1335 case PCI_PRODUCT_INTEL_82440MX_IDE: 1336 case PCI_PRODUCT_INTEL_82801AA_IDE: 1337 case PCI_PRODUCT_INTEL_82801AB_IDE: 1338 case PCI_PRODUCT_INTEL_82801BA_IDE: 1339 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1340 } 1341 } 1342 sc->sc_wdcdev.PIO_cap = 4; 1343 sc->sc_wdcdev.DMA_cap = 2; 1344 switch(sc->sc_pp->ide_product) { 1345 case PCI_PRODUCT_INTEL_82801AA_IDE: 1346 sc->sc_wdcdev.UDMA_cap = 4; 1347 break; 1348 case PCI_PRODUCT_INTEL_82801BA_IDE: 1349 sc->sc_wdcdev.UDMA_cap = 5; 1350 break; 1351 default: 1352 sc->sc_wdcdev.UDMA_cap = 2; 1353 } 1354 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1355 sc->sc_wdcdev.set_modes = piix_setup_channel; 1356 else 1357 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1358 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1359 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1360 1361 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1362 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1363 DEBUG_PROBE); 1364 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1365 WDCDEBUG_PRINT((", sidetim=0x%x", 1366 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1367 DEBUG_PROBE); 1368 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1369 WDCDEBUG_PRINT((", udamreg 0x%x", 1370 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1371 DEBUG_PROBE); 1372 } 1373 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1374 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1375 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) { 1376 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1377 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1378 DEBUG_PROBE); 1379 } 1380 1381 } 1382 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1383 1384 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1385 cp = &sc->pciide_channels[channel]; 1386 /* PIIX is compat-only */ 1387 if (pciide_chansetup(sc, channel, 0) == 0) 1388 continue; 1389 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1390 if ((PIIX_IDETIM_READ(idetim, channel) & 1391 PIIX_IDETIM_IDE) == 0) { 1392 printf("%s: %s channel ignored (disabled)\n", 1393 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1394 continue; 1395 } 1396 /* PIIX are compat-only pciide devices */ 1397 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1398 if (cp->hw_ok == 0) 1399 continue; 1400 if (pciide_chan_candisable(cp)) { 1401 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1402 channel); 1403 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1404 idetim); 1405 } 1406 pciide_map_compat_intr(pa, cp, channel, 0); 1407 if (cp->hw_ok == 0) 1408 continue; 1409 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1410 } 1411 1412 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1413 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1414 DEBUG_PROBE); 1415 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1416 WDCDEBUG_PRINT((", sidetim=0x%x", 1417 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1418 DEBUG_PROBE); 1419 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1420 WDCDEBUG_PRINT((", udamreg 0x%x", 1421 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1422 DEBUG_PROBE); 1423 } 1424 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1425 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE 1426 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) { 1427 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1428 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1429 DEBUG_PROBE); 1430 } 1431 } 1432 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1433 } 1434 1435 void 1436 piix_setup_channel(chp) 1437 struct channel_softc *chp; 1438 { 1439 u_int8_t mode[2], drive; 1440 u_int32_t oidetim, idetim, idedma_ctl; 1441 struct pciide_channel *cp = (struct pciide_channel*)chp; 1442 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1443 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1444 1445 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1446 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1447 idedma_ctl = 0; 1448 1449 /* set up new idetim: Enable IDE registers decode */ 1450 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1451 chp->channel); 1452 1453 /* setup DMA */ 1454 pciide_channel_dma_setup(cp); 1455 1456 /* 1457 * Here we have to mess up with drives mode: PIIX can't have 1458 * different timings for master and slave drives. 1459 * We need to find the best combination. 1460 */ 1461 1462 /* If both drives supports DMA, take the lower mode */ 1463 if ((drvp[0].drive_flags & DRIVE_DMA) && 1464 (drvp[1].drive_flags & DRIVE_DMA)) { 1465 mode[0] = mode[1] = 1466 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1467 drvp[0].DMA_mode = mode[0]; 1468 drvp[1].DMA_mode = mode[1]; 1469 goto ok; 1470 } 1471 /* 1472 * If only one drive supports DMA, use its mode, and 1473 * put the other one in PIO mode 0 if mode not compatible 1474 */ 1475 if (drvp[0].drive_flags & DRIVE_DMA) { 1476 mode[0] = drvp[0].DMA_mode; 1477 mode[1] = drvp[1].PIO_mode; 1478 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1479 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1480 mode[1] = drvp[1].PIO_mode = 0; 1481 goto ok; 1482 } 1483 if (drvp[1].drive_flags & DRIVE_DMA) { 1484 mode[1] = drvp[1].DMA_mode; 1485 mode[0] = drvp[0].PIO_mode; 1486 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1487 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1488 mode[0] = drvp[0].PIO_mode = 0; 1489 goto ok; 1490 } 1491 /* 1492 * If both drives are not DMA, takes the lower mode, unless 1493 * one of them is PIO mode < 2 1494 */ 1495 if (drvp[0].PIO_mode < 2) { 1496 mode[0] = drvp[0].PIO_mode = 0; 1497 mode[1] = drvp[1].PIO_mode; 1498 } else if (drvp[1].PIO_mode < 2) { 1499 mode[1] = drvp[1].PIO_mode = 0; 1500 mode[0] = drvp[0].PIO_mode; 1501 } else { 1502 mode[0] = mode[1] = 1503 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1504 drvp[0].PIO_mode = mode[0]; 1505 drvp[1].PIO_mode = mode[1]; 1506 } 1507 ok: /* The modes are setup */ 1508 for (drive = 0; drive < 2; drive++) { 1509 if (drvp[drive].drive_flags & DRIVE_DMA) { 1510 idetim |= piix_setup_idetim_timings( 1511 mode[drive], 1, chp->channel); 1512 goto end; 1513 } 1514 } 1515 /* If we are there, none of the drives are DMA */ 1516 if (mode[0] >= 2) 1517 idetim |= piix_setup_idetim_timings( 1518 mode[0], 0, chp->channel); 1519 else 1520 idetim |= piix_setup_idetim_timings( 1521 mode[1], 0, chp->channel); 1522 end: /* 1523 * timing mode is now set up in the controller. Enable 1524 * it per-drive 1525 */ 1526 for (drive = 0; drive < 2; drive++) { 1527 /* If no drive, skip */ 1528 if ((drvp[drive].drive_flags & DRIVE) == 0) 1529 continue; 1530 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1531 if (drvp[drive].drive_flags & DRIVE_DMA) 1532 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1533 } 1534 if (idedma_ctl != 0) { 1535 /* Add software bits in status register */ 1536 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1537 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1538 idedma_ctl); 1539 } 1540 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1541 pciide_print_modes(cp); 1542 } 1543 1544 void 1545 piix3_4_setup_channel(chp) 1546 struct channel_softc *chp; 1547 { 1548 struct ata_drive_datas *drvp; 1549 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1550 struct pciide_channel *cp = (struct pciide_channel*)chp; 1551 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1552 int drive; 1553 int channel = chp->channel; 1554 1555 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1556 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1557 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1558 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1559 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1560 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1561 PIIX_SIDETIM_RTC_MASK(channel)); 1562 1563 idedma_ctl = 0; 1564 /* If channel disabled, no need to go further */ 1565 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1566 return; 1567 /* set up new idetim: Enable IDE registers decode */ 1568 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1569 1570 /* setup DMA if needed */ 1571 pciide_channel_dma_setup(cp); 1572 1573 for (drive = 0; drive < 2; drive++) { 1574 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1575 PIIX_UDMATIM_SET(0x3, channel, drive)); 1576 drvp = &chp->ch_drive[drive]; 1577 /* If no drive, skip */ 1578 if ((drvp->drive_flags & DRIVE) == 0) 1579 continue; 1580 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1581 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1582 goto pio; 1583 1584 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1585 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1586 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) { 1587 ideconf |= PIIX_CONFIG_PINGPONG; 1588 } 1589 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) { 1590 /* setup Ultra/100 */ 1591 if (drvp->UDMA_mode > 2 && 1592 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1593 drvp->UDMA_mode = 2; 1594 if (drvp->UDMA_mode > 4) { 1595 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1596 } else { 1597 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1598 if (drvp->UDMA_mode > 2) { 1599 ideconf |= PIIX_CONFIG_UDMA66(channel, 1600 drive); 1601 } else { 1602 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1603 drive); 1604 } 1605 } 1606 } 1607 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1608 /* setup Ultra/66 */ 1609 if (drvp->UDMA_mode > 2 && 1610 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1611 drvp->UDMA_mode = 2; 1612 if (drvp->UDMA_mode > 2) 1613 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1614 else 1615 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1616 } 1617 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1618 (drvp->drive_flags & DRIVE_UDMA)) { 1619 /* use Ultra/DMA */ 1620 drvp->drive_flags &= ~DRIVE_DMA; 1621 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1622 udmareg |= PIIX_UDMATIM_SET( 1623 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1624 } else { 1625 /* use Multiword DMA */ 1626 drvp->drive_flags &= ~DRIVE_UDMA; 1627 if (drive == 0) { 1628 idetim |= piix_setup_idetim_timings( 1629 drvp->DMA_mode, 1, channel); 1630 } else { 1631 sidetim |= piix_setup_sidetim_timings( 1632 drvp->DMA_mode, 1, channel); 1633 idetim =PIIX_IDETIM_SET(idetim, 1634 PIIX_IDETIM_SITRE, channel); 1635 } 1636 } 1637 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1638 1639 pio: /* use PIO mode */ 1640 idetim |= piix_setup_idetim_drvs(drvp); 1641 if (drive == 0) { 1642 idetim |= piix_setup_idetim_timings( 1643 drvp->PIO_mode, 0, channel); 1644 } else { 1645 sidetim |= piix_setup_sidetim_timings( 1646 drvp->PIO_mode, 0, channel); 1647 idetim =PIIX_IDETIM_SET(idetim, 1648 PIIX_IDETIM_SITRE, channel); 1649 } 1650 } 1651 if (idedma_ctl != 0) { 1652 /* Add software bits in status register */ 1653 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1654 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1655 idedma_ctl); 1656 } 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1658 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1659 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1661 pciide_print_modes(cp); 1662 } 1663 1664 1665 /* setup ISP and RTC fields, based on mode */ 1666 static u_int32_t 1667 piix_setup_idetim_timings(mode, dma, channel) 1668 u_int8_t mode; 1669 u_int8_t dma; 1670 u_int8_t channel; 1671 { 1672 1673 if (dma) 1674 return PIIX_IDETIM_SET(0, 1675 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1676 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1677 channel); 1678 else 1679 return PIIX_IDETIM_SET(0, 1680 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1681 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1682 channel); 1683 } 1684 1685 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1686 static u_int32_t 1687 piix_setup_idetim_drvs(drvp) 1688 struct ata_drive_datas *drvp; 1689 { 1690 u_int32_t ret = 0; 1691 struct channel_softc *chp = drvp->chnl_softc; 1692 u_int8_t channel = chp->channel; 1693 u_int8_t drive = drvp->drive; 1694 1695 /* 1696 * If drive is using UDMA, timings setups are independant 1697 * So just check DMA and PIO here. 1698 */ 1699 if (drvp->drive_flags & DRIVE_DMA) { 1700 /* if mode = DMA mode 0, use compatible timings */ 1701 if ((drvp->drive_flags & DRIVE_DMA) && 1702 drvp->DMA_mode == 0) { 1703 drvp->PIO_mode = 0; 1704 return ret; 1705 } 1706 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1707 /* 1708 * PIO and DMA timings are the same, use fast timings for PIO 1709 * too, else use compat timings. 1710 */ 1711 if ((piix_isp_pio[drvp->PIO_mode] != 1712 piix_isp_dma[drvp->DMA_mode]) || 1713 (piix_rtc_pio[drvp->PIO_mode] != 1714 piix_rtc_dma[drvp->DMA_mode])) 1715 drvp->PIO_mode = 0; 1716 /* if PIO mode <= 2, use compat timings for PIO */ 1717 if (drvp->PIO_mode <= 2) { 1718 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1719 channel); 1720 return ret; 1721 } 1722 } 1723 1724 /* 1725 * Now setup PIO modes. If mode < 2, use compat timings. 1726 * Else enable fast timings. Enable IORDY and prefetch/post 1727 * if PIO mode >= 3. 1728 */ 1729 1730 if (drvp->PIO_mode < 2) 1731 return ret; 1732 1733 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1734 if (drvp->PIO_mode >= 3) { 1735 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1736 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1737 } 1738 return ret; 1739 } 1740 1741 /* setup values in SIDETIM registers, based on mode */ 1742 static u_int32_t 1743 piix_setup_sidetim_timings(mode, dma, channel) 1744 u_int8_t mode; 1745 u_int8_t dma; 1746 u_int8_t channel; 1747 { 1748 if (dma) 1749 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1750 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1751 else 1752 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1753 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1754 } 1755 1756 void 1757 amd756_chip_map(sc, pa) 1758 struct pciide_softc *sc; 1759 struct pci_attach_args *pa; 1760 { 1761 struct pciide_channel *cp; 1762 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1763 int channel; 1764 pcireg_t chanenable; 1765 bus_size_t cmdsize, ctlsize; 1766 1767 if (pciide_chipen(sc, pa) == 0) 1768 return; 1769 printf("%s: bus-master DMA support present", 1770 sc->sc_wdcdev.sc_dev.dv_xname); 1771 pciide_mapreg_dma(sc, pa); 1772 printf("\n"); 1773 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1774 WDC_CAPABILITY_MODE; 1775 if (sc->sc_dma_ok) { 1776 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1777 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1778 sc->sc_wdcdev.irqack = pciide_irqack; 1779 } 1780 sc->sc_wdcdev.PIO_cap = 4; 1781 sc->sc_wdcdev.DMA_cap = 2; 1782 sc->sc_wdcdev.UDMA_cap = 4; 1783 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1784 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1785 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1786 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1787 1788 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1789 DEBUG_PROBE); 1790 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1791 cp = &sc->pciide_channels[channel]; 1792 if (pciide_chansetup(sc, channel, interface) == 0) 1793 continue; 1794 1795 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1796 printf("%s: %s channel ignored (disabled)\n", 1797 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1798 continue; 1799 } 1800 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1801 pciide_pci_intr); 1802 1803 if (pciide_chan_candisable(cp)) 1804 chanenable &= ~AMD756_CHAN_EN(channel); 1805 pciide_map_compat_intr(pa, cp, channel, interface); 1806 if (cp->hw_ok == 0) 1807 continue; 1808 1809 amd756_setup_channel(&cp->wdc_channel); 1810 } 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1812 chanenable); 1813 return; 1814 } 1815 1816 void 1817 amd756_setup_channel(chp) 1818 struct channel_softc *chp; 1819 { 1820 u_int32_t udmatim_reg, datatim_reg; 1821 u_int8_t idedma_ctl; 1822 int mode, drive; 1823 struct ata_drive_datas *drvp; 1824 struct pciide_channel *cp = (struct pciide_channel*)chp; 1825 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1826 #ifndef PCIIDE_AMD756_ENABLEDMA 1827 int rev = PCI_REVISION( 1828 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1829 #endif 1830 1831 idedma_ctl = 0; 1832 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1833 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1834 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1835 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1836 1837 /* setup DMA if needed */ 1838 pciide_channel_dma_setup(cp); 1839 1840 for (drive = 0; drive < 2; drive++) { 1841 drvp = &chp->ch_drive[drive]; 1842 /* If no drive, skip */ 1843 if ((drvp->drive_flags & DRIVE) == 0) 1844 continue; 1845 /* add timing values, setup DMA if needed */ 1846 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1847 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1848 mode = drvp->PIO_mode; 1849 goto pio; 1850 } 1851 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1852 (drvp->drive_flags & DRIVE_UDMA)) { 1853 /* use Ultra/DMA */ 1854 drvp->drive_flags &= ~DRIVE_DMA; 1855 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1856 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1857 AMD756_UDMA_TIME(chp->channel, drive, 1858 amd756_udma_tim[drvp->UDMA_mode]); 1859 /* can use PIO timings, MW DMA unused */ 1860 mode = drvp->PIO_mode; 1861 } else { 1862 /* use Multiword DMA, but only if revision is OK */ 1863 drvp->drive_flags &= ~DRIVE_UDMA; 1864 #ifndef PCIIDE_AMD756_ENABLEDMA 1865 /* 1866 * The workaround doesn't seem to be necessary 1867 * with all drives, so it can be disabled by 1868 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1869 * triggered. 1870 */ 1871 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1872 printf("%s:%d:%d: multi-word DMA disabled due " 1873 "to chip revision\n", 1874 sc->sc_wdcdev.sc_dev.dv_xname, 1875 chp->channel, drive); 1876 mode = drvp->PIO_mode; 1877 drvp->drive_flags &= ~DRIVE_DMA; 1878 goto pio; 1879 } 1880 #endif 1881 /* mode = min(pio, dma+2) */ 1882 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1883 mode = drvp->PIO_mode; 1884 else 1885 mode = drvp->DMA_mode + 2; 1886 } 1887 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1888 1889 pio: /* setup PIO mode */ 1890 if (mode <= 2) { 1891 drvp->DMA_mode = 0; 1892 drvp->PIO_mode = 0; 1893 mode = 0; 1894 } else { 1895 drvp->PIO_mode = mode; 1896 drvp->DMA_mode = mode - 2; 1897 } 1898 datatim_reg |= 1899 AMD756_DATATIM_PULSE(chp->channel, drive, 1900 amd756_pio_set[mode]) | 1901 AMD756_DATATIM_RECOV(chp->channel, drive, 1902 amd756_pio_rec[mode]); 1903 } 1904 if (idedma_ctl != 0) { 1905 /* Add software bits in status register */ 1906 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1907 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1908 idedma_ctl); 1909 } 1910 pciide_print_modes(cp); 1911 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1912 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1913 } 1914 1915 void 1916 apollo_chip_map(sc, pa) 1917 struct pciide_softc *sc; 1918 struct pci_attach_args *pa; 1919 { 1920 struct pciide_channel *cp; 1921 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1922 int rev = PCI_REVISION(pa->pa_class); 1923 int channel; 1924 u_int32_t ideconf; 1925 bus_size_t cmdsize, ctlsize; 1926 1927 if (pciide_chipen(sc, pa) == 0) 1928 return; 1929 printf("%s: bus-master DMA support present", 1930 sc->sc_wdcdev.sc_dev.dv_xname); 1931 pciide_mapreg_dma(sc, pa); 1932 printf("\n"); 1933 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1934 WDC_CAPABILITY_MODE; 1935 if (sc->sc_dma_ok) { 1936 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1937 sc->sc_wdcdev.irqack = pciide_irqack; 1938 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE 1939 && rev >= 6) 1940 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1941 } 1942 sc->sc_wdcdev.PIO_cap = 4; 1943 sc->sc_wdcdev.DMA_cap = 2; 1944 sc->sc_wdcdev.UDMA_cap = 2; 1945 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1946 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1947 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1948 1949 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1950 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1951 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1952 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1953 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1954 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1955 DEBUG_PROBE); 1956 1957 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1958 cp = &sc->pciide_channels[channel]; 1959 if (pciide_chansetup(sc, channel, interface) == 0) 1960 continue; 1961 1962 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1963 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1964 printf("%s: %s channel ignored (disabled)\n", 1965 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1966 continue; 1967 } 1968 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1969 pciide_pci_intr); 1970 if (cp->hw_ok == 0) 1971 continue; 1972 if (pciide_chan_candisable(cp)) { 1973 ideconf &= ~APO_IDECONF_EN(channel); 1974 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1975 ideconf); 1976 } 1977 pciide_map_compat_intr(pa, cp, channel, interface); 1978 1979 if (cp->hw_ok == 0) 1980 continue; 1981 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1982 } 1983 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1984 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1985 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1986 } 1987 1988 void 1989 apollo_setup_channel(chp) 1990 struct channel_softc *chp; 1991 { 1992 u_int32_t udmatim_reg, datatim_reg; 1993 u_int8_t idedma_ctl; 1994 int mode, drive; 1995 struct ata_drive_datas *drvp; 1996 struct pciide_channel *cp = (struct pciide_channel*)chp; 1997 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1998 1999 idedma_ctl = 0; 2000 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2001 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2002 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2003 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2004 2005 /* setup DMA if needed */ 2006 pciide_channel_dma_setup(cp); 2007 2008 for (drive = 0; drive < 2; drive++) { 2009 drvp = &chp->ch_drive[drive]; 2010 /* If no drive, skip */ 2011 if ((drvp->drive_flags & DRIVE) == 0) 2012 continue; 2013 /* add timing values, setup DMA if needed */ 2014 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2015 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2016 mode = drvp->PIO_mode; 2017 goto pio; 2018 } 2019 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2020 (drvp->drive_flags & DRIVE_UDMA)) { 2021 /* use Ultra/DMA */ 2022 drvp->drive_flags &= ~DRIVE_DMA; 2023 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2024 APO_UDMA_EN_MTH(chp->channel, drive) | 2025 APO_UDMA_TIME(chp->channel, drive, 2026 apollo_udma_tim[drvp->UDMA_mode]); 2027 /* can use PIO timings, MW DMA unused */ 2028 mode = drvp->PIO_mode; 2029 } else { 2030 /* use Multiword DMA */ 2031 drvp->drive_flags &= ~DRIVE_UDMA; 2032 /* mode = min(pio, dma+2) */ 2033 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2034 mode = drvp->PIO_mode; 2035 else 2036 mode = drvp->DMA_mode + 2; 2037 } 2038 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2039 2040 pio: /* setup PIO mode */ 2041 if (mode <= 2) { 2042 drvp->DMA_mode = 0; 2043 drvp->PIO_mode = 0; 2044 mode = 0; 2045 } else { 2046 drvp->PIO_mode = mode; 2047 drvp->DMA_mode = mode - 2; 2048 } 2049 datatim_reg |= 2050 APO_DATATIM_PULSE(chp->channel, drive, 2051 apollo_pio_set[mode]) | 2052 APO_DATATIM_RECOV(chp->channel, drive, 2053 apollo_pio_rec[mode]); 2054 } 2055 if (idedma_ctl != 0) { 2056 /* Add software bits in status register */ 2057 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2058 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2059 idedma_ctl); 2060 } 2061 pciide_print_modes(cp); 2062 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2063 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2064 } 2065 2066 void 2067 cmd_channel_map(pa, sc, channel) 2068 struct pci_attach_args *pa; 2069 struct pciide_softc *sc; 2070 int channel; 2071 { 2072 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2073 bus_size_t cmdsize, ctlsize; 2074 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2075 int interface; 2076 2077 /* 2078 * The 0648/0649 can be told to identify as a RAID controller. 2079 * In this case, we have to fake interface 2080 */ 2081 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2082 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2083 PCIIDE_INTERFACE_SETTABLE(1); 2084 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2085 CMD_CONF_DSA1) 2086 interface |= PCIIDE_INTERFACE_PCI(0) | 2087 PCIIDE_INTERFACE_PCI(1); 2088 } else { 2089 interface = PCI_INTERFACE(pa->pa_class); 2090 } 2091 2092 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2093 cp->name = PCIIDE_CHANNEL_NAME(channel); 2094 cp->wdc_channel.channel = channel; 2095 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2096 2097 if (channel > 0) { 2098 cp->wdc_channel.ch_queue = 2099 sc->pciide_channels[0].wdc_channel.ch_queue; 2100 } else { 2101 cp->wdc_channel.ch_queue = 2102 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2103 } 2104 if (cp->wdc_channel.ch_queue == NULL) { 2105 printf("%s %s channel: " 2106 "can't allocate memory for command queue", 2107 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2108 return; 2109 } 2110 2111 printf("%s: %s channel %s to %s mode\n", 2112 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2113 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2114 "configured" : "wired", 2115 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2116 "native-PCI" : "compatibility"); 2117 2118 /* 2119 * with a CMD PCI64x, if we get here, the first channel is enabled: 2120 * there's no way to disable the first channel without disabling 2121 * the whole device 2122 */ 2123 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2124 printf("%s: %s channel ignored (disabled)\n", 2125 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2126 return; 2127 } 2128 2129 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2130 if (cp->hw_ok == 0) 2131 return; 2132 if (channel == 1) { 2133 if (pciide_chan_candisable(cp)) { 2134 ctrl &= ~CMD_CTRL_2PORT; 2135 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2136 CMD_CTRL, ctrl); 2137 } 2138 } 2139 pciide_map_compat_intr(pa, cp, channel, interface); 2140 } 2141 2142 int 2143 cmd_pci_intr(arg) 2144 void *arg; 2145 { 2146 struct pciide_softc *sc = arg; 2147 struct pciide_channel *cp; 2148 struct channel_softc *wdc_cp; 2149 int i, rv, crv; 2150 u_int32_t priirq, secirq; 2151 2152 rv = 0; 2153 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2154 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2155 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2156 cp = &sc->pciide_channels[i]; 2157 wdc_cp = &cp->wdc_channel; 2158 /* If a compat channel skip. */ 2159 if (cp->compat) 2160 continue; 2161 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2162 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2163 crv = wdcintr(wdc_cp); 2164 if (crv == 0) 2165 printf("%s:%d: bogus intr\n", 2166 sc->sc_wdcdev.sc_dev.dv_xname, i); 2167 else 2168 rv = 1; 2169 } 2170 } 2171 return rv; 2172 } 2173 2174 void 2175 cmd_chip_map(sc, pa) 2176 struct pciide_softc *sc; 2177 struct pci_attach_args *pa; 2178 { 2179 int channel; 2180 2181 /* 2182 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2183 * and base adresses registers can be disabled at 2184 * hardware level. In this case, the device is wired 2185 * in compat mode and its first channel is always enabled, 2186 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2187 * In fact, it seems that the first channel of the CMD PCI0640 2188 * can't be disabled. 2189 */ 2190 2191 #ifdef PCIIDE_CMD064x_DISABLE 2192 if (pciide_chipen(sc, pa) == 0) 2193 return; 2194 #endif 2195 2196 printf("%s: hardware does not support DMA\n", 2197 sc->sc_wdcdev.sc_dev.dv_xname); 2198 sc->sc_dma_ok = 0; 2199 2200 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2201 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2202 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2203 2204 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2205 cmd_channel_map(pa, sc, channel); 2206 } 2207 } 2208 2209 void 2210 cmd0643_9_chip_map(sc, pa) 2211 struct pciide_softc *sc; 2212 struct pci_attach_args *pa; 2213 { 2214 struct pciide_channel *cp; 2215 int channel; 2216 int rev = PCI_REVISION( 2217 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2218 2219 /* 2220 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2221 * and base adresses registers can be disabled at 2222 * hardware level. In this case, the device is wired 2223 * in compat mode and its first channel is always enabled, 2224 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2225 * In fact, it seems that the first channel of the CMD PCI0640 2226 * can't be disabled. 2227 */ 2228 2229 #ifdef PCIIDE_CMD064x_DISABLE 2230 if (pciide_chipen(sc, pa) == 0) 2231 return; 2232 #endif 2233 printf("%s: bus-master DMA support present", 2234 sc->sc_wdcdev.sc_dev.dv_xname); 2235 pciide_mapreg_dma(sc, pa); 2236 printf("\n"); 2237 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2238 WDC_CAPABILITY_MODE; 2239 if (sc->sc_dma_ok) { 2240 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2241 switch (sc->sc_pp->ide_product) { 2242 case PCI_PRODUCT_CMDTECH_649: 2243 case PCI_PRODUCT_CMDTECH_648: 2244 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2245 sc->sc_wdcdev.UDMA_cap = 4; 2246 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2247 break; 2248 case PCI_PRODUCT_CMDTECH_646: 2249 if (rev >= CMD0646U2_REV) { 2250 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2251 sc->sc_wdcdev.UDMA_cap = 2; 2252 } else if (rev >= CMD0646U_REV) { 2253 /* 2254 * Linux's driver claims that the 646U is broken 2255 * with UDMA. Only enable it if we know what we're 2256 * doing 2257 */ 2258 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2259 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2260 sc->sc_wdcdev.UDMA_cap = 2; 2261 #endif 2262 /* explicitely disable UDMA */ 2263 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2264 CMD_UDMATIM(0), 0); 2265 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2266 CMD_UDMATIM(1), 0); 2267 } 2268 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2269 break; 2270 default: 2271 sc->sc_wdcdev.irqack = pciide_irqack; 2272 } 2273 } 2274 2275 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2276 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2277 sc->sc_wdcdev.PIO_cap = 4; 2278 sc->sc_wdcdev.DMA_cap = 2; 2279 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2280 2281 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2282 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2283 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2284 DEBUG_PROBE); 2285 2286 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2287 cp = &sc->pciide_channels[channel]; 2288 cmd_channel_map(pa, sc, channel); 2289 if (cp->hw_ok == 0) 2290 continue; 2291 cmd0643_9_setup_channel(&cp->wdc_channel); 2292 } 2293 /* 2294 * note - this also makes sure we clear the irq disable and reset 2295 * bits 2296 */ 2297 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2298 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2299 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2300 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2301 DEBUG_PROBE); 2302 } 2303 2304 void 2305 cmd0643_9_setup_channel(chp) 2306 struct channel_softc *chp; 2307 { 2308 struct ata_drive_datas *drvp; 2309 u_int8_t tim; 2310 u_int32_t idedma_ctl, udma_reg; 2311 int drive; 2312 struct pciide_channel *cp = (struct pciide_channel*)chp; 2313 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2314 2315 idedma_ctl = 0; 2316 /* setup DMA if needed */ 2317 pciide_channel_dma_setup(cp); 2318 2319 for (drive = 0; drive < 2; drive++) { 2320 drvp = &chp->ch_drive[drive]; 2321 /* If no drive, skip */ 2322 if ((drvp->drive_flags & DRIVE) == 0) 2323 continue; 2324 /* add timing values, setup DMA if needed */ 2325 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2326 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2327 if (drvp->drive_flags & DRIVE_UDMA) { 2328 /* UltraDMA on a 646U2, 0648 or 0649 */ 2329 drvp->drive_flags &= ~DRIVE_DMA; 2330 udma_reg = pciide_pci_read(sc->sc_pc, 2331 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2332 if (drvp->UDMA_mode > 2 && 2333 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2334 CMD_BICSR) & 2335 CMD_BICSR_80(chp->channel)) == 0) 2336 drvp->UDMA_mode = 2; 2337 if (drvp->UDMA_mode > 2) 2338 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2339 else if (sc->sc_wdcdev.UDMA_cap > 2) 2340 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2341 udma_reg |= CMD_UDMATIM_UDMA(drive); 2342 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2343 CMD_UDMATIM_TIM_OFF(drive)); 2344 udma_reg |= 2345 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2346 CMD_UDMATIM_TIM_OFF(drive)); 2347 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2348 CMD_UDMATIM(chp->channel), udma_reg); 2349 } else { 2350 /* 2351 * use Multiword DMA. 2352 * Timings will be used for both PIO and DMA, 2353 * so adjust DMA mode if needed 2354 * if we have a 0646U2/8/9, turn off UDMA 2355 */ 2356 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2357 udma_reg = pciide_pci_read(sc->sc_pc, 2358 sc->sc_tag, 2359 CMD_UDMATIM(chp->channel)); 2360 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2361 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2362 CMD_UDMATIM(chp->channel), 2363 udma_reg); 2364 } 2365 if (drvp->PIO_mode >= 3 && 2366 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2367 drvp->DMA_mode = drvp->PIO_mode - 2; 2368 } 2369 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2370 } 2371 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2372 } 2373 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2374 CMD_DATA_TIM(chp->channel, drive), tim); 2375 } 2376 if (idedma_ctl != 0) { 2377 /* Add software bits in status register */ 2378 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2379 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2380 idedma_ctl); 2381 } 2382 pciide_print_modes(cp); 2383 } 2384 2385 void 2386 cmd646_9_irqack(chp) 2387 struct channel_softc *chp; 2388 { 2389 u_int32_t priirq, secirq; 2390 struct pciide_channel *cp = (struct pciide_channel*)chp; 2391 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2392 2393 if (chp->channel == 0) { 2394 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2395 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2396 } else { 2397 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2398 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2399 } 2400 pciide_irqack(chp); 2401 } 2402 2403 void 2404 cy693_chip_map(sc, pa) 2405 struct pciide_softc *sc; 2406 struct pci_attach_args *pa; 2407 { 2408 struct pciide_channel *cp; 2409 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2410 bus_size_t cmdsize, ctlsize; 2411 2412 if (pciide_chipen(sc, pa) == 0) 2413 return; 2414 /* 2415 * this chip has 2 PCI IDE functions, one for primary and one for 2416 * secondary. So we need to call pciide_mapregs_compat() with 2417 * the real channel 2418 */ 2419 if (pa->pa_function == 1) { 2420 sc->sc_cy_compatchan = 0; 2421 } else if (pa->pa_function == 2) { 2422 sc->sc_cy_compatchan = 1; 2423 } else { 2424 printf("%s: unexpected PCI function %d\n", 2425 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2426 return; 2427 } 2428 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2429 printf("%s: bus-master DMA support present", 2430 sc->sc_wdcdev.sc_dev.dv_xname); 2431 pciide_mapreg_dma(sc, pa); 2432 } else { 2433 printf("%s: hardware does not support DMA", 2434 sc->sc_wdcdev.sc_dev.dv_xname); 2435 sc->sc_dma_ok = 0; 2436 } 2437 printf("\n"); 2438 2439 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2440 if (sc->sc_cy_handle == NULL) { 2441 printf("%s: unable to map hyperCache control registers\n", 2442 sc->sc_wdcdev.sc_dev.dv_xname); 2443 sc->sc_dma_ok = 0; 2444 } 2445 2446 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2447 WDC_CAPABILITY_MODE; 2448 if (sc->sc_dma_ok) { 2449 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2450 sc->sc_wdcdev.irqack = pciide_irqack; 2451 } 2452 sc->sc_wdcdev.PIO_cap = 4; 2453 sc->sc_wdcdev.DMA_cap = 2; 2454 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2455 2456 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2457 sc->sc_wdcdev.nchannels = 1; 2458 2459 /* Only one channel for this chip; if we are here it's enabled */ 2460 cp = &sc->pciide_channels[0]; 2461 sc->wdc_chanarray[0] = &cp->wdc_channel; 2462 cp->name = PCIIDE_CHANNEL_NAME(0); 2463 cp->wdc_channel.channel = 0; 2464 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2465 cp->wdc_channel.ch_queue = 2466 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2467 if (cp->wdc_channel.ch_queue == NULL) { 2468 printf("%s primary channel: " 2469 "can't allocate memory for command queue", 2470 sc->sc_wdcdev.sc_dev.dv_xname); 2471 return; 2472 } 2473 printf("%s: primary channel %s to ", 2474 sc->sc_wdcdev.sc_dev.dv_xname, 2475 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2476 "configured" : "wired"); 2477 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2478 printf("native-PCI"); 2479 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2480 pciide_pci_intr); 2481 } else { 2482 printf("compatibility"); 2483 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2484 &cmdsize, &ctlsize); 2485 } 2486 printf(" mode\n"); 2487 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2488 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2489 wdcattach(&cp->wdc_channel); 2490 if (pciide_chan_candisable(cp)) { 2491 pci_conf_write(sc->sc_pc, sc->sc_tag, 2492 PCI_COMMAND_STATUS_REG, 0); 2493 } 2494 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2495 if (cp->hw_ok == 0) 2496 return; 2497 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2498 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2499 cy693_setup_channel(&cp->wdc_channel); 2500 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2501 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2502 } 2503 2504 void 2505 cy693_setup_channel(chp) 2506 struct channel_softc *chp; 2507 { 2508 struct ata_drive_datas *drvp; 2509 int drive; 2510 u_int32_t cy_cmd_ctrl; 2511 u_int32_t idedma_ctl; 2512 struct pciide_channel *cp = (struct pciide_channel*)chp; 2513 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2514 int dma_mode = -1; 2515 2516 cy_cmd_ctrl = idedma_ctl = 0; 2517 2518 /* setup DMA if needed */ 2519 pciide_channel_dma_setup(cp); 2520 2521 for (drive = 0; drive < 2; drive++) { 2522 drvp = &chp->ch_drive[drive]; 2523 /* If no drive, skip */ 2524 if ((drvp->drive_flags & DRIVE) == 0) 2525 continue; 2526 /* add timing values, setup DMA if needed */ 2527 if (drvp->drive_flags & DRIVE_DMA) { 2528 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2529 /* use Multiword DMA */ 2530 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2531 dma_mode = drvp->DMA_mode; 2532 } 2533 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2534 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2535 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2536 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2537 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2538 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2539 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2540 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2541 } 2542 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2543 chp->ch_drive[0].DMA_mode = dma_mode; 2544 chp->ch_drive[1].DMA_mode = dma_mode; 2545 2546 if (dma_mode == -1) 2547 dma_mode = 0; 2548 2549 if (sc->sc_cy_handle != NULL) { 2550 /* Note: `multiple' is implied. */ 2551 cy82c693_write(sc->sc_cy_handle, 2552 (sc->sc_cy_compatchan == 0) ? 2553 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2554 } 2555 2556 pciide_print_modes(cp); 2557 2558 if (idedma_ctl != 0) { 2559 /* Add software bits in status register */ 2560 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2561 IDEDMA_CTL, idedma_ctl); 2562 } 2563 } 2564 2565 void 2566 sis_chip_map(sc, pa) 2567 struct pciide_softc *sc; 2568 struct pci_attach_args *pa; 2569 { 2570 struct pciide_channel *cp; 2571 int channel; 2572 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2573 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2574 pcireg_t rev = PCI_REVISION(pa->pa_class); 2575 bus_size_t cmdsize, ctlsize; 2576 2577 if (pciide_chipen(sc, pa) == 0) 2578 return; 2579 printf("%s: bus-master DMA support present", 2580 sc->sc_wdcdev.sc_dev.dv_xname); 2581 pciide_mapreg_dma(sc, pa); 2582 printf("\n"); 2583 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2584 WDC_CAPABILITY_MODE; 2585 if (sc->sc_dma_ok) { 2586 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2587 sc->sc_wdcdev.irqack = pciide_irqack; 2588 if (rev > 0xd0) 2589 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2590 } 2591 2592 sc->sc_wdcdev.PIO_cap = 4; 2593 sc->sc_wdcdev.DMA_cap = 2; 2594 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2595 sc->sc_wdcdev.UDMA_cap = 2; 2596 sc->sc_wdcdev.set_modes = sis_setup_channel; 2597 2598 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2599 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2600 2601 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2602 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2603 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2604 2605 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2606 cp = &sc->pciide_channels[channel]; 2607 if (pciide_chansetup(sc, channel, interface) == 0) 2608 continue; 2609 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2610 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2611 printf("%s: %s channel ignored (disabled)\n", 2612 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2613 continue; 2614 } 2615 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2616 pciide_pci_intr); 2617 if (cp->hw_ok == 0) 2618 continue; 2619 if (pciide_chan_candisable(cp)) { 2620 if (channel == 0) 2621 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2622 else 2623 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2624 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2625 sis_ctr0); 2626 } 2627 pciide_map_compat_intr(pa, cp, channel, interface); 2628 if (cp->hw_ok == 0) 2629 continue; 2630 sis_setup_channel(&cp->wdc_channel); 2631 } 2632 } 2633 2634 void 2635 sis_setup_channel(chp) 2636 struct channel_softc *chp; 2637 { 2638 struct ata_drive_datas *drvp; 2639 int drive; 2640 u_int32_t sis_tim; 2641 u_int32_t idedma_ctl; 2642 struct pciide_channel *cp = (struct pciide_channel*)chp; 2643 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2644 2645 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2646 "channel %d 0x%x\n", chp->channel, 2647 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2648 DEBUG_PROBE); 2649 sis_tim = 0; 2650 idedma_ctl = 0; 2651 /* setup DMA if needed */ 2652 pciide_channel_dma_setup(cp); 2653 2654 for (drive = 0; drive < 2; drive++) { 2655 drvp = &chp->ch_drive[drive]; 2656 /* If no drive, skip */ 2657 if ((drvp->drive_flags & DRIVE) == 0) 2658 continue; 2659 /* add timing values, setup DMA if needed */ 2660 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2661 (drvp->drive_flags & DRIVE_UDMA) == 0) 2662 goto pio; 2663 2664 if (drvp->drive_flags & DRIVE_UDMA) { 2665 /* use Ultra/DMA */ 2666 drvp->drive_flags &= ~DRIVE_DMA; 2667 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2668 SIS_TIM_UDMA_TIME_OFF(drive); 2669 sis_tim |= SIS_TIM_UDMA_EN(drive); 2670 } else { 2671 /* 2672 * use Multiword DMA 2673 * Timings will be used for both PIO and DMA, 2674 * so adjust DMA mode if needed 2675 */ 2676 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2677 drvp->PIO_mode = drvp->DMA_mode + 2; 2678 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2679 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2680 drvp->PIO_mode - 2 : 0; 2681 if (drvp->DMA_mode == 0) 2682 drvp->PIO_mode = 0; 2683 } 2684 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2685 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2686 SIS_TIM_ACT_OFF(drive); 2687 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2688 SIS_TIM_REC_OFF(drive); 2689 } 2690 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2691 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2692 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2693 if (idedma_ctl != 0) { 2694 /* Add software bits in status register */ 2695 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2696 IDEDMA_CTL, idedma_ctl); 2697 } 2698 pciide_print_modes(cp); 2699 } 2700 2701 void 2702 acer_chip_map(sc, pa) 2703 struct pciide_softc *sc; 2704 struct pci_attach_args *pa; 2705 { 2706 struct pciide_channel *cp; 2707 int channel; 2708 pcireg_t cr, interface; 2709 bus_size_t cmdsize, ctlsize; 2710 2711 if (pciide_chipen(sc, pa) == 0) 2712 return; 2713 printf("%s: bus-master DMA support present", 2714 sc->sc_wdcdev.sc_dev.dv_xname); 2715 pciide_mapreg_dma(sc, pa); 2716 printf("\n"); 2717 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2718 WDC_CAPABILITY_MODE; 2719 if (sc->sc_dma_ok) { 2720 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2721 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2722 sc->sc_wdcdev.irqack = pciide_irqack; 2723 } 2724 2725 sc->sc_wdcdev.PIO_cap = 4; 2726 sc->sc_wdcdev.DMA_cap = 2; 2727 sc->sc_wdcdev.UDMA_cap = 2; 2728 sc->sc_wdcdev.set_modes = acer_setup_channel; 2729 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2730 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2731 2732 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2733 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2734 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2735 2736 /* Enable "microsoft register bits" R/W. */ 2737 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2738 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2739 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2740 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2741 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2742 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2743 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2744 ~ACER_CHANSTATUSREGS_RO); 2745 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2746 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2747 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2748 /* Don't use cr, re-read the real register content instead */ 2749 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2750 PCI_CLASS_REG)); 2751 2752 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2753 cp = &sc->pciide_channels[channel]; 2754 if (pciide_chansetup(sc, channel, interface) == 0) 2755 continue; 2756 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2757 printf("%s: %s channel ignored (disabled)\n", 2758 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2759 continue; 2760 } 2761 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2762 acer_pci_intr); 2763 if (cp->hw_ok == 0) 2764 continue; 2765 if (pciide_chan_candisable(cp)) { 2766 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2767 pci_conf_write(sc->sc_pc, sc->sc_tag, 2768 PCI_CLASS_REG, cr); 2769 } 2770 pciide_map_compat_intr(pa, cp, channel, interface); 2771 acer_setup_channel(&cp->wdc_channel); 2772 } 2773 } 2774 2775 void 2776 acer_setup_channel(chp) 2777 struct channel_softc *chp; 2778 { 2779 struct ata_drive_datas *drvp; 2780 int drive; 2781 u_int32_t acer_fifo_udma; 2782 u_int32_t idedma_ctl; 2783 struct pciide_channel *cp = (struct pciide_channel*)chp; 2784 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2785 2786 idedma_ctl = 0; 2787 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2788 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2789 acer_fifo_udma), DEBUG_PROBE); 2790 /* setup DMA if needed */ 2791 pciide_channel_dma_setup(cp); 2792 2793 for (drive = 0; drive < 2; drive++) { 2794 drvp = &chp->ch_drive[drive]; 2795 /* If no drive, skip */ 2796 if ((drvp->drive_flags & DRIVE) == 0) 2797 continue; 2798 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2799 "channel %d drive %d 0x%x\n", chp->channel, drive, 2800 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2801 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2802 /* clear FIFO/DMA mode */ 2803 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2804 ACER_UDMA_EN(chp->channel, drive) | 2805 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2806 2807 /* add timing values, setup DMA if needed */ 2808 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2809 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2810 acer_fifo_udma |= 2811 ACER_FTH_OPL(chp->channel, drive, 0x1); 2812 goto pio; 2813 } 2814 2815 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2816 if (drvp->drive_flags & DRIVE_UDMA) { 2817 /* use Ultra/DMA */ 2818 drvp->drive_flags &= ~DRIVE_DMA; 2819 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2820 acer_fifo_udma |= 2821 ACER_UDMA_TIM(chp->channel, drive, 2822 acer_udma[drvp->UDMA_mode]); 2823 } else { 2824 /* 2825 * use Multiword DMA 2826 * Timings will be used for both PIO and DMA, 2827 * so adjust DMA mode if needed 2828 */ 2829 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2830 drvp->PIO_mode = drvp->DMA_mode + 2; 2831 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2832 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2833 drvp->PIO_mode - 2 : 0; 2834 if (drvp->DMA_mode == 0) 2835 drvp->PIO_mode = 0; 2836 } 2837 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2838 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2839 ACER_IDETIM(chp->channel, drive), 2840 acer_pio[drvp->PIO_mode]); 2841 } 2842 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2843 acer_fifo_udma), DEBUG_PROBE); 2844 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2845 if (idedma_ctl != 0) { 2846 /* Add software bits in status register */ 2847 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2848 IDEDMA_CTL, idedma_ctl); 2849 } 2850 pciide_print_modes(cp); 2851 } 2852 2853 int 2854 acer_pci_intr(arg) 2855 void *arg; 2856 { 2857 struct pciide_softc *sc = arg; 2858 struct pciide_channel *cp; 2859 struct channel_softc *wdc_cp; 2860 int i, rv, crv; 2861 u_int32_t chids; 2862 2863 rv = 0; 2864 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2865 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2866 cp = &sc->pciide_channels[i]; 2867 wdc_cp = &cp->wdc_channel; 2868 /* If a compat channel skip. */ 2869 if (cp->compat) 2870 continue; 2871 if (chids & ACER_CHIDS_INT(i)) { 2872 crv = wdcintr(wdc_cp); 2873 if (crv == 0) 2874 printf("%s:%d: bogus intr\n", 2875 sc->sc_wdcdev.sc_dev.dv_xname, i); 2876 else 2877 rv = 1; 2878 } 2879 } 2880 return rv; 2881 } 2882 2883 void 2884 hpt_chip_map(sc, pa) 2885 struct pciide_softc *sc; 2886 struct pci_attach_args *pa; 2887 { 2888 struct pciide_channel *cp; 2889 int i, compatchan, revision; 2890 pcireg_t interface; 2891 bus_size_t cmdsize, ctlsize; 2892 2893 if (pciide_chipen(sc, pa) == 0) 2894 return; 2895 revision = PCI_REVISION(pa->pa_class); 2896 2897 /* 2898 * when the chip is in native mode it identifies itself as a 2899 * 'misc mass storage'. Fake interface in this case. 2900 */ 2901 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2902 interface = PCI_INTERFACE(pa->pa_class); 2903 } else { 2904 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2905 PCIIDE_INTERFACE_PCI(0); 2906 if (revision == HPT370_REV) 2907 interface |= PCIIDE_INTERFACE_PCI(1); 2908 } 2909 2910 printf("%s: bus-master DMA support present", 2911 sc->sc_wdcdev.sc_dev.dv_xname); 2912 pciide_mapreg_dma(sc, pa); 2913 printf("\n"); 2914 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2915 WDC_CAPABILITY_MODE; 2916 if (sc->sc_dma_ok) { 2917 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2918 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2919 sc->sc_wdcdev.irqack = pciide_irqack; 2920 } 2921 sc->sc_wdcdev.PIO_cap = 4; 2922 sc->sc_wdcdev.DMA_cap = 2; 2923 2924 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2925 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2926 if (revision == HPT366_REV) { 2927 sc->sc_wdcdev.UDMA_cap = 4; 2928 /* 2929 * The 366 has 2 PCI IDE functions, one for primary and one 2930 * for secondary. So we need to call pciide_mapregs_compat() 2931 * with the real channel 2932 */ 2933 if (pa->pa_function == 0) { 2934 compatchan = 0; 2935 } else if (pa->pa_function == 1) { 2936 compatchan = 1; 2937 } else { 2938 printf("%s: unexpected PCI function %d\n", 2939 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2940 return; 2941 } 2942 sc->sc_wdcdev.nchannels = 1; 2943 } else { 2944 sc->sc_wdcdev.nchannels = 2; 2945 sc->sc_wdcdev.UDMA_cap = 5; 2946 } 2947 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2948 cp = &sc->pciide_channels[i]; 2949 if (sc->sc_wdcdev.nchannels > 1) { 2950 compatchan = i; 2951 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2952 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2953 printf("%s: %s channel ignored (disabled)\n", 2954 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2955 continue; 2956 } 2957 } 2958 if (pciide_chansetup(sc, i, interface) == 0) 2959 continue; 2960 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2961 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2962 &ctlsize, hpt_pci_intr); 2963 } else { 2964 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2965 &cmdsize, &ctlsize); 2966 } 2967 if (cp->hw_ok == 0) 2968 return; 2969 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2970 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2971 wdcattach(&cp->wdc_channel); 2972 hpt_setup_channel(&cp->wdc_channel); 2973 } 2974 if (revision == HPT370_REV) { 2975 /* 2976 * HPT370_REV has a bit to disable interrupts, make sure 2977 * to clear it 2978 */ 2979 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2980 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2981 ~HPT_CSEL_IRQDIS); 2982 } 2983 return; 2984 } 2985 2986 void 2987 hpt_setup_channel(chp) 2988 struct channel_softc *chp; 2989 { 2990 struct ata_drive_datas *drvp; 2991 int drive; 2992 int cable; 2993 u_int32_t before, after; 2994 u_int32_t idedma_ctl; 2995 struct pciide_channel *cp = (struct pciide_channel*)chp; 2996 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2997 2998 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2999 3000 /* setup DMA if needed */ 3001 pciide_channel_dma_setup(cp); 3002 3003 idedma_ctl = 0; 3004 3005 /* Per drive settings */ 3006 for (drive = 0; drive < 2; drive++) { 3007 drvp = &chp->ch_drive[drive]; 3008 /* If no drive, skip */ 3009 if ((drvp->drive_flags & DRIVE) == 0) 3010 continue; 3011 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3012 HPT_IDETIM(chp->channel, drive)); 3013 3014 /* add timing values, setup DMA if needed */ 3015 if (drvp->drive_flags & DRIVE_UDMA) { 3016 /* use Ultra/DMA */ 3017 drvp->drive_flags &= ~DRIVE_DMA; 3018 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3019 drvp->UDMA_mode > 2) 3020 drvp->UDMA_mode = 2; 3021 after = (sc->sc_wdcdev.nchannels == 2) ? 3022 hpt370_udma[drvp->UDMA_mode] : 3023 hpt366_udma[drvp->UDMA_mode]; 3024 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3025 } else if (drvp->drive_flags & DRIVE_DMA) { 3026 /* 3027 * use Multiword DMA. 3028 * Timings will be used for both PIO and DMA, so adjust 3029 * DMA mode if needed 3030 */ 3031 if (drvp->PIO_mode >= 3 && 3032 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3033 drvp->DMA_mode = drvp->PIO_mode - 2; 3034 } 3035 after = (sc->sc_wdcdev.nchannels == 2) ? 3036 hpt370_dma[drvp->DMA_mode] : 3037 hpt366_dma[drvp->DMA_mode]; 3038 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3039 } else { 3040 /* PIO only */ 3041 after = (sc->sc_wdcdev.nchannels == 2) ? 3042 hpt370_pio[drvp->PIO_mode] : 3043 hpt366_pio[drvp->PIO_mode]; 3044 } 3045 pci_conf_write(sc->sc_pc, sc->sc_tag, 3046 HPT_IDETIM(chp->channel, drive), after); 3047 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3048 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3049 after, before), DEBUG_PROBE); 3050 } 3051 if (idedma_ctl != 0) { 3052 /* Add software bits in status register */ 3053 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3054 IDEDMA_CTL, idedma_ctl); 3055 } 3056 pciide_print_modes(cp); 3057 } 3058 3059 int 3060 hpt_pci_intr(arg) 3061 void *arg; 3062 { 3063 struct pciide_softc *sc = arg; 3064 struct pciide_channel *cp; 3065 struct channel_softc *wdc_cp; 3066 int rv = 0; 3067 int dmastat, i, crv; 3068 3069 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3070 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3071 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3072 if((dmastat & IDEDMA_CTL_INTR) == 0) 3073 continue; 3074 cp = &sc->pciide_channels[i]; 3075 wdc_cp = &cp->wdc_channel; 3076 crv = wdcintr(wdc_cp); 3077 if (crv == 0) { 3078 printf("%s:%d: bogus intr\n", 3079 sc->sc_wdcdev.sc_dev.dv_xname, i); 3080 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3081 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3082 } else 3083 rv = 1; 3084 } 3085 return rv; 3086 } 3087 3088 3089 /* A macro to test product */ 3090 #define PDC_IS_262(sc) \ 3091 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3092 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3093 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3094 3095 void 3096 pdc202xx_chip_map(sc, pa) 3097 struct pciide_softc *sc; 3098 struct pci_attach_args *pa; 3099 { 3100 struct pciide_channel *cp; 3101 int channel; 3102 pcireg_t interface, st, mode; 3103 bus_size_t cmdsize, ctlsize; 3104 3105 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3106 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3107 DEBUG_PROBE); 3108 if (pciide_chipen(sc, pa) == 0) 3109 return; 3110 3111 /* turn off RAID mode */ 3112 st &= ~PDC2xx_STATE_IDERAID; 3113 3114 /* 3115 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3116 * mode. We have to fake interface 3117 */ 3118 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3119 if (st & PDC2xx_STATE_NATIVE) 3120 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3121 3122 printf("%s: bus-master DMA support present", 3123 sc->sc_wdcdev.sc_dev.dv_xname); 3124 pciide_mapreg_dma(sc, pa); 3125 printf("\n"); 3126 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3127 WDC_CAPABILITY_MODE; 3128 if (sc->sc_dma_ok) { 3129 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3130 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3131 sc->sc_wdcdev.irqack = pciide_irqack; 3132 } 3133 sc->sc_wdcdev.PIO_cap = 4; 3134 sc->sc_wdcdev.DMA_cap = 2; 3135 if (PDC_IS_262(sc)) 3136 sc->sc_wdcdev.UDMA_cap = 4; 3137 else 3138 sc->sc_wdcdev.UDMA_cap = 2; 3139 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3140 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3141 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3142 3143 /* setup failsafe defaults */ 3144 mode = 0; 3145 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3146 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3147 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3148 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3149 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3150 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3151 "initial timings 0x%x, now 0x%x\n", channel, 3152 pci_conf_read(sc->sc_pc, sc->sc_tag, 3153 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3154 DEBUG_PROBE); 3155 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3156 mode | PDC2xx_TIM_IORDYp); 3157 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3158 "initial timings 0x%x, now 0x%x\n", channel, 3159 pci_conf_read(sc->sc_pc, sc->sc_tag, 3160 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3161 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3162 mode); 3163 } 3164 3165 mode = PDC2xx_SCR_DMA; 3166 if (PDC_IS_262(sc)) { 3167 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3168 } else { 3169 /* the BIOS set it up this way */ 3170 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3171 } 3172 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3173 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3174 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3175 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3176 DEBUG_PROBE); 3177 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3178 3179 /* controller initial state register is OK even without BIOS */ 3180 /* Set DMA mode to IDE DMA compatibility */ 3181 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3182 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3183 DEBUG_PROBE); 3184 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3185 mode | 0x1); 3186 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3187 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3188 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3189 mode | 0x1); 3190 3191 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3192 cp = &sc->pciide_channels[channel]; 3193 if (pciide_chansetup(sc, channel, interface) == 0) 3194 continue; 3195 if ((st & (PDC_IS_262(sc) ? 3196 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3197 printf("%s: %s channel ignored (disabled)\n", 3198 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3199 continue; 3200 } 3201 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3202 pdc202xx_pci_intr); 3203 if (cp->hw_ok == 0) 3204 continue; 3205 if (pciide_chan_candisable(cp)) 3206 st &= ~(PDC_IS_262(sc) ? 3207 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3208 pciide_map_compat_intr(pa, cp, channel, interface); 3209 pdc202xx_setup_channel(&cp->wdc_channel); 3210 } 3211 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3212 DEBUG_PROBE); 3213 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3214 return; 3215 } 3216 3217 void 3218 pdc202xx_setup_channel(chp) 3219 struct channel_softc *chp; 3220 { 3221 struct ata_drive_datas *drvp; 3222 int drive; 3223 pcireg_t mode, st; 3224 u_int32_t idedma_ctl, scr, atapi; 3225 struct pciide_channel *cp = (struct pciide_channel*)chp; 3226 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3227 int channel = chp->channel; 3228 3229 /* setup DMA if needed */ 3230 pciide_channel_dma_setup(cp); 3231 3232 idedma_ctl = 0; 3233 3234 /* Per channel settings */ 3235 if (PDC_IS_262(sc)) { 3236 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3237 PDC262_U66); 3238 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3239 /* Trimm UDMA mode */ 3240 if ((st & PDC262_STATE_80P(channel)) != 0 || 3241 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3242 chp->ch_drive[0].UDMA_mode <= 2) || 3243 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3244 chp->ch_drive[1].UDMA_mode <= 2)) { 3245 if (chp->ch_drive[0].UDMA_mode > 2) 3246 chp->ch_drive[0].UDMA_mode = 2; 3247 if (chp->ch_drive[1].UDMA_mode > 2) 3248 chp->ch_drive[1].UDMA_mode = 2; 3249 } 3250 /* Set U66 if needed */ 3251 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3252 chp->ch_drive[0].UDMA_mode > 2) || 3253 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3254 chp->ch_drive[1].UDMA_mode > 2)) 3255 scr |= PDC262_U66_EN(channel); 3256 else 3257 scr &= ~PDC262_U66_EN(channel); 3258 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3259 PDC262_U66, scr); 3260 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3261 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3262 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3263 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3264 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3265 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3266 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3267 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3268 atapi = 0; 3269 else 3270 atapi = PDC262_ATAPI_UDMA; 3271 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3272 PDC262_ATAPI(channel), atapi); 3273 } 3274 } 3275 for (drive = 0; drive < 2; drive++) { 3276 drvp = &chp->ch_drive[drive]; 3277 /* If no drive, skip */ 3278 if ((drvp->drive_flags & DRIVE) == 0) 3279 continue; 3280 mode = 0; 3281 if (drvp->drive_flags & DRIVE_UDMA) { 3282 /* use Ultra/DMA */ 3283 drvp->drive_flags &= ~DRIVE_DMA; 3284 mode = PDC2xx_TIM_SET_MB(mode, 3285 pdc2xx_udma_mb[drvp->UDMA_mode]); 3286 mode = PDC2xx_TIM_SET_MC(mode, 3287 pdc2xx_udma_mc[drvp->UDMA_mode]); 3288 drvp->drive_flags &= ~DRIVE_DMA; 3289 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3290 } else if (drvp->drive_flags & DRIVE_DMA) { 3291 mode = PDC2xx_TIM_SET_MB(mode, 3292 pdc2xx_dma_mb[drvp->DMA_mode]); 3293 mode = PDC2xx_TIM_SET_MC(mode, 3294 pdc2xx_dma_mc[drvp->DMA_mode]); 3295 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3296 } else { 3297 mode = PDC2xx_TIM_SET_MB(mode, 3298 pdc2xx_dma_mb[0]); 3299 mode = PDC2xx_TIM_SET_MC(mode, 3300 pdc2xx_dma_mc[0]); 3301 } 3302 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3303 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3304 if (drvp->drive_flags & DRIVE_ATA) 3305 mode |= PDC2xx_TIM_PRE; 3306 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3307 if (drvp->PIO_mode >= 3) { 3308 mode |= PDC2xx_TIM_IORDY; 3309 if (drive == 0) 3310 mode |= PDC2xx_TIM_IORDYp; 3311 } 3312 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3313 "timings 0x%x\n", 3314 sc->sc_wdcdev.sc_dev.dv_xname, 3315 chp->channel, drive, mode), DEBUG_PROBE); 3316 pci_conf_write(sc->sc_pc, sc->sc_tag, 3317 PDC2xx_TIM(chp->channel, drive), mode); 3318 } 3319 if (idedma_ctl != 0) { 3320 /* Add software bits in status register */ 3321 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3322 IDEDMA_CTL, idedma_ctl); 3323 } 3324 pciide_print_modes(cp); 3325 } 3326 3327 int 3328 pdc202xx_pci_intr(arg) 3329 void *arg; 3330 { 3331 struct pciide_softc *sc = arg; 3332 struct pciide_channel *cp; 3333 struct channel_softc *wdc_cp; 3334 int i, rv, crv; 3335 u_int32_t scr; 3336 3337 rv = 0; 3338 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3339 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3340 cp = &sc->pciide_channels[i]; 3341 wdc_cp = &cp->wdc_channel; 3342 /* If a compat channel skip. */ 3343 if (cp->compat) 3344 continue; 3345 if (scr & PDC2xx_SCR_INT(i)) { 3346 crv = wdcintr(wdc_cp); 3347 if (crv == 0) 3348 printf("%s:%d: bogus intr\n", 3349 sc->sc_wdcdev.sc_dev.dv_xname, i); 3350 else 3351 rv = 1; 3352 } 3353 } 3354 return rv; 3355 } 3356 3357 void 3358 opti_chip_map(sc, pa) 3359 struct pciide_softc *sc; 3360 struct pci_attach_args *pa; 3361 { 3362 struct pciide_channel *cp; 3363 bus_size_t cmdsize, ctlsize; 3364 pcireg_t interface; 3365 u_int8_t init_ctrl; 3366 int channel; 3367 3368 if (pciide_chipen(sc, pa) == 0) 3369 return; 3370 printf("%s: bus-master DMA support present", 3371 sc->sc_wdcdev.sc_dev.dv_xname); 3372 pciide_mapreg_dma(sc, pa); 3373 printf("\n"); 3374 3375 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3376 WDC_CAPABILITY_MODE; 3377 sc->sc_wdcdev.PIO_cap = 4; 3378 if (sc->sc_dma_ok) { 3379 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3380 sc->sc_wdcdev.irqack = pciide_irqack; 3381 sc->sc_wdcdev.DMA_cap = 2; 3382 } 3383 sc->sc_wdcdev.set_modes = opti_setup_channel; 3384 3385 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3386 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3387 3388 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3389 OPTI_REG_INIT_CONTROL); 3390 3391 interface = PCI_INTERFACE(pa->pa_class); 3392 3393 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3394 cp = &sc->pciide_channels[channel]; 3395 if (pciide_chansetup(sc, channel, interface) == 0) 3396 continue; 3397 if (channel == 1 && 3398 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3399 printf("%s: %s channel ignored (disabled)\n", 3400 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3401 continue; 3402 } 3403 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3404 pciide_pci_intr); 3405 if (cp->hw_ok == 0) 3406 continue; 3407 pciide_map_compat_intr(pa, cp, channel, interface); 3408 if (cp->hw_ok == 0) 3409 continue; 3410 opti_setup_channel(&cp->wdc_channel); 3411 } 3412 } 3413 3414 void 3415 opti_setup_channel(chp) 3416 struct channel_softc *chp; 3417 { 3418 struct ata_drive_datas *drvp; 3419 struct pciide_channel *cp = (struct pciide_channel*)chp; 3420 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3421 int drive, spd; 3422 int mode[2]; 3423 u_int8_t rv, mr; 3424 3425 /* 3426 * The `Delay' and `Address Setup Time' fields of the 3427 * Miscellaneous Register are always zero initially. 3428 */ 3429 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3430 mr &= ~(OPTI_MISC_DELAY_MASK | 3431 OPTI_MISC_ADDR_SETUP_MASK | 3432 OPTI_MISC_INDEX_MASK); 3433 3434 /* Prime the control register before setting timing values */ 3435 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3436 3437 /* Determine the clockrate of the PCIbus the chip is attached to */ 3438 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3439 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3440 3441 /* setup DMA if needed */ 3442 pciide_channel_dma_setup(cp); 3443 3444 for (drive = 0; drive < 2; drive++) { 3445 drvp = &chp->ch_drive[drive]; 3446 /* If no drive, skip */ 3447 if ((drvp->drive_flags & DRIVE) == 0) { 3448 mode[drive] = -1; 3449 continue; 3450 } 3451 3452 if ((drvp->drive_flags & DRIVE_DMA)) { 3453 /* 3454 * Timings will be used for both PIO and DMA, 3455 * so adjust DMA mode if needed 3456 */ 3457 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3458 drvp->PIO_mode = drvp->DMA_mode + 2; 3459 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3460 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3461 drvp->PIO_mode - 2 : 0; 3462 if (drvp->DMA_mode == 0) 3463 drvp->PIO_mode = 0; 3464 3465 mode[drive] = drvp->DMA_mode + 5; 3466 } else 3467 mode[drive] = drvp->PIO_mode; 3468 3469 if (drive && mode[0] >= 0 && 3470 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3471 /* 3472 * Can't have two drives using different values 3473 * for `Address Setup Time'. 3474 * Slow down the faster drive to compensate. 3475 */ 3476 int d = (opti_tim_as[spd][mode[0]] > 3477 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3478 3479 mode[d] = mode[1-d]; 3480 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3481 chp->ch_drive[d].DMA_mode = 0; 3482 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3483 } 3484 } 3485 3486 for (drive = 0; drive < 2; drive++) { 3487 int m; 3488 if ((m = mode[drive]) < 0) 3489 continue; 3490 3491 /* Set the Address Setup Time and select appropriate index */ 3492 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3493 rv |= OPTI_MISC_INDEX(drive); 3494 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3495 3496 /* Set the pulse width and recovery timing parameters */ 3497 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3498 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3499 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3500 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3501 3502 /* Set the Enhanced Mode register appropriately */ 3503 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3504 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3505 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3506 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3507 } 3508 3509 /* Finally, enable the timings */ 3510 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3511 3512 pciide_print_modes(cp); 3513 } 3514
Indexes created Thu Oct 02 10:09:58 GMT 2025