pciide.c revision 1.107.2.11
1 /* $NetBSD: pciide.c,v 1.107.2.11 2002/04/01 07:46:41 nathanw Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.107.2.11 2002/04/01 07:46:41 nathanw Exp $"); 81 82 #ifndef WDCDEBUG 83 #define WDCDEBUG 84 #endif 85 86 #define DEBUG_DMA 0x01 87 #define DEBUG_XFERS 0x02 88 #define DEBUG_FUNCS 0x08 89 #define DEBUG_PROBE 0x10 90 #ifdef WDCDEBUG 91 int wdcdebug_pciide_mask = 0; 92 #define WDCDEBUG_PRINT(args, level) \ 93 if (wdcdebug_pciide_mask & (level)) printf args 94 #else 95 #define WDCDEBUG_PRINT(args, level) 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 102 #include <uvm/uvm_extern.h> 103 104 #include <machine/endian.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 #include <dev/pci/pciide_opti_reg.h> 120 #include <dev/pci/pciide_hpt_reg.h> 121 #include <dev/pci/pciide_acard_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 static int acer_isabr_match __P(( struct pci_attach_args *)); 192 193 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void pdc202xx_setup_channel __P((struct channel_softc*)); 195 void pdc20268_setup_channel __P((struct channel_softc*)); 196 int pdc202xx_pci_intr __P((void *)); 197 int pdc20265_pci_intr __P((void *)); 198 199 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void opti_setup_channel __P((struct channel_softc*)); 201 202 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void hpt_setup_channel __P((struct channel_softc*)); 204 int hpt_pci_intr __P((void *)); 205 206 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 207 void acard_setup_channel __P((struct channel_softc*)); 208 int acard_pci_intr __P((void *)); 209 210 #ifdef PCIIDE_WINBOND_ENABLE 211 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 #endif 213 214 void pciide_channel_dma_setup __P((struct pciide_channel *)); 215 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 216 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 217 void pciide_dma_start __P((void*, int, int)); 218 int pciide_dma_finish __P((void*, int, int, int)); 219 void pciide_irqack __P((struct channel_softc *)); 220 void pciide_print_modes __P((struct pciide_channel *)); 221 222 struct pciide_product_desc { 223 u_int32_t ide_product; 224 int ide_flags; 225 const char *ide_name; 226 /* map and setup chip, probe drives */ 227 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 228 }; 229 230 /* Flags for ide_flags */ 231 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 232 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 233 234 /* Default product description for devices not known from this controller */ 235 const struct pciide_product_desc default_product_desc = { 236 0, 237 0, 238 "Generic PCI IDE controller", 239 default_chip_map, 240 }; 241 242 const struct pciide_product_desc pciide_intel_products[] = { 243 { PCI_PRODUCT_INTEL_82092AA, 244 0, 245 "Intel 82092AA IDE controller", 246 default_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82371FB_IDE, 249 0, 250 "Intel 82371FB IDE controller (PIIX)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82371SB_IDE, 254 0, 255 "Intel 82371SB IDE Interface (PIIX3)", 256 piix_chip_map, 257 }, 258 { PCI_PRODUCT_INTEL_82371AB_IDE, 259 0, 260 "Intel 82371AB IDE controller (PIIX4)", 261 piix_chip_map, 262 }, 263 { PCI_PRODUCT_INTEL_82440MX_IDE, 264 0, 265 "Intel 82440MX IDE controller", 266 piix_chip_map 267 }, 268 { PCI_PRODUCT_INTEL_82801AA_IDE, 269 0, 270 "Intel 82801AA IDE Controller (ICH)", 271 piix_chip_map, 272 }, 273 { PCI_PRODUCT_INTEL_82801AB_IDE, 274 0, 275 "Intel 82801AB IDE Controller (ICH0)", 276 piix_chip_map, 277 }, 278 { PCI_PRODUCT_INTEL_82801BA_IDE, 279 0, 280 "Intel 82801BA IDE Controller (ICH2)", 281 piix_chip_map, 282 }, 283 { PCI_PRODUCT_INTEL_82801BAM_IDE, 284 0, 285 "Intel 82801BAM IDE Controller (ICH2)", 286 piix_chip_map, 287 }, 288 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 289 0, 290 "Intel 82201CA IDE Controller", 291 piix_chip_map, 292 }, 293 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 294 0, 295 "Intel 82201CA IDE Controller", 296 piix_chip_map, 297 }, 298 { 0, 299 0, 300 NULL, 301 NULL 302 } 303 }; 304 305 const struct pciide_product_desc pciide_amd_products[] = { 306 { PCI_PRODUCT_AMD_PBC756_IDE, 307 0, 308 "Advanced Micro Devices AMD756 IDE Controller", 309 amd7x6_chip_map 310 }, 311 { PCI_PRODUCT_AMD_PBC766_IDE, 312 0, 313 "Advanced Micro Devices AMD766 IDE Controller", 314 amd7x6_chip_map 315 }, 316 { PCI_PRODUCT_AMD_PBC768_IDE, 317 0, 318 "Advanced Micro Devices AMD768 IDE Controller", 319 amd7x6_chip_map 320 }, 321 { 0, 322 0, 323 NULL, 324 NULL 325 } 326 }; 327 328 const struct pciide_product_desc pciide_cmd_products[] = { 329 { PCI_PRODUCT_CMDTECH_640, 330 0, 331 "CMD Technology PCI0640", 332 cmd_chip_map 333 }, 334 { PCI_PRODUCT_CMDTECH_643, 335 0, 336 "CMD Technology PCI0643", 337 cmd0643_9_chip_map, 338 }, 339 { PCI_PRODUCT_CMDTECH_646, 340 0, 341 "CMD Technology PCI0646", 342 cmd0643_9_chip_map, 343 }, 344 { PCI_PRODUCT_CMDTECH_648, 345 IDE_PCI_CLASS_OVERRIDE, 346 "CMD Technology PCI0648", 347 cmd0643_9_chip_map, 348 }, 349 { PCI_PRODUCT_CMDTECH_649, 350 IDE_PCI_CLASS_OVERRIDE, 351 "CMD Technology PCI0649", 352 cmd0643_9_chip_map, 353 }, 354 { 0, 355 0, 356 NULL, 357 NULL 358 } 359 }; 360 361 const struct pciide_product_desc pciide_via_products[] = { 362 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 363 0, 364 NULL, 365 apollo_chip_map, 366 }, 367 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 368 0, 369 NULL, 370 apollo_chip_map, 371 }, 372 { 0, 373 0, 374 NULL, 375 NULL 376 } 377 }; 378 379 const struct pciide_product_desc pciide_cypress_products[] = { 380 { PCI_PRODUCT_CONTAQ_82C693, 381 IDE_16BIT_IOSPACE, 382 "Cypress 82C693 IDE Controller", 383 cy693_chip_map, 384 }, 385 { 0, 386 0, 387 NULL, 388 NULL 389 } 390 }; 391 392 const struct pciide_product_desc pciide_sis_products[] = { 393 { PCI_PRODUCT_SIS_5597_IDE, 394 0, 395 "Silicon Integrated System 5597/5598 IDE controller", 396 sis_chip_map, 397 }, 398 { 0, 399 0, 400 NULL, 401 NULL 402 } 403 }; 404 405 const struct pciide_product_desc pciide_acer_products[] = { 406 { PCI_PRODUCT_ALI_M5229, 407 0, 408 "Acer Labs M5229 UDMA IDE Controller", 409 acer_chip_map, 410 }, 411 { 0, 412 0, 413 NULL, 414 NULL 415 } 416 }; 417 418 const struct pciide_product_desc pciide_promise_products[] = { 419 { PCI_PRODUCT_PROMISE_ULTRA33, 420 IDE_PCI_CLASS_OVERRIDE, 421 "Promise Ultra33/ATA Bus Master IDE Accelerator", 422 pdc202xx_chip_map, 423 }, 424 { PCI_PRODUCT_PROMISE_ULTRA66, 425 IDE_PCI_CLASS_OVERRIDE, 426 "Promise Ultra66/ATA Bus Master IDE Accelerator", 427 pdc202xx_chip_map, 428 }, 429 { PCI_PRODUCT_PROMISE_ULTRA100, 430 IDE_PCI_CLASS_OVERRIDE, 431 "Promise Ultra100/ATA Bus Master IDE Accelerator", 432 pdc202xx_chip_map, 433 }, 434 { PCI_PRODUCT_PROMISE_ULTRA100X, 435 IDE_PCI_CLASS_OVERRIDE, 436 "Promise Ultra100/ATA Bus Master IDE Accelerator", 437 pdc202xx_chip_map, 438 }, 439 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 440 IDE_PCI_CLASS_OVERRIDE, 441 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 442 pdc202xx_chip_map, 443 }, 444 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 445 IDE_PCI_CLASS_OVERRIDE, 446 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 447 pdc202xx_chip_map, 448 }, 449 { PCI_PRODUCT_PROMISE_ULTRA133, 450 IDE_PCI_CLASS_OVERRIDE, 451 "Promise Ultra133/ATA Bus Master IDE Accelerator", 452 pdc202xx_chip_map, 453 }, 454 { 0, 455 0, 456 NULL, 457 NULL 458 } 459 }; 460 461 const struct pciide_product_desc pciide_opti_products[] = { 462 { PCI_PRODUCT_OPTI_82C621, 463 0, 464 "OPTi 82c621 PCI IDE controller", 465 opti_chip_map, 466 }, 467 { PCI_PRODUCT_OPTI_82C568, 468 0, 469 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 470 opti_chip_map, 471 }, 472 { PCI_PRODUCT_OPTI_82D568, 473 0, 474 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 475 opti_chip_map, 476 }, 477 { 0, 478 0, 479 NULL, 480 NULL 481 } 482 }; 483 484 const struct pciide_product_desc pciide_triones_products[] = { 485 { PCI_PRODUCT_TRIONES_HPT366, 486 IDE_PCI_CLASS_OVERRIDE, 487 NULL, 488 hpt_chip_map, 489 }, 490 { 0, 491 0, 492 NULL, 493 NULL 494 } 495 }; 496 497 const struct pciide_product_desc pciide_acard_products[] = { 498 { PCI_PRODUCT_ACARD_ATP850U, 499 IDE_PCI_CLASS_OVERRIDE, 500 "Acard ATP850U Ultra33 IDE Controller", 501 acard_chip_map, 502 }, 503 { PCI_PRODUCT_ACARD_ATP860, 504 IDE_PCI_CLASS_OVERRIDE, 505 "Acard ATP860 Ultra66 IDE Controller", 506 acard_chip_map, 507 }, 508 { PCI_PRODUCT_ACARD_ATP860A, 509 IDE_PCI_CLASS_OVERRIDE, 510 "Acard ATP860-A Ultra66 IDE Controller", 511 acard_chip_map, 512 }, 513 { 0, 514 0, 515 NULL, 516 NULL 517 } 518 }; 519 520 #ifdef PCIIDE_SERVERWORKS_ENABLE 521 const struct pciide_product_desc pciide_serverworks_products[] = { 522 { PCI_PRODUCT_SERVERWORKS_IDE, 523 0, 524 "ServerWorks ROSB4 IDE Controller", 525 piix_chip_map, 526 }, 527 { 0, 528 0, 529 NULL, 530 } 531 }; 532 #endif 533 534 #ifdef PCIIDE_WINBOND_ENABLE 535 const struct pciide_product_desc pciide_winbond_products[] = { 536 { PCI_PRODUCT_WINBOND_W83C553F_1, 537 0, 538 "Winbond W83C553F IDE controller", 539 winbond_chip_map, 540 }, 541 { 0, 542 0, 543 NULL, 544 } 545 }; 546 #endif 547 548 struct pciide_vendor_desc { 549 u_int32_t ide_vendor; 550 const struct pciide_product_desc *ide_products; 551 }; 552 553 const struct pciide_vendor_desc pciide_vendors[] = { 554 { PCI_VENDOR_INTEL, pciide_intel_products }, 555 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 556 { PCI_VENDOR_VIATECH, pciide_via_products }, 557 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 558 { PCI_VENDOR_SIS, pciide_sis_products }, 559 { PCI_VENDOR_ALI, pciide_acer_products }, 560 { PCI_VENDOR_PROMISE, pciide_promise_products }, 561 { PCI_VENDOR_AMD, pciide_amd_products }, 562 { PCI_VENDOR_OPTI, pciide_opti_products }, 563 { PCI_VENDOR_TRIONES, pciide_triones_products }, 564 { PCI_VENDOR_ACARD, pciide_acard_products }, 565 #ifdef PCIIDE_SERVERWORKS_ENABLE 566 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 567 #endif 568 #ifdef PCIIDE_WINBOND_ENABLE 569 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 570 #endif 571 { 0, NULL } 572 }; 573 574 /* options passed via the 'flags' config keyword */ 575 #define PCIIDE_OPTIONS_DMA 0x01 576 #define PCIIDE_OPTIONS_NODMA 0x02 577 578 int pciide_match __P((struct device *, struct cfdata *, void *)); 579 void pciide_attach __P((struct device *, struct device *, void *)); 580 581 struct cfattach pciide_ca = { 582 sizeof(struct pciide_softc), pciide_match, pciide_attach 583 }; 584 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 585 int pciide_mapregs_compat __P(( struct pci_attach_args *, 586 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 587 int pciide_mapregs_native __P((struct pci_attach_args *, 588 struct pciide_channel *, bus_size_t *, bus_size_t *, 589 int (*pci_intr) __P((void *)))); 590 void pciide_mapreg_dma __P((struct pciide_softc *, 591 struct pci_attach_args *)); 592 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 593 void pciide_mapchan __P((struct pci_attach_args *, 594 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 595 int (*pci_intr) __P((void *)))); 596 int pciide_chan_candisable __P((struct pciide_channel *)); 597 void pciide_map_compat_intr __P(( struct pci_attach_args *, 598 struct pciide_channel *, int, int)); 599 int pciide_compat_intr __P((void *)); 600 int pciide_pci_intr __P((void *)); 601 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 602 603 const struct pciide_product_desc * 604 pciide_lookup_product(id) 605 u_int32_t id; 606 { 607 const struct pciide_product_desc *pp; 608 const struct pciide_vendor_desc *vp; 609 610 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 611 if (PCI_VENDOR(id) == vp->ide_vendor) 612 break; 613 614 if ((pp = vp->ide_products) == NULL) 615 return NULL; 616 617 for (; pp->chip_map != NULL; pp++) 618 if (PCI_PRODUCT(id) == pp->ide_product) 619 break; 620 621 if (pp->chip_map == NULL) 622 return NULL; 623 return pp; 624 } 625 626 int 627 pciide_match(parent, match, aux) 628 struct device *parent; 629 struct cfdata *match; 630 void *aux; 631 { 632 struct pci_attach_args *pa = aux; 633 const struct pciide_product_desc *pp; 634 635 /* 636 * Check the ID register to see that it's a PCI IDE controller. 637 * If it is, we assume that we can deal with it; it _should_ 638 * work in a standardized way... 639 */ 640 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 641 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 642 return (1); 643 } 644 645 /* 646 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 647 * controllers. Let see if we can deal with it anyway. 648 */ 649 pp = pciide_lookup_product(pa->pa_id); 650 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 651 return (1); 652 } 653 654 return (0); 655 } 656 657 void 658 pciide_attach(parent, self, aux) 659 struct device *parent, *self; 660 void *aux; 661 { 662 struct pci_attach_args *pa = aux; 663 pci_chipset_tag_t pc = pa->pa_pc; 664 pcitag_t tag = pa->pa_tag; 665 struct pciide_softc *sc = (struct pciide_softc *)self; 666 pcireg_t csr; 667 char devinfo[256]; 668 const char *displaydev; 669 670 sc->sc_pp = pciide_lookup_product(pa->pa_id); 671 if (sc->sc_pp == NULL) { 672 sc->sc_pp = &default_product_desc; 673 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 674 displaydev = devinfo; 675 } else 676 displaydev = sc->sc_pp->ide_name; 677 678 /* if displaydev == NULL, printf is done in chip-specific map */ 679 if (displaydev) 680 printf(": %s (rev. 0x%02x)\n", displaydev, 681 PCI_REVISION(pa->pa_class)); 682 683 sc->sc_pc = pa->pa_pc; 684 sc->sc_tag = pa->pa_tag; 685 #ifdef WDCDEBUG 686 if (wdcdebug_pciide_mask & DEBUG_PROBE) 687 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 688 #endif 689 sc->sc_pp->chip_map(sc, pa); 690 691 if (sc->sc_dma_ok) { 692 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 693 csr |= PCI_COMMAND_MASTER_ENABLE; 694 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 695 } 696 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 697 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 698 } 699 700 /* tell wether the chip is enabled or not */ 701 int 702 pciide_chipen(sc, pa) 703 struct pciide_softc *sc; 704 struct pci_attach_args *pa; 705 { 706 pcireg_t csr; 707 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 708 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 709 PCI_COMMAND_STATUS_REG); 710 printf("%s: device disabled (at %s)\n", 711 sc->sc_wdcdev.sc_dev.dv_xname, 712 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 713 "device" : "bridge"); 714 return 0; 715 } 716 return 1; 717 } 718 719 int 720 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 721 struct pci_attach_args *pa; 722 struct pciide_channel *cp; 723 int compatchan; 724 bus_size_t *cmdsizep, *ctlsizep; 725 { 726 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 727 struct channel_softc *wdc_cp = &cp->wdc_channel; 728 729 cp->compat = 1; 730 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 731 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 732 733 wdc_cp->cmd_iot = pa->pa_iot; 734 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 735 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 736 printf("%s: couldn't map %s channel cmd regs\n", 737 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 738 return (0); 739 } 740 741 wdc_cp->ctl_iot = pa->pa_iot; 742 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 743 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 744 printf("%s: couldn't map %s channel ctl regs\n", 745 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 746 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 747 PCIIDE_COMPAT_CMD_SIZE); 748 return (0); 749 } 750 751 return (1); 752 } 753 754 int 755 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 756 struct pci_attach_args * pa; 757 struct pciide_channel *cp; 758 bus_size_t *cmdsizep, *ctlsizep; 759 int (*pci_intr) __P((void *)); 760 { 761 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 762 struct channel_softc *wdc_cp = &cp->wdc_channel; 763 const char *intrstr; 764 pci_intr_handle_t intrhandle; 765 766 cp->compat = 0; 767 768 if (sc->sc_pci_ih == NULL) { 769 if (pci_intr_map(pa, &intrhandle) != 0) { 770 printf("%s: couldn't map native-PCI interrupt\n", 771 sc->sc_wdcdev.sc_dev.dv_xname); 772 return 0; 773 } 774 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 775 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 776 intrhandle, IPL_BIO, pci_intr, sc); 777 if (sc->sc_pci_ih != NULL) { 778 printf("%s: using %s for native-PCI interrupt\n", 779 sc->sc_wdcdev.sc_dev.dv_xname, 780 intrstr ? intrstr : "unknown interrupt"); 781 } else { 782 printf("%s: couldn't establish native-PCI interrupt", 783 sc->sc_wdcdev.sc_dev.dv_xname); 784 if (intrstr != NULL) 785 printf(" at %s", intrstr); 786 printf("\n"); 787 return 0; 788 } 789 } 790 cp->ih = sc->sc_pci_ih; 791 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 792 PCI_MAPREG_TYPE_IO, 0, 793 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 794 printf("%s: couldn't map %s channel cmd regs\n", 795 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 796 return 0; 797 } 798 799 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 800 PCI_MAPREG_TYPE_IO, 0, 801 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 802 printf("%s: couldn't map %s channel ctl regs\n", 803 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 804 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 805 return 0; 806 } 807 /* 808 * In native mode, 4 bytes of I/O space are mapped for the control 809 * register, the control register is at offset 2. Pass the generic 810 * code a handle for only one byte at the rigth offset. 811 */ 812 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 813 &wdc_cp->ctl_ioh) != 0) { 814 printf("%s: unable to subregion %s channel ctl regs\n", 815 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 816 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 817 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 818 return 0; 819 } 820 return (1); 821 } 822 823 void 824 pciide_mapreg_dma(sc, pa) 825 struct pciide_softc *sc; 826 struct pci_attach_args *pa; 827 { 828 pcireg_t maptype; 829 bus_addr_t addr; 830 831 /* 832 * Map DMA registers 833 * 834 * Note that sc_dma_ok is the right variable to test to see if 835 * DMA can be done. If the interface doesn't support DMA, 836 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 837 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 838 * non-zero if the interface supports DMA and the registers 839 * could be mapped. 840 * 841 * XXX Note that despite the fact that the Bus Master IDE specs 842 * XXX say that "The bus master IDE function uses 16 bytes of IO 843 * XXX space," some controllers (at least the United 844 * XXX Microelectronics UM8886BF) place it in memory space. 845 */ 846 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 847 PCIIDE_REG_BUS_MASTER_DMA); 848 849 switch (maptype) { 850 case PCI_MAPREG_TYPE_IO: 851 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 852 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 853 &addr, NULL, NULL) == 0); 854 if (sc->sc_dma_ok == 0) { 855 printf(", but unused (couldn't query registers)"); 856 break; 857 } 858 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 859 && addr >= 0x10000) { 860 sc->sc_dma_ok = 0; 861 printf(", but unused (registers at unsafe address " 862 "%#lx)", (unsigned long)addr); 863 break; 864 } 865 /* FALLTHROUGH */ 866 867 case PCI_MAPREG_MEM_TYPE_32BIT: 868 sc->sc_dma_ok = (pci_mapreg_map(pa, 869 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 870 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 871 sc->sc_dmat = pa->pa_dmat; 872 if (sc->sc_dma_ok == 0) { 873 printf(", but unused (couldn't map registers)"); 874 } else { 875 sc->sc_wdcdev.dma_arg = sc; 876 sc->sc_wdcdev.dma_init = pciide_dma_init; 877 sc->sc_wdcdev.dma_start = pciide_dma_start; 878 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 879 } 880 881 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 882 PCIIDE_OPTIONS_NODMA) { 883 printf(", but unused (forced off by config file)"); 884 sc->sc_dma_ok = 0; 885 } 886 break; 887 888 default: 889 sc->sc_dma_ok = 0; 890 printf(", but unsupported register maptype (0x%x)", maptype); 891 } 892 } 893 894 int 895 pciide_compat_intr(arg) 896 void *arg; 897 { 898 struct pciide_channel *cp = arg; 899 900 #ifdef DIAGNOSTIC 901 /* should only be called for a compat channel */ 902 if (cp->compat == 0) 903 panic("pciide compat intr called for non-compat chan %p\n", cp); 904 #endif 905 return (wdcintr(&cp->wdc_channel)); 906 } 907 908 int 909 pciide_pci_intr(arg) 910 void *arg; 911 { 912 struct pciide_softc *sc = arg; 913 struct pciide_channel *cp; 914 struct channel_softc *wdc_cp; 915 int i, rv, crv; 916 917 rv = 0; 918 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 919 cp = &sc->pciide_channels[i]; 920 wdc_cp = &cp->wdc_channel; 921 922 /* If a compat channel skip. */ 923 if (cp->compat) 924 continue; 925 /* if this channel not waiting for intr, skip */ 926 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 927 continue; 928 929 crv = wdcintr(wdc_cp); 930 if (crv == 0) 931 ; /* leave rv alone */ 932 else if (crv == 1) 933 rv = 1; /* claim the intr */ 934 else if (rv == 0) /* crv should be -1 in this case */ 935 rv = crv; /* if we've done no better, take it */ 936 } 937 return (rv); 938 } 939 940 void 941 pciide_channel_dma_setup(cp) 942 struct pciide_channel *cp; 943 { 944 int drive; 945 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 946 struct ata_drive_datas *drvp; 947 948 for (drive = 0; drive < 2; drive++) { 949 drvp = &cp->wdc_channel.ch_drive[drive]; 950 /* If no drive, skip */ 951 if ((drvp->drive_flags & DRIVE) == 0) 952 continue; 953 /* setup DMA if needed */ 954 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 955 (drvp->drive_flags & DRIVE_UDMA) == 0) || 956 sc->sc_dma_ok == 0) { 957 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 958 continue; 959 } 960 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 961 != 0) { 962 /* Abort DMA setup */ 963 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 964 continue; 965 } 966 } 967 } 968 969 int 970 pciide_dma_table_setup(sc, channel, drive) 971 struct pciide_softc *sc; 972 int channel, drive; 973 { 974 bus_dma_segment_t seg; 975 int error, rseg; 976 const bus_size_t dma_table_size = 977 sizeof(struct idedma_table) * NIDEDMA_TABLES; 978 struct pciide_dma_maps *dma_maps = 979 &sc->pciide_channels[channel].dma_maps[drive]; 980 981 /* If table was already allocated, just return */ 982 if (dma_maps->dma_table) 983 return 0; 984 985 /* Allocate memory for the DMA tables and map it */ 986 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 987 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 988 BUS_DMA_NOWAIT)) != 0) { 989 printf("%s:%d: unable to allocate table DMA for " 990 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 991 channel, drive, error); 992 return error; 993 } 994 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 995 dma_table_size, 996 (caddr_t *)&dma_maps->dma_table, 997 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 998 printf("%s:%d: unable to map table DMA for" 999 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1000 channel, drive, error); 1001 return error; 1002 } 1003 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1004 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1005 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1006 1007 /* Create and load table DMA map for this disk */ 1008 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1009 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1010 &dma_maps->dmamap_table)) != 0) { 1011 printf("%s:%d: unable to create table DMA map for " 1012 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1013 channel, drive, error); 1014 return error; 1015 } 1016 if ((error = bus_dmamap_load(sc->sc_dmat, 1017 dma_maps->dmamap_table, 1018 dma_maps->dma_table, 1019 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1020 printf("%s:%d: unable to load table DMA map for " 1021 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1022 channel, drive, error); 1023 return error; 1024 } 1025 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1026 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1027 DEBUG_PROBE); 1028 /* Create a xfer DMA map for this drive */ 1029 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1030 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1031 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1032 &dma_maps->dmamap_xfer)) != 0) { 1033 printf("%s:%d: unable to create xfer DMA map for " 1034 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1035 channel, drive, error); 1036 return error; 1037 } 1038 return 0; 1039 } 1040 1041 int 1042 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1043 void *v; 1044 int channel, drive; 1045 void *databuf; 1046 size_t datalen; 1047 int flags; 1048 { 1049 struct pciide_softc *sc = v; 1050 int error, seg; 1051 struct pciide_dma_maps *dma_maps = 1052 &sc->pciide_channels[channel].dma_maps[drive]; 1053 1054 error = bus_dmamap_load(sc->sc_dmat, 1055 dma_maps->dmamap_xfer, 1056 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1057 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1058 if (error) { 1059 printf("%s:%d: unable to load xfer DMA map for" 1060 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1061 channel, drive, error); 1062 return error; 1063 } 1064 1065 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1066 dma_maps->dmamap_xfer->dm_mapsize, 1067 (flags & WDC_DMA_READ) ? 1068 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1069 1070 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1071 #ifdef DIAGNOSTIC 1072 /* A segment must not cross a 64k boundary */ 1073 { 1074 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1075 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1076 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1077 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1078 printf("pciide_dma: segment %d physical addr 0x%lx" 1079 " len 0x%lx not properly aligned\n", 1080 seg, phys, len); 1081 panic("pciide_dma: buf align"); 1082 } 1083 } 1084 #endif 1085 dma_maps->dma_table[seg].base_addr = 1086 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1087 dma_maps->dma_table[seg].byte_count = 1088 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1089 IDEDMA_BYTE_COUNT_MASK); 1090 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1091 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1092 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1093 1094 } 1095 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1096 htole32(IDEDMA_BYTE_COUNT_EOT); 1097 1098 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1099 dma_maps->dmamap_table->dm_mapsize, 1100 BUS_DMASYNC_PREWRITE); 1101 1102 /* Maps are ready. Start DMA function */ 1103 #ifdef DIAGNOSTIC 1104 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1105 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1106 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1107 panic("pciide_dma_init: table align"); 1108 } 1109 #endif 1110 1111 /* Clear status bits */ 1112 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1113 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1114 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1115 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1116 /* Write table addr */ 1117 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1118 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1119 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1120 /* set read/write */ 1121 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1122 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1123 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1124 /* remember flags */ 1125 dma_maps->dma_flags = flags; 1126 return 0; 1127 } 1128 1129 void 1130 pciide_dma_start(v, channel, drive) 1131 void *v; 1132 int channel, drive; 1133 { 1134 struct pciide_softc *sc = v; 1135 1136 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1137 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1138 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1139 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1140 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1141 } 1142 1143 int 1144 pciide_dma_finish(v, channel, drive, force) 1145 void *v; 1146 int channel, drive; 1147 int force; 1148 { 1149 struct pciide_softc *sc = v; 1150 u_int8_t status; 1151 int error = 0; 1152 struct pciide_dma_maps *dma_maps = 1153 &sc->pciide_channels[channel].dma_maps[drive]; 1154 1155 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1156 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1157 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1158 DEBUG_XFERS); 1159 1160 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1161 return WDC_DMAST_NOIRQ; 1162 1163 /* stop DMA channel */ 1164 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1165 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1166 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1167 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1168 1169 /* Unload the map of the data buffer */ 1170 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1171 dma_maps->dmamap_xfer->dm_mapsize, 1172 (dma_maps->dma_flags & WDC_DMA_READ) ? 1173 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1174 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1175 1176 if ((status & IDEDMA_CTL_ERR) != 0) { 1177 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1178 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1179 error |= WDC_DMAST_ERR; 1180 } 1181 1182 if ((status & IDEDMA_CTL_INTR) == 0) { 1183 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1184 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1185 drive, status); 1186 error |= WDC_DMAST_NOIRQ; 1187 } 1188 1189 if ((status & IDEDMA_CTL_ACT) != 0) { 1190 /* data underrun, may be a valid condition for ATAPI */ 1191 error |= WDC_DMAST_UNDER; 1192 } 1193 return error; 1194 } 1195 1196 void 1197 pciide_irqack(chp) 1198 struct channel_softc *chp; 1199 { 1200 struct pciide_channel *cp = (struct pciide_channel*)chp; 1201 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1202 1203 /* clear status bits in IDE DMA registers */ 1204 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1205 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1206 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1207 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1208 } 1209 1210 /* some common code used by several chip_map */ 1211 int 1212 pciide_chansetup(sc, channel, interface) 1213 struct pciide_softc *sc; 1214 int channel; 1215 pcireg_t interface; 1216 { 1217 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1218 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1219 cp->name = PCIIDE_CHANNEL_NAME(channel); 1220 cp->wdc_channel.channel = channel; 1221 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1222 cp->wdc_channel.ch_queue = 1223 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1224 if (cp->wdc_channel.ch_queue == NULL) { 1225 printf("%s %s channel: " 1226 "can't allocate memory for command queue", 1227 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1228 return 0; 1229 } 1230 printf("%s: %s channel %s to %s mode\n", 1231 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1232 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1233 "configured" : "wired", 1234 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1235 "native-PCI" : "compatibility"); 1236 return 1; 1237 } 1238 1239 /* some common code used by several chip channel_map */ 1240 void 1241 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1242 struct pci_attach_args *pa; 1243 struct pciide_channel *cp; 1244 pcireg_t interface; 1245 bus_size_t *cmdsizep, *ctlsizep; 1246 int (*pci_intr) __P((void *)); 1247 { 1248 struct channel_softc *wdc_cp = &cp->wdc_channel; 1249 1250 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1251 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1252 pci_intr); 1253 else 1254 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1255 wdc_cp->channel, cmdsizep, ctlsizep); 1256 1257 if (cp->hw_ok == 0) 1258 return; 1259 wdc_cp->data32iot = wdc_cp->cmd_iot; 1260 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1261 wdcattach(wdc_cp); 1262 } 1263 1264 /* 1265 * Generic code to call to know if a channel can be disabled. Return 1 1266 * if channel can be disabled, 0 if not 1267 */ 1268 int 1269 pciide_chan_candisable(cp) 1270 struct pciide_channel *cp; 1271 { 1272 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1273 struct channel_softc *wdc_cp = &cp->wdc_channel; 1274 1275 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1276 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1277 printf("%s: disabling %s channel (no drives)\n", 1278 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1279 cp->hw_ok = 0; 1280 return 1; 1281 } 1282 return 0; 1283 } 1284 1285 /* 1286 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1287 * Set hw_ok=0 on failure 1288 */ 1289 void 1290 pciide_map_compat_intr(pa, cp, compatchan, interface) 1291 struct pci_attach_args *pa; 1292 struct pciide_channel *cp; 1293 int compatchan, interface; 1294 { 1295 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1296 struct channel_softc *wdc_cp = &cp->wdc_channel; 1297 1298 if (cp->hw_ok == 0) 1299 return; 1300 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1301 return; 1302 1303 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1304 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1305 pa, compatchan, pciide_compat_intr, cp); 1306 if (cp->ih == NULL) { 1307 #endif 1308 printf("%s: no compatibility interrupt for use by %s " 1309 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1310 cp->hw_ok = 0; 1311 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1312 } 1313 #endif 1314 } 1315 1316 void 1317 pciide_print_modes(cp) 1318 struct pciide_channel *cp; 1319 { 1320 wdc_print_modes(&cp->wdc_channel); 1321 } 1322 1323 void 1324 default_chip_map(sc, pa) 1325 struct pciide_softc *sc; 1326 struct pci_attach_args *pa; 1327 { 1328 struct pciide_channel *cp; 1329 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1330 pcireg_t csr; 1331 int channel, drive; 1332 struct ata_drive_datas *drvp; 1333 u_int8_t idedma_ctl; 1334 bus_size_t cmdsize, ctlsize; 1335 char *failreason; 1336 1337 if (pciide_chipen(sc, pa) == 0) 1338 return; 1339 1340 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1341 printf("%s: bus-master DMA support present", 1342 sc->sc_wdcdev.sc_dev.dv_xname); 1343 if (sc->sc_pp == &default_product_desc && 1344 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1345 PCIIDE_OPTIONS_DMA) == 0) { 1346 printf(", but unused (no driver support)"); 1347 sc->sc_dma_ok = 0; 1348 } else { 1349 pciide_mapreg_dma(sc, pa); 1350 if (sc->sc_dma_ok != 0) 1351 printf(", used without full driver " 1352 "support"); 1353 } 1354 } else { 1355 printf("%s: hardware does not support DMA", 1356 sc->sc_wdcdev.sc_dev.dv_xname); 1357 sc->sc_dma_ok = 0; 1358 } 1359 printf("\n"); 1360 if (sc->sc_dma_ok) { 1361 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1362 sc->sc_wdcdev.irqack = pciide_irqack; 1363 } 1364 sc->sc_wdcdev.PIO_cap = 0; 1365 sc->sc_wdcdev.DMA_cap = 0; 1366 1367 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1368 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1369 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1370 1371 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1372 cp = &sc->pciide_channels[channel]; 1373 if (pciide_chansetup(sc, channel, interface) == 0) 1374 continue; 1375 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1376 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1377 &ctlsize, pciide_pci_intr); 1378 } else { 1379 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1380 channel, &cmdsize, &ctlsize); 1381 } 1382 if (cp->hw_ok == 0) 1383 continue; 1384 /* 1385 * Check to see if something appears to be there. 1386 */ 1387 failreason = NULL; 1388 if (!wdcprobe(&cp->wdc_channel)) { 1389 failreason = "not responding; disabled or no drives?"; 1390 goto next; 1391 } 1392 /* 1393 * Now, make sure it's actually attributable to this PCI IDE 1394 * channel by trying to access the channel again while the 1395 * PCI IDE controller's I/O space is disabled. (If the 1396 * channel no longer appears to be there, it belongs to 1397 * this controller.) YUCK! 1398 */ 1399 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1400 PCI_COMMAND_STATUS_REG); 1401 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1402 csr & ~PCI_COMMAND_IO_ENABLE); 1403 if (wdcprobe(&cp->wdc_channel)) 1404 failreason = "other hardware responding at addresses"; 1405 pci_conf_write(sc->sc_pc, sc->sc_tag, 1406 PCI_COMMAND_STATUS_REG, csr); 1407 next: 1408 if (failreason) { 1409 printf("%s: %s channel ignored (%s)\n", 1410 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1411 failreason); 1412 cp->hw_ok = 0; 1413 bus_space_unmap(cp->wdc_channel.cmd_iot, 1414 cp->wdc_channel.cmd_ioh, cmdsize); 1415 bus_space_unmap(cp->wdc_channel.ctl_iot, 1416 cp->wdc_channel.ctl_ioh, ctlsize); 1417 } else { 1418 pciide_map_compat_intr(pa, cp, channel, interface); 1419 } 1420 if (cp->hw_ok) { 1421 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1422 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1423 wdcattach(&cp->wdc_channel); 1424 } 1425 } 1426 1427 if (sc->sc_dma_ok == 0) 1428 return; 1429 1430 /* Allocate DMA maps */ 1431 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1432 idedma_ctl = 0; 1433 cp = &sc->pciide_channels[channel]; 1434 for (drive = 0; drive < 2; drive++) { 1435 drvp = &cp->wdc_channel.ch_drive[drive]; 1436 /* If no drive, skip */ 1437 if ((drvp->drive_flags & DRIVE) == 0) 1438 continue; 1439 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1440 continue; 1441 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1442 /* Abort DMA setup */ 1443 printf("%s:%d:%d: can't allocate DMA maps, " 1444 "using PIO transfers\n", 1445 sc->sc_wdcdev.sc_dev.dv_xname, 1446 channel, drive); 1447 drvp->drive_flags &= ~DRIVE_DMA; 1448 } 1449 printf("%s:%d:%d: using DMA data transfers\n", 1450 sc->sc_wdcdev.sc_dev.dv_xname, 1451 channel, drive); 1452 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1453 } 1454 if (idedma_ctl != 0) { 1455 /* Add software bits in status register */ 1456 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1457 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1458 idedma_ctl); 1459 } 1460 } 1461 } 1462 1463 void 1464 piix_chip_map(sc, pa) 1465 struct pciide_softc *sc; 1466 struct pci_attach_args *pa; 1467 { 1468 struct pciide_channel *cp; 1469 int channel; 1470 u_int32_t idetim; 1471 bus_size_t cmdsize, ctlsize; 1472 1473 if (pciide_chipen(sc, pa) == 0) 1474 return; 1475 1476 printf("%s: bus-master DMA support present", 1477 sc->sc_wdcdev.sc_dev.dv_xname); 1478 pciide_mapreg_dma(sc, pa); 1479 printf("\n"); 1480 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1481 WDC_CAPABILITY_MODE; 1482 if (sc->sc_dma_ok) { 1483 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1484 sc->sc_wdcdev.irqack = pciide_irqack; 1485 switch(sc->sc_pp->ide_product) { 1486 case PCI_PRODUCT_INTEL_82371AB_IDE: 1487 case PCI_PRODUCT_INTEL_82440MX_IDE: 1488 case PCI_PRODUCT_INTEL_82801AA_IDE: 1489 case PCI_PRODUCT_INTEL_82801AB_IDE: 1490 case PCI_PRODUCT_INTEL_82801BA_IDE: 1491 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1492 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1493 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1494 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1495 } 1496 } 1497 sc->sc_wdcdev.PIO_cap = 4; 1498 sc->sc_wdcdev.DMA_cap = 2; 1499 switch(sc->sc_pp->ide_product) { 1500 case PCI_PRODUCT_INTEL_82801AA_IDE: 1501 sc->sc_wdcdev.UDMA_cap = 4; 1502 break; 1503 case PCI_PRODUCT_INTEL_82801BA_IDE: 1504 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1505 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1506 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1507 sc->sc_wdcdev.UDMA_cap = 5; 1508 break; 1509 default: 1510 sc->sc_wdcdev.UDMA_cap = 2; 1511 } 1512 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1513 sc->sc_wdcdev.set_modes = piix_setup_channel; 1514 else 1515 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1516 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1517 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1518 1519 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1520 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1521 DEBUG_PROBE); 1522 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1523 WDCDEBUG_PRINT((", sidetim=0x%x", 1524 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1525 DEBUG_PROBE); 1526 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1527 WDCDEBUG_PRINT((", udamreg 0x%x", 1528 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1529 DEBUG_PROBE); 1530 } 1531 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1532 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1533 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1534 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1535 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1536 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1537 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1538 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1539 DEBUG_PROBE); 1540 } 1541 1542 } 1543 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1544 1545 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1546 cp = &sc->pciide_channels[channel]; 1547 /* PIIX is compat-only */ 1548 if (pciide_chansetup(sc, channel, 0) == 0) 1549 continue; 1550 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1551 if ((PIIX_IDETIM_READ(idetim, channel) & 1552 PIIX_IDETIM_IDE) == 0) { 1553 printf("%s: %s channel ignored (disabled)\n", 1554 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1555 continue; 1556 } 1557 /* PIIX are compat-only pciide devices */ 1558 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1559 if (cp->hw_ok == 0) 1560 continue; 1561 if (pciide_chan_candisable(cp)) { 1562 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1563 channel); 1564 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1565 idetim); 1566 } 1567 pciide_map_compat_intr(pa, cp, channel, 0); 1568 if (cp->hw_ok == 0) 1569 continue; 1570 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1571 } 1572 1573 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1574 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1575 DEBUG_PROBE); 1576 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1577 WDCDEBUG_PRINT((", sidetim=0x%x", 1578 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1579 DEBUG_PROBE); 1580 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1581 WDCDEBUG_PRINT((", udamreg 0x%x", 1582 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1583 DEBUG_PROBE); 1584 } 1585 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1586 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1587 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1588 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1589 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1590 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1591 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1592 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1593 DEBUG_PROBE); 1594 } 1595 } 1596 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1597 } 1598 1599 void 1600 piix_setup_channel(chp) 1601 struct channel_softc *chp; 1602 { 1603 u_int8_t mode[2], drive; 1604 u_int32_t oidetim, idetim, idedma_ctl; 1605 struct pciide_channel *cp = (struct pciide_channel*)chp; 1606 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1607 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1608 1609 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1610 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1611 idedma_ctl = 0; 1612 1613 /* set up new idetim: Enable IDE registers decode */ 1614 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1615 chp->channel); 1616 1617 /* setup DMA */ 1618 pciide_channel_dma_setup(cp); 1619 1620 /* 1621 * Here we have to mess up with drives mode: PIIX can't have 1622 * different timings for master and slave drives. 1623 * We need to find the best combination. 1624 */ 1625 1626 /* If both drives supports DMA, take the lower mode */ 1627 if ((drvp[0].drive_flags & DRIVE_DMA) && 1628 (drvp[1].drive_flags & DRIVE_DMA)) { 1629 mode[0] = mode[1] = 1630 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1631 drvp[0].DMA_mode = mode[0]; 1632 drvp[1].DMA_mode = mode[1]; 1633 goto ok; 1634 } 1635 /* 1636 * If only one drive supports DMA, use its mode, and 1637 * put the other one in PIO mode 0 if mode not compatible 1638 */ 1639 if (drvp[0].drive_flags & DRIVE_DMA) { 1640 mode[0] = drvp[0].DMA_mode; 1641 mode[1] = drvp[1].PIO_mode; 1642 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1643 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1644 mode[1] = drvp[1].PIO_mode = 0; 1645 goto ok; 1646 } 1647 if (drvp[1].drive_flags & DRIVE_DMA) { 1648 mode[1] = drvp[1].DMA_mode; 1649 mode[0] = drvp[0].PIO_mode; 1650 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1651 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1652 mode[0] = drvp[0].PIO_mode = 0; 1653 goto ok; 1654 } 1655 /* 1656 * If both drives are not DMA, takes the lower mode, unless 1657 * one of them is PIO mode < 2 1658 */ 1659 if (drvp[0].PIO_mode < 2) { 1660 mode[0] = drvp[0].PIO_mode = 0; 1661 mode[1] = drvp[1].PIO_mode; 1662 } else if (drvp[1].PIO_mode < 2) { 1663 mode[1] = drvp[1].PIO_mode = 0; 1664 mode[0] = drvp[0].PIO_mode; 1665 } else { 1666 mode[0] = mode[1] = 1667 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1668 drvp[0].PIO_mode = mode[0]; 1669 drvp[1].PIO_mode = mode[1]; 1670 } 1671 ok: /* The modes are setup */ 1672 for (drive = 0; drive < 2; drive++) { 1673 if (drvp[drive].drive_flags & DRIVE_DMA) { 1674 idetim |= piix_setup_idetim_timings( 1675 mode[drive], 1, chp->channel); 1676 goto end; 1677 } 1678 } 1679 /* If we are there, none of the drives are DMA */ 1680 if (mode[0] >= 2) 1681 idetim |= piix_setup_idetim_timings( 1682 mode[0], 0, chp->channel); 1683 else 1684 idetim |= piix_setup_idetim_timings( 1685 mode[1], 0, chp->channel); 1686 end: /* 1687 * timing mode is now set up in the controller. Enable 1688 * it per-drive 1689 */ 1690 for (drive = 0; drive < 2; drive++) { 1691 /* If no drive, skip */ 1692 if ((drvp[drive].drive_flags & DRIVE) == 0) 1693 continue; 1694 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1695 if (drvp[drive].drive_flags & DRIVE_DMA) 1696 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1697 } 1698 if (idedma_ctl != 0) { 1699 /* Add software bits in status register */ 1700 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1701 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1702 idedma_ctl); 1703 } 1704 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1705 pciide_print_modes(cp); 1706 } 1707 1708 void 1709 piix3_4_setup_channel(chp) 1710 struct channel_softc *chp; 1711 { 1712 struct ata_drive_datas *drvp; 1713 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1714 struct pciide_channel *cp = (struct pciide_channel*)chp; 1715 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1716 int drive; 1717 int channel = chp->channel; 1718 1719 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1720 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1721 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1722 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1723 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1724 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1725 PIIX_SIDETIM_RTC_MASK(channel)); 1726 1727 idedma_ctl = 0; 1728 /* If channel disabled, no need to go further */ 1729 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1730 return; 1731 /* set up new idetim: Enable IDE registers decode */ 1732 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1733 1734 /* setup DMA if needed */ 1735 pciide_channel_dma_setup(cp); 1736 1737 for (drive = 0; drive < 2; drive++) { 1738 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1739 PIIX_UDMATIM_SET(0x3, channel, drive)); 1740 drvp = &chp->ch_drive[drive]; 1741 /* If no drive, skip */ 1742 if ((drvp->drive_flags & DRIVE) == 0) 1743 continue; 1744 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1745 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1746 goto pio; 1747 1748 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1749 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1750 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1751 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1752 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1753 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1754 ideconf |= PIIX_CONFIG_PINGPONG; 1755 } 1756 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1757 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1758 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1759 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1760 /* setup Ultra/100 */ 1761 if (drvp->UDMA_mode > 2 && 1762 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1763 drvp->UDMA_mode = 2; 1764 if (drvp->UDMA_mode > 4) { 1765 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1766 } else { 1767 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1768 if (drvp->UDMA_mode > 2) { 1769 ideconf |= PIIX_CONFIG_UDMA66(channel, 1770 drive); 1771 } else { 1772 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1773 drive); 1774 } 1775 } 1776 } 1777 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1778 /* setup Ultra/66 */ 1779 if (drvp->UDMA_mode > 2 && 1780 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1781 drvp->UDMA_mode = 2; 1782 if (drvp->UDMA_mode > 2) 1783 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1784 else 1785 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1786 } 1787 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1788 (drvp->drive_flags & DRIVE_UDMA)) { 1789 /* use Ultra/DMA */ 1790 drvp->drive_flags &= ~DRIVE_DMA; 1791 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1792 udmareg |= PIIX_UDMATIM_SET( 1793 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1794 } else { 1795 /* use Multiword DMA */ 1796 drvp->drive_flags &= ~DRIVE_UDMA; 1797 if (drive == 0) { 1798 idetim |= piix_setup_idetim_timings( 1799 drvp->DMA_mode, 1, channel); 1800 } else { 1801 sidetim |= piix_setup_sidetim_timings( 1802 drvp->DMA_mode, 1, channel); 1803 idetim =PIIX_IDETIM_SET(idetim, 1804 PIIX_IDETIM_SITRE, channel); 1805 } 1806 } 1807 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1808 1809 pio: /* use PIO mode */ 1810 idetim |= piix_setup_idetim_drvs(drvp); 1811 if (drive == 0) { 1812 idetim |= piix_setup_idetim_timings( 1813 drvp->PIO_mode, 0, channel); 1814 } else { 1815 sidetim |= piix_setup_sidetim_timings( 1816 drvp->PIO_mode, 0, channel); 1817 idetim =PIIX_IDETIM_SET(idetim, 1818 PIIX_IDETIM_SITRE, channel); 1819 } 1820 } 1821 if (idedma_ctl != 0) { 1822 /* Add software bits in status register */ 1823 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1824 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1825 idedma_ctl); 1826 } 1827 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1828 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1829 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1830 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1831 pciide_print_modes(cp); 1832 } 1833 1834 1835 /* setup ISP and RTC fields, based on mode */ 1836 static u_int32_t 1837 piix_setup_idetim_timings(mode, dma, channel) 1838 u_int8_t mode; 1839 u_int8_t dma; 1840 u_int8_t channel; 1841 { 1842 1843 if (dma) 1844 return PIIX_IDETIM_SET(0, 1845 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1846 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1847 channel); 1848 else 1849 return PIIX_IDETIM_SET(0, 1850 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1851 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1852 channel); 1853 } 1854 1855 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1856 static u_int32_t 1857 piix_setup_idetim_drvs(drvp) 1858 struct ata_drive_datas *drvp; 1859 { 1860 u_int32_t ret = 0; 1861 struct channel_softc *chp = drvp->chnl_softc; 1862 u_int8_t channel = chp->channel; 1863 u_int8_t drive = drvp->drive; 1864 1865 /* 1866 * If drive is using UDMA, timings setups are independant 1867 * So just check DMA and PIO here. 1868 */ 1869 if (drvp->drive_flags & DRIVE_DMA) { 1870 /* if mode = DMA mode 0, use compatible timings */ 1871 if ((drvp->drive_flags & DRIVE_DMA) && 1872 drvp->DMA_mode == 0) { 1873 drvp->PIO_mode = 0; 1874 return ret; 1875 } 1876 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1877 /* 1878 * PIO and DMA timings are the same, use fast timings for PIO 1879 * too, else use compat timings. 1880 */ 1881 if ((piix_isp_pio[drvp->PIO_mode] != 1882 piix_isp_dma[drvp->DMA_mode]) || 1883 (piix_rtc_pio[drvp->PIO_mode] != 1884 piix_rtc_dma[drvp->DMA_mode])) 1885 drvp->PIO_mode = 0; 1886 /* if PIO mode <= 2, use compat timings for PIO */ 1887 if (drvp->PIO_mode <= 2) { 1888 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1889 channel); 1890 return ret; 1891 } 1892 } 1893 1894 /* 1895 * Now setup PIO modes. If mode < 2, use compat timings. 1896 * Else enable fast timings. Enable IORDY and prefetch/post 1897 * if PIO mode >= 3. 1898 */ 1899 1900 if (drvp->PIO_mode < 2) 1901 return ret; 1902 1903 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1904 if (drvp->PIO_mode >= 3) { 1905 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1906 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1907 } 1908 return ret; 1909 } 1910 1911 /* setup values in SIDETIM registers, based on mode */ 1912 static u_int32_t 1913 piix_setup_sidetim_timings(mode, dma, channel) 1914 u_int8_t mode; 1915 u_int8_t dma; 1916 u_int8_t channel; 1917 { 1918 if (dma) 1919 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1920 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1921 else 1922 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1923 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1924 } 1925 1926 void 1927 amd7x6_chip_map(sc, pa) 1928 struct pciide_softc *sc; 1929 struct pci_attach_args *pa; 1930 { 1931 struct pciide_channel *cp; 1932 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1933 int channel; 1934 pcireg_t chanenable; 1935 bus_size_t cmdsize, ctlsize; 1936 1937 if (pciide_chipen(sc, pa) == 0) 1938 return; 1939 printf("%s: bus-master DMA support present", 1940 sc->sc_wdcdev.sc_dev.dv_xname); 1941 pciide_mapreg_dma(sc, pa); 1942 printf("\n"); 1943 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1944 WDC_CAPABILITY_MODE; 1945 if (sc->sc_dma_ok) { 1946 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1947 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1948 sc->sc_wdcdev.irqack = pciide_irqack; 1949 } 1950 sc->sc_wdcdev.PIO_cap = 4; 1951 sc->sc_wdcdev.DMA_cap = 2; 1952 1953 switch (sc->sc_pp->ide_product) { 1954 case PCI_PRODUCT_AMD_PBC766_IDE: 1955 case PCI_PRODUCT_AMD_PBC768_IDE: 1956 sc->sc_wdcdev.UDMA_cap = 5; 1957 break; 1958 default: 1959 sc->sc_wdcdev.UDMA_cap = 4; 1960 } 1961 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1962 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1963 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1964 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1965 1966 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1967 DEBUG_PROBE); 1968 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1969 cp = &sc->pciide_channels[channel]; 1970 if (pciide_chansetup(sc, channel, interface) == 0) 1971 continue; 1972 1973 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1974 printf("%s: %s channel ignored (disabled)\n", 1975 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1976 continue; 1977 } 1978 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1979 pciide_pci_intr); 1980 1981 if (pciide_chan_candisable(cp)) 1982 chanenable &= ~AMD7X6_CHAN_EN(channel); 1983 pciide_map_compat_intr(pa, cp, channel, interface); 1984 if (cp->hw_ok == 0) 1985 continue; 1986 1987 amd7x6_setup_channel(&cp->wdc_channel); 1988 } 1989 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1990 chanenable); 1991 return; 1992 } 1993 1994 void 1995 amd7x6_setup_channel(chp) 1996 struct channel_softc *chp; 1997 { 1998 u_int32_t udmatim_reg, datatim_reg; 1999 u_int8_t idedma_ctl; 2000 int mode, drive; 2001 struct ata_drive_datas *drvp; 2002 struct pciide_channel *cp = (struct pciide_channel*)chp; 2003 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2004 #ifndef PCIIDE_AMD756_ENABLEDMA 2005 int rev = PCI_REVISION( 2006 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2007 #endif 2008 2009 idedma_ctl = 0; 2010 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2011 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2012 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2013 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2014 2015 /* setup DMA if needed */ 2016 pciide_channel_dma_setup(cp); 2017 2018 for (drive = 0; drive < 2; drive++) { 2019 drvp = &chp->ch_drive[drive]; 2020 /* If no drive, skip */ 2021 if ((drvp->drive_flags & DRIVE) == 0) 2022 continue; 2023 /* add timing values, setup DMA if needed */ 2024 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2025 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2026 mode = drvp->PIO_mode; 2027 goto pio; 2028 } 2029 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2030 (drvp->drive_flags & DRIVE_UDMA)) { 2031 /* use Ultra/DMA */ 2032 drvp->drive_flags &= ~DRIVE_DMA; 2033 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2034 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2035 AMD7X6_UDMA_TIME(chp->channel, drive, 2036 amd7x6_udma_tim[drvp->UDMA_mode]); 2037 /* can use PIO timings, MW DMA unused */ 2038 mode = drvp->PIO_mode; 2039 } else { 2040 /* use Multiword DMA, but only if revision is OK */ 2041 drvp->drive_flags &= ~DRIVE_UDMA; 2042 #ifndef PCIIDE_AMD756_ENABLEDMA 2043 /* 2044 * The workaround doesn't seem to be necessary 2045 * with all drives, so it can be disabled by 2046 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2047 * triggered. 2048 */ 2049 if (sc->sc_pp->ide_product == 2050 PCI_PRODUCT_AMD_PBC756_IDE && 2051 AMD756_CHIPREV_DISABLEDMA(rev)) { 2052 printf("%s:%d:%d: multi-word DMA disabled due " 2053 "to chip revision\n", 2054 sc->sc_wdcdev.sc_dev.dv_xname, 2055 chp->channel, drive); 2056 mode = drvp->PIO_mode; 2057 drvp->drive_flags &= ~DRIVE_DMA; 2058 goto pio; 2059 } 2060 #endif 2061 /* mode = min(pio, dma+2) */ 2062 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2063 mode = drvp->PIO_mode; 2064 else 2065 mode = drvp->DMA_mode + 2; 2066 } 2067 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2068 2069 pio: /* setup PIO mode */ 2070 if (mode <= 2) { 2071 drvp->DMA_mode = 0; 2072 drvp->PIO_mode = 0; 2073 mode = 0; 2074 } else { 2075 drvp->PIO_mode = mode; 2076 drvp->DMA_mode = mode - 2; 2077 } 2078 datatim_reg |= 2079 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2080 amd7x6_pio_set[mode]) | 2081 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2082 amd7x6_pio_rec[mode]); 2083 } 2084 if (idedma_ctl != 0) { 2085 /* Add software bits in status register */ 2086 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2087 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2088 idedma_ctl); 2089 } 2090 pciide_print_modes(cp); 2091 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2092 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2093 } 2094 2095 void 2096 apollo_chip_map(sc, pa) 2097 struct pciide_softc *sc; 2098 struct pci_attach_args *pa; 2099 { 2100 struct pciide_channel *cp; 2101 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2102 int channel; 2103 u_int32_t ideconf; 2104 bus_size_t cmdsize, ctlsize; 2105 pcitag_t pcib_tag; 2106 pcireg_t pcib_id, pcib_class; 2107 2108 if (pciide_chipen(sc, pa) == 0) 2109 return; 2110 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2111 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2112 /* and read ID and rev of the ISA bridge */ 2113 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2114 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2115 printf(": VIA Technologies "); 2116 switch (PCI_PRODUCT(pcib_id)) { 2117 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2118 printf("VT82C586 (Apollo VP) "); 2119 if(PCI_REVISION(pcib_class) >= 0x02) { 2120 printf("ATA33 controller\n"); 2121 sc->sc_wdcdev.UDMA_cap = 2; 2122 } else { 2123 printf("controller\n"); 2124 sc->sc_wdcdev.UDMA_cap = 0; 2125 } 2126 break; 2127 case PCI_PRODUCT_VIATECH_VT82C596A: 2128 printf("VT82C596A (Apollo Pro) "); 2129 if (PCI_REVISION(pcib_class) >= 0x12) { 2130 printf("ATA66 controller\n"); 2131 sc->sc_wdcdev.UDMA_cap = 4; 2132 } else { 2133 printf("ATA33 controller\n"); 2134 sc->sc_wdcdev.UDMA_cap = 2; 2135 } 2136 break; 2137 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2138 printf("VT82C686A (Apollo KX133) "); 2139 if (PCI_REVISION(pcib_class) >= 0x40) { 2140 printf("ATA100 controller\n"); 2141 sc->sc_wdcdev.UDMA_cap = 5; 2142 } else { 2143 printf("ATA66 controller\n"); 2144 sc->sc_wdcdev.UDMA_cap = 4; 2145 } 2146 break; 2147 case PCI_PRODUCT_VIATECH_VT8233: 2148 printf("VT8233 ATA100 controller\n"); 2149 sc->sc_wdcdev.UDMA_cap = 5; 2150 break; 2151 default: 2152 printf("unknown ATA controller\n"); 2153 sc->sc_wdcdev.UDMA_cap = 0; 2154 } 2155 2156 printf("%s: bus-master DMA support present", 2157 sc->sc_wdcdev.sc_dev.dv_xname); 2158 pciide_mapreg_dma(sc, pa); 2159 printf("\n"); 2160 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2161 WDC_CAPABILITY_MODE; 2162 if (sc->sc_dma_ok) { 2163 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2164 sc->sc_wdcdev.irqack = pciide_irqack; 2165 if (sc->sc_wdcdev.UDMA_cap > 0) 2166 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2167 } 2168 sc->sc_wdcdev.PIO_cap = 4; 2169 sc->sc_wdcdev.DMA_cap = 2; 2170 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2171 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2172 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2173 2174 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2175 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2176 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2177 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2178 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2179 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2180 DEBUG_PROBE); 2181 2182 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2183 cp = &sc->pciide_channels[channel]; 2184 if (pciide_chansetup(sc, channel, interface) == 0) 2185 continue; 2186 2187 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2188 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2189 printf("%s: %s channel ignored (disabled)\n", 2190 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2191 continue; 2192 } 2193 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2194 pciide_pci_intr); 2195 if (cp->hw_ok == 0) 2196 continue; 2197 if (pciide_chan_candisable(cp)) { 2198 ideconf &= ~APO_IDECONF_EN(channel); 2199 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2200 ideconf); 2201 } 2202 pciide_map_compat_intr(pa, cp, channel, interface); 2203 2204 if (cp->hw_ok == 0) 2205 continue; 2206 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2207 } 2208 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2209 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2210 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2211 } 2212 2213 void 2214 apollo_setup_channel(chp) 2215 struct channel_softc *chp; 2216 { 2217 u_int32_t udmatim_reg, datatim_reg; 2218 u_int8_t idedma_ctl; 2219 int mode, drive; 2220 struct ata_drive_datas *drvp; 2221 struct pciide_channel *cp = (struct pciide_channel*)chp; 2222 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2223 2224 idedma_ctl = 0; 2225 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2226 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2227 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2228 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2229 2230 /* setup DMA if needed */ 2231 pciide_channel_dma_setup(cp); 2232 2233 for (drive = 0; drive < 2; drive++) { 2234 drvp = &chp->ch_drive[drive]; 2235 /* If no drive, skip */ 2236 if ((drvp->drive_flags & DRIVE) == 0) 2237 continue; 2238 /* add timing values, setup DMA if needed */ 2239 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2240 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2241 mode = drvp->PIO_mode; 2242 goto pio; 2243 } 2244 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2245 (drvp->drive_flags & DRIVE_UDMA)) { 2246 /* use Ultra/DMA */ 2247 drvp->drive_flags &= ~DRIVE_DMA; 2248 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2249 APO_UDMA_EN_MTH(chp->channel, drive); 2250 if (sc->sc_wdcdev.UDMA_cap == 5) { 2251 /* 686b */ 2252 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2253 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2254 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2255 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2256 /* 596b or 686a */ 2257 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2258 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2259 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2260 } else { 2261 /* 596a or 586b */ 2262 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2263 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2264 } 2265 /* can use PIO timings, MW DMA unused */ 2266 mode = drvp->PIO_mode; 2267 } else { 2268 /* use Multiword DMA */ 2269 drvp->drive_flags &= ~DRIVE_UDMA; 2270 /* mode = min(pio, dma+2) */ 2271 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2272 mode = drvp->PIO_mode; 2273 else 2274 mode = drvp->DMA_mode + 2; 2275 } 2276 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2277 2278 pio: /* setup PIO mode */ 2279 if (mode <= 2) { 2280 drvp->DMA_mode = 0; 2281 drvp->PIO_mode = 0; 2282 mode = 0; 2283 } else { 2284 drvp->PIO_mode = mode; 2285 drvp->DMA_mode = mode - 2; 2286 } 2287 datatim_reg |= 2288 APO_DATATIM_PULSE(chp->channel, drive, 2289 apollo_pio_set[mode]) | 2290 APO_DATATIM_RECOV(chp->channel, drive, 2291 apollo_pio_rec[mode]); 2292 } 2293 if (idedma_ctl != 0) { 2294 /* Add software bits in status register */ 2295 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2296 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2297 idedma_ctl); 2298 } 2299 pciide_print_modes(cp); 2300 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2301 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2302 } 2303 2304 void 2305 cmd_channel_map(pa, sc, channel) 2306 struct pci_attach_args *pa; 2307 struct pciide_softc *sc; 2308 int channel; 2309 { 2310 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2311 bus_size_t cmdsize, ctlsize; 2312 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2313 int interface, one_channel; 2314 2315 /* 2316 * The 0648/0649 can be told to identify as a RAID controller. 2317 * In this case, we have to fake interface 2318 */ 2319 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2320 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2321 PCIIDE_INTERFACE_SETTABLE(1); 2322 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2323 CMD_CONF_DSA1) 2324 interface |= PCIIDE_INTERFACE_PCI(0) | 2325 PCIIDE_INTERFACE_PCI(1); 2326 } else { 2327 interface = PCI_INTERFACE(pa->pa_class); 2328 } 2329 2330 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2331 cp->name = PCIIDE_CHANNEL_NAME(channel); 2332 cp->wdc_channel.channel = channel; 2333 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2334 2335 /* 2336 * Older CMD64X doesn't have independant channels 2337 */ 2338 switch (sc->sc_pp->ide_product) { 2339 case PCI_PRODUCT_CMDTECH_649: 2340 one_channel = 0; 2341 break; 2342 default: 2343 one_channel = 1; 2344 break; 2345 } 2346 2347 if (channel > 0 && one_channel) { 2348 cp->wdc_channel.ch_queue = 2349 sc->pciide_channels[0].wdc_channel.ch_queue; 2350 } else { 2351 cp->wdc_channel.ch_queue = 2352 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2353 } 2354 if (cp->wdc_channel.ch_queue == NULL) { 2355 printf("%s %s channel: " 2356 "can't allocate memory for command queue", 2357 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2358 return; 2359 } 2360 2361 printf("%s: %s channel %s to %s mode\n", 2362 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2363 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2364 "configured" : "wired", 2365 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2366 "native-PCI" : "compatibility"); 2367 2368 /* 2369 * with a CMD PCI64x, if we get here, the first channel is enabled: 2370 * there's no way to disable the first channel without disabling 2371 * the whole device 2372 */ 2373 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2374 printf("%s: %s channel ignored (disabled)\n", 2375 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2376 return; 2377 } 2378 2379 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2380 if (cp->hw_ok == 0) 2381 return; 2382 if (channel == 1) { 2383 if (pciide_chan_candisable(cp)) { 2384 ctrl &= ~CMD_CTRL_2PORT; 2385 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2386 CMD_CTRL, ctrl); 2387 } 2388 } 2389 pciide_map_compat_intr(pa, cp, channel, interface); 2390 } 2391 2392 int 2393 cmd_pci_intr(arg) 2394 void *arg; 2395 { 2396 struct pciide_softc *sc = arg; 2397 struct pciide_channel *cp; 2398 struct channel_softc *wdc_cp; 2399 int i, rv, crv; 2400 u_int32_t priirq, secirq; 2401 2402 rv = 0; 2403 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2404 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2405 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2406 cp = &sc->pciide_channels[i]; 2407 wdc_cp = &cp->wdc_channel; 2408 /* If a compat channel skip. */ 2409 if (cp->compat) 2410 continue; 2411 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2412 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2413 crv = wdcintr(wdc_cp); 2414 if (crv == 0) 2415 printf("%s:%d: bogus intr\n", 2416 sc->sc_wdcdev.sc_dev.dv_xname, i); 2417 else 2418 rv = 1; 2419 } 2420 } 2421 return rv; 2422 } 2423 2424 void 2425 cmd_chip_map(sc, pa) 2426 struct pciide_softc *sc; 2427 struct pci_attach_args *pa; 2428 { 2429 int channel; 2430 2431 /* 2432 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2433 * and base adresses registers can be disabled at 2434 * hardware level. In this case, the device is wired 2435 * in compat mode and its first channel is always enabled, 2436 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2437 * In fact, it seems that the first channel of the CMD PCI0640 2438 * can't be disabled. 2439 */ 2440 2441 #ifdef PCIIDE_CMD064x_DISABLE 2442 if (pciide_chipen(sc, pa) == 0) 2443 return; 2444 #endif 2445 2446 printf("%s: hardware does not support DMA\n", 2447 sc->sc_wdcdev.sc_dev.dv_xname); 2448 sc->sc_dma_ok = 0; 2449 2450 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2451 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2452 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2453 2454 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2455 cmd_channel_map(pa, sc, channel); 2456 } 2457 } 2458 2459 void 2460 cmd0643_9_chip_map(sc, pa) 2461 struct pciide_softc *sc; 2462 struct pci_attach_args *pa; 2463 { 2464 struct pciide_channel *cp; 2465 int channel; 2466 int rev = PCI_REVISION( 2467 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2468 2469 /* 2470 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2471 * and base adresses registers can be disabled at 2472 * hardware level. In this case, the device is wired 2473 * in compat mode and its first channel is always enabled, 2474 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2475 * In fact, it seems that the first channel of the CMD PCI0640 2476 * can't be disabled. 2477 */ 2478 2479 #ifdef PCIIDE_CMD064x_DISABLE 2480 if (pciide_chipen(sc, pa) == 0) 2481 return; 2482 #endif 2483 printf("%s: bus-master DMA support present", 2484 sc->sc_wdcdev.sc_dev.dv_xname); 2485 pciide_mapreg_dma(sc, pa); 2486 printf("\n"); 2487 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2488 WDC_CAPABILITY_MODE; 2489 if (sc->sc_dma_ok) { 2490 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2491 switch (sc->sc_pp->ide_product) { 2492 case PCI_PRODUCT_CMDTECH_649: 2493 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2494 sc->sc_wdcdev.UDMA_cap = 5; 2495 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2496 break; 2497 case PCI_PRODUCT_CMDTECH_648: 2498 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2499 sc->sc_wdcdev.UDMA_cap = 4; 2500 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2501 break; 2502 case PCI_PRODUCT_CMDTECH_646: 2503 if (rev >= CMD0646U2_REV) { 2504 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2505 sc->sc_wdcdev.UDMA_cap = 2; 2506 } else if (rev >= CMD0646U_REV) { 2507 /* 2508 * Linux's driver claims that the 646U is broken 2509 * with UDMA. Only enable it if we know what we're 2510 * doing 2511 */ 2512 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2513 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2514 sc->sc_wdcdev.UDMA_cap = 2; 2515 #endif 2516 /* explicitly disable UDMA */ 2517 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2518 CMD_UDMATIM(0), 0); 2519 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2520 CMD_UDMATIM(1), 0); 2521 } 2522 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2523 break; 2524 default: 2525 sc->sc_wdcdev.irqack = pciide_irqack; 2526 } 2527 } 2528 2529 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2530 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2531 sc->sc_wdcdev.PIO_cap = 4; 2532 sc->sc_wdcdev.DMA_cap = 2; 2533 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2534 2535 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2536 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2537 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2538 DEBUG_PROBE); 2539 2540 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2541 cp = &sc->pciide_channels[channel]; 2542 cmd_channel_map(pa, sc, channel); 2543 if (cp->hw_ok == 0) 2544 continue; 2545 cmd0643_9_setup_channel(&cp->wdc_channel); 2546 } 2547 /* 2548 * note - this also makes sure we clear the irq disable and reset 2549 * bits 2550 */ 2551 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2552 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2553 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2554 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2555 DEBUG_PROBE); 2556 } 2557 2558 void 2559 cmd0643_9_setup_channel(chp) 2560 struct channel_softc *chp; 2561 { 2562 struct ata_drive_datas *drvp; 2563 u_int8_t tim; 2564 u_int32_t idedma_ctl, udma_reg; 2565 int drive; 2566 struct pciide_channel *cp = (struct pciide_channel*)chp; 2567 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2568 2569 idedma_ctl = 0; 2570 /* setup DMA if needed */ 2571 pciide_channel_dma_setup(cp); 2572 2573 for (drive = 0; drive < 2; drive++) { 2574 drvp = &chp->ch_drive[drive]; 2575 /* If no drive, skip */ 2576 if ((drvp->drive_flags & DRIVE) == 0) 2577 continue; 2578 /* add timing values, setup DMA if needed */ 2579 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2580 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2581 if (drvp->drive_flags & DRIVE_UDMA) { 2582 /* UltraDMA on a 646U2, 0648 or 0649 */ 2583 drvp->drive_flags &= ~DRIVE_DMA; 2584 udma_reg = pciide_pci_read(sc->sc_pc, 2585 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2586 if (drvp->UDMA_mode > 2 && 2587 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2588 CMD_BICSR) & 2589 CMD_BICSR_80(chp->channel)) == 0) 2590 drvp->UDMA_mode = 2; 2591 if (drvp->UDMA_mode > 2) 2592 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2593 else if (sc->sc_wdcdev.UDMA_cap > 2) 2594 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2595 udma_reg |= CMD_UDMATIM_UDMA(drive); 2596 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2597 CMD_UDMATIM_TIM_OFF(drive)); 2598 udma_reg |= 2599 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2600 CMD_UDMATIM_TIM_OFF(drive)); 2601 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2602 CMD_UDMATIM(chp->channel), udma_reg); 2603 } else { 2604 /* 2605 * use Multiword DMA. 2606 * Timings will be used for both PIO and DMA, 2607 * so adjust DMA mode if needed 2608 * if we have a 0646U2/8/9, turn off UDMA 2609 */ 2610 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2611 udma_reg = pciide_pci_read(sc->sc_pc, 2612 sc->sc_tag, 2613 CMD_UDMATIM(chp->channel)); 2614 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2615 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2616 CMD_UDMATIM(chp->channel), 2617 udma_reg); 2618 } 2619 if (drvp->PIO_mode >= 3 && 2620 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2621 drvp->DMA_mode = drvp->PIO_mode - 2; 2622 } 2623 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2624 } 2625 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2626 } 2627 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2628 CMD_DATA_TIM(chp->channel, drive), tim); 2629 } 2630 if (idedma_ctl != 0) { 2631 /* Add software bits in status register */ 2632 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2633 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2634 idedma_ctl); 2635 } 2636 pciide_print_modes(cp); 2637 } 2638 2639 void 2640 cmd646_9_irqack(chp) 2641 struct channel_softc *chp; 2642 { 2643 u_int32_t priirq, secirq; 2644 struct pciide_channel *cp = (struct pciide_channel*)chp; 2645 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2646 2647 if (chp->channel == 0) { 2648 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2649 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2650 } else { 2651 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2652 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2653 } 2654 pciide_irqack(chp); 2655 } 2656 2657 void 2658 cy693_chip_map(sc, pa) 2659 struct pciide_softc *sc; 2660 struct pci_attach_args *pa; 2661 { 2662 struct pciide_channel *cp; 2663 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2664 bus_size_t cmdsize, ctlsize; 2665 2666 if (pciide_chipen(sc, pa) == 0) 2667 return; 2668 /* 2669 * this chip has 2 PCI IDE functions, one for primary and one for 2670 * secondary. So we need to call pciide_mapregs_compat() with 2671 * the real channel 2672 */ 2673 if (pa->pa_function == 1) { 2674 sc->sc_cy_compatchan = 0; 2675 } else if (pa->pa_function == 2) { 2676 sc->sc_cy_compatchan = 1; 2677 } else { 2678 printf("%s: unexpected PCI function %d\n", 2679 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2680 return; 2681 } 2682 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2683 printf("%s: bus-master DMA support present", 2684 sc->sc_wdcdev.sc_dev.dv_xname); 2685 pciide_mapreg_dma(sc, pa); 2686 } else { 2687 printf("%s: hardware does not support DMA", 2688 sc->sc_wdcdev.sc_dev.dv_xname); 2689 sc->sc_dma_ok = 0; 2690 } 2691 printf("\n"); 2692 2693 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2694 if (sc->sc_cy_handle == NULL) { 2695 printf("%s: unable to map hyperCache control registers\n", 2696 sc->sc_wdcdev.sc_dev.dv_xname); 2697 sc->sc_dma_ok = 0; 2698 } 2699 2700 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2701 WDC_CAPABILITY_MODE; 2702 if (sc->sc_dma_ok) { 2703 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2704 sc->sc_wdcdev.irqack = pciide_irqack; 2705 } 2706 sc->sc_wdcdev.PIO_cap = 4; 2707 sc->sc_wdcdev.DMA_cap = 2; 2708 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2709 2710 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2711 sc->sc_wdcdev.nchannels = 1; 2712 2713 /* Only one channel for this chip; if we are here it's enabled */ 2714 cp = &sc->pciide_channels[0]; 2715 sc->wdc_chanarray[0] = &cp->wdc_channel; 2716 cp->name = PCIIDE_CHANNEL_NAME(0); 2717 cp->wdc_channel.channel = 0; 2718 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2719 cp->wdc_channel.ch_queue = 2720 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2721 if (cp->wdc_channel.ch_queue == NULL) { 2722 printf("%s primary channel: " 2723 "can't allocate memory for command queue", 2724 sc->sc_wdcdev.sc_dev.dv_xname); 2725 return; 2726 } 2727 printf("%s: primary channel %s to ", 2728 sc->sc_wdcdev.sc_dev.dv_xname, 2729 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2730 "configured" : "wired"); 2731 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2732 printf("native-PCI"); 2733 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2734 pciide_pci_intr); 2735 } else { 2736 printf("compatibility"); 2737 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2738 &cmdsize, &ctlsize); 2739 } 2740 printf(" mode\n"); 2741 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2742 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2743 wdcattach(&cp->wdc_channel); 2744 if (pciide_chan_candisable(cp)) { 2745 pci_conf_write(sc->sc_pc, sc->sc_tag, 2746 PCI_COMMAND_STATUS_REG, 0); 2747 } 2748 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2749 if (cp->hw_ok == 0) 2750 return; 2751 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2752 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2753 cy693_setup_channel(&cp->wdc_channel); 2754 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2755 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2756 } 2757 2758 void 2759 cy693_setup_channel(chp) 2760 struct channel_softc *chp; 2761 { 2762 struct ata_drive_datas *drvp; 2763 int drive; 2764 u_int32_t cy_cmd_ctrl; 2765 u_int32_t idedma_ctl; 2766 struct pciide_channel *cp = (struct pciide_channel*)chp; 2767 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2768 int dma_mode = -1; 2769 2770 cy_cmd_ctrl = idedma_ctl = 0; 2771 2772 /* setup DMA if needed */ 2773 pciide_channel_dma_setup(cp); 2774 2775 for (drive = 0; drive < 2; drive++) { 2776 drvp = &chp->ch_drive[drive]; 2777 /* If no drive, skip */ 2778 if ((drvp->drive_flags & DRIVE) == 0) 2779 continue; 2780 /* add timing values, setup DMA if needed */ 2781 if (drvp->drive_flags & DRIVE_DMA) { 2782 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2783 /* use Multiword DMA */ 2784 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2785 dma_mode = drvp->DMA_mode; 2786 } 2787 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2788 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2789 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2790 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2791 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2792 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2793 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2794 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2795 } 2796 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2797 chp->ch_drive[0].DMA_mode = dma_mode; 2798 chp->ch_drive[1].DMA_mode = dma_mode; 2799 2800 if (dma_mode == -1) 2801 dma_mode = 0; 2802 2803 if (sc->sc_cy_handle != NULL) { 2804 /* Note: `multiple' is implied. */ 2805 cy82c693_write(sc->sc_cy_handle, 2806 (sc->sc_cy_compatchan == 0) ? 2807 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2808 } 2809 2810 pciide_print_modes(cp); 2811 2812 if (idedma_ctl != 0) { 2813 /* Add software bits in status register */ 2814 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2815 IDEDMA_CTL, idedma_ctl); 2816 } 2817 } 2818 2819 static int 2820 sis_hostbr_match(pa) 2821 struct pci_attach_args *pa; 2822 { 2823 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2824 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2825 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2826 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2827 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2828 } 2829 2830 void 2831 sis_chip_map(sc, pa) 2832 struct pciide_softc *sc; 2833 struct pci_attach_args *pa; 2834 { 2835 struct pciide_channel *cp; 2836 int channel; 2837 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2838 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2839 pcireg_t rev = PCI_REVISION(pa->pa_class); 2840 bus_size_t cmdsize, ctlsize; 2841 pcitag_t pchb_tag; 2842 pcireg_t pchb_id, pchb_class; 2843 2844 if (pciide_chipen(sc, pa) == 0) 2845 return; 2846 printf("%s: bus-master DMA support present", 2847 sc->sc_wdcdev.sc_dev.dv_xname); 2848 pciide_mapreg_dma(sc, pa); 2849 printf("\n"); 2850 2851 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2852 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2853 /* and read ID and rev of the ISA bridge */ 2854 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2855 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2856 2857 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2858 WDC_CAPABILITY_MODE; 2859 if (sc->sc_dma_ok) { 2860 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2861 sc->sc_wdcdev.irqack = pciide_irqack; 2862 /* 2863 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2864 * have problems with UDMA (info provided by Christos) 2865 */ 2866 if (rev >= 0xd0 && 2867 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2868 PCI_REVISION(pchb_class) >= 0x03)) 2869 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2870 } 2871 2872 sc->sc_wdcdev.PIO_cap = 4; 2873 sc->sc_wdcdev.DMA_cap = 2; 2874 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2875 /* 2876 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2877 * chipsets. 2878 */ 2879 sc->sc_wdcdev.UDMA_cap = 2880 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2881 sc->sc_wdcdev.set_modes = sis_setup_channel; 2882 2883 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2884 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2885 2886 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2887 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2888 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2889 2890 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2891 cp = &sc->pciide_channels[channel]; 2892 if (pciide_chansetup(sc, channel, interface) == 0) 2893 continue; 2894 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2895 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2896 printf("%s: %s channel ignored (disabled)\n", 2897 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2898 continue; 2899 } 2900 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2901 pciide_pci_intr); 2902 if (cp->hw_ok == 0) 2903 continue; 2904 if (pciide_chan_candisable(cp)) { 2905 if (channel == 0) 2906 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2907 else 2908 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2909 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2910 sis_ctr0); 2911 } 2912 pciide_map_compat_intr(pa, cp, channel, interface); 2913 if (cp->hw_ok == 0) 2914 continue; 2915 sis_setup_channel(&cp->wdc_channel); 2916 } 2917 } 2918 2919 void 2920 sis_setup_channel(chp) 2921 struct channel_softc *chp; 2922 { 2923 struct ata_drive_datas *drvp; 2924 int drive; 2925 u_int32_t sis_tim; 2926 u_int32_t idedma_ctl; 2927 struct pciide_channel *cp = (struct pciide_channel*)chp; 2928 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2929 2930 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2931 "channel %d 0x%x\n", chp->channel, 2932 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2933 DEBUG_PROBE); 2934 sis_tim = 0; 2935 idedma_ctl = 0; 2936 /* setup DMA if needed */ 2937 pciide_channel_dma_setup(cp); 2938 2939 for (drive = 0; drive < 2; drive++) { 2940 drvp = &chp->ch_drive[drive]; 2941 /* If no drive, skip */ 2942 if ((drvp->drive_flags & DRIVE) == 0) 2943 continue; 2944 /* add timing values, setup DMA if needed */ 2945 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2946 (drvp->drive_flags & DRIVE_UDMA) == 0) 2947 goto pio; 2948 2949 if (drvp->drive_flags & DRIVE_UDMA) { 2950 /* use Ultra/DMA */ 2951 drvp->drive_flags &= ~DRIVE_DMA; 2952 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2953 SIS_TIM_UDMA_TIME_OFF(drive); 2954 sis_tim |= SIS_TIM_UDMA_EN(drive); 2955 } else { 2956 /* 2957 * use Multiword DMA 2958 * Timings will be used for both PIO and DMA, 2959 * so adjust DMA mode if needed 2960 */ 2961 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2962 drvp->PIO_mode = drvp->DMA_mode + 2; 2963 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2964 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2965 drvp->PIO_mode - 2 : 0; 2966 if (drvp->DMA_mode == 0) 2967 drvp->PIO_mode = 0; 2968 } 2969 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2970 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2971 SIS_TIM_ACT_OFF(drive); 2972 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2973 SIS_TIM_REC_OFF(drive); 2974 } 2975 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2976 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2977 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2978 if (idedma_ctl != 0) { 2979 /* Add software bits in status register */ 2980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2981 IDEDMA_CTL, idedma_ctl); 2982 } 2983 pciide_print_modes(cp); 2984 } 2985 2986 static int 2987 acer_isabr_match(pa) 2988 struct pci_attach_args *pa; 2989 { 2990 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 2991 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 2992 } 2993 2994 void 2995 acer_chip_map(sc, pa) 2996 struct pciide_softc *sc; 2997 struct pci_attach_args *pa; 2998 { 2999 struct pci_attach_args isa_pa; 3000 struct pciide_channel *cp; 3001 int channel; 3002 pcireg_t cr, interface; 3003 bus_size_t cmdsize, ctlsize; 3004 pcireg_t rev = PCI_REVISION(pa->pa_class); 3005 3006 if (pciide_chipen(sc, pa) == 0) 3007 return; 3008 printf("%s: bus-master DMA support present", 3009 sc->sc_wdcdev.sc_dev.dv_xname); 3010 pciide_mapreg_dma(sc, pa); 3011 printf("\n"); 3012 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3013 WDC_CAPABILITY_MODE; 3014 if (sc->sc_dma_ok) { 3015 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3016 if (rev >= 0x20) { 3017 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3018 if (rev >= 0xC4) 3019 sc->sc_wdcdev.UDMA_cap = 5; 3020 else if (rev >= 0xC2) 3021 sc->sc_wdcdev.UDMA_cap = 4; 3022 else 3023 sc->sc_wdcdev.UDMA_cap = 2; 3024 } 3025 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3026 sc->sc_wdcdev.irqack = pciide_irqack; 3027 } 3028 3029 sc->sc_wdcdev.PIO_cap = 4; 3030 sc->sc_wdcdev.DMA_cap = 2; 3031 sc->sc_wdcdev.set_modes = acer_setup_channel; 3032 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3033 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3034 3035 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3036 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3037 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3038 3039 /* Enable "microsoft register bits" R/W. */ 3040 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3041 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3042 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3043 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3044 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3045 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3046 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3047 ~ACER_CHANSTATUSREGS_RO); 3048 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3049 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3050 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3051 /* Don't use cr, re-read the real register content instead */ 3052 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3053 PCI_CLASS_REG)); 3054 3055 /* From linux: enable "Cable Detection" */ 3056 if (rev >= 0xC2) { 3057 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3058 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3059 | ACER_0x4B_CDETECT); 3060 /* set south-bridge's enable bit, m1533, 0x79 */ 3061 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 3062 printf("%s: can't find PCI/ISA bridge, downgrading " 3063 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 3064 sc->sc_wdcdev.UDMA_cap = 2; 3065 } else { 3066 if (rev == 0xC2) 3067 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3068 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3069 ACER_0x79, 3070 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3071 ACER_0x79) 3072 | ACER_0x79_REVC2_EN); 3073 else 3074 /* 1553/1535 (m1533, 0x79, bit 1) */ 3075 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3076 ACER_0x79, 3077 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3078 ACER_0x79) 3079 | ACER_0x79_EN); 3080 } 3081 } 3082 3083 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3084 cp = &sc->pciide_channels[channel]; 3085 if (pciide_chansetup(sc, channel, interface) == 0) 3086 continue; 3087 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3088 printf("%s: %s channel ignored (disabled)\n", 3089 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3090 continue; 3091 } 3092 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3093 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3094 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3095 if (cp->hw_ok == 0) 3096 continue; 3097 if (pciide_chan_candisable(cp)) { 3098 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3099 pci_conf_write(sc->sc_pc, sc->sc_tag, 3100 PCI_CLASS_REG, cr); 3101 } 3102 pciide_map_compat_intr(pa, cp, channel, interface); 3103 acer_setup_channel(&cp->wdc_channel); 3104 } 3105 } 3106 3107 void 3108 acer_setup_channel(chp) 3109 struct channel_softc *chp; 3110 { 3111 struct ata_drive_datas *drvp; 3112 int drive; 3113 u_int32_t acer_fifo_udma; 3114 u_int32_t idedma_ctl; 3115 struct pciide_channel *cp = (struct pciide_channel*)chp; 3116 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3117 3118 idedma_ctl = 0; 3119 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3120 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3121 acer_fifo_udma), DEBUG_PROBE); 3122 /* setup DMA if needed */ 3123 pciide_channel_dma_setup(cp); 3124 3125 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3126 DRIVE_UDMA) { /* check 80 pins cable */ 3127 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3128 ACER_0x4A_80PIN(chp->channel)) { 3129 if (chp->ch_drive[0].UDMA_mode > 2) 3130 chp->ch_drive[0].UDMA_mode = 2; 3131 if (chp->ch_drive[1].UDMA_mode > 2) 3132 chp->ch_drive[1].UDMA_mode = 2; 3133 } 3134 } 3135 3136 for (drive = 0; drive < 2; drive++) { 3137 drvp = &chp->ch_drive[drive]; 3138 /* If no drive, skip */ 3139 if ((drvp->drive_flags & DRIVE) == 0) 3140 continue; 3141 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3142 "channel %d drive %d 0x%x\n", chp->channel, drive, 3143 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3144 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3145 /* clear FIFO/DMA mode */ 3146 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3147 ACER_UDMA_EN(chp->channel, drive) | 3148 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3149 3150 /* add timing values, setup DMA if needed */ 3151 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3152 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3153 acer_fifo_udma |= 3154 ACER_FTH_OPL(chp->channel, drive, 0x1); 3155 goto pio; 3156 } 3157 3158 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3159 if (drvp->drive_flags & DRIVE_UDMA) { 3160 /* use Ultra/DMA */ 3161 drvp->drive_flags &= ~DRIVE_DMA; 3162 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3163 acer_fifo_udma |= 3164 ACER_UDMA_TIM(chp->channel, drive, 3165 acer_udma[drvp->UDMA_mode]); 3166 /* XXX disable if one drive < UDMA3 ? */ 3167 if (drvp->UDMA_mode >= 3) { 3168 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3169 ACER_0x4B, 3170 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3171 ACER_0x4B) | ACER_0x4B_UDMA66); 3172 } 3173 } else { 3174 /* 3175 * use Multiword DMA 3176 * Timings will be used for both PIO and DMA, 3177 * so adjust DMA mode if needed 3178 */ 3179 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3180 drvp->PIO_mode = drvp->DMA_mode + 2; 3181 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3182 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3183 drvp->PIO_mode - 2 : 0; 3184 if (drvp->DMA_mode == 0) 3185 drvp->PIO_mode = 0; 3186 } 3187 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3188 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3189 ACER_IDETIM(chp->channel, drive), 3190 acer_pio[drvp->PIO_mode]); 3191 } 3192 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3193 acer_fifo_udma), DEBUG_PROBE); 3194 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3195 if (idedma_ctl != 0) { 3196 /* Add software bits in status register */ 3197 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3198 IDEDMA_CTL, idedma_ctl); 3199 } 3200 pciide_print_modes(cp); 3201 } 3202 3203 int 3204 acer_pci_intr(arg) 3205 void *arg; 3206 { 3207 struct pciide_softc *sc = arg; 3208 struct pciide_channel *cp; 3209 struct channel_softc *wdc_cp; 3210 int i, rv, crv; 3211 u_int32_t chids; 3212 3213 rv = 0; 3214 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3215 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3216 cp = &sc->pciide_channels[i]; 3217 wdc_cp = &cp->wdc_channel; 3218 /* If a compat channel skip. */ 3219 if (cp->compat) 3220 continue; 3221 if (chids & ACER_CHIDS_INT(i)) { 3222 crv = wdcintr(wdc_cp); 3223 if (crv == 0) 3224 printf("%s:%d: bogus intr\n", 3225 sc->sc_wdcdev.sc_dev.dv_xname, i); 3226 else 3227 rv = 1; 3228 } 3229 } 3230 return rv; 3231 } 3232 3233 void 3234 hpt_chip_map(sc, pa) 3235 struct pciide_softc *sc; 3236 struct pci_attach_args *pa; 3237 { 3238 struct pciide_channel *cp; 3239 int i, compatchan, revision; 3240 pcireg_t interface; 3241 bus_size_t cmdsize, ctlsize; 3242 3243 if (pciide_chipen(sc, pa) == 0) 3244 return; 3245 revision = PCI_REVISION(pa->pa_class); 3246 printf(": Triones/Highpoint "); 3247 if (revision == HPT370_REV) 3248 printf("HPT370 IDE Controller\n"); 3249 else if (revision == HPT370A_REV) 3250 printf("HPT370A IDE Controller\n"); 3251 else if (revision == HPT366_REV) 3252 printf("HPT366 IDE Controller\n"); 3253 else 3254 printf("unknown HPT IDE controller rev %d\n", revision); 3255 3256 /* 3257 * when the chip is in native mode it identifies itself as a 3258 * 'misc mass storage'. Fake interface in this case. 3259 */ 3260 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3261 interface = PCI_INTERFACE(pa->pa_class); 3262 } else { 3263 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3264 PCIIDE_INTERFACE_PCI(0); 3265 if (revision == HPT370_REV || revision == HPT370A_REV) 3266 interface |= PCIIDE_INTERFACE_PCI(1); 3267 } 3268 3269 printf("%s: bus-master DMA support present", 3270 sc->sc_wdcdev.sc_dev.dv_xname); 3271 pciide_mapreg_dma(sc, pa); 3272 printf("\n"); 3273 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3274 WDC_CAPABILITY_MODE; 3275 if (sc->sc_dma_ok) { 3276 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3277 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3278 sc->sc_wdcdev.irqack = pciide_irqack; 3279 } 3280 sc->sc_wdcdev.PIO_cap = 4; 3281 sc->sc_wdcdev.DMA_cap = 2; 3282 3283 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3284 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3285 if (revision == HPT366_REV) { 3286 sc->sc_wdcdev.UDMA_cap = 4; 3287 /* 3288 * The 366 has 2 PCI IDE functions, one for primary and one 3289 * for secondary. So we need to call pciide_mapregs_compat() 3290 * with the real channel 3291 */ 3292 if (pa->pa_function == 0) { 3293 compatchan = 0; 3294 } else if (pa->pa_function == 1) { 3295 compatchan = 1; 3296 } else { 3297 printf("%s: unexpected PCI function %d\n", 3298 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3299 return; 3300 } 3301 sc->sc_wdcdev.nchannels = 1; 3302 } else { 3303 sc->sc_wdcdev.nchannels = 2; 3304 sc->sc_wdcdev.UDMA_cap = 5; 3305 } 3306 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3307 cp = &sc->pciide_channels[i]; 3308 if (sc->sc_wdcdev.nchannels > 1) { 3309 compatchan = i; 3310 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3311 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3312 printf("%s: %s channel ignored (disabled)\n", 3313 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3314 continue; 3315 } 3316 } 3317 if (pciide_chansetup(sc, i, interface) == 0) 3318 continue; 3319 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3320 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3321 &ctlsize, hpt_pci_intr); 3322 } else { 3323 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3324 &cmdsize, &ctlsize); 3325 } 3326 if (cp->hw_ok == 0) 3327 return; 3328 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3329 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3330 wdcattach(&cp->wdc_channel); 3331 hpt_setup_channel(&cp->wdc_channel); 3332 } 3333 if (revision == HPT370_REV || revision == HPT370A_REV) { 3334 /* 3335 * HPT370_REV has a bit to disable interrupts, make sure 3336 * to clear it 3337 */ 3338 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3339 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3340 ~HPT_CSEL_IRQDIS); 3341 } 3342 return; 3343 } 3344 3345 void 3346 hpt_setup_channel(chp) 3347 struct channel_softc *chp; 3348 { 3349 struct ata_drive_datas *drvp; 3350 int drive; 3351 int cable; 3352 u_int32_t before, after; 3353 u_int32_t idedma_ctl; 3354 struct pciide_channel *cp = (struct pciide_channel*)chp; 3355 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3356 3357 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3358 3359 /* setup DMA if needed */ 3360 pciide_channel_dma_setup(cp); 3361 3362 idedma_ctl = 0; 3363 3364 /* Per drive settings */ 3365 for (drive = 0; drive < 2; drive++) { 3366 drvp = &chp->ch_drive[drive]; 3367 /* If no drive, skip */ 3368 if ((drvp->drive_flags & DRIVE) == 0) 3369 continue; 3370 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3371 HPT_IDETIM(chp->channel, drive)); 3372 3373 /* add timing values, setup DMA if needed */ 3374 if (drvp->drive_flags & DRIVE_UDMA) { 3375 /* use Ultra/DMA */ 3376 drvp->drive_flags &= ~DRIVE_DMA; 3377 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3378 drvp->UDMA_mode > 2) 3379 drvp->UDMA_mode = 2; 3380 after = (sc->sc_wdcdev.nchannels == 2) ? 3381 hpt370_udma[drvp->UDMA_mode] : 3382 hpt366_udma[drvp->UDMA_mode]; 3383 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3384 } else if (drvp->drive_flags & DRIVE_DMA) { 3385 /* 3386 * use Multiword DMA. 3387 * Timings will be used for both PIO and DMA, so adjust 3388 * DMA mode if needed 3389 */ 3390 if (drvp->PIO_mode >= 3 && 3391 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3392 drvp->DMA_mode = drvp->PIO_mode - 2; 3393 } 3394 after = (sc->sc_wdcdev.nchannels == 2) ? 3395 hpt370_dma[drvp->DMA_mode] : 3396 hpt366_dma[drvp->DMA_mode]; 3397 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3398 } else { 3399 /* PIO only */ 3400 after = (sc->sc_wdcdev.nchannels == 2) ? 3401 hpt370_pio[drvp->PIO_mode] : 3402 hpt366_pio[drvp->PIO_mode]; 3403 } 3404 pci_conf_write(sc->sc_pc, sc->sc_tag, 3405 HPT_IDETIM(chp->channel, drive), after); 3406 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3407 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3408 after, before), DEBUG_PROBE); 3409 } 3410 if (idedma_ctl != 0) { 3411 /* Add software bits in status register */ 3412 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3413 IDEDMA_CTL, idedma_ctl); 3414 } 3415 pciide_print_modes(cp); 3416 } 3417 3418 int 3419 hpt_pci_intr(arg) 3420 void *arg; 3421 { 3422 struct pciide_softc *sc = arg; 3423 struct pciide_channel *cp; 3424 struct channel_softc *wdc_cp; 3425 int rv = 0; 3426 int dmastat, i, crv; 3427 3428 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3429 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3430 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3431 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3432 IDEDMA_CTL_INTR) 3433 continue; 3434 cp = &sc->pciide_channels[i]; 3435 wdc_cp = &cp->wdc_channel; 3436 crv = wdcintr(wdc_cp); 3437 if (crv == 0) { 3438 printf("%s:%d: bogus intr\n", 3439 sc->sc_wdcdev.sc_dev.dv_xname, i); 3440 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3441 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3442 } else 3443 rv = 1; 3444 } 3445 return rv; 3446 } 3447 3448 3449 /* Macros to test product */ 3450 #define PDC_IS_262(sc) \ 3451 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3452 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3453 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3454 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3455 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3456 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3457 #define PDC_IS_265(sc) \ 3458 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3459 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3460 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3461 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3462 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3463 #define PDC_IS_268(sc) \ 3464 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3465 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3466 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3467 3468 void 3469 pdc202xx_chip_map(sc, pa) 3470 struct pciide_softc *sc; 3471 struct pci_attach_args *pa; 3472 { 3473 struct pciide_channel *cp; 3474 int channel; 3475 pcireg_t interface, st, mode; 3476 bus_size_t cmdsize, ctlsize; 3477 3478 if (!PDC_IS_268(sc)) { 3479 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3480 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3481 st), DEBUG_PROBE); 3482 } 3483 if (pciide_chipen(sc, pa) == 0) 3484 return; 3485 3486 /* turn off RAID mode */ 3487 if (!PDC_IS_268(sc)) 3488 st &= ~PDC2xx_STATE_IDERAID; 3489 3490 /* 3491 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3492 * mode. We have to fake interface 3493 */ 3494 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3495 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3496 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3497 3498 printf("%s: bus-master DMA support present", 3499 sc->sc_wdcdev.sc_dev.dv_xname); 3500 pciide_mapreg_dma(sc, pa); 3501 printf("\n"); 3502 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3503 WDC_CAPABILITY_MODE; 3504 if (sc->sc_dma_ok) { 3505 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3506 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3507 sc->sc_wdcdev.irqack = pciide_irqack; 3508 } 3509 sc->sc_wdcdev.PIO_cap = 4; 3510 sc->sc_wdcdev.DMA_cap = 2; 3511 if (PDC_IS_265(sc)) 3512 sc->sc_wdcdev.UDMA_cap = 5; 3513 else if (PDC_IS_262(sc)) 3514 sc->sc_wdcdev.UDMA_cap = 4; 3515 else 3516 sc->sc_wdcdev.UDMA_cap = 2; 3517 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3518 pdc20268_setup_channel : pdc202xx_setup_channel; 3519 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3520 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3521 3522 if (!PDC_IS_268(sc)) { 3523 /* setup failsafe defaults */ 3524 mode = 0; 3525 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3526 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3527 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3528 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3529 for (channel = 0; 3530 channel < sc->sc_wdcdev.nchannels; 3531 channel++) { 3532 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3533 "drive 0 initial timings 0x%x, now 0x%x\n", 3534 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3535 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3536 DEBUG_PROBE); 3537 pci_conf_write(sc->sc_pc, sc->sc_tag, 3538 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3539 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3540 "drive 1 initial timings 0x%x, now 0x%x\n", 3541 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3542 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3543 pci_conf_write(sc->sc_pc, sc->sc_tag, 3544 PDC2xx_TIM(channel, 1), mode); 3545 } 3546 3547 mode = PDC2xx_SCR_DMA; 3548 if (PDC_IS_262(sc)) { 3549 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3550 } else { 3551 /* the BIOS set it up this way */ 3552 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3553 } 3554 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3555 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3556 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3557 "now 0x%x\n", 3558 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3559 PDC2xx_SCR), 3560 mode), DEBUG_PROBE); 3561 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3562 PDC2xx_SCR, mode); 3563 3564 /* controller initial state register is OK even without BIOS */ 3565 /* Set DMA mode to IDE DMA compatibility */ 3566 mode = 3567 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3568 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3569 DEBUG_PROBE); 3570 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3571 mode | 0x1); 3572 mode = 3573 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3574 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3575 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3576 mode | 0x1); 3577 } 3578 3579 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3580 cp = &sc->pciide_channels[channel]; 3581 if (pciide_chansetup(sc, channel, interface) == 0) 3582 continue; 3583 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3584 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3585 printf("%s: %s channel ignored (disabled)\n", 3586 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3587 continue; 3588 } 3589 if (PDC_IS_265(sc)) 3590 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3591 pdc20265_pci_intr); 3592 else 3593 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3594 pdc202xx_pci_intr); 3595 if (cp->hw_ok == 0) 3596 continue; 3597 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3598 st &= ~(PDC_IS_262(sc) ? 3599 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3600 pciide_map_compat_intr(pa, cp, channel, interface); 3601 pdc202xx_setup_channel(&cp->wdc_channel); 3602 } 3603 if (!PDC_IS_268(sc)) { 3604 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3605 "0x%x\n", st), DEBUG_PROBE); 3606 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3607 } 3608 return; 3609 } 3610 3611 void 3612 pdc202xx_setup_channel(chp) 3613 struct channel_softc *chp; 3614 { 3615 struct ata_drive_datas *drvp; 3616 int drive; 3617 pcireg_t mode, st; 3618 u_int32_t idedma_ctl, scr, atapi; 3619 struct pciide_channel *cp = (struct pciide_channel*)chp; 3620 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3621 int channel = chp->channel; 3622 3623 /* setup DMA if needed */ 3624 pciide_channel_dma_setup(cp); 3625 3626 idedma_ctl = 0; 3627 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3628 sc->sc_wdcdev.sc_dev.dv_xname, 3629 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3630 DEBUG_PROBE); 3631 3632 /* Per channel settings */ 3633 if (PDC_IS_262(sc)) { 3634 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3635 PDC262_U66); 3636 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3637 /* Trim UDMA mode */ 3638 if ((st & PDC262_STATE_80P(channel)) != 0 || 3639 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3640 chp->ch_drive[0].UDMA_mode <= 2) || 3641 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3642 chp->ch_drive[1].UDMA_mode <= 2)) { 3643 if (chp->ch_drive[0].UDMA_mode > 2) 3644 chp->ch_drive[0].UDMA_mode = 2; 3645 if (chp->ch_drive[1].UDMA_mode > 2) 3646 chp->ch_drive[1].UDMA_mode = 2; 3647 } 3648 /* Set U66 if needed */ 3649 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3650 chp->ch_drive[0].UDMA_mode > 2) || 3651 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3652 chp->ch_drive[1].UDMA_mode > 2)) 3653 scr |= PDC262_U66_EN(channel); 3654 else 3655 scr &= ~PDC262_U66_EN(channel); 3656 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3657 PDC262_U66, scr); 3658 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3659 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3660 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3661 PDC262_ATAPI(channel))), DEBUG_PROBE); 3662 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3663 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3664 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3665 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3666 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3667 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3668 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3669 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3670 atapi = 0; 3671 else 3672 atapi = PDC262_ATAPI_UDMA; 3673 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3674 PDC262_ATAPI(channel), atapi); 3675 } 3676 } 3677 for (drive = 0; drive < 2; drive++) { 3678 drvp = &chp->ch_drive[drive]; 3679 /* If no drive, skip */ 3680 if ((drvp->drive_flags & DRIVE) == 0) 3681 continue; 3682 mode = 0; 3683 if (drvp->drive_flags & DRIVE_UDMA) { 3684 /* use Ultra/DMA */ 3685 drvp->drive_flags &= ~DRIVE_DMA; 3686 mode = PDC2xx_TIM_SET_MB(mode, 3687 pdc2xx_udma_mb[drvp->UDMA_mode]); 3688 mode = PDC2xx_TIM_SET_MC(mode, 3689 pdc2xx_udma_mc[drvp->UDMA_mode]); 3690 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3691 } else if (drvp->drive_flags & DRIVE_DMA) { 3692 mode = PDC2xx_TIM_SET_MB(mode, 3693 pdc2xx_dma_mb[drvp->DMA_mode]); 3694 mode = PDC2xx_TIM_SET_MC(mode, 3695 pdc2xx_dma_mc[drvp->DMA_mode]); 3696 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3697 } else { 3698 mode = PDC2xx_TIM_SET_MB(mode, 3699 pdc2xx_dma_mb[0]); 3700 mode = PDC2xx_TIM_SET_MC(mode, 3701 pdc2xx_dma_mc[0]); 3702 } 3703 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3704 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3705 if (drvp->drive_flags & DRIVE_ATA) 3706 mode |= PDC2xx_TIM_PRE; 3707 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3708 if (drvp->PIO_mode >= 3) { 3709 mode |= PDC2xx_TIM_IORDY; 3710 if (drive == 0) 3711 mode |= PDC2xx_TIM_IORDYp; 3712 } 3713 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3714 "timings 0x%x\n", 3715 sc->sc_wdcdev.sc_dev.dv_xname, 3716 chp->channel, drive, mode), DEBUG_PROBE); 3717 pci_conf_write(sc->sc_pc, sc->sc_tag, 3718 PDC2xx_TIM(chp->channel, drive), mode); 3719 } 3720 if (idedma_ctl != 0) { 3721 /* Add software bits in status register */ 3722 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3723 IDEDMA_CTL, idedma_ctl); 3724 } 3725 pciide_print_modes(cp); 3726 } 3727 3728 void 3729 pdc20268_setup_channel(chp) 3730 struct channel_softc *chp; 3731 { 3732 struct ata_drive_datas *drvp; 3733 int drive; 3734 u_int32_t idedma_ctl; 3735 struct pciide_channel *cp = (struct pciide_channel*)chp; 3736 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3737 int u100; 3738 3739 /* setup DMA if needed */ 3740 pciide_channel_dma_setup(cp); 3741 3742 idedma_ctl = 0; 3743 3744 /* I don't know what this is for, FreeBSD does it ... */ 3745 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3746 IDEDMA_CMD + 0x1, 0x0b); 3747 3748 /* 3749 * I don't know what this is for; FreeBSD checks this ... this is not 3750 * cable type detect. 3751 */ 3752 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3753 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3754 3755 for (drive = 0; drive < 2; drive++) { 3756 drvp = &chp->ch_drive[drive]; 3757 /* If no drive, skip */ 3758 if ((drvp->drive_flags & DRIVE) == 0) 3759 continue; 3760 if (drvp->drive_flags & DRIVE_UDMA) { 3761 /* use Ultra/DMA */ 3762 drvp->drive_flags &= ~DRIVE_DMA; 3763 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3764 if (drvp->UDMA_mode > 2 && u100 == 0) 3765 drvp->UDMA_mode = 2; 3766 } else if (drvp->drive_flags & DRIVE_DMA) { 3767 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3768 } 3769 } 3770 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3771 if (idedma_ctl != 0) { 3772 /* Add software bits in status register */ 3773 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3774 IDEDMA_CTL, idedma_ctl); 3775 } 3776 pciide_print_modes(cp); 3777 } 3778 3779 int 3780 pdc202xx_pci_intr(arg) 3781 void *arg; 3782 { 3783 struct pciide_softc *sc = arg; 3784 struct pciide_channel *cp; 3785 struct channel_softc *wdc_cp; 3786 int i, rv, crv; 3787 u_int32_t scr; 3788 3789 rv = 0; 3790 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3791 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3792 cp = &sc->pciide_channels[i]; 3793 wdc_cp = &cp->wdc_channel; 3794 /* If a compat channel skip. */ 3795 if (cp->compat) 3796 continue; 3797 if (scr & PDC2xx_SCR_INT(i)) { 3798 crv = wdcintr(wdc_cp); 3799 if (crv == 0) 3800 printf("%s:%d: bogus intr (reg 0x%x)\n", 3801 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3802 else 3803 rv = 1; 3804 } 3805 } 3806 return rv; 3807 } 3808 3809 int 3810 pdc20265_pci_intr(arg) 3811 void *arg; 3812 { 3813 struct pciide_softc *sc = arg; 3814 struct pciide_channel *cp; 3815 struct channel_softc *wdc_cp; 3816 int i, rv, crv; 3817 u_int32_t dmastat; 3818 3819 rv = 0; 3820 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3821 cp = &sc->pciide_channels[i]; 3822 wdc_cp = &cp->wdc_channel; 3823 /* If a compat channel skip. */ 3824 if (cp->compat) 3825 continue; 3826 /* 3827 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3828 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3829 * So use it instead (requires 2 reg reads instead of 1, 3830 * but we can't do it another way). 3831 */ 3832 dmastat = bus_space_read_1(sc->sc_dma_iot, 3833 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3834 if((dmastat & IDEDMA_CTL_INTR) == 0) 3835 continue; 3836 crv = wdcintr(wdc_cp); 3837 if (crv == 0) 3838 printf("%s:%d: bogus intr\n", 3839 sc->sc_wdcdev.sc_dev.dv_xname, i); 3840 else 3841 rv = 1; 3842 } 3843 return rv; 3844 } 3845 3846 void 3847 opti_chip_map(sc, pa) 3848 struct pciide_softc *sc; 3849 struct pci_attach_args *pa; 3850 { 3851 struct pciide_channel *cp; 3852 bus_size_t cmdsize, ctlsize; 3853 pcireg_t interface; 3854 u_int8_t init_ctrl; 3855 int channel; 3856 3857 if (pciide_chipen(sc, pa) == 0) 3858 return; 3859 printf("%s: bus-master DMA support present", 3860 sc->sc_wdcdev.sc_dev.dv_xname); 3861 3862 /* 3863 * XXXSCW: 3864 * There seem to be a couple of buggy revisions/implementations 3865 * of the OPTi pciide chipset. This kludge seems to fix one of 3866 * the reported problems (PR/11644) but still fails for the 3867 * other (PR/13151), although the latter may be due to other 3868 * issues too... 3869 */ 3870 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3871 printf(" but disabled due to chip rev. <= 0x12"); 3872 sc->sc_dma_ok = 0; 3873 sc->sc_wdcdev.cap = 0; 3874 } else { 3875 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3876 pciide_mapreg_dma(sc, pa); 3877 } 3878 printf("\n"); 3879 3880 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3881 sc->sc_wdcdev.PIO_cap = 4; 3882 if (sc->sc_dma_ok) { 3883 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3884 sc->sc_wdcdev.irqack = pciide_irqack; 3885 sc->sc_wdcdev.DMA_cap = 2; 3886 } 3887 sc->sc_wdcdev.set_modes = opti_setup_channel; 3888 3889 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3890 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3891 3892 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3893 OPTI_REG_INIT_CONTROL); 3894 3895 interface = PCI_INTERFACE(pa->pa_class); 3896 3897 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3898 cp = &sc->pciide_channels[channel]; 3899 if (pciide_chansetup(sc, channel, interface) == 0) 3900 continue; 3901 if (channel == 1 && 3902 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3903 printf("%s: %s channel ignored (disabled)\n", 3904 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3905 continue; 3906 } 3907 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3908 pciide_pci_intr); 3909 if (cp->hw_ok == 0) 3910 continue; 3911 pciide_map_compat_intr(pa, cp, channel, interface); 3912 if (cp->hw_ok == 0) 3913 continue; 3914 opti_setup_channel(&cp->wdc_channel); 3915 } 3916 } 3917 3918 void 3919 opti_setup_channel(chp) 3920 struct channel_softc *chp; 3921 { 3922 struct ata_drive_datas *drvp; 3923 struct pciide_channel *cp = (struct pciide_channel*)chp; 3924 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3925 int drive, spd; 3926 int mode[2]; 3927 u_int8_t rv, mr; 3928 3929 /* 3930 * The `Delay' and `Address Setup Time' fields of the 3931 * Miscellaneous Register are always zero initially. 3932 */ 3933 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3934 mr &= ~(OPTI_MISC_DELAY_MASK | 3935 OPTI_MISC_ADDR_SETUP_MASK | 3936 OPTI_MISC_INDEX_MASK); 3937 3938 /* Prime the control register before setting timing values */ 3939 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3940 3941 /* Determine the clockrate of the PCIbus the chip is attached to */ 3942 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3943 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3944 3945 /* setup DMA if needed */ 3946 pciide_channel_dma_setup(cp); 3947 3948 for (drive = 0; drive < 2; drive++) { 3949 drvp = &chp->ch_drive[drive]; 3950 /* If no drive, skip */ 3951 if ((drvp->drive_flags & DRIVE) == 0) { 3952 mode[drive] = -1; 3953 continue; 3954 } 3955 3956 if ((drvp->drive_flags & DRIVE_DMA)) { 3957 /* 3958 * Timings will be used for both PIO and DMA, 3959 * so adjust DMA mode if needed 3960 */ 3961 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3962 drvp->PIO_mode = drvp->DMA_mode + 2; 3963 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3964 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3965 drvp->PIO_mode - 2 : 0; 3966 if (drvp->DMA_mode == 0) 3967 drvp->PIO_mode = 0; 3968 3969 mode[drive] = drvp->DMA_mode + 5; 3970 } else 3971 mode[drive] = drvp->PIO_mode; 3972 3973 if (drive && mode[0] >= 0 && 3974 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3975 /* 3976 * Can't have two drives using different values 3977 * for `Address Setup Time'. 3978 * Slow down the faster drive to compensate. 3979 */ 3980 int d = (opti_tim_as[spd][mode[0]] > 3981 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3982 3983 mode[d] = mode[1-d]; 3984 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3985 chp->ch_drive[d].DMA_mode = 0; 3986 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3987 } 3988 } 3989 3990 for (drive = 0; drive < 2; drive++) { 3991 int m; 3992 if ((m = mode[drive]) < 0) 3993 continue; 3994 3995 /* Set the Address Setup Time and select appropriate index */ 3996 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3997 rv |= OPTI_MISC_INDEX(drive); 3998 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3999 4000 /* Set the pulse width and recovery timing parameters */ 4001 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4002 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4003 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4004 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4005 4006 /* Set the Enhanced Mode register appropriately */ 4007 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4008 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4009 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4010 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4011 } 4012 4013 /* Finally, enable the timings */ 4014 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4015 4016 pciide_print_modes(cp); 4017 } 4018 4019 #define ACARD_IS_850(sc) \ 4020 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4021 4022 void 4023 acard_chip_map(sc, pa) 4024 struct pciide_softc *sc; 4025 struct pci_attach_args *pa; 4026 { 4027 struct pciide_channel *cp; 4028 int i; 4029 pcireg_t interface; 4030 bus_size_t cmdsize, ctlsize; 4031 4032 if (pciide_chipen(sc, pa) == 0) 4033 return; 4034 4035 /* 4036 * when the chip is in native mode it identifies itself as a 4037 * 'misc mass storage'. Fake interface in this case. 4038 */ 4039 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4040 interface = PCI_INTERFACE(pa->pa_class); 4041 } else { 4042 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4043 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4044 } 4045 4046 printf("%s: bus-master DMA support present", 4047 sc->sc_wdcdev.sc_dev.dv_xname); 4048 pciide_mapreg_dma(sc, pa); 4049 printf("\n"); 4050 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4051 WDC_CAPABILITY_MODE; 4052 4053 if (sc->sc_dma_ok) { 4054 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4055 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4056 sc->sc_wdcdev.irqack = pciide_irqack; 4057 } 4058 sc->sc_wdcdev.PIO_cap = 4; 4059 sc->sc_wdcdev.DMA_cap = 2; 4060 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4061 4062 sc->sc_wdcdev.set_modes = acard_setup_channel; 4063 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4064 sc->sc_wdcdev.nchannels = 2; 4065 4066 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4067 cp = &sc->pciide_channels[i]; 4068 if (pciide_chansetup(sc, i, interface) == 0) 4069 continue; 4070 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4071 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4072 &ctlsize, pciide_pci_intr); 4073 } else { 4074 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4075 &cmdsize, &ctlsize); 4076 } 4077 if (cp->hw_ok == 0) 4078 return; 4079 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4080 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4081 wdcattach(&cp->wdc_channel); 4082 acard_setup_channel(&cp->wdc_channel); 4083 } 4084 if (!ACARD_IS_850(sc)) { 4085 u_int32_t reg; 4086 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4087 reg &= ~ATP860_CTRL_INT; 4088 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4089 } 4090 } 4091 4092 void 4093 acard_setup_channel(chp) 4094 struct channel_softc *chp; 4095 { 4096 struct ata_drive_datas *drvp; 4097 struct pciide_channel *cp = (struct pciide_channel*)chp; 4098 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4099 int channel = chp->channel; 4100 int drive; 4101 u_int32_t idetime, udma_mode; 4102 u_int32_t idedma_ctl; 4103 4104 /* setup DMA if needed */ 4105 pciide_channel_dma_setup(cp); 4106 4107 if (ACARD_IS_850(sc)) { 4108 idetime = 0; 4109 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4110 udma_mode &= ~ATP850_UDMA_MASK(channel); 4111 } else { 4112 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4113 idetime &= ~ATP860_SETTIME_MASK(channel); 4114 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4115 udma_mode &= ~ATP860_UDMA_MASK(channel); 4116 4117 /* check 80 pins cable */ 4118 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4119 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4120 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4121 & ATP860_CTRL_80P(chp->channel)) { 4122 if (chp->ch_drive[0].UDMA_mode > 2) 4123 chp->ch_drive[0].UDMA_mode = 2; 4124 if (chp->ch_drive[1].UDMA_mode > 2) 4125 chp->ch_drive[1].UDMA_mode = 2; 4126 } 4127 } 4128 } 4129 4130 idedma_ctl = 0; 4131 4132 /* Per drive settings */ 4133 for (drive = 0; drive < 2; drive++) { 4134 drvp = &chp->ch_drive[drive]; 4135 /* If no drive, skip */ 4136 if ((drvp->drive_flags & DRIVE) == 0) 4137 continue; 4138 /* add timing values, setup DMA if needed */ 4139 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4140 (drvp->drive_flags & DRIVE_UDMA)) { 4141 /* use Ultra/DMA */ 4142 if (ACARD_IS_850(sc)) { 4143 idetime |= ATP850_SETTIME(drive, 4144 acard_act_udma[drvp->UDMA_mode], 4145 acard_rec_udma[drvp->UDMA_mode]); 4146 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4147 acard_udma_conf[drvp->UDMA_mode]); 4148 } else { 4149 idetime |= ATP860_SETTIME(channel, drive, 4150 acard_act_udma[drvp->UDMA_mode], 4151 acard_rec_udma[drvp->UDMA_mode]); 4152 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4153 acard_udma_conf[drvp->UDMA_mode]); 4154 } 4155 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4156 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4157 (drvp->drive_flags & DRIVE_DMA)) { 4158 /* use Multiword DMA */ 4159 drvp->drive_flags &= ~DRIVE_UDMA; 4160 if (ACARD_IS_850(sc)) { 4161 idetime |= ATP850_SETTIME(drive, 4162 acard_act_dma[drvp->DMA_mode], 4163 acard_rec_dma[drvp->DMA_mode]); 4164 } else { 4165 idetime |= ATP860_SETTIME(channel, drive, 4166 acard_act_dma[drvp->DMA_mode], 4167 acard_rec_dma[drvp->DMA_mode]); 4168 } 4169 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4170 } else { 4171 /* PIO only */ 4172 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4173 if (ACARD_IS_850(sc)) { 4174 idetime |= ATP850_SETTIME(drive, 4175 acard_act_pio[drvp->PIO_mode], 4176 acard_rec_pio[drvp->PIO_mode]); 4177 } else { 4178 idetime |= ATP860_SETTIME(channel, drive, 4179 acard_act_pio[drvp->PIO_mode], 4180 acard_rec_pio[drvp->PIO_mode]); 4181 } 4182 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4183 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4184 | ATP8x0_CTRL_EN(channel)); 4185 } 4186 } 4187 4188 if (idedma_ctl != 0) { 4189 /* Add software bits in status register */ 4190 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4191 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4192 } 4193 pciide_print_modes(cp); 4194 4195 if (ACARD_IS_850(sc)) { 4196 pci_conf_write(sc->sc_pc, sc->sc_tag, 4197 ATP850_IDETIME(channel), idetime); 4198 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4199 } else { 4200 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4201 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4202 } 4203 } 4204 4205 int 4206 acard_pci_intr(arg) 4207 void *arg; 4208 { 4209 struct pciide_softc *sc = arg; 4210 struct pciide_channel *cp; 4211 struct channel_softc *wdc_cp; 4212 int rv = 0; 4213 int dmastat, i, crv; 4214 4215 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4216 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4217 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4218 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4219 continue; 4220 cp = &sc->pciide_channels[i]; 4221 wdc_cp = &cp->wdc_channel; 4222 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4223 (void)wdcintr(wdc_cp); 4224 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4225 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4226 continue; 4227 } 4228 crv = wdcintr(wdc_cp); 4229 if (crv == 0) 4230 printf("%s:%d: bogus intr\n", 4231 sc->sc_wdcdev.sc_dev.dv_xname, i); 4232 else if (crv == 1) 4233 rv = 1; 4234 else if (rv == 0) 4235 rv = crv; 4236 } 4237 return rv; 4238 } 4239
Indexes created Thu Oct 02 10:09:58 GMT 2025