pciide.c revision 1.107.2.12
1 /* $NetBSD: pciide.c,v 1.107.2.12 2002/04/17 00:06:05 nathanw Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.107.2.12 2002/04/17 00:06:05 nathanw Exp $"); 81 82 #ifndef WDCDEBUG 83 #define WDCDEBUG 84 #endif 85 86 #define DEBUG_DMA 0x01 87 #define DEBUG_XFERS 0x02 88 #define DEBUG_FUNCS 0x08 89 #define DEBUG_PROBE 0x10 90 #ifdef WDCDEBUG 91 int wdcdebug_pciide_mask = 0; 92 #define WDCDEBUG_PRINT(args, level) \ 93 if (wdcdebug_pciide_mask & (level)) printf args 94 #else 95 #define WDCDEBUG_PRINT(args, level) 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 102 #include <uvm/uvm_extern.h> 103 104 #include <machine/endian.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 #include <dev/pci/pciide_opti_reg.h> 120 #include <dev/pci/pciide_hpt_reg.h> 121 #include <dev/pci/pciide_acard_reg.h> 122 #include <dev/pci/pciide_sl82c105_reg.h> 123 #include <dev/pci/cy82c693var.h> 124 125 #include "opt_pciide.h" 126 127 /* inlines for reading/writing 8-bit PCI registers */ 128 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 129 int)); 130 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 131 int, u_int8_t)); 132 133 static __inline u_int8_t 134 pciide_pci_read(pc, pa, reg) 135 pci_chipset_tag_t pc; 136 pcitag_t pa; 137 int reg; 138 { 139 140 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 141 ((reg & 0x03) * 8) & 0xff); 142 } 143 144 static __inline void 145 pciide_pci_write(pc, pa, reg, val) 146 pci_chipset_tag_t pc; 147 pcitag_t pa; 148 int reg; 149 u_int8_t val; 150 { 151 pcireg_t pcival; 152 153 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 154 pcival &= ~(0xff << ((reg & 0x03) * 8)); 155 pcival |= (val << ((reg & 0x03) * 8)); 156 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 157 } 158 159 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 161 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void piix_setup_channel __P((struct channel_softc*)); 163 void piix3_4_setup_channel __P((struct channel_softc*)); 164 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 165 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 166 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 167 168 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void amd7x6_setup_channel __P((struct channel_softc*)); 170 171 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void apollo_setup_channel __P((struct channel_softc*)); 173 174 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cmd0643_9_setup_channel __P((struct channel_softc*)); 177 void cmd_channel_map __P((struct pci_attach_args *, 178 struct pciide_softc *, int)); 179 int cmd_pci_intr __P((void *)); 180 void cmd646_9_irqack __P((struct channel_softc *)); 181 182 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void cy693_setup_channel __P((struct channel_softc*)); 184 185 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void sis_setup_channel __P((struct channel_softc*)); 187 static int sis_hostbr_match __P(( struct pci_attach_args *)); 188 189 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void acer_setup_channel __P((struct channel_softc*)); 191 int acer_pci_intr __P((void *)); 192 static int acer_isabr_match __P(( struct pci_attach_args *)); 193 194 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void pdc202xx_setup_channel __P((struct channel_softc*)); 196 void pdc20268_setup_channel __P((struct channel_softc*)); 197 int pdc202xx_pci_intr __P((void *)); 198 int pdc20265_pci_intr __P((void *)); 199 200 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void opti_setup_channel __P((struct channel_softc*)); 202 203 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 204 void hpt_setup_channel __P((struct channel_softc*)); 205 int hpt_pci_intr __P((void *)); 206 207 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 void acard_setup_channel __P((struct channel_softc*)); 209 int acard_pci_intr __P((void *)); 210 211 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 void serverworks_setup_channel __P((struct channel_softc*)); 213 int serverworks_pci_intr __P((void *)); 214 215 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 216 void sl82c105_setup_channel __P((struct channel_softc*)); 217 218 void pciide_channel_dma_setup __P((struct pciide_channel *)); 219 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 220 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 221 void pciide_dma_start __P((void*, int, int)); 222 int pciide_dma_finish __P((void*, int, int, int)); 223 void pciide_irqack __P((struct channel_softc *)); 224 void pciide_print_modes __P((struct pciide_channel *)); 225 226 struct pciide_product_desc { 227 u_int32_t ide_product; 228 int ide_flags; 229 const char *ide_name; 230 /* map and setup chip, probe drives */ 231 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 232 }; 233 234 /* Flags for ide_flags */ 235 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 236 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 237 238 /* Default product description for devices not known from this controller */ 239 const struct pciide_product_desc default_product_desc = { 240 0, 241 0, 242 "Generic PCI IDE controller", 243 default_chip_map, 244 }; 245 246 const struct pciide_product_desc pciide_intel_products[] = { 247 { PCI_PRODUCT_INTEL_82092AA, 248 0, 249 "Intel 82092AA IDE controller", 250 default_chip_map, 251 }, 252 { PCI_PRODUCT_INTEL_82371FB_IDE, 253 0, 254 "Intel 82371FB IDE controller (PIIX)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82371SB_IDE, 258 0, 259 "Intel 82371SB IDE Interface (PIIX3)", 260 piix_chip_map, 261 }, 262 { PCI_PRODUCT_INTEL_82371AB_IDE, 263 0, 264 "Intel 82371AB IDE controller (PIIX4)", 265 piix_chip_map, 266 }, 267 { PCI_PRODUCT_INTEL_82440MX_IDE, 268 0, 269 "Intel 82440MX IDE controller", 270 piix_chip_map 271 }, 272 { PCI_PRODUCT_INTEL_82801AA_IDE, 273 0, 274 "Intel 82801AA IDE Controller (ICH)", 275 piix_chip_map, 276 }, 277 { PCI_PRODUCT_INTEL_82801AB_IDE, 278 0, 279 "Intel 82801AB IDE Controller (ICH0)", 280 piix_chip_map, 281 }, 282 { PCI_PRODUCT_INTEL_82801BA_IDE, 283 0, 284 "Intel 82801BA IDE Controller (ICH2)", 285 piix_chip_map, 286 }, 287 { PCI_PRODUCT_INTEL_82801BAM_IDE, 288 0, 289 "Intel 82801BAM IDE Controller (ICH2)", 290 piix_chip_map, 291 }, 292 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 293 0, 294 "Intel 82201CA IDE Controller", 295 piix_chip_map, 296 }, 297 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 298 0, 299 "Intel 82201CA IDE Controller", 300 piix_chip_map, 301 }, 302 { 0, 303 0, 304 NULL, 305 NULL 306 } 307 }; 308 309 const struct pciide_product_desc pciide_amd_products[] = { 310 { PCI_PRODUCT_AMD_PBC756_IDE, 311 0, 312 "Advanced Micro Devices AMD756 IDE Controller", 313 amd7x6_chip_map 314 }, 315 { PCI_PRODUCT_AMD_PBC766_IDE, 316 0, 317 "Advanced Micro Devices AMD766 IDE Controller", 318 amd7x6_chip_map 319 }, 320 { PCI_PRODUCT_AMD_PBC768_IDE, 321 0, 322 "Advanced Micro Devices AMD768 IDE Controller", 323 amd7x6_chip_map 324 }, 325 { 0, 326 0, 327 NULL, 328 NULL 329 } 330 }; 331 332 const struct pciide_product_desc pciide_cmd_products[] = { 333 { PCI_PRODUCT_CMDTECH_640, 334 0, 335 "CMD Technology PCI0640", 336 cmd_chip_map 337 }, 338 { PCI_PRODUCT_CMDTECH_643, 339 0, 340 "CMD Technology PCI0643", 341 cmd0643_9_chip_map, 342 }, 343 { PCI_PRODUCT_CMDTECH_646, 344 0, 345 "CMD Technology PCI0646", 346 cmd0643_9_chip_map, 347 }, 348 { PCI_PRODUCT_CMDTECH_648, 349 IDE_PCI_CLASS_OVERRIDE, 350 "CMD Technology PCI0648", 351 cmd0643_9_chip_map, 352 }, 353 { PCI_PRODUCT_CMDTECH_649, 354 IDE_PCI_CLASS_OVERRIDE, 355 "CMD Technology PCI0649", 356 cmd0643_9_chip_map, 357 }, 358 { 0, 359 0, 360 NULL, 361 NULL 362 } 363 }; 364 365 const struct pciide_product_desc pciide_via_products[] = { 366 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 367 0, 368 NULL, 369 apollo_chip_map, 370 }, 371 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 372 0, 373 NULL, 374 apollo_chip_map, 375 }, 376 { 0, 377 0, 378 NULL, 379 NULL 380 } 381 }; 382 383 const struct pciide_product_desc pciide_cypress_products[] = { 384 { PCI_PRODUCT_CONTAQ_82C693, 385 IDE_16BIT_IOSPACE, 386 "Cypress 82C693 IDE Controller", 387 cy693_chip_map, 388 }, 389 { 0, 390 0, 391 NULL, 392 NULL 393 } 394 }; 395 396 const struct pciide_product_desc pciide_sis_products[] = { 397 { PCI_PRODUCT_SIS_5597_IDE, 398 0, 399 "Silicon Integrated System 5597/5598 IDE controller", 400 sis_chip_map, 401 }, 402 { 0, 403 0, 404 NULL, 405 NULL 406 } 407 }; 408 409 const struct pciide_product_desc pciide_acer_products[] = { 410 { PCI_PRODUCT_ALI_M5229, 411 0, 412 "Acer Labs M5229 UDMA IDE Controller", 413 acer_chip_map, 414 }, 415 { 0, 416 0, 417 NULL, 418 NULL 419 } 420 }; 421 422 const struct pciide_product_desc pciide_promise_products[] = { 423 { PCI_PRODUCT_PROMISE_ULTRA33, 424 IDE_PCI_CLASS_OVERRIDE, 425 "Promise Ultra33/ATA Bus Master IDE Accelerator", 426 pdc202xx_chip_map, 427 }, 428 { PCI_PRODUCT_PROMISE_ULTRA66, 429 IDE_PCI_CLASS_OVERRIDE, 430 "Promise Ultra66/ATA Bus Master IDE Accelerator", 431 pdc202xx_chip_map, 432 }, 433 { PCI_PRODUCT_PROMISE_ULTRA100, 434 IDE_PCI_CLASS_OVERRIDE, 435 "Promise Ultra100/ATA Bus Master IDE Accelerator", 436 pdc202xx_chip_map, 437 }, 438 { PCI_PRODUCT_PROMISE_ULTRA100X, 439 IDE_PCI_CLASS_OVERRIDE, 440 "Promise Ultra100/ATA Bus Master IDE Accelerator", 441 pdc202xx_chip_map, 442 }, 443 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 444 IDE_PCI_CLASS_OVERRIDE, 445 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 446 pdc202xx_chip_map, 447 }, 448 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 449 IDE_PCI_CLASS_OVERRIDE, 450 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 451 pdc202xx_chip_map, 452 }, 453 { PCI_PRODUCT_PROMISE_ULTRA133, 454 IDE_PCI_CLASS_OVERRIDE, 455 "Promise Ultra133/ATA Bus Master IDE Accelerator", 456 pdc202xx_chip_map, 457 }, 458 { 0, 459 0, 460 NULL, 461 NULL 462 } 463 }; 464 465 const struct pciide_product_desc pciide_opti_products[] = { 466 { PCI_PRODUCT_OPTI_82C621, 467 0, 468 "OPTi 82c621 PCI IDE controller", 469 opti_chip_map, 470 }, 471 { PCI_PRODUCT_OPTI_82C568, 472 0, 473 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 474 opti_chip_map, 475 }, 476 { PCI_PRODUCT_OPTI_82D568, 477 0, 478 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 479 opti_chip_map, 480 }, 481 { 0, 482 0, 483 NULL, 484 NULL 485 } 486 }; 487 488 const struct pciide_product_desc pciide_triones_products[] = { 489 { PCI_PRODUCT_TRIONES_HPT366, 490 IDE_PCI_CLASS_OVERRIDE, 491 NULL, 492 hpt_chip_map, 493 }, 494 { 0, 495 0, 496 NULL, 497 NULL 498 } 499 }; 500 501 const struct pciide_product_desc pciide_acard_products[] = { 502 { PCI_PRODUCT_ACARD_ATP850U, 503 IDE_PCI_CLASS_OVERRIDE, 504 "Acard ATP850U Ultra33 IDE Controller", 505 acard_chip_map, 506 }, 507 { PCI_PRODUCT_ACARD_ATP860, 508 IDE_PCI_CLASS_OVERRIDE, 509 "Acard ATP860 Ultra66 IDE Controller", 510 acard_chip_map, 511 }, 512 { PCI_PRODUCT_ACARD_ATP860A, 513 IDE_PCI_CLASS_OVERRIDE, 514 "Acard ATP860-A Ultra66 IDE Controller", 515 acard_chip_map, 516 }, 517 { 0, 518 0, 519 NULL, 520 NULL 521 } 522 }; 523 524 const struct pciide_product_desc pciide_serverworks_products[] = { 525 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 526 0, 527 "ServerWorks OSB4 IDE Controller", 528 serverworks_chip_map, 529 }, 530 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 531 0, 532 "ServerWorks CSB5 IDE Controller", 533 serverworks_chip_map, 534 }, 535 { 0, 536 0, 537 NULL, 538 } 539 }; 540 541 const struct pciide_product_desc pciide_symphony_products[] = { 542 { PCI_PRODUCT_SYMPHONY_82C105, 543 0, 544 "Symphony Labs 82C105 IDE controller", 545 sl82c105_chip_map, 546 }, 547 { 0, 548 0, 549 NULL, 550 } 551 }; 552 553 const struct pciide_product_desc pciide_winbond_products[] = { 554 { PCI_PRODUCT_WINBOND_W83C553F_1, 555 0, 556 "Winbond W83C553F IDE controller", 557 sl82c105_chip_map, 558 }, 559 { 0, 560 0, 561 NULL, 562 } 563 }; 564 565 struct pciide_vendor_desc { 566 u_int32_t ide_vendor; 567 const struct pciide_product_desc *ide_products; 568 }; 569 570 const struct pciide_vendor_desc pciide_vendors[] = { 571 { PCI_VENDOR_INTEL, pciide_intel_products }, 572 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 573 { PCI_VENDOR_VIATECH, pciide_via_products }, 574 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 575 { PCI_VENDOR_SIS, pciide_sis_products }, 576 { PCI_VENDOR_ALI, pciide_acer_products }, 577 { PCI_VENDOR_PROMISE, pciide_promise_products }, 578 { PCI_VENDOR_AMD, pciide_amd_products }, 579 { PCI_VENDOR_OPTI, pciide_opti_products }, 580 { PCI_VENDOR_TRIONES, pciide_triones_products }, 581 { PCI_VENDOR_ACARD, pciide_acard_products }, 582 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 583 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 584 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 585 { 0, NULL } 586 }; 587 588 /* options passed via the 'flags' config keyword */ 589 #define PCIIDE_OPTIONS_DMA 0x01 590 #define PCIIDE_OPTIONS_NODMA 0x02 591 592 int pciide_match __P((struct device *, struct cfdata *, void *)); 593 void pciide_attach __P((struct device *, struct device *, void *)); 594 595 struct cfattach pciide_ca = { 596 sizeof(struct pciide_softc), pciide_match, pciide_attach 597 }; 598 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 599 int pciide_mapregs_compat __P(( struct pci_attach_args *, 600 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 601 int pciide_mapregs_native __P((struct pci_attach_args *, 602 struct pciide_channel *, bus_size_t *, bus_size_t *, 603 int (*pci_intr) __P((void *)))); 604 void pciide_mapreg_dma __P((struct pciide_softc *, 605 struct pci_attach_args *)); 606 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 607 void pciide_mapchan __P((struct pci_attach_args *, 608 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 609 int (*pci_intr) __P((void *)))); 610 int pciide_chan_candisable __P((struct pciide_channel *)); 611 void pciide_map_compat_intr __P(( struct pci_attach_args *, 612 struct pciide_channel *, int, int)); 613 int pciide_compat_intr __P((void *)); 614 int pciide_pci_intr __P((void *)); 615 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 616 617 const struct pciide_product_desc * 618 pciide_lookup_product(id) 619 u_int32_t id; 620 { 621 const struct pciide_product_desc *pp; 622 const struct pciide_vendor_desc *vp; 623 624 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 625 if (PCI_VENDOR(id) == vp->ide_vendor) 626 break; 627 628 if ((pp = vp->ide_products) == NULL) 629 return NULL; 630 631 for (; pp->chip_map != NULL; pp++) 632 if (PCI_PRODUCT(id) == pp->ide_product) 633 break; 634 635 if (pp->chip_map == NULL) 636 return NULL; 637 return pp; 638 } 639 640 int 641 pciide_match(parent, match, aux) 642 struct device *parent; 643 struct cfdata *match; 644 void *aux; 645 { 646 struct pci_attach_args *pa = aux; 647 const struct pciide_product_desc *pp; 648 649 /* 650 * Check the ID register to see that it's a PCI IDE controller. 651 * If it is, we assume that we can deal with it; it _should_ 652 * work in a standardized way... 653 */ 654 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 655 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 656 return (1); 657 } 658 659 /* 660 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 661 * controllers. Let see if we can deal with it anyway. 662 */ 663 pp = pciide_lookup_product(pa->pa_id); 664 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 665 return (1); 666 } 667 668 return (0); 669 } 670 671 void 672 pciide_attach(parent, self, aux) 673 struct device *parent, *self; 674 void *aux; 675 { 676 struct pci_attach_args *pa = aux; 677 pci_chipset_tag_t pc = pa->pa_pc; 678 pcitag_t tag = pa->pa_tag; 679 struct pciide_softc *sc = (struct pciide_softc *)self; 680 pcireg_t csr; 681 char devinfo[256]; 682 const char *displaydev; 683 684 sc->sc_pp = pciide_lookup_product(pa->pa_id); 685 if (sc->sc_pp == NULL) { 686 sc->sc_pp = &default_product_desc; 687 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 688 displaydev = devinfo; 689 } else 690 displaydev = sc->sc_pp->ide_name; 691 692 /* if displaydev == NULL, printf is done in chip-specific map */ 693 if (displaydev) 694 printf(": %s (rev. 0x%02x)\n", displaydev, 695 PCI_REVISION(pa->pa_class)); 696 697 sc->sc_pc = pa->pa_pc; 698 sc->sc_tag = pa->pa_tag; 699 #ifdef WDCDEBUG 700 if (wdcdebug_pciide_mask & DEBUG_PROBE) 701 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 702 #endif 703 sc->sc_pp->chip_map(sc, pa); 704 705 if (sc->sc_dma_ok) { 706 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 707 csr |= PCI_COMMAND_MASTER_ENABLE; 708 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 709 } 710 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 711 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 712 } 713 714 /* tell wether the chip is enabled or not */ 715 int 716 pciide_chipen(sc, pa) 717 struct pciide_softc *sc; 718 struct pci_attach_args *pa; 719 { 720 pcireg_t csr; 721 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 722 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 723 PCI_COMMAND_STATUS_REG); 724 printf("%s: device disabled (at %s)\n", 725 sc->sc_wdcdev.sc_dev.dv_xname, 726 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 727 "device" : "bridge"); 728 return 0; 729 } 730 return 1; 731 } 732 733 int 734 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 735 struct pci_attach_args *pa; 736 struct pciide_channel *cp; 737 int compatchan; 738 bus_size_t *cmdsizep, *ctlsizep; 739 { 740 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 741 struct channel_softc *wdc_cp = &cp->wdc_channel; 742 743 cp->compat = 1; 744 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 745 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 746 747 wdc_cp->cmd_iot = pa->pa_iot; 748 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 749 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 750 printf("%s: couldn't map %s channel cmd regs\n", 751 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 752 return (0); 753 } 754 755 wdc_cp->ctl_iot = pa->pa_iot; 756 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 757 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 758 printf("%s: couldn't map %s channel ctl regs\n", 759 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 760 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 761 PCIIDE_COMPAT_CMD_SIZE); 762 return (0); 763 } 764 765 return (1); 766 } 767 768 int 769 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 770 struct pci_attach_args * pa; 771 struct pciide_channel *cp; 772 bus_size_t *cmdsizep, *ctlsizep; 773 int (*pci_intr) __P((void *)); 774 { 775 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 776 struct channel_softc *wdc_cp = &cp->wdc_channel; 777 const char *intrstr; 778 pci_intr_handle_t intrhandle; 779 780 cp->compat = 0; 781 782 if (sc->sc_pci_ih == NULL) { 783 if (pci_intr_map(pa, &intrhandle) != 0) { 784 printf("%s: couldn't map native-PCI interrupt\n", 785 sc->sc_wdcdev.sc_dev.dv_xname); 786 return 0; 787 } 788 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 789 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 790 intrhandle, IPL_BIO, pci_intr, sc); 791 if (sc->sc_pci_ih != NULL) { 792 printf("%s: using %s for native-PCI interrupt\n", 793 sc->sc_wdcdev.sc_dev.dv_xname, 794 intrstr ? intrstr : "unknown interrupt"); 795 } else { 796 printf("%s: couldn't establish native-PCI interrupt", 797 sc->sc_wdcdev.sc_dev.dv_xname); 798 if (intrstr != NULL) 799 printf(" at %s", intrstr); 800 printf("\n"); 801 return 0; 802 } 803 } 804 cp->ih = sc->sc_pci_ih; 805 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 806 PCI_MAPREG_TYPE_IO, 0, 807 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 808 printf("%s: couldn't map %s channel cmd regs\n", 809 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 810 return 0; 811 } 812 813 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 814 PCI_MAPREG_TYPE_IO, 0, 815 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 816 printf("%s: couldn't map %s channel ctl regs\n", 817 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 818 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 819 return 0; 820 } 821 /* 822 * In native mode, 4 bytes of I/O space are mapped for the control 823 * register, the control register is at offset 2. Pass the generic 824 * code a handle for only one byte at the rigth offset. 825 */ 826 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 827 &wdc_cp->ctl_ioh) != 0) { 828 printf("%s: unable to subregion %s channel ctl regs\n", 829 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 830 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 831 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 832 return 0; 833 } 834 return (1); 835 } 836 837 void 838 pciide_mapreg_dma(sc, pa) 839 struct pciide_softc *sc; 840 struct pci_attach_args *pa; 841 { 842 pcireg_t maptype; 843 bus_addr_t addr; 844 845 /* 846 * Map DMA registers 847 * 848 * Note that sc_dma_ok is the right variable to test to see if 849 * DMA can be done. If the interface doesn't support DMA, 850 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 851 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 852 * non-zero if the interface supports DMA and the registers 853 * could be mapped. 854 * 855 * XXX Note that despite the fact that the Bus Master IDE specs 856 * XXX say that "The bus master IDE function uses 16 bytes of IO 857 * XXX space," some controllers (at least the United 858 * XXX Microelectronics UM8886BF) place it in memory space. 859 */ 860 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 861 PCIIDE_REG_BUS_MASTER_DMA); 862 863 switch (maptype) { 864 case PCI_MAPREG_TYPE_IO: 865 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 866 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 867 &addr, NULL, NULL) == 0); 868 if (sc->sc_dma_ok == 0) { 869 printf(", but unused (couldn't query registers)"); 870 break; 871 } 872 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 873 && addr >= 0x10000) { 874 sc->sc_dma_ok = 0; 875 printf(", but unused (registers at unsafe address " 876 "%#lx)", (unsigned long)addr); 877 break; 878 } 879 /* FALLTHROUGH */ 880 881 case PCI_MAPREG_MEM_TYPE_32BIT: 882 sc->sc_dma_ok = (pci_mapreg_map(pa, 883 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 884 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 885 sc->sc_dmat = pa->pa_dmat; 886 if (sc->sc_dma_ok == 0) { 887 printf(", but unused (couldn't map registers)"); 888 } else { 889 sc->sc_wdcdev.dma_arg = sc; 890 sc->sc_wdcdev.dma_init = pciide_dma_init; 891 sc->sc_wdcdev.dma_start = pciide_dma_start; 892 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 893 } 894 895 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 896 PCIIDE_OPTIONS_NODMA) { 897 printf(", but unused (forced off by config file)"); 898 sc->sc_dma_ok = 0; 899 } 900 break; 901 902 default: 903 sc->sc_dma_ok = 0; 904 printf(", but unsupported register maptype (0x%x)", maptype); 905 } 906 } 907 908 int 909 pciide_compat_intr(arg) 910 void *arg; 911 { 912 struct pciide_channel *cp = arg; 913 914 #ifdef DIAGNOSTIC 915 /* should only be called for a compat channel */ 916 if (cp->compat == 0) 917 panic("pciide compat intr called for non-compat chan %p\n", cp); 918 #endif 919 return (wdcintr(&cp->wdc_channel)); 920 } 921 922 int 923 pciide_pci_intr(arg) 924 void *arg; 925 { 926 struct pciide_softc *sc = arg; 927 struct pciide_channel *cp; 928 struct channel_softc *wdc_cp; 929 int i, rv, crv; 930 931 rv = 0; 932 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 933 cp = &sc->pciide_channels[i]; 934 wdc_cp = &cp->wdc_channel; 935 936 /* If a compat channel skip. */ 937 if (cp->compat) 938 continue; 939 /* if this channel not waiting for intr, skip */ 940 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 941 continue; 942 943 crv = wdcintr(wdc_cp); 944 if (crv == 0) 945 ; /* leave rv alone */ 946 else if (crv == 1) 947 rv = 1; /* claim the intr */ 948 else if (rv == 0) /* crv should be -1 in this case */ 949 rv = crv; /* if we've done no better, take it */ 950 } 951 return (rv); 952 } 953 954 void 955 pciide_channel_dma_setup(cp) 956 struct pciide_channel *cp; 957 { 958 int drive; 959 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 960 struct ata_drive_datas *drvp; 961 962 for (drive = 0; drive < 2; drive++) { 963 drvp = &cp->wdc_channel.ch_drive[drive]; 964 /* If no drive, skip */ 965 if ((drvp->drive_flags & DRIVE) == 0) 966 continue; 967 /* setup DMA if needed */ 968 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 969 (drvp->drive_flags & DRIVE_UDMA) == 0) || 970 sc->sc_dma_ok == 0) { 971 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 972 continue; 973 } 974 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 975 != 0) { 976 /* Abort DMA setup */ 977 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 978 continue; 979 } 980 } 981 } 982 983 int 984 pciide_dma_table_setup(sc, channel, drive) 985 struct pciide_softc *sc; 986 int channel, drive; 987 { 988 bus_dma_segment_t seg; 989 int error, rseg; 990 const bus_size_t dma_table_size = 991 sizeof(struct idedma_table) * NIDEDMA_TABLES; 992 struct pciide_dma_maps *dma_maps = 993 &sc->pciide_channels[channel].dma_maps[drive]; 994 995 /* If table was already allocated, just return */ 996 if (dma_maps->dma_table) 997 return 0; 998 999 /* Allocate memory for the DMA tables and map it */ 1000 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1001 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1002 BUS_DMA_NOWAIT)) != 0) { 1003 printf("%s:%d: unable to allocate table DMA for " 1004 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1005 channel, drive, error); 1006 return error; 1007 } 1008 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1009 dma_table_size, 1010 (caddr_t *)&dma_maps->dma_table, 1011 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1012 printf("%s:%d: unable to map table DMA for" 1013 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1014 channel, drive, error); 1015 return error; 1016 } 1017 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1018 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1019 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1020 1021 /* Create and load table DMA map for this disk */ 1022 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1023 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1024 &dma_maps->dmamap_table)) != 0) { 1025 printf("%s:%d: unable to create table DMA map for " 1026 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1027 channel, drive, error); 1028 return error; 1029 } 1030 if ((error = bus_dmamap_load(sc->sc_dmat, 1031 dma_maps->dmamap_table, 1032 dma_maps->dma_table, 1033 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1034 printf("%s:%d: unable to load table DMA map for " 1035 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1036 channel, drive, error); 1037 return error; 1038 } 1039 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1040 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1041 DEBUG_PROBE); 1042 /* Create a xfer DMA map for this drive */ 1043 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1044 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1045 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1046 &dma_maps->dmamap_xfer)) != 0) { 1047 printf("%s:%d: unable to create xfer DMA map for " 1048 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1049 channel, drive, error); 1050 return error; 1051 } 1052 return 0; 1053 } 1054 1055 int 1056 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1057 void *v; 1058 int channel, drive; 1059 void *databuf; 1060 size_t datalen; 1061 int flags; 1062 { 1063 struct pciide_softc *sc = v; 1064 int error, seg; 1065 struct pciide_dma_maps *dma_maps = 1066 &sc->pciide_channels[channel].dma_maps[drive]; 1067 1068 error = bus_dmamap_load(sc->sc_dmat, 1069 dma_maps->dmamap_xfer, 1070 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1071 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1072 if (error) { 1073 printf("%s:%d: unable to load xfer DMA map for" 1074 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1075 channel, drive, error); 1076 return error; 1077 } 1078 1079 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1080 dma_maps->dmamap_xfer->dm_mapsize, 1081 (flags & WDC_DMA_READ) ? 1082 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1083 1084 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1085 #ifdef DIAGNOSTIC 1086 /* A segment must not cross a 64k boundary */ 1087 { 1088 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1089 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1090 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1091 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1092 printf("pciide_dma: segment %d physical addr 0x%lx" 1093 " len 0x%lx not properly aligned\n", 1094 seg, phys, len); 1095 panic("pciide_dma: buf align"); 1096 } 1097 } 1098 #endif 1099 dma_maps->dma_table[seg].base_addr = 1100 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1101 dma_maps->dma_table[seg].byte_count = 1102 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1103 IDEDMA_BYTE_COUNT_MASK); 1104 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1105 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1106 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1107 1108 } 1109 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1110 htole32(IDEDMA_BYTE_COUNT_EOT); 1111 1112 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1113 dma_maps->dmamap_table->dm_mapsize, 1114 BUS_DMASYNC_PREWRITE); 1115 1116 /* Maps are ready. Start DMA function */ 1117 #ifdef DIAGNOSTIC 1118 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1119 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1120 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1121 panic("pciide_dma_init: table align"); 1122 } 1123 #endif 1124 1125 /* Clear status bits */ 1126 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1127 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1128 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1129 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1130 /* Write table addr */ 1131 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1132 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1133 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1134 /* set read/write */ 1135 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1136 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1137 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1138 /* remember flags */ 1139 dma_maps->dma_flags = flags; 1140 return 0; 1141 } 1142 1143 void 1144 pciide_dma_start(v, channel, drive) 1145 void *v; 1146 int channel, drive; 1147 { 1148 struct pciide_softc *sc = v; 1149 1150 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1151 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1152 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1153 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1154 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1155 } 1156 1157 int 1158 pciide_dma_finish(v, channel, drive, force) 1159 void *v; 1160 int channel, drive; 1161 int force; 1162 { 1163 struct pciide_softc *sc = v; 1164 u_int8_t status; 1165 int error = 0; 1166 struct pciide_dma_maps *dma_maps = 1167 &sc->pciide_channels[channel].dma_maps[drive]; 1168 1169 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1170 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1171 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1172 DEBUG_XFERS); 1173 1174 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1175 return WDC_DMAST_NOIRQ; 1176 1177 /* stop DMA channel */ 1178 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1179 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1180 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1181 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1182 1183 /* Unload the map of the data buffer */ 1184 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1185 dma_maps->dmamap_xfer->dm_mapsize, 1186 (dma_maps->dma_flags & WDC_DMA_READ) ? 1187 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1188 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1189 1190 if ((status & IDEDMA_CTL_ERR) != 0) { 1191 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1192 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1193 error |= WDC_DMAST_ERR; 1194 } 1195 1196 if ((status & IDEDMA_CTL_INTR) == 0) { 1197 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1198 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1199 drive, status); 1200 error |= WDC_DMAST_NOIRQ; 1201 } 1202 1203 if ((status & IDEDMA_CTL_ACT) != 0) { 1204 /* data underrun, may be a valid condition for ATAPI */ 1205 error |= WDC_DMAST_UNDER; 1206 } 1207 return error; 1208 } 1209 1210 void 1211 pciide_irqack(chp) 1212 struct channel_softc *chp; 1213 { 1214 struct pciide_channel *cp = (struct pciide_channel*)chp; 1215 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1216 1217 /* clear status bits in IDE DMA registers */ 1218 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1219 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1220 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1221 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1222 } 1223 1224 /* some common code used by several chip_map */ 1225 int 1226 pciide_chansetup(sc, channel, interface) 1227 struct pciide_softc *sc; 1228 int channel; 1229 pcireg_t interface; 1230 { 1231 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1232 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1233 cp->name = PCIIDE_CHANNEL_NAME(channel); 1234 cp->wdc_channel.channel = channel; 1235 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1236 cp->wdc_channel.ch_queue = 1237 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1238 if (cp->wdc_channel.ch_queue == NULL) { 1239 printf("%s %s channel: " 1240 "can't allocate memory for command queue", 1241 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1242 return 0; 1243 } 1244 printf("%s: %s channel %s to %s mode\n", 1245 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1246 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1247 "configured" : "wired", 1248 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1249 "native-PCI" : "compatibility"); 1250 return 1; 1251 } 1252 1253 /* some common code used by several chip channel_map */ 1254 void 1255 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1256 struct pci_attach_args *pa; 1257 struct pciide_channel *cp; 1258 pcireg_t interface; 1259 bus_size_t *cmdsizep, *ctlsizep; 1260 int (*pci_intr) __P((void *)); 1261 { 1262 struct channel_softc *wdc_cp = &cp->wdc_channel; 1263 1264 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1265 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1266 pci_intr); 1267 else 1268 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1269 wdc_cp->channel, cmdsizep, ctlsizep); 1270 1271 if (cp->hw_ok == 0) 1272 return; 1273 wdc_cp->data32iot = wdc_cp->cmd_iot; 1274 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1275 wdcattach(wdc_cp); 1276 } 1277 1278 /* 1279 * Generic code to call to know if a channel can be disabled. Return 1 1280 * if channel can be disabled, 0 if not 1281 */ 1282 int 1283 pciide_chan_candisable(cp) 1284 struct pciide_channel *cp; 1285 { 1286 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1287 struct channel_softc *wdc_cp = &cp->wdc_channel; 1288 1289 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1290 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1291 printf("%s: disabling %s channel (no drives)\n", 1292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1293 cp->hw_ok = 0; 1294 return 1; 1295 } 1296 return 0; 1297 } 1298 1299 /* 1300 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1301 * Set hw_ok=0 on failure 1302 */ 1303 void 1304 pciide_map_compat_intr(pa, cp, compatchan, interface) 1305 struct pci_attach_args *pa; 1306 struct pciide_channel *cp; 1307 int compatchan, interface; 1308 { 1309 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1310 struct channel_softc *wdc_cp = &cp->wdc_channel; 1311 1312 if (cp->hw_ok == 0) 1313 return; 1314 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1315 return; 1316 1317 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1318 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1319 pa, compatchan, pciide_compat_intr, cp); 1320 if (cp->ih == NULL) { 1321 #endif 1322 printf("%s: no compatibility interrupt for use by %s " 1323 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1324 cp->hw_ok = 0; 1325 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1326 } 1327 #endif 1328 } 1329 1330 void 1331 pciide_print_modes(cp) 1332 struct pciide_channel *cp; 1333 { 1334 wdc_print_modes(&cp->wdc_channel); 1335 } 1336 1337 void 1338 default_chip_map(sc, pa) 1339 struct pciide_softc *sc; 1340 struct pci_attach_args *pa; 1341 { 1342 struct pciide_channel *cp; 1343 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1344 pcireg_t csr; 1345 int channel, drive; 1346 struct ata_drive_datas *drvp; 1347 u_int8_t idedma_ctl; 1348 bus_size_t cmdsize, ctlsize; 1349 char *failreason; 1350 1351 if (pciide_chipen(sc, pa) == 0) 1352 return; 1353 1354 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1355 printf("%s: bus-master DMA support present", 1356 sc->sc_wdcdev.sc_dev.dv_xname); 1357 if (sc->sc_pp == &default_product_desc && 1358 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1359 PCIIDE_OPTIONS_DMA) == 0) { 1360 printf(", but unused (no driver support)"); 1361 sc->sc_dma_ok = 0; 1362 } else { 1363 pciide_mapreg_dma(sc, pa); 1364 if (sc->sc_dma_ok != 0) 1365 printf(", used without full driver " 1366 "support"); 1367 } 1368 } else { 1369 printf("%s: hardware does not support DMA", 1370 sc->sc_wdcdev.sc_dev.dv_xname); 1371 sc->sc_dma_ok = 0; 1372 } 1373 printf("\n"); 1374 if (sc->sc_dma_ok) { 1375 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1376 sc->sc_wdcdev.irqack = pciide_irqack; 1377 } 1378 sc->sc_wdcdev.PIO_cap = 0; 1379 sc->sc_wdcdev.DMA_cap = 0; 1380 1381 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1382 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1383 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1384 1385 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1386 cp = &sc->pciide_channels[channel]; 1387 if (pciide_chansetup(sc, channel, interface) == 0) 1388 continue; 1389 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1390 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1391 &ctlsize, pciide_pci_intr); 1392 } else { 1393 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1394 channel, &cmdsize, &ctlsize); 1395 } 1396 if (cp->hw_ok == 0) 1397 continue; 1398 /* 1399 * Check to see if something appears to be there. 1400 */ 1401 failreason = NULL; 1402 if (!wdcprobe(&cp->wdc_channel)) { 1403 failreason = "not responding; disabled or no drives?"; 1404 goto next; 1405 } 1406 /* 1407 * Now, make sure it's actually attributable to this PCI IDE 1408 * channel by trying to access the channel again while the 1409 * PCI IDE controller's I/O space is disabled. (If the 1410 * channel no longer appears to be there, it belongs to 1411 * this controller.) YUCK! 1412 */ 1413 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1414 PCI_COMMAND_STATUS_REG); 1415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1416 csr & ~PCI_COMMAND_IO_ENABLE); 1417 if (wdcprobe(&cp->wdc_channel)) 1418 failreason = "other hardware responding at addresses"; 1419 pci_conf_write(sc->sc_pc, sc->sc_tag, 1420 PCI_COMMAND_STATUS_REG, csr); 1421 next: 1422 if (failreason) { 1423 printf("%s: %s channel ignored (%s)\n", 1424 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1425 failreason); 1426 cp->hw_ok = 0; 1427 bus_space_unmap(cp->wdc_channel.cmd_iot, 1428 cp->wdc_channel.cmd_ioh, cmdsize); 1429 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1430 bus_space_unmap(cp->wdc_channel.ctl_iot, 1431 cp->ctl_baseioh, ctlsize); 1432 else 1433 bus_space_unmap(cp->wdc_channel.ctl_iot, 1434 cp->wdc_channel.ctl_ioh, ctlsize); 1435 } else { 1436 pciide_map_compat_intr(pa, cp, channel, interface); 1437 } 1438 if (cp->hw_ok) { 1439 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1440 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1441 wdcattach(&cp->wdc_channel); 1442 } 1443 } 1444 1445 if (sc->sc_dma_ok == 0) 1446 return; 1447 1448 /* Allocate DMA maps */ 1449 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1450 idedma_ctl = 0; 1451 cp = &sc->pciide_channels[channel]; 1452 for (drive = 0; drive < 2; drive++) { 1453 drvp = &cp->wdc_channel.ch_drive[drive]; 1454 /* If no drive, skip */ 1455 if ((drvp->drive_flags & DRIVE) == 0) 1456 continue; 1457 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1458 continue; 1459 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1460 /* Abort DMA setup */ 1461 printf("%s:%d:%d: can't allocate DMA maps, " 1462 "using PIO transfers\n", 1463 sc->sc_wdcdev.sc_dev.dv_xname, 1464 channel, drive); 1465 drvp->drive_flags &= ~DRIVE_DMA; 1466 } 1467 printf("%s:%d:%d: using DMA data transfers\n", 1468 sc->sc_wdcdev.sc_dev.dv_xname, 1469 channel, drive); 1470 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1471 } 1472 if (idedma_ctl != 0) { 1473 /* Add software bits in status register */ 1474 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1475 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1476 idedma_ctl); 1477 } 1478 } 1479 } 1480 1481 void 1482 piix_chip_map(sc, pa) 1483 struct pciide_softc *sc; 1484 struct pci_attach_args *pa; 1485 { 1486 struct pciide_channel *cp; 1487 int channel; 1488 u_int32_t idetim; 1489 bus_size_t cmdsize, ctlsize; 1490 1491 if (pciide_chipen(sc, pa) == 0) 1492 return; 1493 1494 printf("%s: bus-master DMA support present", 1495 sc->sc_wdcdev.sc_dev.dv_xname); 1496 pciide_mapreg_dma(sc, pa); 1497 printf("\n"); 1498 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1499 WDC_CAPABILITY_MODE; 1500 if (sc->sc_dma_ok) { 1501 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1502 sc->sc_wdcdev.irqack = pciide_irqack; 1503 switch(sc->sc_pp->ide_product) { 1504 case PCI_PRODUCT_INTEL_82371AB_IDE: 1505 case PCI_PRODUCT_INTEL_82440MX_IDE: 1506 case PCI_PRODUCT_INTEL_82801AA_IDE: 1507 case PCI_PRODUCT_INTEL_82801AB_IDE: 1508 case PCI_PRODUCT_INTEL_82801BA_IDE: 1509 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1510 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1511 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1512 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1513 } 1514 } 1515 sc->sc_wdcdev.PIO_cap = 4; 1516 sc->sc_wdcdev.DMA_cap = 2; 1517 switch(sc->sc_pp->ide_product) { 1518 case PCI_PRODUCT_INTEL_82801AA_IDE: 1519 sc->sc_wdcdev.UDMA_cap = 4; 1520 break; 1521 case PCI_PRODUCT_INTEL_82801BA_IDE: 1522 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1523 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1524 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1525 sc->sc_wdcdev.UDMA_cap = 5; 1526 break; 1527 default: 1528 sc->sc_wdcdev.UDMA_cap = 2; 1529 } 1530 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1531 sc->sc_wdcdev.set_modes = piix_setup_channel; 1532 else 1533 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1534 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1535 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1536 1537 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1538 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1539 DEBUG_PROBE); 1540 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1541 WDCDEBUG_PRINT((", sidetim=0x%x", 1542 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1543 DEBUG_PROBE); 1544 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1545 WDCDEBUG_PRINT((", udamreg 0x%x", 1546 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1547 DEBUG_PROBE); 1548 } 1549 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1555 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1556 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1557 DEBUG_PROBE); 1558 } 1559 1560 } 1561 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1562 1563 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1564 cp = &sc->pciide_channels[channel]; 1565 /* PIIX is compat-only */ 1566 if (pciide_chansetup(sc, channel, 0) == 0) 1567 continue; 1568 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1569 if ((PIIX_IDETIM_READ(idetim, channel) & 1570 PIIX_IDETIM_IDE) == 0) { 1571 printf("%s: %s channel ignored (disabled)\n", 1572 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1573 continue; 1574 } 1575 /* PIIX are compat-only pciide devices */ 1576 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1577 if (cp->hw_ok == 0) 1578 continue; 1579 if (pciide_chan_candisable(cp)) { 1580 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1581 channel); 1582 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1583 idetim); 1584 } 1585 pciide_map_compat_intr(pa, cp, channel, 0); 1586 if (cp->hw_ok == 0) 1587 continue; 1588 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1589 } 1590 1591 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1592 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1593 DEBUG_PROBE); 1594 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1595 WDCDEBUG_PRINT((", sidetim=0x%x", 1596 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1597 DEBUG_PROBE); 1598 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1599 WDCDEBUG_PRINT((", udamreg 0x%x", 1600 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1601 DEBUG_PROBE); 1602 } 1603 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1604 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1605 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1606 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1609 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1610 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1611 DEBUG_PROBE); 1612 } 1613 } 1614 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1615 } 1616 1617 void 1618 piix_setup_channel(chp) 1619 struct channel_softc *chp; 1620 { 1621 u_int8_t mode[2], drive; 1622 u_int32_t oidetim, idetim, idedma_ctl; 1623 struct pciide_channel *cp = (struct pciide_channel*)chp; 1624 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1625 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1626 1627 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1628 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1629 idedma_ctl = 0; 1630 1631 /* set up new idetim: Enable IDE registers decode */ 1632 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1633 chp->channel); 1634 1635 /* setup DMA */ 1636 pciide_channel_dma_setup(cp); 1637 1638 /* 1639 * Here we have to mess up with drives mode: PIIX can't have 1640 * different timings for master and slave drives. 1641 * We need to find the best combination. 1642 */ 1643 1644 /* If both drives supports DMA, take the lower mode */ 1645 if ((drvp[0].drive_flags & DRIVE_DMA) && 1646 (drvp[1].drive_flags & DRIVE_DMA)) { 1647 mode[0] = mode[1] = 1648 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1649 drvp[0].DMA_mode = mode[0]; 1650 drvp[1].DMA_mode = mode[1]; 1651 goto ok; 1652 } 1653 /* 1654 * If only one drive supports DMA, use its mode, and 1655 * put the other one in PIO mode 0 if mode not compatible 1656 */ 1657 if (drvp[0].drive_flags & DRIVE_DMA) { 1658 mode[0] = drvp[0].DMA_mode; 1659 mode[1] = drvp[1].PIO_mode; 1660 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1661 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1662 mode[1] = drvp[1].PIO_mode = 0; 1663 goto ok; 1664 } 1665 if (drvp[1].drive_flags & DRIVE_DMA) { 1666 mode[1] = drvp[1].DMA_mode; 1667 mode[0] = drvp[0].PIO_mode; 1668 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1669 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1670 mode[0] = drvp[0].PIO_mode = 0; 1671 goto ok; 1672 } 1673 /* 1674 * If both drives are not DMA, takes the lower mode, unless 1675 * one of them is PIO mode < 2 1676 */ 1677 if (drvp[0].PIO_mode < 2) { 1678 mode[0] = drvp[0].PIO_mode = 0; 1679 mode[1] = drvp[1].PIO_mode; 1680 } else if (drvp[1].PIO_mode < 2) { 1681 mode[1] = drvp[1].PIO_mode = 0; 1682 mode[0] = drvp[0].PIO_mode; 1683 } else { 1684 mode[0] = mode[1] = 1685 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1686 drvp[0].PIO_mode = mode[0]; 1687 drvp[1].PIO_mode = mode[1]; 1688 } 1689 ok: /* The modes are setup */ 1690 for (drive = 0; drive < 2; drive++) { 1691 if (drvp[drive].drive_flags & DRIVE_DMA) { 1692 idetim |= piix_setup_idetim_timings( 1693 mode[drive], 1, chp->channel); 1694 goto end; 1695 } 1696 } 1697 /* If we are there, none of the drives are DMA */ 1698 if (mode[0] >= 2) 1699 idetim |= piix_setup_idetim_timings( 1700 mode[0], 0, chp->channel); 1701 else 1702 idetim |= piix_setup_idetim_timings( 1703 mode[1], 0, chp->channel); 1704 end: /* 1705 * timing mode is now set up in the controller. Enable 1706 * it per-drive 1707 */ 1708 for (drive = 0; drive < 2; drive++) { 1709 /* If no drive, skip */ 1710 if ((drvp[drive].drive_flags & DRIVE) == 0) 1711 continue; 1712 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1713 if (drvp[drive].drive_flags & DRIVE_DMA) 1714 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1715 } 1716 if (idedma_ctl != 0) { 1717 /* Add software bits in status register */ 1718 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1719 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1720 idedma_ctl); 1721 } 1722 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1723 pciide_print_modes(cp); 1724 } 1725 1726 void 1727 piix3_4_setup_channel(chp) 1728 struct channel_softc *chp; 1729 { 1730 struct ata_drive_datas *drvp; 1731 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1732 struct pciide_channel *cp = (struct pciide_channel*)chp; 1733 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1734 int drive; 1735 int channel = chp->channel; 1736 1737 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1738 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1739 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1740 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1741 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1742 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1743 PIIX_SIDETIM_RTC_MASK(channel)); 1744 1745 idedma_ctl = 0; 1746 /* If channel disabled, no need to go further */ 1747 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1748 return; 1749 /* set up new idetim: Enable IDE registers decode */ 1750 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1751 1752 /* setup DMA if needed */ 1753 pciide_channel_dma_setup(cp); 1754 1755 for (drive = 0; drive < 2; drive++) { 1756 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1757 PIIX_UDMATIM_SET(0x3, channel, drive)); 1758 drvp = &chp->ch_drive[drive]; 1759 /* If no drive, skip */ 1760 if ((drvp->drive_flags & DRIVE) == 0) 1761 continue; 1762 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1763 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1764 goto pio; 1765 1766 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1767 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1768 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1769 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1770 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1771 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1772 ideconf |= PIIX_CONFIG_PINGPONG; 1773 } 1774 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1775 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1776 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1777 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1778 /* setup Ultra/100 */ 1779 if (drvp->UDMA_mode > 2 && 1780 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1781 drvp->UDMA_mode = 2; 1782 if (drvp->UDMA_mode > 4) { 1783 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1784 } else { 1785 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1786 if (drvp->UDMA_mode > 2) { 1787 ideconf |= PIIX_CONFIG_UDMA66(channel, 1788 drive); 1789 } else { 1790 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1791 drive); 1792 } 1793 } 1794 } 1795 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1796 /* setup Ultra/66 */ 1797 if (drvp->UDMA_mode > 2 && 1798 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1799 drvp->UDMA_mode = 2; 1800 if (drvp->UDMA_mode > 2) 1801 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1802 else 1803 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1804 } 1805 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1806 (drvp->drive_flags & DRIVE_UDMA)) { 1807 /* use Ultra/DMA */ 1808 drvp->drive_flags &= ~DRIVE_DMA; 1809 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1810 udmareg |= PIIX_UDMATIM_SET( 1811 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1812 } else { 1813 /* use Multiword DMA */ 1814 drvp->drive_flags &= ~DRIVE_UDMA; 1815 if (drive == 0) { 1816 idetim |= piix_setup_idetim_timings( 1817 drvp->DMA_mode, 1, channel); 1818 } else { 1819 sidetim |= piix_setup_sidetim_timings( 1820 drvp->DMA_mode, 1, channel); 1821 idetim =PIIX_IDETIM_SET(idetim, 1822 PIIX_IDETIM_SITRE, channel); 1823 } 1824 } 1825 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1826 1827 pio: /* use PIO mode */ 1828 idetim |= piix_setup_idetim_drvs(drvp); 1829 if (drive == 0) { 1830 idetim |= piix_setup_idetim_timings( 1831 drvp->PIO_mode, 0, channel); 1832 } else { 1833 sidetim |= piix_setup_sidetim_timings( 1834 drvp->PIO_mode, 0, channel); 1835 idetim =PIIX_IDETIM_SET(idetim, 1836 PIIX_IDETIM_SITRE, channel); 1837 } 1838 } 1839 if (idedma_ctl != 0) { 1840 /* Add software bits in status register */ 1841 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1842 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1843 idedma_ctl); 1844 } 1845 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1846 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1847 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1848 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1849 pciide_print_modes(cp); 1850 } 1851 1852 1853 /* setup ISP and RTC fields, based on mode */ 1854 static u_int32_t 1855 piix_setup_idetim_timings(mode, dma, channel) 1856 u_int8_t mode; 1857 u_int8_t dma; 1858 u_int8_t channel; 1859 { 1860 1861 if (dma) 1862 return PIIX_IDETIM_SET(0, 1863 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1864 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1865 channel); 1866 else 1867 return PIIX_IDETIM_SET(0, 1868 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1869 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1870 channel); 1871 } 1872 1873 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1874 static u_int32_t 1875 piix_setup_idetim_drvs(drvp) 1876 struct ata_drive_datas *drvp; 1877 { 1878 u_int32_t ret = 0; 1879 struct channel_softc *chp = drvp->chnl_softc; 1880 u_int8_t channel = chp->channel; 1881 u_int8_t drive = drvp->drive; 1882 1883 /* 1884 * If drive is using UDMA, timings setups are independant 1885 * So just check DMA and PIO here. 1886 */ 1887 if (drvp->drive_flags & DRIVE_DMA) { 1888 /* if mode = DMA mode 0, use compatible timings */ 1889 if ((drvp->drive_flags & DRIVE_DMA) && 1890 drvp->DMA_mode == 0) { 1891 drvp->PIO_mode = 0; 1892 return ret; 1893 } 1894 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1895 /* 1896 * PIO and DMA timings are the same, use fast timings for PIO 1897 * too, else use compat timings. 1898 */ 1899 if ((piix_isp_pio[drvp->PIO_mode] != 1900 piix_isp_dma[drvp->DMA_mode]) || 1901 (piix_rtc_pio[drvp->PIO_mode] != 1902 piix_rtc_dma[drvp->DMA_mode])) 1903 drvp->PIO_mode = 0; 1904 /* if PIO mode <= 2, use compat timings for PIO */ 1905 if (drvp->PIO_mode <= 2) { 1906 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1907 channel); 1908 return ret; 1909 } 1910 } 1911 1912 /* 1913 * Now setup PIO modes. If mode < 2, use compat timings. 1914 * Else enable fast timings. Enable IORDY and prefetch/post 1915 * if PIO mode >= 3. 1916 */ 1917 1918 if (drvp->PIO_mode < 2) 1919 return ret; 1920 1921 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1922 if (drvp->PIO_mode >= 3) { 1923 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1924 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1925 } 1926 return ret; 1927 } 1928 1929 /* setup values in SIDETIM registers, based on mode */ 1930 static u_int32_t 1931 piix_setup_sidetim_timings(mode, dma, channel) 1932 u_int8_t mode; 1933 u_int8_t dma; 1934 u_int8_t channel; 1935 { 1936 if (dma) 1937 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1938 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1939 else 1940 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1941 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1942 } 1943 1944 void 1945 amd7x6_chip_map(sc, pa) 1946 struct pciide_softc *sc; 1947 struct pci_attach_args *pa; 1948 { 1949 struct pciide_channel *cp; 1950 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1951 int channel; 1952 pcireg_t chanenable; 1953 bus_size_t cmdsize, ctlsize; 1954 1955 if (pciide_chipen(sc, pa) == 0) 1956 return; 1957 printf("%s: bus-master DMA support present", 1958 sc->sc_wdcdev.sc_dev.dv_xname); 1959 pciide_mapreg_dma(sc, pa); 1960 printf("\n"); 1961 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1962 WDC_CAPABILITY_MODE; 1963 if (sc->sc_dma_ok) { 1964 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1965 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1966 sc->sc_wdcdev.irqack = pciide_irqack; 1967 } 1968 sc->sc_wdcdev.PIO_cap = 4; 1969 sc->sc_wdcdev.DMA_cap = 2; 1970 1971 switch (sc->sc_pp->ide_product) { 1972 case PCI_PRODUCT_AMD_PBC766_IDE: 1973 case PCI_PRODUCT_AMD_PBC768_IDE: 1974 sc->sc_wdcdev.UDMA_cap = 5; 1975 break; 1976 default: 1977 sc->sc_wdcdev.UDMA_cap = 4; 1978 } 1979 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1980 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1981 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1982 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1983 1984 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1985 DEBUG_PROBE); 1986 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1987 cp = &sc->pciide_channels[channel]; 1988 if (pciide_chansetup(sc, channel, interface) == 0) 1989 continue; 1990 1991 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1992 printf("%s: %s channel ignored (disabled)\n", 1993 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1994 continue; 1995 } 1996 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1997 pciide_pci_intr); 1998 1999 if (pciide_chan_candisable(cp)) 2000 chanenable &= ~AMD7X6_CHAN_EN(channel); 2001 pciide_map_compat_intr(pa, cp, channel, interface); 2002 if (cp->hw_ok == 0) 2003 continue; 2004 2005 amd7x6_setup_channel(&cp->wdc_channel); 2006 } 2007 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2008 chanenable); 2009 return; 2010 } 2011 2012 void 2013 amd7x6_setup_channel(chp) 2014 struct channel_softc *chp; 2015 { 2016 u_int32_t udmatim_reg, datatim_reg; 2017 u_int8_t idedma_ctl; 2018 int mode, drive; 2019 struct ata_drive_datas *drvp; 2020 struct pciide_channel *cp = (struct pciide_channel*)chp; 2021 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2022 #ifndef PCIIDE_AMD756_ENABLEDMA 2023 int rev = PCI_REVISION( 2024 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2025 #endif 2026 2027 idedma_ctl = 0; 2028 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2029 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2030 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2031 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2032 2033 /* setup DMA if needed */ 2034 pciide_channel_dma_setup(cp); 2035 2036 for (drive = 0; drive < 2; drive++) { 2037 drvp = &chp->ch_drive[drive]; 2038 /* If no drive, skip */ 2039 if ((drvp->drive_flags & DRIVE) == 0) 2040 continue; 2041 /* add timing values, setup DMA if needed */ 2042 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2043 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2044 mode = drvp->PIO_mode; 2045 goto pio; 2046 } 2047 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2048 (drvp->drive_flags & DRIVE_UDMA)) { 2049 /* use Ultra/DMA */ 2050 drvp->drive_flags &= ~DRIVE_DMA; 2051 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2052 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2053 AMD7X6_UDMA_TIME(chp->channel, drive, 2054 amd7x6_udma_tim[drvp->UDMA_mode]); 2055 /* can use PIO timings, MW DMA unused */ 2056 mode = drvp->PIO_mode; 2057 } else { 2058 /* use Multiword DMA, but only if revision is OK */ 2059 drvp->drive_flags &= ~DRIVE_UDMA; 2060 #ifndef PCIIDE_AMD756_ENABLEDMA 2061 /* 2062 * The workaround doesn't seem to be necessary 2063 * with all drives, so it can be disabled by 2064 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2065 * triggered. 2066 */ 2067 if (sc->sc_pp->ide_product == 2068 PCI_PRODUCT_AMD_PBC756_IDE && 2069 AMD756_CHIPREV_DISABLEDMA(rev)) { 2070 printf("%s:%d:%d: multi-word DMA disabled due " 2071 "to chip revision\n", 2072 sc->sc_wdcdev.sc_dev.dv_xname, 2073 chp->channel, drive); 2074 mode = drvp->PIO_mode; 2075 drvp->drive_flags &= ~DRIVE_DMA; 2076 goto pio; 2077 } 2078 #endif 2079 /* mode = min(pio, dma+2) */ 2080 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2081 mode = drvp->PIO_mode; 2082 else 2083 mode = drvp->DMA_mode + 2; 2084 } 2085 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2086 2087 pio: /* setup PIO mode */ 2088 if (mode <= 2) { 2089 drvp->DMA_mode = 0; 2090 drvp->PIO_mode = 0; 2091 mode = 0; 2092 } else { 2093 drvp->PIO_mode = mode; 2094 drvp->DMA_mode = mode - 2; 2095 } 2096 datatim_reg |= 2097 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2098 amd7x6_pio_set[mode]) | 2099 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2100 amd7x6_pio_rec[mode]); 2101 } 2102 if (idedma_ctl != 0) { 2103 /* Add software bits in status register */ 2104 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2105 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2106 idedma_ctl); 2107 } 2108 pciide_print_modes(cp); 2109 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2110 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2111 } 2112 2113 void 2114 apollo_chip_map(sc, pa) 2115 struct pciide_softc *sc; 2116 struct pci_attach_args *pa; 2117 { 2118 struct pciide_channel *cp; 2119 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2120 int channel; 2121 u_int32_t ideconf; 2122 bus_size_t cmdsize, ctlsize; 2123 pcitag_t pcib_tag; 2124 pcireg_t pcib_id, pcib_class; 2125 2126 if (pciide_chipen(sc, pa) == 0) 2127 return; 2128 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2129 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2130 /* and read ID and rev of the ISA bridge */ 2131 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2132 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2133 printf(": VIA Technologies "); 2134 switch (PCI_PRODUCT(pcib_id)) { 2135 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2136 printf("VT82C586 (Apollo VP) "); 2137 if(PCI_REVISION(pcib_class) >= 0x02) { 2138 printf("ATA33 controller\n"); 2139 sc->sc_wdcdev.UDMA_cap = 2; 2140 } else { 2141 printf("controller\n"); 2142 sc->sc_wdcdev.UDMA_cap = 0; 2143 } 2144 break; 2145 case PCI_PRODUCT_VIATECH_VT82C596A: 2146 printf("VT82C596A (Apollo Pro) "); 2147 if (PCI_REVISION(pcib_class) >= 0x12) { 2148 printf("ATA66 controller\n"); 2149 sc->sc_wdcdev.UDMA_cap = 4; 2150 } else { 2151 printf("ATA33 controller\n"); 2152 sc->sc_wdcdev.UDMA_cap = 2; 2153 } 2154 break; 2155 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2156 printf("VT82C686A (Apollo KX133) "); 2157 if (PCI_REVISION(pcib_class) >= 0x40) { 2158 printf("ATA100 controller\n"); 2159 sc->sc_wdcdev.UDMA_cap = 5; 2160 } else { 2161 printf("ATA66 controller\n"); 2162 sc->sc_wdcdev.UDMA_cap = 4; 2163 } 2164 break; 2165 case PCI_PRODUCT_VIATECH_VT8233: 2166 printf("VT8233 ATA100 controller\n"); 2167 sc->sc_wdcdev.UDMA_cap = 5; 2168 break; 2169 default: 2170 printf("unknown ATA controller\n"); 2171 sc->sc_wdcdev.UDMA_cap = 0; 2172 } 2173 2174 printf("%s: bus-master DMA support present", 2175 sc->sc_wdcdev.sc_dev.dv_xname); 2176 pciide_mapreg_dma(sc, pa); 2177 printf("\n"); 2178 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2179 WDC_CAPABILITY_MODE; 2180 if (sc->sc_dma_ok) { 2181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2182 sc->sc_wdcdev.irqack = pciide_irqack; 2183 if (sc->sc_wdcdev.UDMA_cap > 0) 2184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2185 } 2186 sc->sc_wdcdev.PIO_cap = 4; 2187 sc->sc_wdcdev.DMA_cap = 2; 2188 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2189 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2190 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2191 2192 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2193 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2194 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2195 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2196 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2197 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2198 DEBUG_PROBE); 2199 2200 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2201 cp = &sc->pciide_channels[channel]; 2202 if (pciide_chansetup(sc, channel, interface) == 0) 2203 continue; 2204 2205 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2206 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2207 printf("%s: %s channel ignored (disabled)\n", 2208 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2209 continue; 2210 } 2211 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2212 pciide_pci_intr); 2213 if (cp->hw_ok == 0) 2214 continue; 2215 if (pciide_chan_candisable(cp)) { 2216 ideconf &= ~APO_IDECONF_EN(channel); 2217 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2218 ideconf); 2219 } 2220 pciide_map_compat_intr(pa, cp, channel, interface); 2221 2222 if (cp->hw_ok == 0) 2223 continue; 2224 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2225 } 2226 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2227 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2228 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2229 } 2230 2231 void 2232 apollo_setup_channel(chp) 2233 struct channel_softc *chp; 2234 { 2235 u_int32_t udmatim_reg, datatim_reg; 2236 u_int8_t idedma_ctl; 2237 int mode, drive; 2238 struct ata_drive_datas *drvp; 2239 struct pciide_channel *cp = (struct pciide_channel*)chp; 2240 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2241 2242 idedma_ctl = 0; 2243 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2244 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2245 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2246 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2247 2248 /* setup DMA if needed */ 2249 pciide_channel_dma_setup(cp); 2250 2251 for (drive = 0; drive < 2; drive++) { 2252 drvp = &chp->ch_drive[drive]; 2253 /* If no drive, skip */ 2254 if ((drvp->drive_flags & DRIVE) == 0) 2255 continue; 2256 /* add timing values, setup DMA if needed */ 2257 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2258 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2259 mode = drvp->PIO_mode; 2260 goto pio; 2261 } 2262 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2263 (drvp->drive_flags & DRIVE_UDMA)) { 2264 /* use Ultra/DMA */ 2265 drvp->drive_flags &= ~DRIVE_DMA; 2266 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2267 APO_UDMA_EN_MTH(chp->channel, drive); 2268 if (sc->sc_wdcdev.UDMA_cap == 5) { 2269 /* 686b */ 2270 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2271 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2272 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2273 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2274 /* 596b or 686a */ 2275 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2276 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2277 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2278 } else { 2279 /* 596a or 586b */ 2280 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2281 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2282 } 2283 /* can use PIO timings, MW DMA unused */ 2284 mode = drvp->PIO_mode; 2285 } else { 2286 /* use Multiword DMA */ 2287 drvp->drive_flags &= ~DRIVE_UDMA; 2288 /* mode = min(pio, dma+2) */ 2289 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2290 mode = drvp->PIO_mode; 2291 else 2292 mode = drvp->DMA_mode + 2; 2293 } 2294 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2295 2296 pio: /* setup PIO mode */ 2297 if (mode <= 2) { 2298 drvp->DMA_mode = 0; 2299 drvp->PIO_mode = 0; 2300 mode = 0; 2301 } else { 2302 drvp->PIO_mode = mode; 2303 drvp->DMA_mode = mode - 2; 2304 } 2305 datatim_reg |= 2306 APO_DATATIM_PULSE(chp->channel, drive, 2307 apollo_pio_set[mode]) | 2308 APO_DATATIM_RECOV(chp->channel, drive, 2309 apollo_pio_rec[mode]); 2310 } 2311 if (idedma_ctl != 0) { 2312 /* Add software bits in status register */ 2313 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2314 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2315 idedma_ctl); 2316 } 2317 pciide_print_modes(cp); 2318 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2319 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2320 } 2321 2322 void 2323 cmd_channel_map(pa, sc, channel) 2324 struct pci_attach_args *pa; 2325 struct pciide_softc *sc; 2326 int channel; 2327 { 2328 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2329 bus_size_t cmdsize, ctlsize; 2330 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2331 int interface, one_channel; 2332 2333 /* 2334 * The 0648/0649 can be told to identify as a RAID controller. 2335 * In this case, we have to fake interface 2336 */ 2337 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2338 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2339 PCIIDE_INTERFACE_SETTABLE(1); 2340 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2341 CMD_CONF_DSA1) 2342 interface |= PCIIDE_INTERFACE_PCI(0) | 2343 PCIIDE_INTERFACE_PCI(1); 2344 } else { 2345 interface = PCI_INTERFACE(pa->pa_class); 2346 } 2347 2348 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2349 cp->name = PCIIDE_CHANNEL_NAME(channel); 2350 cp->wdc_channel.channel = channel; 2351 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2352 2353 /* 2354 * Older CMD64X doesn't have independant channels 2355 */ 2356 switch (sc->sc_pp->ide_product) { 2357 case PCI_PRODUCT_CMDTECH_649: 2358 one_channel = 0; 2359 break; 2360 default: 2361 one_channel = 1; 2362 break; 2363 } 2364 2365 if (channel > 0 && one_channel) { 2366 cp->wdc_channel.ch_queue = 2367 sc->pciide_channels[0].wdc_channel.ch_queue; 2368 } else { 2369 cp->wdc_channel.ch_queue = 2370 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2371 } 2372 if (cp->wdc_channel.ch_queue == NULL) { 2373 printf("%s %s channel: " 2374 "can't allocate memory for command queue", 2375 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2376 return; 2377 } 2378 2379 printf("%s: %s channel %s to %s mode\n", 2380 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2381 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2382 "configured" : "wired", 2383 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2384 "native-PCI" : "compatibility"); 2385 2386 /* 2387 * with a CMD PCI64x, if we get here, the first channel is enabled: 2388 * there's no way to disable the first channel without disabling 2389 * the whole device 2390 */ 2391 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2392 printf("%s: %s channel ignored (disabled)\n", 2393 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2394 return; 2395 } 2396 2397 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2398 if (cp->hw_ok == 0) 2399 return; 2400 if (channel == 1) { 2401 if (pciide_chan_candisable(cp)) { 2402 ctrl &= ~CMD_CTRL_2PORT; 2403 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2404 CMD_CTRL, ctrl); 2405 } 2406 } 2407 pciide_map_compat_intr(pa, cp, channel, interface); 2408 } 2409 2410 int 2411 cmd_pci_intr(arg) 2412 void *arg; 2413 { 2414 struct pciide_softc *sc = arg; 2415 struct pciide_channel *cp; 2416 struct channel_softc *wdc_cp; 2417 int i, rv, crv; 2418 u_int32_t priirq, secirq; 2419 2420 rv = 0; 2421 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2422 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2423 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2424 cp = &sc->pciide_channels[i]; 2425 wdc_cp = &cp->wdc_channel; 2426 /* If a compat channel skip. */ 2427 if (cp->compat) 2428 continue; 2429 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2430 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2431 crv = wdcintr(wdc_cp); 2432 if (crv == 0) 2433 printf("%s:%d: bogus intr\n", 2434 sc->sc_wdcdev.sc_dev.dv_xname, i); 2435 else 2436 rv = 1; 2437 } 2438 } 2439 return rv; 2440 } 2441 2442 void 2443 cmd_chip_map(sc, pa) 2444 struct pciide_softc *sc; 2445 struct pci_attach_args *pa; 2446 { 2447 int channel; 2448 2449 /* 2450 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2451 * and base adresses registers can be disabled at 2452 * hardware level. In this case, the device is wired 2453 * in compat mode and its first channel is always enabled, 2454 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2455 * In fact, it seems that the first channel of the CMD PCI0640 2456 * can't be disabled. 2457 */ 2458 2459 #ifdef PCIIDE_CMD064x_DISABLE 2460 if (pciide_chipen(sc, pa) == 0) 2461 return; 2462 #endif 2463 2464 printf("%s: hardware does not support DMA\n", 2465 sc->sc_wdcdev.sc_dev.dv_xname); 2466 sc->sc_dma_ok = 0; 2467 2468 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2469 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2470 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2471 2472 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2473 cmd_channel_map(pa, sc, channel); 2474 } 2475 } 2476 2477 void 2478 cmd0643_9_chip_map(sc, pa) 2479 struct pciide_softc *sc; 2480 struct pci_attach_args *pa; 2481 { 2482 struct pciide_channel *cp; 2483 int channel; 2484 pcireg_t rev = PCI_REVISION(pa->pa_class); 2485 2486 /* 2487 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2488 * and base adresses registers can be disabled at 2489 * hardware level. In this case, the device is wired 2490 * in compat mode and its first channel is always enabled, 2491 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2492 * In fact, it seems that the first channel of the CMD PCI0640 2493 * can't be disabled. 2494 */ 2495 2496 #ifdef PCIIDE_CMD064x_DISABLE 2497 if (pciide_chipen(sc, pa) == 0) 2498 return; 2499 #endif 2500 printf("%s: bus-master DMA support present", 2501 sc->sc_wdcdev.sc_dev.dv_xname); 2502 pciide_mapreg_dma(sc, pa); 2503 printf("\n"); 2504 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2505 WDC_CAPABILITY_MODE; 2506 if (sc->sc_dma_ok) { 2507 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2508 switch (sc->sc_pp->ide_product) { 2509 case PCI_PRODUCT_CMDTECH_649: 2510 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2511 sc->sc_wdcdev.UDMA_cap = 5; 2512 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2513 break; 2514 case PCI_PRODUCT_CMDTECH_648: 2515 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2516 sc->sc_wdcdev.UDMA_cap = 4; 2517 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2518 break; 2519 case PCI_PRODUCT_CMDTECH_646: 2520 if (rev >= CMD0646U2_REV) { 2521 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2522 sc->sc_wdcdev.UDMA_cap = 2; 2523 } else if (rev >= CMD0646U_REV) { 2524 /* 2525 * Linux's driver claims that the 646U is broken 2526 * with UDMA. Only enable it if we know what we're 2527 * doing 2528 */ 2529 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2530 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2531 sc->sc_wdcdev.UDMA_cap = 2; 2532 #endif 2533 /* explicitly disable UDMA */ 2534 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2535 CMD_UDMATIM(0), 0); 2536 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2537 CMD_UDMATIM(1), 0); 2538 } 2539 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2540 break; 2541 default: 2542 sc->sc_wdcdev.irqack = pciide_irqack; 2543 } 2544 } 2545 2546 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2547 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2548 sc->sc_wdcdev.PIO_cap = 4; 2549 sc->sc_wdcdev.DMA_cap = 2; 2550 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2551 2552 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2553 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2554 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2555 DEBUG_PROBE); 2556 2557 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2558 cp = &sc->pciide_channels[channel]; 2559 cmd_channel_map(pa, sc, channel); 2560 if (cp->hw_ok == 0) 2561 continue; 2562 cmd0643_9_setup_channel(&cp->wdc_channel); 2563 } 2564 /* 2565 * note - this also makes sure we clear the irq disable and reset 2566 * bits 2567 */ 2568 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2569 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2570 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2571 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2572 DEBUG_PROBE); 2573 } 2574 2575 void 2576 cmd0643_9_setup_channel(chp) 2577 struct channel_softc *chp; 2578 { 2579 struct ata_drive_datas *drvp; 2580 u_int8_t tim; 2581 u_int32_t idedma_ctl, udma_reg; 2582 int drive; 2583 struct pciide_channel *cp = (struct pciide_channel*)chp; 2584 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2585 2586 idedma_ctl = 0; 2587 /* setup DMA if needed */ 2588 pciide_channel_dma_setup(cp); 2589 2590 for (drive = 0; drive < 2; drive++) { 2591 drvp = &chp->ch_drive[drive]; 2592 /* If no drive, skip */ 2593 if ((drvp->drive_flags & DRIVE) == 0) 2594 continue; 2595 /* add timing values, setup DMA if needed */ 2596 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2597 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2598 if (drvp->drive_flags & DRIVE_UDMA) { 2599 /* UltraDMA on a 646U2, 0648 or 0649 */ 2600 drvp->drive_flags &= ~DRIVE_DMA; 2601 udma_reg = pciide_pci_read(sc->sc_pc, 2602 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2603 if (drvp->UDMA_mode > 2 && 2604 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2605 CMD_BICSR) & 2606 CMD_BICSR_80(chp->channel)) == 0) 2607 drvp->UDMA_mode = 2; 2608 if (drvp->UDMA_mode > 2) 2609 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2610 else if (sc->sc_wdcdev.UDMA_cap > 2) 2611 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2612 udma_reg |= CMD_UDMATIM_UDMA(drive); 2613 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2614 CMD_UDMATIM_TIM_OFF(drive)); 2615 udma_reg |= 2616 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2617 CMD_UDMATIM_TIM_OFF(drive)); 2618 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2619 CMD_UDMATIM(chp->channel), udma_reg); 2620 } else { 2621 /* 2622 * use Multiword DMA. 2623 * Timings will be used for both PIO and DMA, 2624 * so adjust DMA mode if needed 2625 * if we have a 0646U2/8/9, turn off UDMA 2626 */ 2627 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2628 udma_reg = pciide_pci_read(sc->sc_pc, 2629 sc->sc_tag, 2630 CMD_UDMATIM(chp->channel)); 2631 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2632 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2633 CMD_UDMATIM(chp->channel), 2634 udma_reg); 2635 } 2636 if (drvp->PIO_mode >= 3 && 2637 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2638 drvp->DMA_mode = drvp->PIO_mode - 2; 2639 } 2640 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2641 } 2642 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2643 } 2644 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2645 CMD_DATA_TIM(chp->channel, drive), tim); 2646 } 2647 if (idedma_ctl != 0) { 2648 /* Add software bits in status register */ 2649 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2650 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2651 idedma_ctl); 2652 } 2653 pciide_print_modes(cp); 2654 } 2655 2656 void 2657 cmd646_9_irqack(chp) 2658 struct channel_softc *chp; 2659 { 2660 u_int32_t priirq, secirq; 2661 struct pciide_channel *cp = (struct pciide_channel*)chp; 2662 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2663 2664 if (chp->channel == 0) { 2665 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2666 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2667 } else { 2668 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2669 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2670 } 2671 pciide_irqack(chp); 2672 } 2673 2674 void 2675 cy693_chip_map(sc, pa) 2676 struct pciide_softc *sc; 2677 struct pci_attach_args *pa; 2678 { 2679 struct pciide_channel *cp; 2680 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2681 bus_size_t cmdsize, ctlsize; 2682 2683 if (pciide_chipen(sc, pa) == 0) 2684 return; 2685 /* 2686 * this chip has 2 PCI IDE functions, one for primary and one for 2687 * secondary. So we need to call pciide_mapregs_compat() with 2688 * the real channel 2689 */ 2690 if (pa->pa_function == 1) { 2691 sc->sc_cy_compatchan = 0; 2692 } else if (pa->pa_function == 2) { 2693 sc->sc_cy_compatchan = 1; 2694 } else { 2695 printf("%s: unexpected PCI function %d\n", 2696 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2697 return; 2698 } 2699 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2700 printf("%s: bus-master DMA support present", 2701 sc->sc_wdcdev.sc_dev.dv_xname); 2702 pciide_mapreg_dma(sc, pa); 2703 } else { 2704 printf("%s: hardware does not support DMA", 2705 sc->sc_wdcdev.sc_dev.dv_xname); 2706 sc->sc_dma_ok = 0; 2707 } 2708 printf("\n"); 2709 2710 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2711 if (sc->sc_cy_handle == NULL) { 2712 printf("%s: unable to map hyperCache control registers\n", 2713 sc->sc_wdcdev.sc_dev.dv_xname); 2714 sc->sc_dma_ok = 0; 2715 } 2716 2717 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2718 WDC_CAPABILITY_MODE; 2719 if (sc->sc_dma_ok) { 2720 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2721 sc->sc_wdcdev.irqack = pciide_irqack; 2722 } 2723 sc->sc_wdcdev.PIO_cap = 4; 2724 sc->sc_wdcdev.DMA_cap = 2; 2725 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2726 2727 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2728 sc->sc_wdcdev.nchannels = 1; 2729 2730 /* Only one channel for this chip; if we are here it's enabled */ 2731 cp = &sc->pciide_channels[0]; 2732 sc->wdc_chanarray[0] = &cp->wdc_channel; 2733 cp->name = PCIIDE_CHANNEL_NAME(0); 2734 cp->wdc_channel.channel = 0; 2735 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2736 cp->wdc_channel.ch_queue = 2737 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2738 if (cp->wdc_channel.ch_queue == NULL) { 2739 printf("%s primary channel: " 2740 "can't allocate memory for command queue", 2741 sc->sc_wdcdev.sc_dev.dv_xname); 2742 return; 2743 } 2744 printf("%s: primary channel %s to ", 2745 sc->sc_wdcdev.sc_dev.dv_xname, 2746 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2747 "configured" : "wired"); 2748 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2749 printf("native-PCI"); 2750 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2751 pciide_pci_intr); 2752 } else { 2753 printf("compatibility"); 2754 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2755 &cmdsize, &ctlsize); 2756 } 2757 printf(" mode\n"); 2758 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2759 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2760 wdcattach(&cp->wdc_channel); 2761 if (pciide_chan_candisable(cp)) { 2762 pci_conf_write(sc->sc_pc, sc->sc_tag, 2763 PCI_COMMAND_STATUS_REG, 0); 2764 } 2765 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2766 if (cp->hw_ok == 0) 2767 return; 2768 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2769 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2770 cy693_setup_channel(&cp->wdc_channel); 2771 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2772 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2773 } 2774 2775 void 2776 cy693_setup_channel(chp) 2777 struct channel_softc *chp; 2778 { 2779 struct ata_drive_datas *drvp; 2780 int drive; 2781 u_int32_t cy_cmd_ctrl; 2782 u_int32_t idedma_ctl; 2783 struct pciide_channel *cp = (struct pciide_channel*)chp; 2784 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2785 int dma_mode = -1; 2786 2787 cy_cmd_ctrl = idedma_ctl = 0; 2788 2789 /* setup DMA if needed */ 2790 pciide_channel_dma_setup(cp); 2791 2792 for (drive = 0; drive < 2; drive++) { 2793 drvp = &chp->ch_drive[drive]; 2794 /* If no drive, skip */ 2795 if ((drvp->drive_flags & DRIVE) == 0) 2796 continue; 2797 /* add timing values, setup DMA if needed */ 2798 if (drvp->drive_flags & DRIVE_DMA) { 2799 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2800 /* use Multiword DMA */ 2801 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2802 dma_mode = drvp->DMA_mode; 2803 } 2804 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2805 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2806 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2807 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2808 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2809 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2810 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2811 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2812 } 2813 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2814 chp->ch_drive[0].DMA_mode = dma_mode; 2815 chp->ch_drive[1].DMA_mode = dma_mode; 2816 2817 if (dma_mode == -1) 2818 dma_mode = 0; 2819 2820 if (sc->sc_cy_handle != NULL) { 2821 /* Note: `multiple' is implied. */ 2822 cy82c693_write(sc->sc_cy_handle, 2823 (sc->sc_cy_compatchan == 0) ? 2824 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2825 } 2826 2827 pciide_print_modes(cp); 2828 2829 if (idedma_ctl != 0) { 2830 /* Add software bits in status register */ 2831 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2832 IDEDMA_CTL, idedma_ctl); 2833 } 2834 } 2835 2836 static int 2837 sis_hostbr_match(pa) 2838 struct pci_attach_args *pa; 2839 { 2840 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2841 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2842 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2843 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2844 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2845 } 2846 2847 void 2848 sis_chip_map(sc, pa) 2849 struct pciide_softc *sc; 2850 struct pci_attach_args *pa; 2851 { 2852 struct pciide_channel *cp; 2853 int channel; 2854 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2855 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2856 pcireg_t rev = PCI_REVISION(pa->pa_class); 2857 bus_size_t cmdsize, ctlsize; 2858 pcitag_t pchb_tag; 2859 pcireg_t pchb_id, pchb_class; 2860 2861 if (pciide_chipen(sc, pa) == 0) 2862 return; 2863 printf("%s: bus-master DMA support present", 2864 sc->sc_wdcdev.sc_dev.dv_xname); 2865 pciide_mapreg_dma(sc, pa); 2866 printf("\n"); 2867 2868 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2869 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2870 /* and read ID and rev of the ISA bridge */ 2871 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2872 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2873 2874 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2875 WDC_CAPABILITY_MODE; 2876 if (sc->sc_dma_ok) { 2877 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2878 sc->sc_wdcdev.irqack = pciide_irqack; 2879 /* 2880 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2881 * have problems with UDMA (info provided by Christos) 2882 */ 2883 if (rev >= 0xd0 && 2884 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2885 PCI_REVISION(pchb_class) >= 0x03)) 2886 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2887 } 2888 2889 sc->sc_wdcdev.PIO_cap = 4; 2890 sc->sc_wdcdev.DMA_cap = 2; 2891 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2892 /* 2893 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2894 * chipsets. 2895 */ 2896 sc->sc_wdcdev.UDMA_cap = 2897 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2898 sc->sc_wdcdev.set_modes = sis_setup_channel; 2899 2900 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2901 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2902 2903 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2904 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2905 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2906 2907 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2908 cp = &sc->pciide_channels[channel]; 2909 if (pciide_chansetup(sc, channel, interface) == 0) 2910 continue; 2911 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2912 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2913 printf("%s: %s channel ignored (disabled)\n", 2914 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2915 continue; 2916 } 2917 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2918 pciide_pci_intr); 2919 if (cp->hw_ok == 0) 2920 continue; 2921 if (pciide_chan_candisable(cp)) { 2922 if (channel == 0) 2923 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2924 else 2925 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2926 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2927 sis_ctr0); 2928 } 2929 pciide_map_compat_intr(pa, cp, channel, interface); 2930 if (cp->hw_ok == 0) 2931 continue; 2932 sis_setup_channel(&cp->wdc_channel); 2933 } 2934 } 2935 2936 void 2937 sis_setup_channel(chp) 2938 struct channel_softc *chp; 2939 { 2940 struct ata_drive_datas *drvp; 2941 int drive; 2942 u_int32_t sis_tim; 2943 u_int32_t idedma_ctl; 2944 struct pciide_channel *cp = (struct pciide_channel*)chp; 2945 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2946 2947 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2948 "channel %d 0x%x\n", chp->channel, 2949 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2950 DEBUG_PROBE); 2951 sis_tim = 0; 2952 idedma_ctl = 0; 2953 /* setup DMA if needed */ 2954 pciide_channel_dma_setup(cp); 2955 2956 for (drive = 0; drive < 2; drive++) { 2957 drvp = &chp->ch_drive[drive]; 2958 /* If no drive, skip */ 2959 if ((drvp->drive_flags & DRIVE) == 0) 2960 continue; 2961 /* add timing values, setup DMA if needed */ 2962 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2963 (drvp->drive_flags & DRIVE_UDMA) == 0) 2964 goto pio; 2965 2966 if (drvp->drive_flags & DRIVE_UDMA) { 2967 /* use Ultra/DMA */ 2968 drvp->drive_flags &= ~DRIVE_DMA; 2969 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2970 SIS_TIM_UDMA_TIME_OFF(drive); 2971 sis_tim |= SIS_TIM_UDMA_EN(drive); 2972 } else { 2973 /* 2974 * use Multiword DMA 2975 * Timings will be used for both PIO and DMA, 2976 * so adjust DMA mode if needed 2977 */ 2978 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2979 drvp->PIO_mode = drvp->DMA_mode + 2; 2980 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2981 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2982 drvp->PIO_mode - 2 : 0; 2983 if (drvp->DMA_mode == 0) 2984 drvp->PIO_mode = 0; 2985 } 2986 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2987 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2988 SIS_TIM_ACT_OFF(drive); 2989 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2990 SIS_TIM_REC_OFF(drive); 2991 } 2992 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2993 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2994 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2995 if (idedma_ctl != 0) { 2996 /* Add software bits in status register */ 2997 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2998 IDEDMA_CTL, idedma_ctl); 2999 } 3000 pciide_print_modes(cp); 3001 } 3002 3003 static int 3004 acer_isabr_match(pa) 3005 struct pci_attach_args *pa; 3006 { 3007 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 3008 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 3009 } 3010 3011 void 3012 acer_chip_map(sc, pa) 3013 struct pciide_softc *sc; 3014 struct pci_attach_args *pa; 3015 { 3016 struct pci_attach_args isa_pa; 3017 struct pciide_channel *cp; 3018 int channel; 3019 pcireg_t cr, interface; 3020 bus_size_t cmdsize, ctlsize; 3021 pcireg_t rev = PCI_REVISION(pa->pa_class); 3022 3023 if (pciide_chipen(sc, pa) == 0) 3024 return; 3025 printf("%s: bus-master DMA support present", 3026 sc->sc_wdcdev.sc_dev.dv_xname); 3027 pciide_mapreg_dma(sc, pa); 3028 printf("\n"); 3029 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3030 WDC_CAPABILITY_MODE; 3031 if (sc->sc_dma_ok) { 3032 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3033 if (rev >= 0x20) { 3034 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3035 if (rev >= 0xC4) 3036 sc->sc_wdcdev.UDMA_cap = 5; 3037 else if (rev >= 0xC2) 3038 sc->sc_wdcdev.UDMA_cap = 4; 3039 else 3040 sc->sc_wdcdev.UDMA_cap = 2; 3041 } 3042 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3043 sc->sc_wdcdev.irqack = pciide_irqack; 3044 } 3045 3046 sc->sc_wdcdev.PIO_cap = 4; 3047 sc->sc_wdcdev.DMA_cap = 2; 3048 sc->sc_wdcdev.set_modes = acer_setup_channel; 3049 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3050 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3051 3052 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3053 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3054 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3055 3056 /* Enable "microsoft register bits" R/W. */ 3057 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3058 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3059 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3060 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3061 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3062 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3063 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3064 ~ACER_CHANSTATUSREGS_RO); 3065 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3066 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3067 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3068 /* Don't use cr, re-read the real register content instead */ 3069 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3070 PCI_CLASS_REG)); 3071 3072 /* From linux: enable "Cable Detection" */ 3073 if (rev >= 0xC2) { 3074 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3075 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3076 | ACER_0x4B_CDETECT); 3077 /* set south-bridge's enable bit, m1533, 0x79 */ 3078 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 3079 printf("%s: can't find PCI/ISA bridge, downgrading " 3080 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 3081 sc->sc_wdcdev.UDMA_cap = 2; 3082 } else { 3083 if (rev == 0xC2) 3084 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3085 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3086 ACER_0x79, 3087 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3088 ACER_0x79) 3089 | ACER_0x79_REVC2_EN); 3090 else 3091 /* 1553/1535 (m1533, 0x79, bit 1) */ 3092 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3093 ACER_0x79, 3094 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3095 ACER_0x79) 3096 | ACER_0x79_EN); 3097 } 3098 } 3099 3100 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3101 cp = &sc->pciide_channels[channel]; 3102 if (pciide_chansetup(sc, channel, interface) == 0) 3103 continue; 3104 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3105 printf("%s: %s channel ignored (disabled)\n", 3106 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3107 continue; 3108 } 3109 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3110 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3111 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3112 if (cp->hw_ok == 0) 3113 continue; 3114 if (pciide_chan_candisable(cp)) { 3115 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3116 pci_conf_write(sc->sc_pc, sc->sc_tag, 3117 PCI_CLASS_REG, cr); 3118 } 3119 pciide_map_compat_intr(pa, cp, channel, interface); 3120 acer_setup_channel(&cp->wdc_channel); 3121 } 3122 } 3123 3124 void 3125 acer_setup_channel(chp) 3126 struct channel_softc *chp; 3127 { 3128 struct ata_drive_datas *drvp; 3129 int drive; 3130 u_int32_t acer_fifo_udma; 3131 u_int32_t idedma_ctl; 3132 struct pciide_channel *cp = (struct pciide_channel*)chp; 3133 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3134 3135 idedma_ctl = 0; 3136 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3137 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3138 acer_fifo_udma), DEBUG_PROBE); 3139 /* setup DMA if needed */ 3140 pciide_channel_dma_setup(cp); 3141 3142 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3143 DRIVE_UDMA) { /* check 80 pins cable */ 3144 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3145 ACER_0x4A_80PIN(chp->channel)) { 3146 if (chp->ch_drive[0].UDMA_mode > 2) 3147 chp->ch_drive[0].UDMA_mode = 2; 3148 if (chp->ch_drive[1].UDMA_mode > 2) 3149 chp->ch_drive[1].UDMA_mode = 2; 3150 } 3151 } 3152 3153 for (drive = 0; drive < 2; drive++) { 3154 drvp = &chp->ch_drive[drive]; 3155 /* If no drive, skip */ 3156 if ((drvp->drive_flags & DRIVE) == 0) 3157 continue; 3158 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3159 "channel %d drive %d 0x%x\n", chp->channel, drive, 3160 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3161 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3162 /* clear FIFO/DMA mode */ 3163 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3164 ACER_UDMA_EN(chp->channel, drive) | 3165 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3166 3167 /* add timing values, setup DMA if needed */ 3168 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3169 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3170 acer_fifo_udma |= 3171 ACER_FTH_OPL(chp->channel, drive, 0x1); 3172 goto pio; 3173 } 3174 3175 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3176 if (drvp->drive_flags & DRIVE_UDMA) { 3177 /* use Ultra/DMA */ 3178 drvp->drive_flags &= ~DRIVE_DMA; 3179 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3180 acer_fifo_udma |= 3181 ACER_UDMA_TIM(chp->channel, drive, 3182 acer_udma[drvp->UDMA_mode]); 3183 /* XXX disable if one drive < UDMA3 ? */ 3184 if (drvp->UDMA_mode >= 3) { 3185 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3186 ACER_0x4B, 3187 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3188 ACER_0x4B) | ACER_0x4B_UDMA66); 3189 } 3190 } else { 3191 /* 3192 * use Multiword DMA 3193 * Timings will be used for both PIO and DMA, 3194 * so adjust DMA mode if needed 3195 */ 3196 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3197 drvp->PIO_mode = drvp->DMA_mode + 2; 3198 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3199 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3200 drvp->PIO_mode - 2 : 0; 3201 if (drvp->DMA_mode == 0) 3202 drvp->PIO_mode = 0; 3203 } 3204 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3205 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3206 ACER_IDETIM(chp->channel, drive), 3207 acer_pio[drvp->PIO_mode]); 3208 } 3209 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3210 acer_fifo_udma), DEBUG_PROBE); 3211 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3212 if (idedma_ctl != 0) { 3213 /* Add software bits in status register */ 3214 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3215 IDEDMA_CTL, idedma_ctl); 3216 } 3217 pciide_print_modes(cp); 3218 } 3219 3220 int 3221 acer_pci_intr(arg) 3222 void *arg; 3223 { 3224 struct pciide_softc *sc = arg; 3225 struct pciide_channel *cp; 3226 struct channel_softc *wdc_cp; 3227 int i, rv, crv; 3228 u_int32_t chids; 3229 3230 rv = 0; 3231 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3232 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3233 cp = &sc->pciide_channels[i]; 3234 wdc_cp = &cp->wdc_channel; 3235 /* If a compat channel skip. */ 3236 if (cp->compat) 3237 continue; 3238 if (chids & ACER_CHIDS_INT(i)) { 3239 crv = wdcintr(wdc_cp); 3240 if (crv == 0) 3241 printf("%s:%d: bogus intr\n", 3242 sc->sc_wdcdev.sc_dev.dv_xname, i); 3243 else 3244 rv = 1; 3245 } 3246 } 3247 return rv; 3248 } 3249 3250 void 3251 hpt_chip_map(sc, pa) 3252 struct pciide_softc *sc; 3253 struct pci_attach_args *pa; 3254 { 3255 struct pciide_channel *cp; 3256 int i, compatchan, revision; 3257 pcireg_t interface; 3258 bus_size_t cmdsize, ctlsize; 3259 3260 if (pciide_chipen(sc, pa) == 0) 3261 return; 3262 revision = PCI_REVISION(pa->pa_class); 3263 printf(": Triones/Highpoint "); 3264 if (revision == HPT370_REV) 3265 printf("HPT370 IDE Controller\n"); 3266 else if (revision == HPT370A_REV) 3267 printf("HPT370A IDE Controller\n"); 3268 else if (revision == HPT366_REV) 3269 printf("HPT366 IDE Controller\n"); 3270 else 3271 printf("unknown HPT IDE controller rev %d\n", revision); 3272 3273 /* 3274 * when the chip is in native mode it identifies itself as a 3275 * 'misc mass storage'. Fake interface in this case. 3276 */ 3277 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3278 interface = PCI_INTERFACE(pa->pa_class); 3279 } else { 3280 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3281 PCIIDE_INTERFACE_PCI(0); 3282 if (revision == HPT370_REV || revision == HPT370A_REV) 3283 interface |= PCIIDE_INTERFACE_PCI(1); 3284 } 3285 3286 printf("%s: bus-master DMA support present", 3287 sc->sc_wdcdev.sc_dev.dv_xname); 3288 pciide_mapreg_dma(sc, pa); 3289 printf("\n"); 3290 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3291 WDC_CAPABILITY_MODE; 3292 if (sc->sc_dma_ok) { 3293 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3294 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3295 sc->sc_wdcdev.irqack = pciide_irqack; 3296 } 3297 sc->sc_wdcdev.PIO_cap = 4; 3298 sc->sc_wdcdev.DMA_cap = 2; 3299 3300 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3301 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3302 if (revision == HPT366_REV) { 3303 sc->sc_wdcdev.UDMA_cap = 4; 3304 /* 3305 * The 366 has 2 PCI IDE functions, one for primary and one 3306 * for secondary. So we need to call pciide_mapregs_compat() 3307 * with the real channel 3308 */ 3309 if (pa->pa_function == 0) { 3310 compatchan = 0; 3311 } else if (pa->pa_function == 1) { 3312 compatchan = 1; 3313 } else { 3314 printf("%s: unexpected PCI function %d\n", 3315 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3316 return; 3317 } 3318 sc->sc_wdcdev.nchannels = 1; 3319 } else { 3320 sc->sc_wdcdev.nchannels = 2; 3321 sc->sc_wdcdev.UDMA_cap = 5; 3322 } 3323 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3324 cp = &sc->pciide_channels[i]; 3325 if (sc->sc_wdcdev.nchannels > 1) { 3326 compatchan = i; 3327 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3328 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3329 printf("%s: %s channel ignored (disabled)\n", 3330 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3331 continue; 3332 } 3333 } 3334 if (pciide_chansetup(sc, i, interface) == 0) 3335 continue; 3336 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3337 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3338 &ctlsize, hpt_pci_intr); 3339 } else { 3340 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3341 &cmdsize, &ctlsize); 3342 } 3343 if (cp->hw_ok == 0) 3344 return; 3345 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3346 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3347 wdcattach(&cp->wdc_channel); 3348 hpt_setup_channel(&cp->wdc_channel); 3349 } 3350 if (revision == HPT370_REV || revision == HPT370A_REV) { 3351 /* 3352 * HPT370_REV has a bit to disable interrupts, make sure 3353 * to clear it 3354 */ 3355 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3356 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3357 ~HPT_CSEL_IRQDIS); 3358 } 3359 return; 3360 } 3361 3362 void 3363 hpt_setup_channel(chp) 3364 struct channel_softc *chp; 3365 { 3366 struct ata_drive_datas *drvp; 3367 int drive; 3368 int cable; 3369 u_int32_t before, after; 3370 u_int32_t idedma_ctl; 3371 struct pciide_channel *cp = (struct pciide_channel*)chp; 3372 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3373 3374 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3375 3376 /* setup DMA if needed */ 3377 pciide_channel_dma_setup(cp); 3378 3379 idedma_ctl = 0; 3380 3381 /* Per drive settings */ 3382 for (drive = 0; drive < 2; drive++) { 3383 drvp = &chp->ch_drive[drive]; 3384 /* If no drive, skip */ 3385 if ((drvp->drive_flags & DRIVE) == 0) 3386 continue; 3387 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3388 HPT_IDETIM(chp->channel, drive)); 3389 3390 /* add timing values, setup DMA if needed */ 3391 if (drvp->drive_flags & DRIVE_UDMA) { 3392 /* use Ultra/DMA */ 3393 drvp->drive_flags &= ~DRIVE_DMA; 3394 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3395 drvp->UDMA_mode > 2) 3396 drvp->UDMA_mode = 2; 3397 after = (sc->sc_wdcdev.nchannels == 2) ? 3398 hpt370_udma[drvp->UDMA_mode] : 3399 hpt366_udma[drvp->UDMA_mode]; 3400 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3401 } else if (drvp->drive_flags & DRIVE_DMA) { 3402 /* 3403 * use Multiword DMA. 3404 * Timings will be used for both PIO and DMA, so adjust 3405 * DMA mode if needed 3406 */ 3407 if (drvp->PIO_mode >= 3 && 3408 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3409 drvp->DMA_mode = drvp->PIO_mode - 2; 3410 } 3411 after = (sc->sc_wdcdev.nchannels == 2) ? 3412 hpt370_dma[drvp->DMA_mode] : 3413 hpt366_dma[drvp->DMA_mode]; 3414 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3415 } else { 3416 /* PIO only */ 3417 after = (sc->sc_wdcdev.nchannels == 2) ? 3418 hpt370_pio[drvp->PIO_mode] : 3419 hpt366_pio[drvp->PIO_mode]; 3420 } 3421 pci_conf_write(sc->sc_pc, sc->sc_tag, 3422 HPT_IDETIM(chp->channel, drive), after); 3423 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3424 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3425 after, before), DEBUG_PROBE); 3426 } 3427 if (idedma_ctl != 0) { 3428 /* Add software bits in status register */ 3429 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3430 IDEDMA_CTL, idedma_ctl); 3431 } 3432 pciide_print_modes(cp); 3433 } 3434 3435 int 3436 hpt_pci_intr(arg) 3437 void *arg; 3438 { 3439 struct pciide_softc *sc = arg; 3440 struct pciide_channel *cp; 3441 struct channel_softc *wdc_cp; 3442 int rv = 0; 3443 int dmastat, i, crv; 3444 3445 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3446 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3447 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3448 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3449 IDEDMA_CTL_INTR) 3450 continue; 3451 cp = &sc->pciide_channels[i]; 3452 wdc_cp = &cp->wdc_channel; 3453 crv = wdcintr(wdc_cp); 3454 if (crv == 0) { 3455 printf("%s:%d: bogus intr\n", 3456 sc->sc_wdcdev.sc_dev.dv_xname, i); 3457 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3458 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3459 } else 3460 rv = 1; 3461 } 3462 return rv; 3463 } 3464 3465 3466 /* Macros to test product */ 3467 #define PDC_IS_262(sc) \ 3468 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3469 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3470 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3471 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3472 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3473 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3474 #define PDC_IS_265(sc) \ 3475 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3476 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3477 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3478 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3479 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3480 #define PDC_IS_268(sc) \ 3481 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3482 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3483 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3484 3485 void 3486 pdc202xx_chip_map(sc, pa) 3487 struct pciide_softc *sc; 3488 struct pci_attach_args *pa; 3489 { 3490 struct pciide_channel *cp; 3491 int channel; 3492 pcireg_t interface, st, mode; 3493 bus_size_t cmdsize, ctlsize; 3494 3495 if (!PDC_IS_268(sc)) { 3496 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3497 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3498 st), DEBUG_PROBE); 3499 } 3500 if (pciide_chipen(sc, pa) == 0) 3501 return; 3502 3503 /* turn off RAID mode */ 3504 if (!PDC_IS_268(sc)) 3505 st &= ~PDC2xx_STATE_IDERAID; 3506 3507 /* 3508 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3509 * mode. We have to fake interface 3510 */ 3511 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3512 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3513 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3514 3515 printf("%s: bus-master DMA support present", 3516 sc->sc_wdcdev.sc_dev.dv_xname); 3517 pciide_mapreg_dma(sc, pa); 3518 printf("\n"); 3519 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3520 WDC_CAPABILITY_MODE; 3521 if (sc->sc_dma_ok) { 3522 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3523 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3524 sc->sc_wdcdev.irqack = pciide_irqack; 3525 } 3526 sc->sc_wdcdev.PIO_cap = 4; 3527 sc->sc_wdcdev.DMA_cap = 2; 3528 if (PDC_IS_265(sc)) 3529 sc->sc_wdcdev.UDMA_cap = 5; 3530 else if (PDC_IS_262(sc)) 3531 sc->sc_wdcdev.UDMA_cap = 4; 3532 else 3533 sc->sc_wdcdev.UDMA_cap = 2; 3534 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3535 pdc20268_setup_channel : pdc202xx_setup_channel; 3536 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3537 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3538 3539 if (!PDC_IS_268(sc)) { 3540 /* setup failsafe defaults */ 3541 mode = 0; 3542 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3543 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3544 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3545 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3546 for (channel = 0; 3547 channel < sc->sc_wdcdev.nchannels; 3548 channel++) { 3549 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3550 "drive 0 initial timings 0x%x, now 0x%x\n", 3551 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3552 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3553 DEBUG_PROBE); 3554 pci_conf_write(sc->sc_pc, sc->sc_tag, 3555 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3556 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3557 "drive 1 initial timings 0x%x, now 0x%x\n", 3558 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3559 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3560 pci_conf_write(sc->sc_pc, sc->sc_tag, 3561 PDC2xx_TIM(channel, 1), mode); 3562 } 3563 3564 mode = PDC2xx_SCR_DMA; 3565 if (PDC_IS_262(sc)) { 3566 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3567 } else { 3568 /* the BIOS set it up this way */ 3569 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3570 } 3571 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3572 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3573 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3574 "now 0x%x\n", 3575 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3576 PDC2xx_SCR), 3577 mode), DEBUG_PROBE); 3578 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3579 PDC2xx_SCR, mode); 3580 3581 /* controller initial state register is OK even without BIOS */ 3582 /* Set DMA mode to IDE DMA compatibility */ 3583 mode = 3584 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3585 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3586 DEBUG_PROBE); 3587 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3588 mode | 0x1); 3589 mode = 3590 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3591 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3592 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3593 mode | 0x1); 3594 } 3595 3596 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3597 cp = &sc->pciide_channels[channel]; 3598 if (pciide_chansetup(sc, channel, interface) == 0) 3599 continue; 3600 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3601 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3602 printf("%s: %s channel ignored (disabled)\n", 3603 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3604 continue; 3605 } 3606 if (PDC_IS_265(sc)) 3607 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3608 pdc20265_pci_intr); 3609 else 3610 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3611 pdc202xx_pci_intr); 3612 if (cp->hw_ok == 0) 3613 continue; 3614 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3615 st &= ~(PDC_IS_262(sc) ? 3616 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3617 pciide_map_compat_intr(pa, cp, channel, interface); 3618 pdc202xx_setup_channel(&cp->wdc_channel); 3619 } 3620 if (!PDC_IS_268(sc)) { 3621 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3622 "0x%x\n", st), DEBUG_PROBE); 3623 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3624 } 3625 return; 3626 } 3627 3628 void 3629 pdc202xx_setup_channel(chp) 3630 struct channel_softc *chp; 3631 { 3632 struct ata_drive_datas *drvp; 3633 int drive; 3634 pcireg_t mode, st; 3635 u_int32_t idedma_ctl, scr, atapi; 3636 struct pciide_channel *cp = (struct pciide_channel*)chp; 3637 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3638 int channel = chp->channel; 3639 3640 /* setup DMA if needed */ 3641 pciide_channel_dma_setup(cp); 3642 3643 idedma_ctl = 0; 3644 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3645 sc->sc_wdcdev.sc_dev.dv_xname, 3646 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3647 DEBUG_PROBE); 3648 3649 /* Per channel settings */ 3650 if (PDC_IS_262(sc)) { 3651 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3652 PDC262_U66); 3653 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3654 /* Trim UDMA mode */ 3655 if ((st & PDC262_STATE_80P(channel)) != 0 || 3656 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3657 chp->ch_drive[0].UDMA_mode <= 2) || 3658 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3659 chp->ch_drive[1].UDMA_mode <= 2)) { 3660 if (chp->ch_drive[0].UDMA_mode > 2) 3661 chp->ch_drive[0].UDMA_mode = 2; 3662 if (chp->ch_drive[1].UDMA_mode > 2) 3663 chp->ch_drive[1].UDMA_mode = 2; 3664 } 3665 /* Set U66 if needed */ 3666 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3667 chp->ch_drive[0].UDMA_mode > 2) || 3668 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3669 chp->ch_drive[1].UDMA_mode > 2)) 3670 scr |= PDC262_U66_EN(channel); 3671 else 3672 scr &= ~PDC262_U66_EN(channel); 3673 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3674 PDC262_U66, scr); 3675 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3676 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3677 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3678 PDC262_ATAPI(channel))), DEBUG_PROBE); 3679 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3680 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3681 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3682 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3683 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3684 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3685 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3686 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3687 atapi = 0; 3688 else 3689 atapi = PDC262_ATAPI_UDMA; 3690 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3691 PDC262_ATAPI(channel), atapi); 3692 } 3693 } 3694 for (drive = 0; drive < 2; drive++) { 3695 drvp = &chp->ch_drive[drive]; 3696 /* If no drive, skip */ 3697 if ((drvp->drive_flags & DRIVE) == 0) 3698 continue; 3699 mode = 0; 3700 if (drvp->drive_flags & DRIVE_UDMA) { 3701 /* use Ultra/DMA */ 3702 drvp->drive_flags &= ~DRIVE_DMA; 3703 mode = PDC2xx_TIM_SET_MB(mode, 3704 pdc2xx_udma_mb[drvp->UDMA_mode]); 3705 mode = PDC2xx_TIM_SET_MC(mode, 3706 pdc2xx_udma_mc[drvp->UDMA_mode]); 3707 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3708 } else if (drvp->drive_flags & DRIVE_DMA) { 3709 mode = PDC2xx_TIM_SET_MB(mode, 3710 pdc2xx_dma_mb[drvp->DMA_mode]); 3711 mode = PDC2xx_TIM_SET_MC(mode, 3712 pdc2xx_dma_mc[drvp->DMA_mode]); 3713 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3714 } else { 3715 mode = PDC2xx_TIM_SET_MB(mode, 3716 pdc2xx_dma_mb[0]); 3717 mode = PDC2xx_TIM_SET_MC(mode, 3718 pdc2xx_dma_mc[0]); 3719 } 3720 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3721 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3722 if (drvp->drive_flags & DRIVE_ATA) 3723 mode |= PDC2xx_TIM_PRE; 3724 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3725 if (drvp->PIO_mode >= 3) { 3726 mode |= PDC2xx_TIM_IORDY; 3727 if (drive == 0) 3728 mode |= PDC2xx_TIM_IORDYp; 3729 } 3730 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3731 "timings 0x%x\n", 3732 sc->sc_wdcdev.sc_dev.dv_xname, 3733 chp->channel, drive, mode), DEBUG_PROBE); 3734 pci_conf_write(sc->sc_pc, sc->sc_tag, 3735 PDC2xx_TIM(chp->channel, drive), mode); 3736 } 3737 if (idedma_ctl != 0) { 3738 /* Add software bits in status register */ 3739 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3740 IDEDMA_CTL, idedma_ctl); 3741 } 3742 pciide_print_modes(cp); 3743 } 3744 3745 void 3746 pdc20268_setup_channel(chp) 3747 struct channel_softc *chp; 3748 { 3749 struct ata_drive_datas *drvp; 3750 int drive; 3751 u_int32_t idedma_ctl; 3752 struct pciide_channel *cp = (struct pciide_channel*)chp; 3753 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3754 int u100; 3755 3756 /* setup DMA if needed */ 3757 pciide_channel_dma_setup(cp); 3758 3759 idedma_ctl = 0; 3760 3761 /* I don't know what this is for, FreeBSD does it ... */ 3762 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3763 IDEDMA_CMD + 0x1, 0x0b); 3764 3765 /* 3766 * I don't know what this is for; FreeBSD checks this ... this is not 3767 * cable type detect. 3768 */ 3769 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3770 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3771 3772 for (drive = 0; drive < 2; drive++) { 3773 drvp = &chp->ch_drive[drive]; 3774 /* If no drive, skip */ 3775 if ((drvp->drive_flags & DRIVE) == 0) 3776 continue; 3777 if (drvp->drive_flags & DRIVE_UDMA) { 3778 /* use Ultra/DMA */ 3779 drvp->drive_flags &= ~DRIVE_DMA; 3780 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3781 if (drvp->UDMA_mode > 2 && u100 == 0) 3782 drvp->UDMA_mode = 2; 3783 } else if (drvp->drive_flags & DRIVE_DMA) { 3784 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3785 } 3786 } 3787 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3788 if (idedma_ctl != 0) { 3789 /* Add software bits in status register */ 3790 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3791 IDEDMA_CTL, idedma_ctl); 3792 } 3793 pciide_print_modes(cp); 3794 } 3795 3796 int 3797 pdc202xx_pci_intr(arg) 3798 void *arg; 3799 { 3800 struct pciide_softc *sc = arg; 3801 struct pciide_channel *cp; 3802 struct channel_softc *wdc_cp; 3803 int i, rv, crv; 3804 u_int32_t scr; 3805 3806 rv = 0; 3807 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3808 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3809 cp = &sc->pciide_channels[i]; 3810 wdc_cp = &cp->wdc_channel; 3811 /* If a compat channel skip. */ 3812 if (cp->compat) 3813 continue; 3814 if (scr & PDC2xx_SCR_INT(i)) { 3815 crv = wdcintr(wdc_cp); 3816 if (crv == 0) 3817 printf("%s:%d: bogus intr (reg 0x%x)\n", 3818 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3819 else 3820 rv = 1; 3821 } 3822 } 3823 return rv; 3824 } 3825 3826 int 3827 pdc20265_pci_intr(arg) 3828 void *arg; 3829 { 3830 struct pciide_softc *sc = arg; 3831 struct pciide_channel *cp; 3832 struct channel_softc *wdc_cp; 3833 int i, rv, crv; 3834 u_int32_t dmastat; 3835 3836 rv = 0; 3837 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3838 cp = &sc->pciide_channels[i]; 3839 wdc_cp = &cp->wdc_channel; 3840 /* If a compat channel skip. */ 3841 if (cp->compat) 3842 continue; 3843 /* 3844 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3845 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3846 * So use it instead (requires 2 reg reads instead of 1, 3847 * but we can't do it another way). 3848 */ 3849 dmastat = bus_space_read_1(sc->sc_dma_iot, 3850 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3851 if((dmastat & IDEDMA_CTL_INTR) == 0) 3852 continue; 3853 crv = wdcintr(wdc_cp); 3854 if (crv == 0) 3855 printf("%s:%d: bogus intr\n", 3856 sc->sc_wdcdev.sc_dev.dv_xname, i); 3857 else 3858 rv = 1; 3859 } 3860 return rv; 3861 } 3862 3863 void 3864 opti_chip_map(sc, pa) 3865 struct pciide_softc *sc; 3866 struct pci_attach_args *pa; 3867 { 3868 struct pciide_channel *cp; 3869 bus_size_t cmdsize, ctlsize; 3870 pcireg_t interface; 3871 u_int8_t init_ctrl; 3872 int channel; 3873 3874 if (pciide_chipen(sc, pa) == 0) 3875 return; 3876 printf("%s: bus-master DMA support present", 3877 sc->sc_wdcdev.sc_dev.dv_xname); 3878 3879 /* 3880 * XXXSCW: 3881 * There seem to be a couple of buggy revisions/implementations 3882 * of the OPTi pciide chipset. This kludge seems to fix one of 3883 * the reported problems (PR/11644) but still fails for the 3884 * other (PR/13151), although the latter may be due to other 3885 * issues too... 3886 */ 3887 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3888 printf(" but disabled due to chip rev. <= 0x12"); 3889 sc->sc_dma_ok = 0; 3890 sc->sc_wdcdev.cap = 0; 3891 } else { 3892 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3893 pciide_mapreg_dma(sc, pa); 3894 } 3895 printf("\n"); 3896 3897 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3898 sc->sc_wdcdev.PIO_cap = 4; 3899 if (sc->sc_dma_ok) { 3900 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3901 sc->sc_wdcdev.irqack = pciide_irqack; 3902 sc->sc_wdcdev.DMA_cap = 2; 3903 } 3904 sc->sc_wdcdev.set_modes = opti_setup_channel; 3905 3906 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3907 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3908 3909 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3910 OPTI_REG_INIT_CONTROL); 3911 3912 interface = PCI_INTERFACE(pa->pa_class); 3913 3914 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3915 cp = &sc->pciide_channels[channel]; 3916 if (pciide_chansetup(sc, channel, interface) == 0) 3917 continue; 3918 if (channel == 1 && 3919 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3920 printf("%s: %s channel ignored (disabled)\n", 3921 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3922 continue; 3923 } 3924 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3925 pciide_pci_intr); 3926 if (cp->hw_ok == 0) 3927 continue; 3928 pciide_map_compat_intr(pa, cp, channel, interface); 3929 if (cp->hw_ok == 0) 3930 continue; 3931 opti_setup_channel(&cp->wdc_channel); 3932 } 3933 } 3934 3935 void 3936 opti_setup_channel(chp) 3937 struct channel_softc *chp; 3938 { 3939 struct ata_drive_datas *drvp; 3940 struct pciide_channel *cp = (struct pciide_channel*)chp; 3941 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3942 int drive, spd; 3943 int mode[2]; 3944 u_int8_t rv, mr; 3945 3946 /* 3947 * The `Delay' and `Address Setup Time' fields of the 3948 * Miscellaneous Register are always zero initially. 3949 */ 3950 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3951 mr &= ~(OPTI_MISC_DELAY_MASK | 3952 OPTI_MISC_ADDR_SETUP_MASK | 3953 OPTI_MISC_INDEX_MASK); 3954 3955 /* Prime the control register before setting timing values */ 3956 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3957 3958 /* Determine the clockrate of the PCIbus the chip is attached to */ 3959 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3960 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3961 3962 /* setup DMA if needed */ 3963 pciide_channel_dma_setup(cp); 3964 3965 for (drive = 0; drive < 2; drive++) { 3966 drvp = &chp->ch_drive[drive]; 3967 /* If no drive, skip */ 3968 if ((drvp->drive_flags & DRIVE) == 0) { 3969 mode[drive] = -1; 3970 continue; 3971 } 3972 3973 if ((drvp->drive_flags & DRIVE_DMA)) { 3974 /* 3975 * Timings will be used for both PIO and DMA, 3976 * so adjust DMA mode if needed 3977 */ 3978 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3979 drvp->PIO_mode = drvp->DMA_mode + 2; 3980 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3981 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3982 drvp->PIO_mode - 2 : 0; 3983 if (drvp->DMA_mode == 0) 3984 drvp->PIO_mode = 0; 3985 3986 mode[drive] = drvp->DMA_mode + 5; 3987 } else 3988 mode[drive] = drvp->PIO_mode; 3989 3990 if (drive && mode[0] >= 0 && 3991 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3992 /* 3993 * Can't have two drives using different values 3994 * for `Address Setup Time'. 3995 * Slow down the faster drive to compensate. 3996 */ 3997 int d = (opti_tim_as[spd][mode[0]] > 3998 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3999 4000 mode[d] = mode[1-d]; 4001 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4002 chp->ch_drive[d].DMA_mode = 0; 4003 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 4004 } 4005 } 4006 4007 for (drive = 0; drive < 2; drive++) { 4008 int m; 4009 if ((m = mode[drive]) < 0) 4010 continue; 4011 4012 /* Set the Address Setup Time and select appropriate index */ 4013 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4014 rv |= OPTI_MISC_INDEX(drive); 4015 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4016 4017 /* Set the pulse width and recovery timing parameters */ 4018 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4019 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4020 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4021 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4022 4023 /* Set the Enhanced Mode register appropriately */ 4024 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4025 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4026 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4027 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4028 } 4029 4030 /* Finally, enable the timings */ 4031 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4032 4033 pciide_print_modes(cp); 4034 } 4035 4036 #define ACARD_IS_850(sc) \ 4037 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4038 4039 void 4040 acard_chip_map(sc, pa) 4041 struct pciide_softc *sc; 4042 struct pci_attach_args *pa; 4043 { 4044 struct pciide_channel *cp; 4045 int i; 4046 pcireg_t interface; 4047 bus_size_t cmdsize, ctlsize; 4048 4049 if (pciide_chipen(sc, pa) == 0) 4050 return; 4051 4052 /* 4053 * when the chip is in native mode it identifies itself as a 4054 * 'misc mass storage'. Fake interface in this case. 4055 */ 4056 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4057 interface = PCI_INTERFACE(pa->pa_class); 4058 } else { 4059 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4060 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4061 } 4062 4063 printf("%s: bus-master DMA support present", 4064 sc->sc_wdcdev.sc_dev.dv_xname); 4065 pciide_mapreg_dma(sc, pa); 4066 printf("\n"); 4067 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4068 WDC_CAPABILITY_MODE; 4069 4070 if (sc->sc_dma_ok) { 4071 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4073 sc->sc_wdcdev.irqack = pciide_irqack; 4074 } 4075 sc->sc_wdcdev.PIO_cap = 4; 4076 sc->sc_wdcdev.DMA_cap = 2; 4077 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4078 4079 sc->sc_wdcdev.set_modes = acard_setup_channel; 4080 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4081 sc->sc_wdcdev.nchannels = 2; 4082 4083 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4084 cp = &sc->pciide_channels[i]; 4085 if (pciide_chansetup(sc, i, interface) == 0) 4086 continue; 4087 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4088 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4089 &ctlsize, pciide_pci_intr); 4090 } else { 4091 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4092 &cmdsize, &ctlsize); 4093 } 4094 if (cp->hw_ok == 0) 4095 return; 4096 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4097 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4098 wdcattach(&cp->wdc_channel); 4099 acard_setup_channel(&cp->wdc_channel); 4100 } 4101 if (!ACARD_IS_850(sc)) { 4102 u_int32_t reg; 4103 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4104 reg &= ~ATP860_CTRL_INT; 4105 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4106 } 4107 } 4108 4109 void 4110 acard_setup_channel(chp) 4111 struct channel_softc *chp; 4112 { 4113 struct ata_drive_datas *drvp; 4114 struct pciide_channel *cp = (struct pciide_channel*)chp; 4115 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4116 int channel = chp->channel; 4117 int drive; 4118 u_int32_t idetime, udma_mode; 4119 u_int32_t idedma_ctl; 4120 4121 /* setup DMA if needed */ 4122 pciide_channel_dma_setup(cp); 4123 4124 if (ACARD_IS_850(sc)) { 4125 idetime = 0; 4126 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4127 udma_mode &= ~ATP850_UDMA_MASK(channel); 4128 } else { 4129 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4130 idetime &= ~ATP860_SETTIME_MASK(channel); 4131 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4132 udma_mode &= ~ATP860_UDMA_MASK(channel); 4133 4134 /* check 80 pins cable */ 4135 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4136 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4137 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4138 & ATP860_CTRL_80P(chp->channel)) { 4139 if (chp->ch_drive[0].UDMA_mode > 2) 4140 chp->ch_drive[0].UDMA_mode = 2; 4141 if (chp->ch_drive[1].UDMA_mode > 2) 4142 chp->ch_drive[1].UDMA_mode = 2; 4143 } 4144 } 4145 } 4146 4147 idedma_ctl = 0; 4148 4149 /* Per drive settings */ 4150 for (drive = 0; drive < 2; drive++) { 4151 drvp = &chp->ch_drive[drive]; 4152 /* If no drive, skip */ 4153 if ((drvp->drive_flags & DRIVE) == 0) 4154 continue; 4155 /* add timing values, setup DMA if needed */ 4156 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4157 (drvp->drive_flags & DRIVE_UDMA)) { 4158 /* use Ultra/DMA */ 4159 if (ACARD_IS_850(sc)) { 4160 idetime |= ATP850_SETTIME(drive, 4161 acard_act_udma[drvp->UDMA_mode], 4162 acard_rec_udma[drvp->UDMA_mode]); 4163 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4164 acard_udma_conf[drvp->UDMA_mode]); 4165 } else { 4166 idetime |= ATP860_SETTIME(channel, drive, 4167 acard_act_udma[drvp->UDMA_mode], 4168 acard_rec_udma[drvp->UDMA_mode]); 4169 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4170 acard_udma_conf[drvp->UDMA_mode]); 4171 } 4172 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4173 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4174 (drvp->drive_flags & DRIVE_DMA)) { 4175 /* use Multiword DMA */ 4176 drvp->drive_flags &= ~DRIVE_UDMA; 4177 if (ACARD_IS_850(sc)) { 4178 idetime |= ATP850_SETTIME(drive, 4179 acard_act_dma[drvp->DMA_mode], 4180 acard_rec_dma[drvp->DMA_mode]); 4181 } else { 4182 idetime |= ATP860_SETTIME(channel, drive, 4183 acard_act_dma[drvp->DMA_mode], 4184 acard_rec_dma[drvp->DMA_mode]); 4185 } 4186 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4187 } else { 4188 /* PIO only */ 4189 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4190 if (ACARD_IS_850(sc)) { 4191 idetime |= ATP850_SETTIME(drive, 4192 acard_act_pio[drvp->PIO_mode], 4193 acard_rec_pio[drvp->PIO_mode]); 4194 } else { 4195 idetime |= ATP860_SETTIME(channel, drive, 4196 acard_act_pio[drvp->PIO_mode], 4197 acard_rec_pio[drvp->PIO_mode]); 4198 } 4199 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4200 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4201 | ATP8x0_CTRL_EN(channel)); 4202 } 4203 } 4204 4205 if (idedma_ctl != 0) { 4206 /* Add software bits in status register */ 4207 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4208 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4209 } 4210 pciide_print_modes(cp); 4211 4212 if (ACARD_IS_850(sc)) { 4213 pci_conf_write(sc->sc_pc, sc->sc_tag, 4214 ATP850_IDETIME(channel), idetime); 4215 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4216 } else { 4217 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4218 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4219 } 4220 } 4221 4222 int 4223 acard_pci_intr(arg) 4224 void *arg; 4225 { 4226 struct pciide_softc *sc = arg; 4227 struct pciide_channel *cp; 4228 struct channel_softc *wdc_cp; 4229 int rv = 0; 4230 int dmastat, i, crv; 4231 4232 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4233 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4234 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4235 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4236 continue; 4237 cp = &sc->pciide_channels[i]; 4238 wdc_cp = &cp->wdc_channel; 4239 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4240 (void)wdcintr(wdc_cp); 4241 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4242 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4243 continue; 4244 } 4245 crv = wdcintr(wdc_cp); 4246 if (crv == 0) 4247 printf("%s:%d: bogus intr\n", 4248 sc->sc_wdcdev.sc_dev.dv_xname, i); 4249 else if (crv == 1) 4250 rv = 1; 4251 else if (rv == 0) 4252 rv = crv; 4253 } 4254 return rv; 4255 } 4256 4257 static int 4258 sl82c105_bugchk(struct pci_attach_args *pa) 4259 { 4260 4261 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4262 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4263 return (0); 4264 4265 if (PCI_REVISION(pa->pa_class) <= 0x05) 4266 return (1); 4267 4268 return (0); 4269 } 4270 4271 void 4272 sl82c105_chip_map(sc, pa) 4273 struct pciide_softc *sc; 4274 struct pci_attach_args *pa; 4275 { 4276 struct pciide_channel *cp; 4277 bus_size_t cmdsize, ctlsize; 4278 pcireg_t interface, idecr; 4279 int channel; 4280 4281 if (pciide_chipen(sc, pa) == 0) 4282 return; 4283 4284 printf("%s: bus-master DMA support present", 4285 sc->sc_wdcdev.sc_dev.dv_xname); 4286 4287 /* 4288 * Check to see if we're part of the Winbond 83c553 Southbridge. 4289 * If so, we need to disable DMA on rev. <= 5 of that chip. 4290 */ 4291 if (pci_find_device(pa, sl82c105_bugchk)) { 4292 printf(" but disabled due to 83c553 rev. <= 0x05"); 4293 sc->sc_dma_ok = 0; 4294 } else 4295 pciide_mapreg_dma(sc, pa); 4296 printf("\n"); 4297 4298 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4299 WDC_CAPABILITY_MODE; 4300 sc->sc_wdcdev.PIO_cap = 4; 4301 if (sc->sc_dma_ok) { 4302 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4303 sc->sc_wdcdev.irqack = pciide_irqack; 4304 sc->sc_wdcdev.DMA_cap = 2; 4305 } 4306 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4307 4308 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4309 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4310 4311 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4312 4313 interface = PCI_INTERFACE(pa->pa_class); 4314 4315 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4316 cp = &sc->pciide_channels[channel]; 4317 if (pciide_chansetup(sc, channel, interface) == 0) 4318 continue; 4319 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4320 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4321 printf("%s: %s channel ignored (disabled)\n", 4322 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4323 continue; 4324 } 4325 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4326 pciide_pci_intr); 4327 if (cp->hw_ok == 0) 4328 continue; 4329 pciide_map_compat_intr(pa, cp, channel, interface); 4330 if (cp->hw_ok == 0) 4331 continue; 4332 sl82c105_setup_channel(&cp->wdc_channel); 4333 } 4334 } 4335 4336 void 4337 sl82c105_setup_channel(chp) 4338 struct channel_softc *chp; 4339 { 4340 struct ata_drive_datas *drvp; 4341 struct pciide_channel *cp = (struct pciide_channel*)chp; 4342 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4343 int pxdx_reg, drive; 4344 pcireg_t pxdx; 4345 4346 /* Set up DMA if needed. */ 4347 pciide_channel_dma_setup(cp); 4348 4349 for (drive = 0; drive < 2; drive++) { 4350 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4351 : SYMPH_P1D0CR) + (drive * 4); 4352 4353 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4354 4355 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4356 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4357 4358 drvp = &chp->ch_drive[drive]; 4359 /* If no drive, skip. */ 4360 if ((drvp->drive_flags & DRIVE) == 0) { 4361 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4362 continue; 4363 } 4364 4365 if (drvp->drive_flags & DRIVE_DMA) { 4366 /* 4367 * Timings will be used for both PIO and DMA, 4368 * so adjust DMA mode if needed. 4369 */ 4370 if (drvp->PIO_mode >= 3) { 4371 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4372 drvp->DMA_mode = drvp->PIO_mode - 2; 4373 if (drvp->DMA_mode < 1) { 4374 /* 4375 * Can't mix both PIO and DMA. 4376 * Disable DMA. 4377 */ 4378 drvp->drive_flags &= ~DRIVE_DMA; 4379 } 4380 } else { 4381 /* 4382 * Can't mix both PIO and DMA. Disable 4383 * DMA. 4384 */ 4385 drvp->drive_flags &= ~DRIVE_DMA; 4386 } 4387 } 4388 4389 if (drvp->drive_flags & DRIVE_DMA) { 4390 /* Use multi-word DMA. */ 4391 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4392 PxDx_CMD_ON_SHIFT; 4393 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4394 } else { 4395 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4396 PxDx_CMD_ON_SHIFT; 4397 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4398 } 4399 4400 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4401 4402 /* ...and set the mode for this drive. */ 4403 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4404 } 4405 4406 pciide_print_modes(cp); 4407 } 4408 4409 void 4410 serverworks_chip_map(sc, pa) 4411 struct pciide_softc *sc; 4412 struct pci_attach_args *pa; 4413 { 4414 struct pciide_channel *cp; 4415 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4416 pcitag_t pcib_tag; 4417 int channel; 4418 bus_size_t cmdsize, ctlsize; 4419 4420 if (pciide_chipen(sc, pa) == 0) 4421 return; 4422 4423 printf("%s: bus-master DMA support present", 4424 sc->sc_wdcdev.sc_dev.dv_xname); 4425 pciide_mapreg_dma(sc, pa); 4426 printf("\n"); 4427 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4428 WDC_CAPABILITY_MODE; 4429 4430 if (sc->sc_dma_ok) { 4431 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4432 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4433 sc->sc_wdcdev.irqack = pciide_irqack; 4434 } 4435 sc->sc_wdcdev.PIO_cap = 4; 4436 sc->sc_wdcdev.DMA_cap = 2; 4437 switch (sc->sc_pp->ide_product) { 4438 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4439 sc->sc_wdcdev.UDMA_cap = 2; 4440 break; 4441 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4442 if (PCI_REVISION(pa->pa_class) < 0x92) 4443 sc->sc_wdcdev.UDMA_cap = 4; 4444 else 4445 sc->sc_wdcdev.UDMA_cap = 5; 4446 break; 4447 } 4448 4449 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4450 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4451 sc->sc_wdcdev.nchannels = 2; 4452 4453 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4454 cp = &sc->pciide_channels[channel]; 4455 if (pciide_chansetup(sc, channel, interface) == 0) 4456 continue; 4457 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4458 serverworks_pci_intr); 4459 if (cp->hw_ok == 0) 4460 return; 4461 pciide_map_compat_intr(pa, cp, channel, interface); 4462 if (cp->hw_ok == 0) 4463 return; 4464 serverworks_setup_channel(&cp->wdc_channel); 4465 } 4466 4467 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4468 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4469 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4470 } 4471 4472 void 4473 serverworks_setup_channel(chp) 4474 struct channel_softc *chp; 4475 { 4476 struct ata_drive_datas *drvp; 4477 struct pciide_channel *cp = (struct pciide_channel*)chp; 4478 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4479 int channel = chp->channel; 4480 int drive, unit; 4481 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4482 u_int32_t idedma_ctl; 4483 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4484 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4485 4486 /* setup DMA if needed */ 4487 pciide_channel_dma_setup(cp); 4488 4489 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4490 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4491 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4492 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4493 4494 pio_time &= ~(0xffff << (16 * channel)); 4495 dma_time &= ~(0xffff << (16 * channel)); 4496 pio_mode &= ~(0xff << (8 * channel + 16)); 4497 udma_mode &= ~(0xff << (8 * channel + 16)); 4498 udma_mode &= ~(3 << (2 * channel)); 4499 4500 idedma_ctl = 0; 4501 4502 /* Per drive settings */ 4503 for (drive = 0; drive < 2; drive++) { 4504 drvp = &chp->ch_drive[drive]; 4505 /* If no drive, skip */ 4506 if ((drvp->drive_flags & DRIVE) == 0) 4507 continue; 4508 unit = drive + 2 * channel; 4509 /* add timing values, setup DMA if needed */ 4510 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4511 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4512 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4513 (drvp->drive_flags & DRIVE_UDMA)) { 4514 /* use Ultra/DMA, check for 80-pin cable */ 4515 if (drvp->UDMA_mode > 2 && 4516 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4517 drvp->UDMA_mode = 2; 4518 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4519 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4520 udma_mode |= 1 << unit; 4521 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4522 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4523 (drvp->drive_flags & DRIVE_DMA)) { 4524 /* use Multiword DMA */ 4525 drvp->drive_flags &= ~DRIVE_UDMA; 4526 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4527 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4528 } else { 4529 /* PIO only */ 4530 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4531 } 4532 } 4533 4534 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4535 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4536 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4537 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4538 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4539 4540 if (idedma_ctl != 0) { 4541 /* Add software bits in status register */ 4542 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4543 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4544 } 4545 pciide_print_modes(cp); 4546 } 4547 4548 int 4549 serverworks_pci_intr(arg) 4550 void *arg; 4551 { 4552 struct pciide_softc *sc = arg; 4553 struct pciide_channel *cp; 4554 struct channel_softc *wdc_cp; 4555 int rv = 0; 4556 int dmastat, i, crv; 4557 4558 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4559 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4560 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4561 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4562 IDEDMA_CTL_INTR) 4563 continue; 4564 cp = &sc->pciide_channels[i]; 4565 wdc_cp = &cp->wdc_channel; 4566 crv = wdcintr(wdc_cp); 4567 if (crv == 0) { 4568 printf("%s:%d: bogus intr\n", 4569 sc->sc_wdcdev.sc_dev.dv_xname, i); 4570 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4571 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4572 } else 4573 rv = 1; 4574 } 4575 return rv; 4576 } 4577
Indexes created Thu Oct 02 10:09:58 GMT 2025