pciide.c revision 1.107.2.14
1 /* $NetBSD: pciide.c,v 1.107.2.14 2002/08/01 02:45:27 nathanw Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.107.2.14 2002/08/01 02:45:27 nathanw Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void cmd680_setup_channel __P((struct channel_softc*)); 182 void cmd680_channel_map __P((struct pci_attach_args *, 183 struct pciide_softc *, int)); 184 185 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void cy693_setup_channel __P((struct channel_softc*)); 187 188 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void sis_setup_channel __P((struct channel_softc*)); 190 static int sis_hostbr_match __P(( struct pci_attach_args *)); 191 192 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void acer_setup_channel __P((struct channel_softc*)); 194 int acer_pci_intr __P((void *)); 195 196 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void pdc202xx_setup_channel __P((struct channel_softc*)); 198 void pdc20268_setup_channel __P((struct channel_softc*)); 199 int pdc202xx_pci_intr __P((void *)); 200 int pdc20265_pci_intr __P((void *)); 201 202 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void opti_setup_channel __P((struct channel_softc*)); 204 205 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void hpt_setup_channel __P((struct channel_softc*)); 207 int hpt_pci_intr __P((void *)); 208 209 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void acard_setup_channel __P((struct channel_softc*)); 211 int acard_pci_intr __P((void *)); 212 213 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void serverworks_setup_channel __P((struct channel_softc*)); 215 int serverworks_pci_intr __P((void *)); 216 217 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 218 void sl82c105_setup_channel __P((struct channel_softc*)); 219 220 void pciide_channel_dma_setup __P((struct pciide_channel *)); 221 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 222 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 223 void pciide_dma_start __P((void*, int, int)); 224 int pciide_dma_finish __P((void*, int, int, int)); 225 void pciide_irqack __P((struct channel_softc *)); 226 void pciide_print_modes __P((struct pciide_channel *)); 227 228 struct pciide_product_desc { 229 u_int32_t ide_product; 230 int ide_flags; 231 const char *ide_name; 232 /* map and setup chip, probe drives */ 233 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 234 }; 235 236 /* Flags for ide_flags */ 237 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 238 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 239 240 /* Default product description for devices not known from this controller */ 241 const struct pciide_product_desc default_product_desc = { 242 0, 243 0, 244 "Generic PCI IDE controller", 245 default_chip_map, 246 }; 247 248 const struct pciide_product_desc pciide_intel_products[] = { 249 { PCI_PRODUCT_INTEL_82092AA, 250 0, 251 "Intel 82092AA IDE controller", 252 default_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82371FB_IDE, 255 0, 256 "Intel 82371FB IDE controller (PIIX)", 257 piix_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82371SB_IDE, 260 0, 261 "Intel 82371SB IDE Interface (PIIX3)", 262 piix_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_82371AB_IDE, 265 0, 266 "Intel 82371AB IDE controller (PIIX4)", 267 piix_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82440MX_IDE, 270 0, 271 "Intel 82440MX IDE controller", 272 piix_chip_map 273 }, 274 { PCI_PRODUCT_INTEL_82801AA_IDE, 275 0, 276 "Intel 82801AA IDE Controller (ICH)", 277 piix_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_82801AB_IDE, 280 0, 281 "Intel 82801AB IDE Controller (ICH0)", 282 piix_chip_map, 283 }, 284 { PCI_PRODUCT_INTEL_82801BA_IDE, 285 0, 286 "Intel 82801BA IDE Controller (ICH2)", 287 piix_chip_map, 288 }, 289 { PCI_PRODUCT_INTEL_82801BAM_IDE, 290 0, 291 "Intel 82801BAM IDE Controller (ICH2)", 292 piix_chip_map, 293 }, 294 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 295 0, 296 "Intel 82801CA IDE Controller", 297 piix_chip_map, 298 }, 299 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 300 0, 301 "Intel 82801CA IDE Controller", 302 piix_chip_map, 303 }, 304 { PCI_PRODUCT_INTEL_82801DB_IDE, 305 0, 306 "Intel 82801DB IDE Controller (ICH4)", 307 piix_chip_map, 308 }, 309 { 0, 310 0, 311 NULL, 312 NULL 313 } 314 }; 315 316 const struct pciide_product_desc pciide_amd_products[] = { 317 { PCI_PRODUCT_AMD_PBC756_IDE, 318 0, 319 "Advanced Micro Devices AMD756 IDE Controller", 320 amd7x6_chip_map 321 }, 322 { PCI_PRODUCT_AMD_PBC766_IDE, 323 0, 324 "Advanced Micro Devices AMD766 IDE Controller", 325 amd7x6_chip_map 326 }, 327 { PCI_PRODUCT_AMD_PBC768_IDE, 328 0, 329 "Advanced Micro Devices AMD768 IDE Controller", 330 amd7x6_chip_map 331 }, 332 { PCI_PRODUCT_AMD_PBC8111_IDE, 333 0, 334 "Advanced Micro Devices AMD8111 IDE Controller", 335 amd7x6_chip_map 336 }, 337 { 0, 338 0, 339 NULL, 340 NULL 341 } 342 }; 343 344 const struct pciide_product_desc pciide_cmd_products[] = { 345 { PCI_PRODUCT_CMDTECH_640, 346 0, 347 "CMD Technology PCI0640", 348 cmd_chip_map 349 }, 350 { PCI_PRODUCT_CMDTECH_643, 351 0, 352 "CMD Technology PCI0643", 353 cmd0643_9_chip_map, 354 }, 355 { PCI_PRODUCT_CMDTECH_646, 356 0, 357 "CMD Technology PCI0646", 358 cmd0643_9_chip_map, 359 }, 360 { PCI_PRODUCT_CMDTECH_648, 361 IDE_PCI_CLASS_OVERRIDE, 362 "CMD Technology PCI0648", 363 cmd0643_9_chip_map, 364 }, 365 { PCI_PRODUCT_CMDTECH_649, 366 IDE_PCI_CLASS_OVERRIDE, 367 "CMD Technology PCI0649", 368 cmd0643_9_chip_map, 369 }, 370 { PCI_PRODUCT_CMDTECH_680, 371 IDE_PCI_CLASS_OVERRIDE, 372 "Silicon Image 0680", 373 cmd680_chip_map, 374 }, 375 { 0, 376 0, 377 NULL, 378 NULL 379 } 380 }; 381 382 const struct pciide_product_desc pciide_via_products[] = { 383 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 384 0, 385 NULL, 386 apollo_chip_map, 387 }, 388 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 389 0, 390 NULL, 391 apollo_chip_map, 392 }, 393 { 0, 394 0, 395 NULL, 396 NULL 397 } 398 }; 399 400 const struct pciide_product_desc pciide_cypress_products[] = { 401 { PCI_PRODUCT_CONTAQ_82C693, 402 IDE_16BIT_IOSPACE, 403 "Cypress 82C693 IDE Controller", 404 cy693_chip_map, 405 }, 406 { 0, 407 0, 408 NULL, 409 NULL 410 } 411 }; 412 413 const struct pciide_product_desc pciide_sis_products[] = { 414 { PCI_PRODUCT_SIS_5597_IDE, 415 0, 416 "Silicon Integrated System 5597/5598 IDE controller", 417 sis_chip_map, 418 }, 419 { 0, 420 0, 421 NULL, 422 NULL 423 } 424 }; 425 426 const struct pciide_product_desc pciide_acer_products[] = { 427 { PCI_PRODUCT_ALI_M5229, 428 0, 429 "Acer Labs M5229 UDMA IDE Controller", 430 acer_chip_map, 431 }, 432 { 0, 433 0, 434 NULL, 435 NULL 436 } 437 }; 438 439 const struct pciide_product_desc pciide_promise_products[] = { 440 { PCI_PRODUCT_PROMISE_ULTRA33, 441 IDE_PCI_CLASS_OVERRIDE, 442 "Promise Ultra33/ATA Bus Master IDE Accelerator", 443 pdc202xx_chip_map, 444 }, 445 { PCI_PRODUCT_PROMISE_ULTRA66, 446 IDE_PCI_CLASS_OVERRIDE, 447 "Promise Ultra66/ATA Bus Master IDE Accelerator", 448 pdc202xx_chip_map, 449 }, 450 { PCI_PRODUCT_PROMISE_ULTRA100, 451 IDE_PCI_CLASS_OVERRIDE, 452 "Promise Ultra100/ATA Bus Master IDE Accelerator", 453 pdc202xx_chip_map, 454 }, 455 { PCI_PRODUCT_PROMISE_ULTRA100X, 456 IDE_PCI_CLASS_OVERRIDE, 457 "Promise Ultra100/ATA Bus Master IDE Accelerator", 458 pdc202xx_chip_map, 459 }, 460 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 461 IDE_PCI_CLASS_OVERRIDE, 462 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 463 pdc202xx_chip_map, 464 }, 465 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 466 IDE_PCI_CLASS_OVERRIDE, 467 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 468 pdc202xx_chip_map, 469 }, 470 { PCI_PRODUCT_PROMISE_ULTRA133, 471 IDE_PCI_CLASS_OVERRIDE, 472 "Promise Ultra133/ATA Bus Master IDE Accelerator", 473 pdc202xx_chip_map, 474 }, 475 { 0, 476 0, 477 NULL, 478 NULL 479 } 480 }; 481 482 const struct pciide_product_desc pciide_opti_products[] = { 483 { PCI_PRODUCT_OPTI_82C621, 484 0, 485 "OPTi 82c621 PCI IDE controller", 486 opti_chip_map, 487 }, 488 { PCI_PRODUCT_OPTI_82C568, 489 0, 490 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 491 opti_chip_map, 492 }, 493 { PCI_PRODUCT_OPTI_82D568, 494 0, 495 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 496 opti_chip_map, 497 }, 498 { 0, 499 0, 500 NULL, 501 NULL 502 } 503 }; 504 505 const struct pciide_product_desc pciide_triones_products[] = { 506 { PCI_PRODUCT_TRIONES_HPT366, 507 IDE_PCI_CLASS_OVERRIDE, 508 NULL, 509 hpt_chip_map, 510 }, 511 { PCI_PRODUCT_TRIONES_HPT374, 512 IDE_PCI_CLASS_OVERRIDE, 513 NULL, 514 hpt_chip_map 515 }, 516 { 0, 517 0, 518 NULL, 519 NULL 520 } 521 }; 522 523 const struct pciide_product_desc pciide_acard_products[] = { 524 { PCI_PRODUCT_ACARD_ATP850U, 525 IDE_PCI_CLASS_OVERRIDE, 526 "Acard ATP850U Ultra33 IDE Controller", 527 acard_chip_map, 528 }, 529 { PCI_PRODUCT_ACARD_ATP860, 530 IDE_PCI_CLASS_OVERRIDE, 531 "Acard ATP860 Ultra66 IDE Controller", 532 acard_chip_map, 533 }, 534 { PCI_PRODUCT_ACARD_ATP860A, 535 IDE_PCI_CLASS_OVERRIDE, 536 "Acard ATP860-A Ultra66 IDE Controller", 537 acard_chip_map, 538 }, 539 { 0, 540 0, 541 NULL, 542 NULL 543 } 544 }; 545 546 const struct pciide_product_desc pciide_serverworks_products[] = { 547 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 548 0, 549 "ServerWorks OSB4 IDE Controller", 550 serverworks_chip_map, 551 }, 552 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 553 0, 554 "ServerWorks CSB5 IDE Controller", 555 serverworks_chip_map, 556 }, 557 { 0, 558 0, 559 NULL, 560 } 561 }; 562 563 const struct pciide_product_desc pciide_symphony_products[] = { 564 { PCI_PRODUCT_SYMPHONY_82C105, 565 0, 566 "Symphony Labs 82C105 IDE controller", 567 sl82c105_chip_map, 568 }, 569 { 0, 570 0, 571 NULL, 572 } 573 }; 574 575 const struct pciide_product_desc pciide_winbond_products[] = { 576 { PCI_PRODUCT_WINBOND_W83C553F_1, 577 0, 578 "Winbond W83C553F IDE controller", 579 sl82c105_chip_map, 580 }, 581 { 0, 582 0, 583 NULL, 584 } 585 }; 586 587 struct pciide_vendor_desc { 588 u_int32_t ide_vendor; 589 const struct pciide_product_desc *ide_products; 590 }; 591 592 const struct pciide_vendor_desc pciide_vendors[] = { 593 { PCI_VENDOR_INTEL, pciide_intel_products }, 594 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 595 { PCI_VENDOR_VIATECH, pciide_via_products }, 596 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 597 { PCI_VENDOR_SIS, pciide_sis_products }, 598 { PCI_VENDOR_ALI, pciide_acer_products }, 599 { PCI_VENDOR_PROMISE, pciide_promise_products }, 600 { PCI_VENDOR_AMD, pciide_amd_products }, 601 { PCI_VENDOR_OPTI, pciide_opti_products }, 602 { PCI_VENDOR_TRIONES, pciide_triones_products }, 603 { PCI_VENDOR_ACARD, pciide_acard_products }, 604 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 605 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 606 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 607 { 0, NULL } 608 }; 609 610 /* options passed via the 'flags' config keyword */ 611 #define PCIIDE_OPTIONS_DMA 0x01 612 #define PCIIDE_OPTIONS_NODMA 0x02 613 614 int pciide_match __P((struct device *, struct cfdata *, void *)); 615 void pciide_attach __P((struct device *, struct device *, void *)); 616 617 struct cfattach pciide_ca = { 618 sizeof(struct pciide_softc), pciide_match, pciide_attach 619 }; 620 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 621 int pciide_mapregs_compat __P(( struct pci_attach_args *, 622 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 623 int pciide_mapregs_native __P((struct pci_attach_args *, 624 struct pciide_channel *, bus_size_t *, bus_size_t *, 625 int (*pci_intr) __P((void *)))); 626 void pciide_mapreg_dma __P((struct pciide_softc *, 627 struct pci_attach_args *)); 628 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 629 void pciide_mapchan __P((struct pci_attach_args *, 630 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 631 int (*pci_intr) __P((void *)))); 632 int pciide_chan_candisable __P((struct pciide_channel *)); 633 void pciide_map_compat_intr __P(( struct pci_attach_args *, 634 struct pciide_channel *, int, int)); 635 int pciide_compat_intr __P((void *)); 636 int pciide_pci_intr __P((void *)); 637 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 638 639 const struct pciide_product_desc * 640 pciide_lookup_product(id) 641 u_int32_t id; 642 { 643 const struct pciide_product_desc *pp; 644 const struct pciide_vendor_desc *vp; 645 646 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 647 if (PCI_VENDOR(id) == vp->ide_vendor) 648 break; 649 650 if ((pp = vp->ide_products) == NULL) 651 return NULL; 652 653 for (; pp->chip_map != NULL; pp++) 654 if (PCI_PRODUCT(id) == pp->ide_product) 655 break; 656 657 if (pp->chip_map == NULL) 658 return NULL; 659 return pp; 660 } 661 662 int 663 pciide_match(parent, match, aux) 664 struct device *parent; 665 struct cfdata *match; 666 void *aux; 667 { 668 struct pci_attach_args *pa = aux; 669 const struct pciide_product_desc *pp; 670 671 /* 672 * Check the ID register to see that it's a PCI IDE controller. 673 * If it is, we assume that we can deal with it; it _should_ 674 * work in a standardized way... 675 */ 676 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 677 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 678 return (1); 679 } 680 681 /* 682 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 683 * controllers. Let see if we can deal with it anyway. 684 */ 685 pp = pciide_lookup_product(pa->pa_id); 686 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 687 return (1); 688 } 689 690 return (0); 691 } 692 693 void 694 pciide_attach(parent, self, aux) 695 struct device *parent, *self; 696 void *aux; 697 { 698 struct pci_attach_args *pa = aux; 699 pci_chipset_tag_t pc = pa->pa_pc; 700 pcitag_t tag = pa->pa_tag; 701 struct pciide_softc *sc = (struct pciide_softc *)self; 702 pcireg_t csr; 703 char devinfo[256]; 704 const char *displaydev; 705 706 sc->sc_pp = pciide_lookup_product(pa->pa_id); 707 if (sc->sc_pp == NULL) { 708 sc->sc_pp = &default_product_desc; 709 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 710 displaydev = devinfo; 711 } else 712 displaydev = sc->sc_pp->ide_name; 713 714 /* if displaydev == NULL, printf is done in chip-specific map */ 715 if (displaydev) 716 printf(": %s (rev. 0x%02x)\n", displaydev, 717 PCI_REVISION(pa->pa_class)); 718 719 sc->sc_pc = pa->pa_pc; 720 sc->sc_tag = pa->pa_tag; 721 #ifdef WDCDEBUG 722 if (wdcdebug_pciide_mask & DEBUG_PROBE) 723 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 724 #endif 725 sc->sc_pp->chip_map(sc, pa); 726 727 if (sc->sc_dma_ok) { 728 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 729 csr |= PCI_COMMAND_MASTER_ENABLE; 730 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 731 } 732 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 733 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 734 } 735 736 /* tell wether the chip is enabled or not */ 737 int 738 pciide_chipen(sc, pa) 739 struct pciide_softc *sc; 740 struct pci_attach_args *pa; 741 { 742 pcireg_t csr; 743 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 744 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 745 PCI_COMMAND_STATUS_REG); 746 printf("%s: device disabled (at %s)\n", 747 sc->sc_wdcdev.sc_dev.dv_xname, 748 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 749 "device" : "bridge"); 750 return 0; 751 } 752 return 1; 753 } 754 755 int 756 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 757 struct pci_attach_args *pa; 758 struct pciide_channel *cp; 759 int compatchan; 760 bus_size_t *cmdsizep, *ctlsizep; 761 { 762 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 763 struct channel_softc *wdc_cp = &cp->wdc_channel; 764 765 cp->compat = 1; 766 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 767 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 768 769 wdc_cp->cmd_iot = pa->pa_iot; 770 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 771 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 772 printf("%s: couldn't map %s channel cmd regs\n", 773 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 774 return (0); 775 } 776 777 wdc_cp->ctl_iot = pa->pa_iot; 778 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 779 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 780 printf("%s: couldn't map %s channel ctl regs\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 782 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 783 PCIIDE_COMPAT_CMD_SIZE); 784 return (0); 785 } 786 787 return (1); 788 } 789 790 int 791 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 792 struct pci_attach_args * pa; 793 struct pciide_channel *cp; 794 bus_size_t *cmdsizep, *ctlsizep; 795 int (*pci_intr) __P((void *)); 796 { 797 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 798 struct channel_softc *wdc_cp = &cp->wdc_channel; 799 const char *intrstr; 800 pci_intr_handle_t intrhandle; 801 802 cp->compat = 0; 803 804 if (sc->sc_pci_ih == NULL) { 805 if (pci_intr_map(pa, &intrhandle) != 0) { 806 printf("%s: couldn't map native-PCI interrupt\n", 807 sc->sc_wdcdev.sc_dev.dv_xname); 808 return 0; 809 } 810 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 811 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 812 intrhandle, IPL_BIO, pci_intr, sc); 813 if (sc->sc_pci_ih != NULL) { 814 printf("%s: using %s for native-PCI interrupt\n", 815 sc->sc_wdcdev.sc_dev.dv_xname, 816 intrstr ? intrstr : "unknown interrupt"); 817 } else { 818 printf("%s: couldn't establish native-PCI interrupt", 819 sc->sc_wdcdev.sc_dev.dv_xname); 820 if (intrstr != NULL) 821 printf(" at %s", intrstr); 822 printf("\n"); 823 return 0; 824 } 825 } 826 cp->ih = sc->sc_pci_ih; 827 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 828 PCI_MAPREG_TYPE_IO, 0, 829 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 830 printf("%s: couldn't map %s channel cmd regs\n", 831 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 832 return 0; 833 } 834 835 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 836 PCI_MAPREG_TYPE_IO, 0, 837 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 838 printf("%s: couldn't map %s channel ctl regs\n", 839 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 840 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 841 return 0; 842 } 843 /* 844 * In native mode, 4 bytes of I/O space are mapped for the control 845 * register, the control register is at offset 2. Pass the generic 846 * code a handle for only one byte at the right offset. 847 */ 848 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 849 &wdc_cp->ctl_ioh) != 0) { 850 printf("%s: unable to subregion %s channel ctl regs\n", 851 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 852 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 853 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 854 return 0; 855 } 856 return (1); 857 } 858 859 void 860 pciide_mapreg_dma(sc, pa) 861 struct pciide_softc *sc; 862 struct pci_attach_args *pa; 863 { 864 pcireg_t maptype; 865 bus_addr_t addr; 866 867 /* 868 * Map DMA registers 869 * 870 * Note that sc_dma_ok is the right variable to test to see if 871 * DMA can be done. If the interface doesn't support DMA, 872 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 873 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 874 * non-zero if the interface supports DMA and the registers 875 * could be mapped. 876 * 877 * XXX Note that despite the fact that the Bus Master IDE specs 878 * XXX say that "The bus master IDE function uses 16 bytes of IO 879 * XXX space," some controllers (at least the United 880 * XXX Microelectronics UM8886BF) place it in memory space. 881 */ 882 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 883 PCIIDE_REG_BUS_MASTER_DMA); 884 885 switch (maptype) { 886 case PCI_MAPREG_TYPE_IO: 887 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 888 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 889 &addr, NULL, NULL) == 0); 890 if (sc->sc_dma_ok == 0) { 891 printf(", but unused (couldn't query registers)"); 892 break; 893 } 894 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 895 && addr >= 0x10000) { 896 sc->sc_dma_ok = 0; 897 printf(", but unused (registers at unsafe address " 898 "%#lx)", (unsigned long)addr); 899 break; 900 } 901 /* FALLTHROUGH */ 902 903 case PCI_MAPREG_MEM_TYPE_32BIT: 904 sc->sc_dma_ok = (pci_mapreg_map(pa, 905 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 906 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 907 sc->sc_dmat = pa->pa_dmat; 908 if (sc->sc_dma_ok == 0) { 909 printf(", but unused (couldn't map registers)"); 910 } else { 911 sc->sc_wdcdev.dma_arg = sc; 912 sc->sc_wdcdev.dma_init = pciide_dma_init; 913 sc->sc_wdcdev.dma_start = pciide_dma_start; 914 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 915 } 916 917 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 918 PCIIDE_OPTIONS_NODMA) { 919 printf(", but unused (forced off by config file)"); 920 sc->sc_dma_ok = 0; 921 } 922 break; 923 924 default: 925 sc->sc_dma_ok = 0; 926 printf(", but unsupported register maptype (0x%x)", maptype); 927 } 928 } 929 930 int 931 pciide_compat_intr(arg) 932 void *arg; 933 { 934 struct pciide_channel *cp = arg; 935 936 #ifdef DIAGNOSTIC 937 /* should only be called for a compat channel */ 938 if (cp->compat == 0) 939 panic("pciide compat intr called for non-compat chan %p\n", cp); 940 #endif 941 return (wdcintr(&cp->wdc_channel)); 942 } 943 944 int 945 pciide_pci_intr(arg) 946 void *arg; 947 { 948 struct pciide_softc *sc = arg; 949 struct pciide_channel *cp; 950 struct channel_softc *wdc_cp; 951 int i, rv, crv; 952 953 rv = 0; 954 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 955 cp = &sc->pciide_channels[i]; 956 wdc_cp = &cp->wdc_channel; 957 958 /* If a compat channel skip. */ 959 if (cp->compat) 960 continue; 961 /* if this channel not waiting for intr, skip */ 962 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 963 continue; 964 965 crv = wdcintr(wdc_cp); 966 if (crv == 0) 967 ; /* leave rv alone */ 968 else if (crv == 1) 969 rv = 1; /* claim the intr */ 970 else if (rv == 0) /* crv should be -1 in this case */ 971 rv = crv; /* if we've done no better, take it */ 972 } 973 return (rv); 974 } 975 976 void 977 pciide_channel_dma_setup(cp) 978 struct pciide_channel *cp; 979 { 980 int drive; 981 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 982 struct ata_drive_datas *drvp; 983 984 for (drive = 0; drive < 2; drive++) { 985 drvp = &cp->wdc_channel.ch_drive[drive]; 986 /* If no drive, skip */ 987 if ((drvp->drive_flags & DRIVE) == 0) 988 continue; 989 /* setup DMA if needed */ 990 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 991 (drvp->drive_flags & DRIVE_UDMA) == 0) || 992 sc->sc_dma_ok == 0) { 993 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 994 continue; 995 } 996 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 997 != 0) { 998 /* Abort DMA setup */ 999 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1000 continue; 1001 } 1002 } 1003 } 1004 1005 int 1006 pciide_dma_table_setup(sc, channel, drive) 1007 struct pciide_softc *sc; 1008 int channel, drive; 1009 { 1010 bus_dma_segment_t seg; 1011 int error, rseg; 1012 const bus_size_t dma_table_size = 1013 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1014 struct pciide_dma_maps *dma_maps = 1015 &sc->pciide_channels[channel].dma_maps[drive]; 1016 1017 /* If table was already allocated, just return */ 1018 if (dma_maps->dma_table) 1019 return 0; 1020 1021 /* Allocate memory for the DMA tables and map it */ 1022 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1023 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1024 BUS_DMA_NOWAIT)) != 0) { 1025 printf("%s:%d: unable to allocate table DMA for " 1026 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1027 channel, drive, error); 1028 return error; 1029 } 1030 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1031 dma_table_size, 1032 (caddr_t *)&dma_maps->dma_table, 1033 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1034 printf("%s:%d: unable to map table DMA for" 1035 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1036 channel, drive, error); 1037 return error; 1038 } 1039 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1040 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1041 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1042 1043 /* Create and load table DMA map for this disk */ 1044 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1045 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1046 &dma_maps->dmamap_table)) != 0) { 1047 printf("%s:%d: unable to create table DMA map for " 1048 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1049 channel, drive, error); 1050 return error; 1051 } 1052 if ((error = bus_dmamap_load(sc->sc_dmat, 1053 dma_maps->dmamap_table, 1054 dma_maps->dma_table, 1055 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1056 printf("%s:%d: unable to load table DMA map for " 1057 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1058 channel, drive, error); 1059 return error; 1060 } 1061 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1062 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1063 DEBUG_PROBE); 1064 /* Create a xfer DMA map for this drive */ 1065 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1066 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1067 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1068 &dma_maps->dmamap_xfer)) != 0) { 1069 printf("%s:%d: unable to create xfer DMA map for " 1070 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1071 channel, drive, error); 1072 return error; 1073 } 1074 return 0; 1075 } 1076 1077 int 1078 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1079 void *v; 1080 int channel, drive; 1081 void *databuf; 1082 size_t datalen; 1083 int flags; 1084 { 1085 struct pciide_softc *sc = v; 1086 int error, seg; 1087 struct pciide_dma_maps *dma_maps = 1088 &sc->pciide_channels[channel].dma_maps[drive]; 1089 1090 error = bus_dmamap_load(sc->sc_dmat, 1091 dma_maps->dmamap_xfer, 1092 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1093 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1094 if (error) { 1095 printf("%s:%d: unable to load xfer DMA map for" 1096 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1097 channel, drive, error); 1098 return error; 1099 } 1100 1101 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1102 dma_maps->dmamap_xfer->dm_mapsize, 1103 (flags & WDC_DMA_READ) ? 1104 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1105 1106 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1107 #ifdef DIAGNOSTIC 1108 /* A segment must not cross a 64k boundary */ 1109 { 1110 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1111 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1112 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1113 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1114 printf("pciide_dma: segment %d physical addr 0x%lx" 1115 " len 0x%lx not properly aligned\n", 1116 seg, phys, len); 1117 panic("pciide_dma: buf align"); 1118 } 1119 } 1120 #endif 1121 dma_maps->dma_table[seg].base_addr = 1122 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1123 dma_maps->dma_table[seg].byte_count = 1124 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1125 IDEDMA_BYTE_COUNT_MASK); 1126 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1127 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1128 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1129 1130 } 1131 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1132 htole32(IDEDMA_BYTE_COUNT_EOT); 1133 1134 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1135 dma_maps->dmamap_table->dm_mapsize, 1136 BUS_DMASYNC_PREWRITE); 1137 1138 /* Maps are ready. Start DMA function */ 1139 #ifdef DIAGNOSTIC 1140 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1141 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1142 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1143 panic("pciide_dma_init: table align"); 1144 } 1145 #endif 1146 1147 /* Clear status bits */ 1148 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1149 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1150 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1151 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1152 /* Write table addr */ 1153 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1154 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1155 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1156 /* set read/write */ 1157 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1158 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1159 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1160 /* remember flags */ 1161 dma_maps->dma_flags = flags; 1162 return 0; 1163 } 1164 1165 void 1166 pciide_dma_start(v, channel, drive) 1167 void *v; 1168 int channel, drive; 1169 { 1170 struct pciide_softc *sc = v; 1171 1172 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1173 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1174 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1175 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1176 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1177 } 1178 1179 int 1180 pciide_dma_finish(v, channel, drive, force) 1181 void *v; 1182 int channel, drive; 1183 int force; 1184 { 1185 struct pciide_softc *sc = v; 1186 u_int8_t status; 1187 int error = 0; 1188 struct pciide_dma_maps *dma_maps = 1189 &sc->pciide_channels[channel].dma_maps[drive]; 1190 1191 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1192 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1193 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1194 DEBUG_XFERS); 1195 1196 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1197 return WDC_DMAST_NOIRQ; 1198 1199 /* stop DMA channel */ 1200 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1201 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1202 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1203 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1204 1205 /* Unload the map of the data buffer */ 1206 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1207 dma_maps->dmamap_xfer->dm_mapsize, 1208 (dma_maps->dma_flags & WDC_DMA_READ) ? 1209 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1210 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1211 1212 if ((status & IDEDMA_CTL_ERR) != 0) { 1213 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1214 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1215 error |= WDC_DMAST_ERR; 1216 } 1217 1218 if ((status & IDEDMA_CTL_INTR) == 0) { 1219 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1220 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1221 drive, status); 1222 error |= WDC_DMAST_NOIRQ; 1223 } 1224 1225 if ((status & IDEDMA_CTL_ACT) != 0) { 1226 /* data underrun, may be a valid condition for ATAPI */ 1227 error |= WDC_DMAST_UNDER; 1228 } 1229 return error; 1230 } 1231 1232 void 1233 pciide_irqack(chp) 1234 struct channel_softc *chp; 1235 { 1236 struct pciide_channel *cp = (struct pciide_channel*)chp; 1237 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1238 1239 /* clear status bits in IDE DMA registers */ 1240 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1241 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1242 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1243 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1244 } 1245 1246 /* some common code used by several chip_map */ 1247 int 1248 pciide_chansetup(sc, channel, interface) 1249 struct pciide_softc *sc; 1250 int channel; 1251 pcireg_t interface; 1252 { 1253 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1254 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1255 cp->name = PCIIDE_CHANNEL_NAME(channel); 1256 cp->wdc_channel.channel = channel; 1257 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1258 cp->wdc_channel.ch_queue = 1259 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1260 if (cp->wdc_channel.ch_queue == NULL) { 1261 printf("%s %s channel: " 1262 "can't allocate memory for command queue", 1263 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1264 return 0; 1265 } 1266 printf("%s: %s channel %s to %s mode\n", 1267 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1268 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1269 "configured" : "wired", 1270 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1271 "native-PCI" : "compatibility"); 1272 return 1; 1273 } 1274 1275 /* some common code used by several chip channel_map */ 1276 void 1277 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1278 struct pci_attach_args *pa; 1279 struct pciide_channel *cp; 1280 pcireg_t interface; 1281 bus_size_t *cmdsizep, *ctlsizep; 1282 int (*pci_intr) __P((void *)); 1283 { 1284 struct channel_softc *wdc_cp = &cp->wdc_channel; 1285 1286 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1287 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1288 pci_intr); 1289 else 1290 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1291 wdc_cp->channel, cmdsizep, ctlsizep); 1292 1293 if (cp->hw_ok == 0) 1294 return; 1295 wdc_cp->data32iot = wdc_cp->cmd_iot; 1296 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1297 wdcattach(wdc_cp); 1298 } 1299 1300 /* 1301 * Generic code to call to know if a channel can be disabled. Return 1 1302 * if channel can be disabled, 0 if not 1303 */ 1304 int 1305 pciide_chan_candisable(cp) 1306 struct pciide_channel *cp; 1307 { 1308 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1309 struct channel_softc *wdc_cp = &cp->wdc_channel; 1310 1311 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1312 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1313 printf("%s: disabling %s channel (no drives)\n", 1314 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1315 cp->hw_ok = 0; 1316 return 1; 1317 } 1318 return 0; 1319 } 1320 1321 /* 1322 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1323 * Set hw_ok=0 on failure 1324 */ 1325 void 1326 pciide_map_compat_intr(pa, cp, compatchan, interface) 1327 struct pci_attach_args *pa; 1328 struct pciide_channel *cp; 1329 int compatchan, interface; 1330 { 1331 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1332 struct channel_softc *wdc_cp = &cp->wdc_channel; 1333 1334 if (cp->hw_ok == 0) 1335 return; 1336 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1337 return; 1338 1339 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1340 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1341 pa, compatchan, pciide_compat_intr, cp); 1342 if (cp->ih == NULL) { 1343 #endif 1344 printf("%s: no compatibility interrupt for use by %s " 1345 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1346 cp->hw_ok = 0; 1347 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1348 } 1349 #endif 1350 } 1351 1352 void 1353 pciide_print_modes(cp) 1354 struct pciide_channel *cp; 1355 { 1356 wdc_print_modes(&cp->wdc_channel); 1357 } 1358 1359 void 1360 default_chip_map(sc, pa) 1361 struct pciide_softc *sc; 1362 struct pci_attach_args *pa; 1363 { 1364 struct pciide_channel *cp; 1365 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1366 pcireg_t csr; 1367 int channel, drive; 1368 struct ata_drive_datas *drvp; 1369 u_int8_t idedma_ctl; 1370 bus_size_t cmdsize, ctlsize; 1371 char *failreason; 1372 1373 if (pciide_chipen(sc, pa) == 0) 1374 return; 1375 1376 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1377 printf("%s: bus-master DMA support present", 1378 sc->sc_wdcdev.sc_dev.dv_xname); 1379 if (sc->sc_pp == &default_product_desc && 1380 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1381 PCIIDE_OPTIONS_DMA) == 0) { 1382 printf(", but unused (no driver support)"); 1383 sc->sc_dma_ok = 0; 1384 } else { 1385 pciide_mapreg_dma(sc, pa); 1386 if (sc->sc_dma_ok != 0) 1387 printf(", used without full driver " 1388 "support"); 1389 } 1390 } else { 1391 printf("%s: hardware does not support DMA", 1392 sc->sc_wdcdev.sc_dev.dv_xname); 1393 sc->sc_dma_ok = 0; 1394 } 1395 printf("\n"); 1396 if (sc->sc_dma_ok) { 1397 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1398 sc->sc_wdcdev.irqack = pciide_irqack; 1399 } 1400 sc->sc_wdcdev.PIO_cap = 0; 1401 sc->sc_wdcdev.DMA_cap = 0; 1402 1403 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1404 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1405 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1406 1407 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1408 cp = &sc->pciide_channels[channel]; 1409 if (pciide_chansetup(sc, channel, interface) == 0) 1410 continue; 1411 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1412 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1413 &ctlsize, pciide_pci_intr); 1414 } else { 1415 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1416 channel, &cmdsize, &ctlsize); 1417 } 1418 if (cp->hw_ok == 0) 1419 continue; 1420 /* 1421 * Check to see if something appears to be there. 1422 */ 1423 failreason = NULL; 1424 if (!wdcprobe(&cp->wdc_channel)) { 1425 failreason = "not responding; disabled or no drives?"; 1426 goto next; 1427 } 1428 /* 1429 * Now, make sure it's actually attributable to this PCI IDE 1430 * channel by trying to access the channel again while the 1431 * PCI IDE controller's I/O space is disabled. (If the 1432 * channel no longer appears to be there, it belongs to 1433 * this controller.) YUCK! 1434 */ 1435 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1436 PCI_COMMAND_STATUS_REG); 1437 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1438 csr & ~PCI_COMMAND_IO_ENABLE); 1439 if (wdcprobe(&cp->wdc_channel)) 1440 failreason = "other hardware responding at addresses"; 1441 pci_conf_write(sc->sc_pc, sc->sc_tag, 1442 PCI_COMMAND_STATUS_REG, csr); 1443 next: 1444 if (failreason) { 1445 printf("%s: %s channel ignored (%s)\n", 1446 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1447 failreason); 1448 cp->hw_ok = 0; 1449 bus_space_unmap(cp->wdc_channel.cmd_iot, 1450 cp->wdc_channel.cmd_ioh, cmdsize); 1451 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1452 bus_space_unmap(cp->wdc_channel.ctl_iot, 1453 cp->ctl_baseioh, ctlsize); 1454 else 1455 bus_space_unmap(cp->wdc_channel.ctl_iot, 1456 cp->wdc_channel.ctl_ioh, ctlsize); 1457 } else { 1458 pciide_map_compat_intr(pa, cp, channel, interface); 1459 } 1460 if (cp->hw_ok) { 1461 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1462 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1463 wdcattach(&cp->wdc_channel); 1464 } 1465 } 1466 1467 if (sc->sc_dma_ok == 0) 1468 return; 1469 1470 /* Allocate DMA maps */ 1471 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1472 idedma_ctl = 0; 1473 cp = &sc->pciide_channels[channel]; 1474 for (drive = 0; drive < 2; drive++) { 1475 drvp = &cp->wdc_channel.ch_drive[drive]; 1476 /* If no drive, skip */ 1477 if ((drvp->drive_flags & DRIVE) == 0) 1478 continue; 1479 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1480 continue; 1481 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1482 /* Abort DMA setup */ 1483 printf("%s:%d:%d: can't allocate DMA maps, " 1484 "using PIO transfers\n", 1485 sc->sc_wdcdev.sc_dev.dv_xname, 1486 channel, drive); 1487 drvp->drive_flags &= ~DRIVE_DMA; 1488 } 1489 printf("%s:%d:%d: using DMA data transfers\n", 1490 sc->sc_wdcdev.sc_dev.dv_xname, 1491 channel, drive); 1492 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1493 } 1494 if (idedma_ctl != 0) { 1495 /* Add software bits in status register */ 1496 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1497 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1498 idedma_ctl); 1499 } 1500 } 1501 } 1502 1503 void 1504 piix_chip_map(sc, pa) 1505 struct pciide_softc *sc; 1506 struct pci_attach_args *pa; 1507 { 1508 struct pciide_channel *cp; 1509 int channel; 1510 u_int32_t idetim; 1511 bus_size_t cmdsize, ctlsize; 1512 1513 if (pciide_chipen(sc, pa) == 0) 1514 return; 1515 1516 printf("%s: bus-master DMA support present", 1517 sc->sc_wdcdev.sc_dev.dv_xname); 1518 pciide_mapreg_dma(sc, pa); 1519 printf("\n"); 1520 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1521 WDC_CAPABILITY_MODE; 1522 if (sc->sc_dma_ok) { 1523 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1524 sc->sc_wdcdev.irqack = pciide_irqack; 1525 switch(sc->sc_pp->ide_product) { 1526 case PCI_PRODUCT_INTEL_82371AB_IDE: 1527 case PCI_PRODUCT_INTEL_82440MX_IDE: 1528 case PCI_PRODUCT_INTEL_82801AA_IDE: 1529 case PCI_PRODUCT_INTEL_82801AB_IDE: 1530 case PCI_PRODUCT_INTEL_82801BA_IDE: 1531 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1532 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1533 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1534 case PCI_PRODUCT_INTEL_82801DB_IDE: 1535 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1536 } 1537 } 1538 sc->sc_wdcdev.PIO_cap = 4; 1539 sc->sc_wdcdev.DMA_cap = 2; 1540 switch(sc->sc_pp->ide_product) { 1541 case PCI_PRODUCT_INTEL_82801AA_IDE: 1542 sc->sc_wdcdev.UDMA_cap = 4; 1543 break; 1544 case PCI_PRODUCT_INTEL_82801BA_IDE: 1545 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1546 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1547 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1548 case PCI_PRODUCT_INTEL_82801DB_IDE: 1549 sc->sc_wdcdev.UDMA_cap = 5; 1550 break; 1551 default: 1552 sc->sc_wdcdev.UDMA_cap = 2; 1553 } 1554 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1555 sc->sc_wdcdev.set_modes = piix_setup_channel; 1556 else 1557 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1558 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1559 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1560 1561 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1562 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1563 DEBUG_PROBE); 1564 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1565 WDCDEBUG_PRINT((", sidetim=0x%x", 1566 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1567 DEBUG_PROBE); 1568 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1569 WDCDEBUG_PRINT((", udamreg 0x%x", 1570 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1571 DEBUG_PROBE); 1572 } 1573 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1574 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1580 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1581 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1582 DEBUG_PROBE); 1583 } 1584 1585 } 1586 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1587 1588 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1589 cp = &sc->pciide_channels[channel]; 1590 /* PIIX is compat-only */ 1591 if (pciide_chansetup(sc, channel, 0) == 0) 1592 continue; 1593 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1594 if ((PIIX_IDETIM_READ(idetim, channel) & 1595 PIIX_IDETIM_IDE) == 0) { 1596 printf("%s: %s channel ignored (disabled)\n", 1597 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1598 continue; 1599 } 1600 /* PIIX are compat-only pciide devices */ 1601 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1602 if (cp->hw_ok == 0) 1603 continue; 1604 if (pciide_chan_candisable(cp)) { 1605 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1606 channel); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1608 idetim); 1609 } 1610 pciide_map_compat_intr(pa, cp, channel, 0); 1611 if (cp->hw_ok == 0) 1612 continue; 1613 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1614 } 1615 1616 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1617 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1618 DEBUG_PROBE); 1619 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1620 WDCDEBUG_PRINT((", sidetim=0x%x", 1621 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1622 DEBUG_PROBE); 1623 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1624 WDCDEBUG_PRINT((", udamreg 0x%x", 1625 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1626 DEBUG_PROBE); 1627 } 1628 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1635 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1636 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1637 DEBUG_PROBE); 1638 } 1639 } 1640 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1641 } 1642 1643 void 1644 piix_setup_channel(chp) 1645 struct channel_softc *chp; 1646 { 1647 u_int8_t mode[2], drive; 1648 u_int32_t oidetim, idetim, idedma_ctl; 1649 struct pciide_channel *cp = (struct pciide_channel*)chp; 1650 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1651 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1652 1653 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1654 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1655 idedma_ctl = 0; 1656 1657 /* set up new idetim: Enable IDE registers decode */ 1658 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1659 chp->channel); 1660 1661 /* setup DMA */ 1662 pciide_channel_dma_setup(cp); 1663 1664 /* 1665 * Here we have to mess up with drives mode: PIIX can't have 1666 * different timings for master and slave drives. 1667 * We need to find the best combination. 1668 */ 1669 1670 /* If both drives supports DMA, take the lower mode */ 1671 if ((drvp[0].drive_flags & DRIVE_DMA) && 1672 (drvp[1].drive_flags & DRIVE_DMA)) { 1673 mode[0] = mode[1] = 1674 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1675 drvp[0].DMA_mode = mode[0]; 1676 drvp[1].DMA_mode = mode[1]; 1677 goto ok; 1678 } 1679 /* 1680 * If only one drive supports DMA, use its mode, and 1681 * put the other one in PIO mode 0 if mode not compatible 1682 */ 1683 if (drvp[0].drive_flags & DRIVE_DMA) { 1684 mode[0] = drvp[0].DMA_mode; 1685 mode[1] = drvp[1].PIO_mode; 1686 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1687 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1688 mode[1] = drvp[1].PIO_mode = 0; 1689 goto ok; 1690 } 1691 if (drvp[1].drive_flags & DRIVE_DMA) { 1692 mode[1] = drvp[1].DMA_mode; 1693 mode[0] = drvp[0].PIO_mode; 1694 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1695 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1696 mode[0] = drvp[0].PIO_mode = 0; 1697 goto ok; 1698 } 1699 /* 1700 * If both drives are not DMA, takes the lower mode, unless 1701 * one of them is PIO mode < 2 1702 */ 1703 if (drvp[0].PIO_mode < 2) { 1704 mode[0] = drvp[0].PIO_mode = 0; 1705 mode[1] = drvp[1].PIO_mode; 1706 } else if (drvp[1].PIO_mode < 2) { 1707 mode[1] = drvp[1].PIO_mode = 0; 1708 mode[0] = drvp[0].PIO_mode; 1709 } else { 1710 mode[0] = mode[1] = 1711 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1712 drvp[0].PIO_mode = mode[0]; 1713 drvp[1].PIO_mode = mode[1]; 1714 } 1715 ok: /* The modes are setup */ 1716 for (drive = 0; drive < 2; drive++) { 1717 if (drvp[drive].drive_flags & DRIVE_DMA) { 1718 idetim |= piix_setup_idetim_timings( 1719 mode[drive], 1, chp->channel); 1720 goto end; 1721 } 1722 } 1723 /* If we are there, none of the drives are DMA */ 1724 if (mode[0] >= 2) 1725 idetim |= piix_setup_idetim_timings( 1726 mode[0], 0, chp->channel); 1727 else 1728 idetim |= piix_setup_idetim_timings( 1729 mode[1], 0, chp->channel); 1730 end: /* 1731 * timing mode is now set up in the controller. Enable 1732 * it per-drive 1733 */ 1734 for (drive = 0; drive < 2; drive++) { 1735 /* If no drive, skip */ 1736 if ((drvp[drive].drive_flags & DRIVE) == 0) 1737 continue; 1738 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1739 if (drvp[drive].drive_flags & DRIVE_DMA) 1740 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1741 } 1742 if (idedma_ctl != 0) { 1743 /* Add software bits in status register */ 1744 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1745 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1746 idedma_ctl); 1747 } 1748 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1749 pciide_print_modes(cp); 1750 } 1751 1752 void 1753 piix3_4_setup_channel(chp) 1754 struct channel_softc *chp; 1755 { 1756 struct ata_drive_datas *drvp; 1757 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1758 struct pciide_channel *cp = (struct pciide_channel*)chp; 1759 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1760 int drive; 1761 int channel = chp->channel; 1762 1763 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1764 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1765 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1766 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1767 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1768 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1769 PIIX_SIDETIM_RTC_MASK(channel)); 1770 1771 idedma_ctl = 0; 1772 /* If channel disabled, no need to go further */ 1773 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1774 return; 1775 /* set up new idetim: Enable IDE registers decode */ 1776 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1777 1778 /* setup DMA if needed */ 1779 pciide_channel_dma_setup(cp); 1780 1781 for (drive = 0; drive < 2; drive++) { 1782 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1783 PIIX_UDMATIM_SET(0x3, channel, drive)); 1784 drvp = &chp->ch_drive[drive]; 1785 /* If no drive, skip */ 1786 if ((drvp->drive_flags & DRIVE) == 0) 1787 continue; 1788 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1789 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1790 goto pio; 1791 1792 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1793 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1794 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1795 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1796 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1797 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1798 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1799 ideconf |= PIIX_CONFIG_PINGPONG; 1800 } 1801 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1802 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1803 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1804 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1805 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1806 /* setup Ultra/100 */ 1807 if (drvp->UDMA_mode > 2 && 1808 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1809 drvp->UDMA_mode = 2; 1810 if (drvp->UDMA_mode > 4) { 1811 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1812 } else { 1813 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1814 if (drvp->UDMA_mode > 2) { 1815 ideconf |= PIIX_CONFIG_UDMA66(channel, 1816 drive); 1817 } else { 1818 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1819 drive); 1820 } 1821 } 1822 } 1823 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1824 /* setup Ultra/66 */ 1825 if (drvp->UDMA_mode > 2 && 1826 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1827 drvp->UDMA_mode = 2; 1828 if (drvp->UDMA_mode > 2) 1829 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1830 else 1831 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1832 } 1833 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1834 (drvp->drive_flags & DRIVE_UDMA)) { 1835 /* use Ultra/DMA */ 1836 drvp->drive_flags &= ~DRIVE_DMA; 1837 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1838 udmareg |= PIIX_UDMATIM_SET( 1839 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1840 } else { 1841 /* use Multiword DMA */ 1842 drvp->drive_flags &= ~DRIVE_UDMA; 1843 if (drive == 0) { 1844 idetim |= piix_setup_idetim_timings( 1845 drvp->DMA_mode, 1, channel); 1846 } else { 1847 sidetim |= piix_setup_sidetim_timings( 1848 drvp->DMA_mode, 1, channel); 1849 idetim =PIIX_IDETIM_SET(idetim, 1850 PIIX_IDETIM_SITRE, channel); 1851 } 1852 } 1853 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1854 1855 pio: /* use PIO mode */ 1856 idetim |= piix_setup_idetim_drvs(drvp); 1857 if (drive == 0) { 1858 idetim |= piix_setup_idetim_timings( 1859 drvp->PIO_mode, 0, channel); 1860 } else { 1861 sidetim |= piix_setup_sidetim_timings( 1862 drvp->PIO_mode, 0, channel); 1863 idetim =PIIX_IDETIM_SET(idetim, 1864 PIIX_IDETIM_SITRE, channel); 1865 } 1866 } 1867 if (idedma_ctl != 0) { 1868 /* Add software bits in status register */ 1869 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1870 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1871 idedma_ctl); 1872 } 1873 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1874 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1875 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1876 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1877 pciide_print_modes(cp); 1878 } 1879 1880 1881 /* setup ISP and RTC fields, based on mode */ 1882 static u_int32_t 1883 piix_setup_idetim_timings(mode, dma, channel) 1884 u_int8_t mode; 1885 u_int8_t dma; 1886 u_int8_t channel; 1887 { 1888 1889 if (dma) 1890 return PIIX_IDETIM_SET(0, 1891 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1892 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1893 channel); 1894 else 1895 return PIIX_IDETIM_SET(0, 1896 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1897 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1898 channel); 1899 } 1900 1901 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1902 static u_int32_t 1903 piix_setup_idetim_drvs(drvp) 1904 struct ata_drive_datas *drvp; 1905 { 1906 u_int32_t ret = 0; 1907 struct channel_softc *chp = drvp->chnl_softc; 1908 u_int8_t channel = chp->channel; 1909 u_int8_t drive = drvp->drive; 1910 1911 /* 1912 * If drive is using UDMA, timings setups are independant 1913 * So just check DMA and PIO here. 1914 */ 1915 if (drvp->drive_flags & DRIVE_DMA) { 1916 /* if mode = DMA mode 0, use compatible timings */ 1917 if ((drvp->drive_flags & DRIVE_DMA) && 1918 drvp->DMA_mode == 0) { 1919 drvp->PIO_mode = 0; 1920 return ret; 1921 } 1922 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1923 /* 1924 * PIO and DMA timings are the same, use fast timings for PIO 1925 * too, else use compat timings. 1926 */ 1927 if ((piix_isp_pio[drvp->PIO_mode] != 1928 piix_isp_dma[drvp->DMA_mode]) || 1929 (piix_rtc_pio[drvp->PIO_mode] != 1930 piix_rtc_dma[drvp->DMA_mode])) 1931 drvp->PIO_mode = 0; 1932 /* if PIO mode <= 2, use compat timings for PIO */ 1933 if (drvp->PIO_mode <= 2) { 1934 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1935 channel); 1936 return ret; 1937 } 1938 } 1939 1940 /* 1941 * Now setup PIO modes. If mode < 2, use compat timings. 1942 * Else enable fast timings. Enable IORDY and prefetch/post 1943 * if PIO mode >= 3. 1944 */ 1945 1946 if (drvp->PIO_mode < 2) 1947 return ret; 1948 1949 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1950 if (drvp->PIO_mode >= 3) { 1951 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1952 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1953 } 1954 return ret; 1955 } 1956 1957 /* setup values in SIDETIM registers, based on mode */ 1958 static u_int32_t 1959 piix_setup_sidetim_timings(mode, dma, channel) 1960 u_int8_t mode; 1961 u_int8_t dma; 1962 u_int8_t channel; 1963 { 1964 if (dma) 1965 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1966 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1967 else 1968 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1969 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1970 } 1971 1972 void 1973 amd7x6_chip_map(sc, pa) 1974 struct pciide_softc *sc; 1975 struct pci_attach_args *pa; 1976 { 1977 struct pciide_channel *cp; 1978 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1979 int channel; 1980 pcireg_t chanenable; 1981 bus_size_t cmdsize, ctlsize; 1982 1983 if (pciide_chipen(sc, pa) == 0) 1984 return; 1985 printf("%s: bus-master DMA support present", 1986 sc->sc_wdcdev.sc_dev.dv_xname); 1987 pciide_mapreg_dma(sc, pa); 1988 printf("\n"); 1989 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1990 WDC_CAPABILITY_MODE; 1991 if (sc->sc_dma_ok) { 1992 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1993 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1994 sc->sc_wdcdev.irqack = pciide_irqack; 1995 } 1996 sc->sc_wdcdev.PIO_cap = 4; 1997 sc->sc_wdcdev.DMA_cap = 2; 1998 1999 switch (sc->sc_pp->ide_product) { 2000 case PCI_PRODUCT_AMD_PBC766_IDE: 2001 case PCI_PRODUCT_AMD_PBC768_IDE: 2002 case PCI_PRODUCT_AMD_PBC8111_IDE: 2003 sc->sc_wdcdev.UDMA_cap = 5; 2004 break; 2005 default: 2006 sc->sc_wdcdev.UDMA_cap = 4; 2007 } 2008 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2009 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2010 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2011 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 2012 2013 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2014 DEBUG_PROBE); 2015 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2016 cp = &sc->pciide_channels[channel]; 2017 if (pciide_chansetup(sc, channel, interface) == 0) 2018 continue; 2019 2020 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2021 printf("%s: %s channel ignored (disabled)\n", 2022 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2023 continue; 2024 } 2025 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2026 pciide_pci_intr); 2027 2028 if (pciide_chan_candisable(cp)) 2029 chanenable &= ~AMD7X6_CHAN_EN(channel); 2030 pciide_map_compat_intr(pa, cp, channel, interface); 2031 if (cp->hw_ok == 0) 2032 continue; 2033 2034 amd7x6_setup_channel(&cp->wdc_channel); 2035 } 2036 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2037 chanenable); 2038 return; 2039 } 2040 2041 void 2042 amd7x6_setup_channel(chp) 2043 struct channel_softc *chp; 2044 { 2045 u_int32_t udmatim_reg, datatim_reg; 2046 u_int8_t idedma_ctl; 2047 int mode, drive; 2048 struct ata_drive_datas *drvp; 2049 struct pciide_channel *cp = (struct pciide_channel*)chp; 2050 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2051 #ifndef PCIIDE_AMD756_ENABLEDMA 2052 int rev = PCI_REVISION( 2053 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2054 #endif 2055 2056 idedma_ctl = 0; 2057 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2058 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2059 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2060 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2061 2062 /* setup DMA if needed */ 2063 pciide_channel_dma_setup(cp); 2064 2065 for (drive = 0; drive < 2; drive++) { 2066 drvp = &chp->ch_drive[drive]; 2067 /* If no drive, skip */ 2068 if ((drvp->drive_flags & DRIVE) == 0) 2069 continue; 2070 /* add timing values, setup DMA if needed */ 2071 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2072 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2073 mode = drvp->PIO_mode; 2074 goto pio; 2075 } 2076 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2077 (drvp->drive_flags & DRIVE_UDMA)) { 2078 /* use Ultra/DMA */ 2079 drvp->drive_flags &= ~DRIVE_DMA; 2080 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2081 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2082 AMD7X6_UDMA_TIME(chp->channel, drive, 2083 amd7x6_udma_tim[drvp->UDMA_mode]); 2084 /* can use PIO timings, MW DMA unused */ 2085 mode = drvp->PIO_mode; 2086 } else { 2087 /* use Multiword DMA, but only if revision is OK */ 2088 drvp->drive_flags &= ~DRIVE_UDMA; 2089 #ifndef PCIIDE_AMD756_ENABLEDMA 2090 /* 2091 * The workaround doesn't seem to be necessary 2092 * with all drives, so it can be disabled by 2093 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2094 * triggered. 2095 */ 2096 if (sc->sc_pp->ide_product == 2097 PCI_PRODUCT_AMD_PBC756_IDE && 2098 AMD756_CHIPREV_DISABLEDMA(rev)) { 2099 printf("%s:%d:%d: multi-word DMA disabled due " 2100 "to chip revision\n", 2101 sc->sc_wdcdev.sc_dev.dv_xname, 2102 chp->channel, drive); 2103 mode = drvp->PIO_mode; 2104 drvp->drive_flags &= ~DRIVE_DMA; 2105 goto pio; 2106 } 2107 #endif 2108 /* mode = min(pio, dma+2) */ 2109 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2110 mode = drvp->PIO_mode; 2111 else 2112 mode = drvp->DMA_mode + 2; 2113 } 2114 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2115 2116 pio: /* setup PIO mode */ 2117 if (mode <= 2) { 2118 drvp->DMA_mode = 0; 2119 drvp->PIO_mode = 0; 2120 mode = 0; 2121 } else { 2122 drvp->PIO_mode = mode; 2123 drvp->DMA_mode = mode - 2; 2124 } 2125 datatim_reg |= 2126 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2127 amd7x6_pio_set[mode]) | 2128 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2129 amd7x6_pio_rec[mode]); 2130 } 2131 if (idedma_ctl != 0) { 2132 /* Add software bits in status register */ 2133 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2134 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2135 idedma_ctl); 2136 } 2137 pciide_print_modes(cp); 2138 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2139 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2140 } 2141 2142 void 2143 apollo_chip_map(sc, pa) 2144 struct pciide_softc *sc; 2145 struct pci_attach_args *pa; 2146 { 2147 struct pciide_channel *cp; 2148 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2149 int channel; 2150 u_int32_t ideconf; 2151 bus_size_t cmdsize, ctlsize; 2152 pcitag_t pcib_tag; 2153 pcireg_t pcib_id, pcib_class; 2154 2155 if (pciide_chipen(sc, pa) == 0) 2156 return; 2157 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2158 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2159 /* and read ID and rev of the ISA bridge */ 2160 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2161 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2162 printf(": VIA Technologies "); 2163 switch (PCI_PRODUCT(pcib_id)) { 2164 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2165 printf("VT82C586 (Apollo VP) "); 2166 if(PCI_REVISION(pcib_class) >= 0x02) { 2167 printf("ATA33 controller\n"); 2168 sc->sc_wdcdev.UDMA_cap = 2; 2169 } else { 2170 printf("controller\n"); 2171 sc->sc_wdcdev.UDMA_cap = 0; 2172 } 2173 break; 2174 case PCI_PRODUCT_VIATECH_VT82C596A: 2175 printf("VT82C596A (Apollo Pro) "); 2176 if (PCI_REVISION(pcib_class) >= 0x12) { 2177 printf("ATA66 controller\n"); 2178 sc->sc_wdcdev.UDMA_cap = 4; 2179 } else { 2180 printf("ATA33 controller\n"); 2181 sc->sc_wdcdev.UDMA_cap = 2; 2182 } 2183 break; 2184 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2185 printf("VT82C686A (Apollo KX133) "); 2186 if (PCI_REVISION(pcib_class) >= 0x40) { 2187 printf("ATA100 controller\n"); 2188 sc->sc_wdcdev.UDMA_cap = 5; 2189 } else { 2190 printf("ATA66 controller\n"); 2191 sc->sc_wdcdev.UDMA_cap = 4; 2192 } 2193 break; 2194 case PCI_PRODUCT_VIATECH_VT8231: 2195 printf("VT8231 ATA100 controller\n"); 2196 sc->sc_wdcdev.UDMA_cap = 5; 2197 break; 2198 case PCI_PRODUCT_VIATECH_VT8233: 2199 printf("VT8233 ATA100 controller\n"); 2200 sc->sc_wdcdev.UDMA_cap = 5; 2201 break; 2202 case PCI_PRODUCT_VIATECH_VT8233A: 2203 printf("VT8233A ATA133 controller\n"); 2204 /* XXX use ATA100 untill ATA133 is supported */ 2205 sc->sc_wdcdev.UDMA_cap = 5; 2206 break; 2207 default: 2208 printf("unknown ATA controller\n"); 2209 sc->sc_wdcdev.UDMA_cap = 0; 2210 } 2211 2212 printf("%s: bus-master DMA support present", 2213 sc->sc_wdcdev.sc_dev.dv_xname); 2214 pciide_mapreg_dma(sc, pa); 2215 printf("\n"); 2216 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2217 WDC_CAPABILITY_MODE; 2218 if (sc->sc_dma_ok) { 2219 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2220 sc->sc_wdcdev.irqack = pciide_irqack; 2221 if (sc->sc_wdcdev.UDMA_cap > 0) 2222 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2223 } 2224 sc->sc_wdcdev.PIO_cap = 4; 2225 sc->sc_wdcdev.DMA_cap = 2; 2226 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2227 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2228 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2229 2230 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2231 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2232 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2233 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2234 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2235 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2236 DEBUG_PROBE); 2237 2238 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2239 cp = &sc->pciide_channels[channel]; 2240 if (pciide_chansetup(sc, channel, interface) == 0) 2241 continue; 2242 2243 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2244 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2245 printf("%s: %s channel ignored (disabled)\n", 2246 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2247 continue; 2248 } 2249 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2250 pciide_pci_intr); 2251 if (cp->hw_ok == 0) 2252 continue; 2253 if (pciide_chan_candisable(cp)) { 2254 ideconf &= ~APO_IDECONF_EN(channel); 2255 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2256 ideconf); 2257 } 2258 pciide_map_compat_intr(pa, cp, channel, interface); 2259 2260 if (cp->hw_ok == 0) 2261 continue; 2262 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2263 } 2264 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2265 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2266 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2267 } 2268 2269 void 2270 apollo_setup_channel(chp) 2271 struct channel_softc *chp; 2272 { 2273 u_int32_t udmatim_reg, datatim_reg; 2274 u_int8_t idedma_ctl; 2275 int mode, drive; 2276 struct ata_drive_datas *drvp; 2277 struct pciide_channel *cp = (struct pciide_channel*)chp; 2278 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2279 2280 idedma_ctl = 0; 2281 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2282 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2283 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2284 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2285 2286 /* setup DMA if needed */ 2287 pciide_channel_dma_setup(cp); 2288 2289 for (drive = 0; drive < 2; drive++) { 2290 drvp = &chp->ch_drive[drive]; 2291 /* If no drive, skip */ 2292 if ((drvp->drive_flags & DRIVE) == 0) 2293 continue; 2294 /* add timing values, setup DMA if needed */ 2295 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2296 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2297 mode = drvp->PIO_mode; 2298 goto pio; 2299 } 2300 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2301 (drvp->drive_flags & DRIVE_UDMA)) { 2302 /* use Ultra/DMA */ 2303 drvp->drive_flags &= ~DRIVE_DMA; 2304 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2305 APO_UDMA_EN_MTH(chp->channel, drive); 2306 if (sc->sc_wdcdev.UDMA_cap == 5) { 2307 /* 686b */ 2308 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2309 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2310 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2311 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2312 /* 596b or 686a */ 2313 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2314 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2315 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2316 } else { 2317 /* 596a or 586b */ 2318 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2319 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2320 } 2321 /* can use PIO timings, MW DMA unused */ 2322 mode = drvp->PIO_mode; 2323 } else { 2324 /* use Multiword DMA */ 2325 drvp->drive_flags &= ~DRIVE_UDMA; 2326 /* mode = min(pio, dma+2) */ 2327 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2328 mode = drvp->PIO_mode; 2329 else 2330 mode = drvp->DMA_mode + 2; 2331 } 2332 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2333 2334 pio: /* setup PIO mode */ 2335 if (mode <= 2) { 2336 drvp->DMA_mode = 0; 2337 drvp->PIO_mode = 0; 2338 mode = 0; 2339 } else { 2340 drvp->PIO_mode = mode; 2341 drvp->DMA_mode = mode - 2; 2342 } 2343 datatim_reg |= 2344 APO_DATATIM_PULSE(chp->channel, drive, 2345 apollo_pio_set[mode]) | 2346 APO_DATATIM_RECOV(chp->channel, drive, 2347 apollo_pio_rec[mode]); 2348 } 2349 if (idedma_ctl != 0) { 2350 /* Add software bits in status register */ 2351 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2352 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2353 idedma_ctl); 2354 } 2355 pciide_print_modes(cp); 2356 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2357 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2358 } 2359 2360 void 2361 cmd_channel_map(pa, sc, channel) 2362 struct pci_attach_args *pa; 2363 struct pciide_softc *sc; 2364 int channel; 2365 { 2366 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2367 bus_size_t cmdsize, ctlsize; 2368 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2369 int interface, one_channel; 2370 2371 /* 2372 * The 0648/0649 can be told to identify as a RAID controller. 2373 * In this case, we have to fake interface 2374 */ 2375 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2376 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2377 PCIIDE_INTERFACE_SETTABLE(1); 2378 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2379 CMD_CONF_DSA1) 2380 interface |= PCIIDE_INTERFACE_PCI(0) | 2381 PCIIDE_INTERFACE_PCI(1); 2382 } else { 2383 interface = PCI_INTERFACE(pa->pa_class); 2384 } 2385 2386 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2387 cp->name = PCIIDE_CHANNEL_NAME(channel); 2388 cp->wdc_channel.channel = channel; 2389 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2390 2391 /* 2392 * Older CMD64X doesn't have independant channels 2393 */ 2394 switch (sc->sc_pp->ide_product) { 2395 case PCI_PRODUCT_CMDTECH_649: 2396 one_channel = 0; 2397 break; 2398 default: 2399 one_channel = 1; 2400 break; 2401 } 2402 2403 if (channel > 0 && one_channel) { 2404 cp->wdc_channel.ch_queue = 2405 sc->pciide_channels[0].wdc_channel.ch_queue; 2406 } else { 2407 cp->wdc_channel.ch_queue = 2408 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2409 } 2410 if (cp->wdc_channel.ch_queue == NULL) { 2411 printf("%s %s channel: " 2412 "can't allocate memory for command queue", 2413 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2414 return; 2415 } 2416 2417 printf("%s: %s channel %s to %s mode\n", 2418 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2419 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2420 "configured" : "wired", 2421 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2422 "native-PCI" : "compatibility"); 2423 2424 /* 2425 * with a CMD PCI64x, if we get here, the first channel is enabled: 2426 * there's no way to disable the first channel without disabling 2427 * the whole device 2428 */ 2429 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2430 printf("%s: %s channel ignored (disabled)\n", 2431 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2432 return; 2433 } 2434 2435 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2436 if (cp->hw_ok == 0) 2437 return; 2438 if (channel == 1) { 2439 if (pciide_chan_candisable(cp)) { 2440 ctrl &= ~CMD_CTRL_2PORT; 2441 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2442 CMD_CTRL, ctrl); 2443 } 2444 } 2445 pciide_map_compat_intr(pa, cp, channel, interface); 2446 } 2447 2448 int 2449 cmd_pci_intr(arg) 2450 void *arg; 2451 { 2452 struct pciide_softc *sc = arg; 2453 struct pciide_channel *cp; 2454 struct channel_softc *wdc_cp; 2455 int i, rv, crv; 2456 u_int32_t priirq, secirq; 2457 2458 rv = 0; 2459 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2460 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2461 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2462 cp = &sc->pciide_channels[i]; 2463 wdc_cp = &cp->wdc_channel; 2464 /* If a compat channel skip. */ 2465 if (cp->compat) 2466 continue; 2467 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2468 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2469 crv = wdcintr(wdc_cp); 2470 if (crv == 0) 2471 printf("%s:%d: bogus intr\n", 2472 sc->sc_wdcdev.sc_dev.dv_xname, i); 2473 else 2474 rv = 1; 2475 } 2476 } 2477 return rv; 2478 } 2479 2480 void 2481 cmd_chip_map(sc, pa) 2482 struct pciide_softc *sc; 2483 struct pci_attach_args *pa; 2484 { 2485 int channel; 2486 2487 /* 2488 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2489 * and base adresses registers can be disabled at 2490 * hardware level. In this case, the device is wired 2491 * in compat mode and its first channel is always enabled, 2492 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2493 * In fact, it seems that the first channel of the CMD PCI0640 2494 * can't be disabled. 2495 */ 2496 2497 #ifdef PCIIDE_CMD064x_DISABLE 2498 if (pciide_chipen(sc, pa) == 0) 2499 return; 2500 #endif 2501 2502 printf("%s: hardware does not support DMA\n", 2503 sc->sc_wdcdev.sc_dev.dv_xname); 2504 sc->sc_dma_ok = 0; 2505 2506 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2507 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2508 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2509 2510 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2511 cmd_channel_map(pa, sc, channel); 2512 } 2513 } 2514 2515 void 2516 cmd0643_9_chip_map(sc, pa) 2517 struct pciide_softc *sc; 2518 struct pci_attach_args *pa; 2519 { 2520 struct pciide_channel *cp; 2521 int channel; 2522 pcireg_t rev = PCI_REVISION(pa->pa_class); 2523 2524 /* 2525 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2526 * and base adresses registers can be disabled at 2527 * hardware level. In this case, the device is wired 2528 * in compat mode and its first channel is always enabled, 2529 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2530 * In fact, it seems that the first channel of the CMD PCI0640 2531 * can't be disabled. 2532 */ 2533 2534 #ifdef PCIIDE_CMD064x_DISABLE 2535 if (pciide_chipen(sc, pa) == 0) 2536 return; 2537 #endif 2538 printf("%s: bus-master DMA support present", 2539 sc->sc_wdcdev.sc_dev.dv_xname); 2540 pciide_mapreg_dma(sc, pa); 2541 printf("\n"); 2542 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2543 WDC_CAPABILITY_MODE; 2544 if (sc->sc_dma_ok) { 2545 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2546 switch (sc->sc_pp->ide_product) { 2547 case PCI_PRODUCT_CMDTECH_649: 2548 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2549 sc->sc_wdcdev.UDMA_cap = 5; 2550 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2551 break; 2552 case PCI_PRODUCT_CMDTECH_648: 2553 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2554 sc->sc_wdcdev.UDMA_cap = 4; 2555 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2556 break; 2557 case PCI_PRODUCT_CMDTECH_646: 2558 if (rev >= CMD0646U2_REV) { 2559 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2560 sc->sc_wdcdev.UDMA_cap = 2; 2561 } else if (rev >= CMD0646U_REV) { 2562 /* 2563 * Linux's driver claims that the 646U is broken 2564 * with UDMA. Only enable it if we know what we're 2565 * doing 2566 */ 2567 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2568 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2569 sc->sc_wdcdev.UDMA_cap = 2; 2570 #endif 2571 /* explicitly disable UDMA */ 2572 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2573 CMD_UDMATIM(0), 0); 2574 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2575 CMD_UDMATIM(1), 0); 2576 } 2577 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2578 break; 2579 default: 2580 sc->sc_wdcdev.irqack = pciide_irqack; 2581 } 2582 } 2583 2584 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2585 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2586 sc->sc_wdcdev.PIO_cap = 4; 2587 sc->sc_wdcdev.DMA_cap = 2; 2588 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2589 2590 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2591 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2592 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2593 DEBUG_PROBE); 2594 2595 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2596 cp = &sc->pciide_channels[channel]; 2597 cmd_channel_map(pa, sc, channel); 2598 if (cp->hw_ok == 0) 2599 continue; 2600 cmd0643_9_setup_channel(&cp->wdc_channel); 2601 } 2602 /* 2603 * note - this also makes sure we clear the irq disable and reset 2604 * bits 2605 */ 2606 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2607 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2608 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2609 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2610 DEBUG_PROBE); 2611 } 2612 2613 void 2614 cmd0643_9_setup_channel(chp) 2615 struct channel_softc *chp; 2616 { 2617 struct ata_drive_datas *drvp; 2618 u_int8_t tim; 2619 u_int32_t idedma_ctl, udma_reg; 2620 int drive; 2621 struct pciide_channel *cp = (struct pciide_channel*)chp; 2622 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2623 2624 idedma_ctl = 0; 2625 /* setup DMA if needed */ 2626 pciide_channel_dma_setup(cp); 2627 2628 for (drive = 0; drive < 2; drive++) { 2629 drvp = &chp->ch_drive[drive]; 2630 /* If no drive, skip */ 2631 if ((drvp->drive_flags & DRIVE) == 0) 2632 continue; 2633 /* add timing values, setup DMA if needed */ 2634 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2635 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2636 if (drvp->drive_flags & DRIVE_UDMA) { 2637 /* UltraDMA on a 646U2, 0648 or 0649 */ 2638 drvp->drive_flags &= ~DRIVE_DMA; 2639 udma_reg = pciide_pci_read(sc->sc_pc, 2640 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2641 if (drvp->UDMA_mode > 2 && 2642 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2643 CMD_BICSR) & 2644 CMD_BICSR_80(chp->channel)) == 0) 2645 drvp->UDMA_mode = 2; 2646 if (drvp->UDMA_mode > 2) 2647 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2648 else if (sc->sc_wdcdev.UDMA_cap > 2) 2649 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2650 udma_reg |= CMD_UDMATIM_UDMA(drive); 2651 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2652 CMD_UDMATIM_TIM_OFF(drive)); 2653 udma_reg |= 2654 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2655 CMD_UDMATIM_TIM_OFF(drive)); 2656 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2657 CMD_UDMATIM(chp->channel), udma_reg); 2658 } else { 2659 /* 2660 * use Multiword DMA. 2661 * Timings will be used for both PIO and DMA, 2662 * so adjust DMA mode if needed 2663 * if we have a 0646U2/8/9, turn off UDMA 2664 */ 2665 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2666 udma_reg = pciide_pci_read(sc->sc_pc, 2667 sc->sc_tag, 2668 CMD_UDMATIM(chp->channel)); 2669 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2670 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2671 CMD_UDMATIM(chp->channel), 2672 udma_reg); 2673 } 2674 if (drvp->PIO_mode >= 3 && 2675 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2676 drvp->DMA_mode = drvp->PIO_mode - 2; 2677 } 2678 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2679 } 2680 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2681 } 2682 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2683 CMD_DATA_TIM(chp->channel, drive), tim); 2684 } 2685 if (idedma_ctl != 0) { 2686 /* Add software bits in status register */ 2687 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2688 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2689 idedma_ctl); 2690 } 2691 pciide_print_modes(cp); 2692 } 2693 2694 void 2695 cmd646_9_irqack(chp) 2696 struct channel_softc *chp; 2697 { 2698 u_int32_t priirq, secirq; 2699 struct pciide_channel *cp = (struct pciide_channel*)chp; 2700 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2701 2702 if (chp->channel == 0) { 2703 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2704 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2705 } else { 2706 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2707 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2708 } 2709 pciide_irqack(chp); 2710 } 2711 2712 void 2713 cmd680_chip_map(sc, pa) 2714 struct pciide_softc *sc; 2715 struct pci_attach_args *pa; 2716 { 2717 struct pciide_channel *cp; 2718 int channel; 2719 2720 if (pciide_chipen(sc, pa) == 0) 2721 return; 2722 printf("%s: bus-master DMA support present", 2723 sc->sc_wdcdev.sc_dev.dv_xname); 2724 pciide_mapreg_dma(sc, pa); 2725 printf("\n"); 2726 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2727 WDC_CAPABILITY_MODE; 2728 if (sc->sc_dma_ok) { 2729 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2730 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2731 sc->sc_wdcdev.UDMA_cap = 6; 2732 sc->sc_wdcdev.irqack = pciide_irqack; 2733 } 2734 2735 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2736 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2737 sc->sc_wdcdev.PIO_cap = 4; 2738 sc->sc_wdcdev.DMA_cap = 2; 2739 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2740 2741 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2742 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2743 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2744 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2745 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2746 cp = &sc->pciide_channels[channel]; 2747 cmd680_channel_map(pa, sc, channel); 2748 if (cp->hw_ok == 0) 2749 continue; 2750 cmd680_setup_channel(&cp->wdc_channel); 2751 } 2752 } 2753 2754 void 2755 cmd680_channel_map(pa, sc, channel) 2756 struct pci_attach_args *pa; 2757 struct pciide_softc *sc; 2758 int channel; 2759 { 2760 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2761 bus_size_t cmdsize, ctlsize; 2762 int interface, i, reg; 2763 static const u_int8_t init_val[] = 2764 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2765 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2766 2767 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2768 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2769 PCIIDE_INTERFACE_SETTABLE(1); 2770 interface |= PCIIDE_INTERFACE_PCI(0) | 2771 PCIIDE_INTERFACE_PCI(1); 2772 } else { 2773 interface = PCI_INTERFACE(pa->pa_class); 2774 } 2775 2776 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2777 cp->name = PCIIDE_CHANNEL_NAME(channel); 2778 cp->wdc_channel.channel = channel; 2779 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2780 2781 cp->wdc_channel.ch_queue = 2782 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2783 if (cp->wdc_channel.ch_queue == NULL) { 2784 printf("%s %s channel: " 2785 "can't allocate memory for command queue", 2786 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2787 return; 2788 } 2789 2790 /* XXX */ 2791 reg = 0xa2 + channel * 16; 2792 for (i = 0; i < sizeof(init_val); i++) 2793 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2794 2795 printf("%s: %s channel %s to %s mode\n", 2796 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2797 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2798 "configured" : "wired", 2799 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2800 "native-PCI" : "compatibility"); 2801 2802 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2803 if (cp->hw_ok == 0) 2804 return; 2805 pciide_map_compat_intr(pa, cp, channel, interface); 2806 } 2807 2808 void 2809 cmd680_setup_channel(chp) 2810 struct channel_softc *chp; 2811 { 2812 struct ata_drive_datas *drvp; 2813 u_int8_t mode, off, scsc; 2814 u_int16_t val; 2815 u_int32_t idedma_ctl; 2816 int drive; 2817 struct pciide_channel *cp = (struct pciide_channel*)chp; 2818 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2819 pci_chipset_tag_t pc = sc->sc_pc; 2820 pcitag_t pa = sc->sc_tag; 2821 static const u_int8_t udma2_tbl[] = 2822 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2823 static const u_int8_t udma_tbl[] = 2824 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2825 static const u_int16_t dma_tbl[] = 2826 { 0x2208, 0x10c2, 0x10c1 }; 2827 static const u_int16_t pio_tbl[] = 2828 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2829 2830 idedma_ctl = 0; 2831 pciide_channel_dma_setup(cp); 2832 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2833 2834 for (drive = 0; drive < 2; drive++) { 2835 drvp = &chp->ch_drive[drive]; 2836 /* If no drive, skip */ 2837 if ((drvp->drive_flags & DRIVE) == 0) 2838 continue; 2839 mode &= ~(0x03 << (drive * 4)); 2840 if (drvp->drive_flags & DRIVE_UDMA) { 2841 drvp->drive_flags &= ~DRIVE_DMA; 2842 off = 0xa0 + chp->channel * 16; 2843 if (drvp->UDMA_mode > 2 && 2844 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2845 drvp->UDMA_mode = 2; 2846 scsc = pciide_pci_read(pc, pa, 0x8a); 2847 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 2848 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 2849 scsc = pciide_pci_read(pc, pa, 0x8a); 2850 if ((scsc & 0x30) == 0) 2851 drvp->UDMA_mode = 5; 2852 } 2853 mode |= 0x03 << (drive * 4); 2854 off = 0xac + chp->channel * 16 + drive * 2; 2855 val = pciide_pci_read(pc, pa, off) & ~0x3f; 2856 if (scsc & 0x30) 2857 val |= udma2_tbl[drvp->UDMA_mode]; 2858 else 2859 val |= udma_tbl[drvp->UDMA_mode]; 2860 pciide_pci_write(pc, pa, off, val); 2861 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2862 } else if (drvp->drive_flags & DRIVE_DMA) { 2863 mode |= 0x02 << (drive * 4); 2864 off = 0xa8 + chp->channel * 16 + drive * 2; 2865 val = dma_tbl[drvp->DMA_mode]; 2866 pciide_pci_write(pc, pa, off, val & 0xff); 2867 pciide_pci_write(pc, pa, off, val >> 8); 2868 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2869 } else { 2870 mode |= 0x01 << (drive * 4); 2871 off = 0xa4 + chp->channel * 16 + drive * 2; 2872 val = pio_tbl[drvp->PIO_mode]; 2873 pciide_pci_write(pc, pa, off, val & 0xff); 2874 pciide_pci_write(pc, pa, off, val >> 8); 2875 } 2876 } 2877 2878 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 2879 if (idedma_ctl != 0) { 2880 /* Add software bits in status register */ 2881 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2882 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2883 idedma_ctl); 2884 } 2885 pciide_print_modes(cp); 2886 } 2887 2888 void 2889 cy693_chip_map(sc, pa) 2890 struct pciide_softc *sc; 2891 struct pci_attach_args *pa; 2892 { 2893 struct pciide_channel *cp; 2894 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2895 bus_size_t cmdsize, ctlsize; 2896 2897 if (pciide_chipen(sc, pa) == 0) 2898 return; 2899 /* 2900 * this chip has 2 PCI IDE functions, one for primary and one for 2901 * secondary. So we need to call pciide_mapregs_compat() with 2902 * the real channel 2903 */ 2904 if (pa->pa_function == 1) { 2905 sc->sc_cy_compatchan = 0; 2906 } else if (pa->pa_function == 2) { 2907 sc->sc_cy_compatchan = 1; 2908 } else { 2909 printf("%s: unexpected PCI function %d\n", 2910 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2911 return; 2912 } 2913 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2914 printf("%s: bus-master DMA support present", 2915 sc->sc_wdcdev.sc_dev.dv_xname); 2916 pciide_mapreg_dma(sc, pa); 2917 } else { 2918 printf("%s: hardware does not support DMA", 2919 sc->sc_wdcdev.sc_dev.dv_xname); 2920 sc->sc_dma_ok = 0; 2921 } 2922 printf("\n"); 2923 2924 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2925 if (sc->sc_cy_handle == NULL) { 2926 printf("%s: unable to map hyperCache control registers\n", 2927 sc->sc_wdcdev.sc_dev.dv_xname); 2928 sc->sc_dma_ok = 0; 2929 } 2930 2931 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2932 WDC_CAPABILITY_MODE; 2933 if (sc->sc_dma_ok) { 2934 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2935 sc->sc_wdcdev.irqack = pciide_irqack; 2936 } 2937 sc->sc_wdcdev.PIO_cap = 4; 2938 sc->sc_wdcdev.DMA_cap = 2; 2939 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2940 2941 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2942 sc->sc_wdcdev.nchannels = 1; 2943 2944 /* Only one channel for this chip; if we are here it's enabled */ 2945 cp = &sc->pciide_channels[0]; 2946 sc->wdc_chanarray[0] = &cp->wdc_channel; 2947 cp->name = PCIIDE_CHANNEL_NAME(0); 2948 cp->wdc_channel.channel = 0; 2949 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2950 cp->wdc_channel.ch_queue = 2951 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2952 if (cp->wdc_channel.ch_queue == NULL) { 2953 printf("%s primary channel: " 2954 "can't allocate memory for command queue", 2955 sc->sc_wdcdev.sc_dev.dv_xname); 2956 return; 2957 } 2958 printf("%s: primary channel %s to ", 2959 sc->sc_wdcdev.sc_dev.dv_xname, 2960 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2961 "configured" : "wired"); 2962 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2963 printf("native-PCI"); 2964 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2965 pciide_pci_intr); 2966 } else { 2967 printf("compatibility"); 2968 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2969 &cmdsize, &ctlsize); 2970 } 2971 printf(" mode\n"); 2972 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2973 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2974 wdcattach(&cp->wdc_channel); 2975 if (pciide_chan_candisable(cp)) { 2976 pci_conf_write(sc->sc_pc, sc->sc_tag, 2977 PCI_COMMAND_STATUS_REG, 0); 2978 } 2979 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2980 if (cp->hw_ok == 0) 2981 return; 2982 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2983 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2984 cy693_setup_channel(&cp->wdc_channel); 2985 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2986 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2987 } 2988 2989 void 2990 cy693_setup_channel(chp) 2991 struct channel_softc *chp; 2992 { 2993 struct ata_drive_datas *drvp; 2994 int drive; 2995 u_int32_t cy_cmd_ctrl; 2996 u_int32_t idedma_ctl; 2997 struct pciide_channel *cp = (struct pciide_channel*)chp; 2998 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2999 int dma_mode = -1; 3000 3001 cy_cmd_ctrl = idedma_ctl = 0; 3002 3003 /* setup DMA if needed */ 3004 pciide_channel_dma_setup(cp); 3005 3006 for (drive = 0; drive < 2; drive++) { 3007 drvp = &chp->ch_drive[drive]; 3008 /* If no drive, skip */ 3009 if ((drvp->drive_flags & DRIVE) == 0) 3010 continue; 3011 /* add timing values, setup DMA if needed */ 3012 if (drvp->drive_flags & DRIVE_DMA) { 3013 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3014 /* use Multiword DMA */ 3015 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3016 dma_mode = drvp->DMA_mode; 3017 } 3018 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3019 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3020 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3021 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3022 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3023 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3024 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3025 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3026 } 3027 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3028 chp->ch_drive[0].DMA_mode = dma_mode; 3029 chp->ch_drive[1].DMA_mode = dma_mode; 3030 3031 if (dma_mode == -1) 3032 dma_mode = 0; 3033 3034 if (sc->sc_cy_handle != NULL) { 3035 /* Note: `multiple' is implied. */ 3036 cy82c693_write(sc->sc_cy_handle, 3037 (sc->sc_cy_compatchan == 0) ? 3038 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3039 } 3040 3041 pciide_print_modes(cp); 3042 3043 if (idedma_ctl != 0) { 3044 /* Add software bits in status register */ 3045 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3046 IDEDMA_CTL, idedma_ctl); 3047 } 3048 } 3049 3050 static int 3051 sis_hostbr_match(pa) 3052 struct pci_attach_args *pa; 3053 { 3054 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 3055 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 3056 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 3057 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 3058 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 3059 } 3060 3061 void 3062 sis_chip_map(sc, pa) 3063 struct pciide_softc *sc; 3064 struct pci_attach_args *pa; 3065 { 3066 struct pciide_channel *cp; 3067 int channel; 3068 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3069 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3070 pcireg_t rev = PCI_REVISION(pa->pa_class); 3071 bus_size_t cmdsize, ctlsize; 3072 pcitag_t pchb_tag; 3073 pcireg_t pchb_id, pchb_class; 3074 3075 if (pciide_chipen(sc, pa) == 0) 3076 return; 3077 printf("%s: bus-master DMA support present", 3078 sc->sc_wdcdev.sc_dev.dv_xname); 3079 pciide_mapreg_dma(sc, pa); 3080 printf("\n"); 3081 3082 /* get a PCI tag for the host bridge (function 0 of the same device) */ 3083 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 3084 /* and read ID and rev of the ISA bridge */ 3085 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 3086 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 3087 3088 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3089 WDC_CAPABILITY_MODE; 3090 if (sc->sc_dma_ok) { 3091 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3092 sc->sc_wdcdev.irqack = pciide_irqack; 3093 /* 3094 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3095 * have problems with UDMA (info provided by Christos) 3096 */ 3097 if (rev >= 0xd0 && 3098 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 3099 PCI_REVISION(pchb_class) >= 0x03)) 3100 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3101 } 3102 3103 sc->sc_wdcdev.PIO_cap = 4; 3104 sc->sc_wdcdev.DMA_cap = 2; 3105 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 3106 /* 3107 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 3108 * chipsets. 3109 */ 3110 sc->sc_wdcdev.UDMA_cap = 3111 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 3112 sc->sc_wdcdev.set_modes = sis_setup_channel; 3113 3114 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3115 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3116 3117 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3118 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3119 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 3120 3121 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3122 cp = &sc->pciide_channels[channel]; 3123 if (pciide_chansetup(sc, channel, interface) == 0) 3124 continue; 3125 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3126 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3127 printf("%s: %s channel ignored (disabled)\n", 3128 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3129 continue; 3130 } 3131 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3132 pciide_pci_intr); 3133 if (cp->hw_ok == 0) 3134 continue; 3135 if (pciide_chan_candisable(cp)) { 3136 if (channel == 0) 3137 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3138 else 3139 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3140 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3141 sis_ctr0); 3142 } 3143 pciide_map_compat_intr(pa, cp, channel, interface); 3144 if (cp->hw_ok == 0) 3145 continue; 3146 sis_setup_channel(&cp->wdc_channel); 3147 } 3148 } 3149 3150 void 3151 sis_setup_channel(chp) 3152 struct channel_softc *chp; 3153 { 3154 struct ata_drive_datas *drvp; 3155 int drive; 3156 u_int32_t sis_tim; 3157 u_int32_t idedma_ctl; 3158 struct pciide_channel *cp = (struct pciide_channel*)chp; 3159 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3160 3161 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3162 "channel %d 0x%x\n", chp->channel, 3163 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3164 DEBUG_PROBE); 3165 sis_tim = 0; 3166 idedma_ctl = 0; 3167 /* setup DMA if needed */ 3168 pciide_channel_dma_setup(cp); 3169 3170 for (drive = 0; drive < 2; drive++) { 3171 drvp = &chp->ch_drive[drive]; 3172 /* If no drive, skip */ 3173 if ((drvp->drive_flags & DRIVE) == 0) 3174 continue; 3175 /* add timing values, setup DMA if needed */ 3176 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3177 (drvp->drive_flags & DRIVE_UDMA) == 0) 3178 goto pio; 3179 3180 if (drvp->drive_flags & DRIVE_UDMA) { 3181 /* use Ultra/DMA */ 3182 drvp->drive_flags &= ~DRIVE_DMA; 3183 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 3184 SIS_TIM_UDMA_TIME_OFF(drive); 3185 sis_tim |= SIS_TIM_UDMA_EN(drive); 3186 } else { 3187 /* 3188 * use Multiword DMA 3189 * Timings will be used for both PIO and DMA, 3190 * so adjust DMA mode if needed 3191 */ 3192 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3193 drvp->PIO_mode = drvp->DMA_mode + 2; 3194 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3195 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3196 drvp->PIO_mode - 2 : 0; 3197 if (drvp->DMA_mode == 0) 3198 drvp->PIO_mode = 0; 3199 } 3200 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3201 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 3202 SIS_TIM_ACT_OFF(drive); 3203 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3204 SIS_TIM_REC_OFF(drive); 3205 } 3206 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3207 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3208 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3209 if (idedma_ctl != 0) { 3210 /* Add software bits in status register */ 3211 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3212 IDEDMA_CTL, idedma_ctl); 3213 } 3214 pciide_print_modes(cp); 3215 } 3216 3217 void 3218 acer_chip_map(sc, pa) 3219 struct pciide_softc *sc; 3220 struct pci_attach_args *pa; 3221 { 3222 struct pciide_channel *cp; 3223 int channel; 3224 pcireg_t cr, interface; 3225 bus_size_t cmdsize, ctlsize; 3226 pcireg_t rev = PCI_REVISION(pa->pa_class); 3227 3228 if (pciide_chipen(sc, pa) == 0) 3229 return; 3230 printf("%s: bus-master DMA support present", 3231 sc->sc_wdcdev.sc_dev.dv_xname); 3232 pciide_mapreg_dma(sc, pa); 3233 printf("\n"); 3234 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3235 WDC_CAPABILITY_MODE; 3236 if (sc->sc_dma_ok) { 3237 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3238 if (rev >= 0x20) { 3239 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3240 if (rev >= 0xC4) 3241 sc->sc_wdcdev.UDMA_cap = 5; 3242 else if (rev >= 0xC2) 3243 sc->sc_wdcdev.UDMA_cap = 4; 3244 else 3245 sc->sc_wdcdev.UDMA_cap = 2; 3246 } 3247 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3248 sc->sc_wdcdev.irqack = pciide_irqack; 3249 } 3250 3251 sc->sc_wdcdev.PIO_cap = 4; 3252 sc->sc_wdcdev.DMA_cap = 2; 3253 sc->sc_wdcdev.set_modes = acer_setup_channel; 3254 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3255 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3256 3257 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3258 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3259 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3260 3261 /* Enable "microsoft register bits" R/W. */ 3262 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3263 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3264 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3265 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3266 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3267 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3268 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3269 ~ACER_CHANSTATUSREGS_RO); 3270 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3271 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3272 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3273 /* Don't use cr, re-read the real register content instead */ 3274 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3275 PCI_CLASS_REG)); 3276 3277 /* From linux: enable "Cable Detection" */ 3278 if (rev >= 0xC2) { 3279 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3280 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3281 | ACER_0x4B_CDETECT); 3282 } 3283 3284 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3285 cp = &sc->pciide_channels[channel]; 3286 if (pciide_chansetup(sc, channel, interface) == 0) 3287 continue; 3288 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3289 printf("%s: %s channel ignored (disabled)\n", 3290 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3291 continue; 3292 } 3293 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3294 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3295 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3296 if (cp->hw_ok == 0) 3297 continue; 3298 if (pciide_chan_candisable(cp)) { 3299 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3300 pci_conf_write(sc->sc_pc, sc->sc_tag, 3301 PCI_CLASS_REG, cr); 3302 } 3303 pciide_map_compat_intr(pa, cp, channel, interface); 3304 acer_setup_channel(&cp->wdc_channel); 3305 } 3306 } 3307 3308 void 3309 acer_setup_channel(chp) 3310 struct channel_softc *chp; 3311 { 3312 struct ata_drive_datas *drvp; 3313 int drive; 3314 u_int32_t acer_fifo_udma; 3315 u_int32_t idedma_ctl; 3316 struct pciide_channel *cp = (struct pciide_channel*)chp; 3317 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3318 3319 idedma_ctl = 0; 3320 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3321 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3322 acer_fifo_udma), DEBUG_PROBE); 3323 /* setup DMA if needed */ 3324 pciide_channel_dma_setup(cp); 3325 3326 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3327 DRIVE_UDMA) { /* check 80 pins cable */ 3328 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3329 ACER_0x4A_80PIN(chp->channel)) { 3330 if (chp->ch_drive[0].UDMA_mode > 2) 3331 chp->ch_drive[0].UDMA_mode = 2; 3332 if (chp->ch_drive[1].UDMA_mode > 2) 3333 chp->ch_drive[1].UDMA_mode = 2; 3334 } 3335 } 3336 3337 for (drive = 0; drive < 2; drive++) { 3338 drvp = &chp->ch_drive[drive]; 3339 /* If no drive, skip */ 3340 if ((drvp->drive_flags & DRIVE) == 0) 3341 continue; 3342 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3343 "channel %d drive %d 0x%x\n", chp->channel, drive, 3344 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3345 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3346 /* clear FIFO/DMA mode */ 3347 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3348 ACER_UDMA_EN(chp->channel, drive) | 3349 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3350 3351 /* add timing values, setup DMA if needed */ 3352 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3353 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3354 acer_fifo_udma |= 3355 ACER_FTH_OPL(chp->channel, drive, 0x1); 3356 goto pio; 3357 } 3358 3359 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3360 if (drvp->drive_flags & DRIVE_UDMA) { 3361 /* use Ultra/DMA */ 3362 drvp->drive_flags &= ~DRIVE_DMA; 3363 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3364 acer_fifo_udma |= 3365 ACER_UDMA_TIM(chp->channel, drive, 3366 acer_udma[drvp->UDMA_mode]); 3367 /* XXX disable if one drive < UDMA3 ? */ 3368 if (drvp->UDMA_mode >= 3) { 3369 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3370 ACER_0x4B, 3371 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3372 ACER_0x4B) | ACER_0x4B_UDMA66); 3373 } 3374 } else { 3375 /* 3376 * use Multiword DMA 3377 * Timings will be used for both PIO and DMA, 3378 * so adjust DMA mode if needed 3379 */ 3380 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3381 drvp->PIO_mode = drvp->DMA_mode + 2; 3382 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3383 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3384 drvp->PIO_mode - 2 : 0; 3385 if (drvp->DMA_mode == 0) 3386 drvp->PIO_mode = 0; 3387 } 3388 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3389 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3390 ACER_IDETIM(chp->channel, drive), 3391 acer_pio[drvp->PIO_mode]); 3392 } 3393 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3394 acer_fifo_udma), DEBUG_PROBE); 3395 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3396 if (idedma_ctl != 0) { 3397 /* Add software bits in status register */ 3398 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3399 IDEDMA_CTL, idedma_ctl); 3400 } 3401 pciide_print_modes(cp); 3402 } 3403 3404 int 3405 acer_pci_intr(arg) 3406 void *arg; 3407 { 3408 struct pciide_softc *sc = arg; 3409 struct pciide_channel *cp; 3410 struct channel_softc *wdc_cp; 3411 int i, rv, crv; 3412 u_int32_t chids; 3413 3414 rv = 0; 3415 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3416 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3417 cp = &sc->pciide_channels[i]; 3418 wdc_cp = &cp->wdc_channel; 3419 /* If a compat channel skip. */ 3420 if (cp->compat) 3421 continue; 3422 if (chids & ACER_CHIDS_INT(i)) { 3423 crv = wdcintr(wdc_cp); 3424 if (crv == 0) 3425 printf("%s:%d: bogus intr\n", 3426 sc->sc_wdcdev.sc_dev.dv_xname, i); 3427 else 3428 rv = 1; 3429 } 3430 } 3431 return rv; 3432 } 3433 3434 void 3435 hpt_chip_map(sc, pa) 3436 struct pciide_softc *sc; 3437 struct pci_attach_args *pa; 3438 { 3439 struct pciide_channel *cp; 3440 int i, compatchan, revision; 3441 pcireg_t interface; 3442 bus_size_t cmdsize, ctlsize; 3443 3444 if (pciide_chipen(sc, pa) == 0) 3445 return; 3446 revision = PCI_REVISION(pa->pa_class); 3447 printf(": Triones/Highpoint "); 3448 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3449 printf("HPT374 IDE Controller\n"); 3450 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3451 if (revision == HPT370_REV) 3452 printf("HPT370 IDE Controller\n"); 3453 else if (revision == HPT370A_REV) 3454 printf("HPT370A IDE Controller\n"); 3455 else if (revision == HPT366_REV) 3456 printf("HPT366 IDE Controller\n"); 3457 else 3458 printf("unknown HPT IDE controller rev %d\n", revision); 3459 } else 3460 printf("unknown HPT IDE controller 0x%x\n", 3461 sc->sc_pp->ide_product); 3462 3463 /* 3464 * when the chip is in native mode it identifies itself as a 3465 * 'misc mass storage'. Fake interface in this case. 3466 */ 3467 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3468 interface = PCI_INTERFACE(pa->pa_class); 3469 } else { 3470 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3471 PCIIDE_INTERFACE_PCI(0); 3472 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3473 (revision == HPT370_REV || revision == HPT370A_REV)) || 3474 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3475 interface |= PCIIDE_INTERFACE_PCI(1); 3476 } 3477 3478 printf("%s: bus-master DMA support present", 3479 sc->sc_wdcdev.sc_dev.dv_xname); 3480 pciide_mapreg_dma(sc, pa); 3481 printf("\n"); 3482 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3483 WDC_CAPABILITY_MODE; 3484 if (sc->sc_dma_ok) { 3485 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3486 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3487 sc->sc_wdcdev.irqack = pciide_irqack; 3488 } 3489 sc->sc_wdcdev.PIO_cap = 4; 3490 sc->sc_wdcdev.DMA_cap = 2; 3491 3492 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3493 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3494 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3495 revision == HPT366_REV) { 3496 sc->sc_wdcdev.UDMA_cap = 4; 3497 /* 3498 * The 366 has 2 PCI IDE functions, one for primary and one 3499 * for secondary. So we need to call pciide_mapregs_compat() 3500 * with the real channel 3501 */ 3502 if (pa->pa_function == 0) { 3503 compatchan = 0; 3504 } else if (pa->pa_function == 1) { 3505 compatchan = 1; 3506 } else { 3507 printf("%s: unexpected PCI function %d\n", 3508 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3509 return; 3510 } 3511 sc->sc_wdcdev.nchannels = 1; 3512 } else { 3513 sc->sc_wdcdev.nchannels = 2; 3514 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3515 sc->sc_wdcdev.UDMA_cap = 6; 3516 else 3517 sc->sc_wdcdev.UDMA_cap = 5; 3518 } 3519 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3520 cp = &sc->pciide_channels[i]; 3521 if (sc->sc_wdcdev.nchannels > 1) { 3522 compatchan = i; 3523 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3524 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3525 printf("%s: %s channel ignored (disabled)\n", 3526 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3527 continue; 3528 } 3529 } 3530 if (pciide_chansetup(sc, i, interface) == 0) 3531 continue; 3532 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3533 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3534 &ctlsize, hpt_pci_intr); 3535 } else { 3536 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3537 &cmdsize, &ctlsize); 3538 } 3539 if (cp->hw_ok == 0) 3540 return; 3541 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3542 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3543 wdcattach(&cp->wdc_channel); 3544 hpt_setup_channel(&cp->wdc_channel); 3545 } 3546 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3547 (revision == HPT370_REV || revision == HPT370A_REV)) || 3548 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3549 /* 3550 * HPT370_REV and highter has a bit to disable interrupts, 3551 * make sure to clear it 3552 */ 3553 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3554 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3555 ~HPT_CSEL_IRQDIS); 3556 } 3557 /* set clocks, etc (mandatory on 374, optional otherwise) */ 3558 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3559 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3560 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3561 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3562 return; 3563 } 3564 3565 void 3566 hpt_setup_channel(chp) 3567 struct channel_softc *chp; 3568 { 3569 struct ata_drive_datas *drvp; 3570 int drive; 3571 int cable; 3572 u_int32_t before, after; 3573 u_int32_t idedma_ctl; 3574 struct pciide_channel *cp = (struct pciide_channel*)chp; 3575 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3576 3577 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3578 3579 /* setup DMA if needed */ 3580 pciide_channel_dma_setup(cp); 3581 3582 idedma_ctl = 0; 3583 3584 /* Per drive settings */ 3585 for (drive = 0; drive < 2; drive++) { 3586 drvp = &chp->ch_drive[drive]; 3587 /* If no drive, skip */ 3588 if ((drvp->drive_flags & DRIVE) == 0) 3589 continue; 3590 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3591 HPT_IDETIM(chp->channel, drive)); 3592 3593 /* add timing values, setup DMA if needed */ 3594 if (drvp->drive_flags & DRIVE_UDMA) { 3595 /* use Ultra/DMA */ 3596 drvp->drive_flags &= ~DRIVE_DMA; 3597 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3598 drvp->UDMA_mode > 2) 3599 drvp->UDMA_mode = 2; 3600 after = (sc->sc_wdcdev.nchannels == 2) ? 3601 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3602 hpt374_udma[drvp->UDMA_mode] : 3603 hpt370_udma[drvp->UDMA_mode]) : 3604 hpt366_udma[drvp->UDMA_mode]; 3605 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3606 } else if (drvp->drive_flags & DRIVE_DMA) { 3607 /* 3608 * use Multiword DMA. 3609 * Timings will be used for both PIO and DMA, so adjust 3610 * DMA mode if needed 3611 */ 3612 if (drvp->PIO_mode >= 3 && 3613 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3614 drvp->DMA_mode = drvp->PIO_mode - 2; 3615 } 3616 after = (sc->sc_wdcdev.nchannels == 2) ? 3617 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3618 hpt374_dma[drvp->DMA_mode] : 3619 hpt370_dma[drvp->DMA_mode]) : 3620 hpt366_dma[drvp->DMA_mode]; 3621 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3622 } else { 3623 /* PIO only */ 3624 after = (sc->sc_wdcdev.nchannels == 2) ? 3625 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3626 hpt374_pio[drvp->PIO_mode] : 3627 hpt370_pio[drvp->PIO_mode]) : 3628 hpt366_pio[drvp->PIO_mode]; 3629 } 3630 pci_conf_write(sc->sc_pc, sc->sc_tag, 3631 HPT_IDETIM(chp->channel, drive), after); 3632 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3633 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3634 after, before), DEBUG_PROBE); 3635 } 3636 if (idedma_ctl != 0) { 3637 /* Add software bits in status register */ 3638 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3639 IDEDMA_CTL, idedma_ctl); 3640 } 3641 pciide_print_modes(cp); 3642 } 3643 3644 int 3645 hpt_pci_intr(arg) 3646 void *arg; 3647 { 3648 struct pciide_softc *sc = arg; 3649 struct pciide_channel *cp; 3650 struct channel_softc *wdc_cp; 3651 int rv = 0; 3652 int dmastat, i, crv; 3653 3654 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3655 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3656 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3657 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3658 IDEDMA_CTL_INTR) 3659 continue; 3660 cp = &sc->pciide_channels[i]; 3661 wdc_cp = &cp->wdc_channel; 3662 crv = wdcintr(wdc_cp); 3663 if (crv == 0) { 3664 printf("%s:%d: bogus intr\n", 3665 sc->sc_wdcdev.sc_dev.dv_xname, i); 3666 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3667 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3668 } else 3669 rv = 1; 3670 } 3671 return rv; 3672 } 3673 3674 3675 /* Macros to test product */ 3676 #define PDC_IS_262(sc) \ 3677 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3678 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3679 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3680 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3681 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3682 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3683 #define PDC_IS_265(sc) \ 3684 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3685 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3686 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3687 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3688 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3689 #define PDC_IS_268(sc) \ 3690 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3691 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3692 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3693 3694 void 3695 pdc202xx_chip_map(sc, pa) 3696 struct pciide_softc *sc; 3697 struct pci_attach_args *pa; 3698 { 3699 struct pciide_channel *cp; 3700 int channel; 3701 pcireg_t interface, st, mode; 3702 bus_size_t cmdsize, ctlsize; 3703 3704 if (!PDC_IS_268(sc)) { 3705 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3706 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3707 st), DEBUG_PROBE); 3708 } 3709 if (pciide_chipen(sc, pa) == 0) 3710 return; 3711 3712 /* turn off RAID mode */ 3713 if (!PDC_IS_268(sc)) 3714 st &= ~PDC2xx_STATE_IDERAID; 3715 3716 /* 3717 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3718 * mode. We have to fake interface 3719 */ 3720 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3721 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3722 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3723 3724 printf("%s: bus-master DMA support present", 3725 sc->sc_wdcdev.sc_dev.dv_xname); 3726 pciide_mapreg_dma(sc, pa); 3727 printf("\n"); 3728 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3729 WDC_CAPABILITY_MODE; 3730 if (sc->sc_dma_ok) { 3731 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3732 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3733 sc->sc_wdcdev.irqack = pciide_irqack; 3734 } 3735 sc->sc_wdcdev.PIO_cap = 4; 3736 sc->sc_wdcdev.DMA_cap = 2; 3737 if (PDC_IS_265(sc)) 3738 sc->sc_wdcdev.UDMA_cap = 5; 3739 else if (PDC_IS_262(sc)) 3740 sc->sc_wdcdev.UDMA_cap = 4; 3741 else 3742 sc->sc_wdcdev.UDMA_cap = 2; 3743 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3744 pdc20268_setup_channel : pdc202xx_setup_channel; 3745 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3746 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3747 3748 if (!PDC_IS_268(sc)) { 3749 /* setup failsafe defaults */ 3750 mode = 0; 3751 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3752 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3753 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3754 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3755 for (channel = 0; 3756 channel < sc->sc_wdcdev.nchannels; 3757 channel++) { 3758 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3759 "drive 0 initial timings 0x%x, now 0x%x\n", 3760 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3761 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3762 DEBUG_PROBE); 3763 pci_conf_write(sc->sc_pc, sc->sc_tag, 3764 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3765 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3766 "drive 1 initial timings 0x%x, now 0x%x\n", 3767 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3768 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3769 pci_conf_write(sc->sc_pc, sc->sc_tag, 3770 PDC2xx_TIM(channel, 1), mode); 3771 } 3772 3773 mode = PDC2xx_SCR_DMA; 3774 if (PDC_IS_262(sc)) { 3775 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3776 } else { 3777 /* the BIOS set it up this way */ 3778 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3779 } 3780 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3781 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3782 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3783 "now 0x%x\n", 3784 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3785 PDC2xx_SCR), 3786 mode), DEBUG_PROBE); 3787 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3788 PDC2xx_SCR, mode); 3789 3790 /* controller initial state register is OK even without BIOS */ 3791 /* Set DMA mode to IDE DMA compatibility */ 3792 mode = 3793 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3794 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3795 DEBUG_PROBE); 3796 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3797 mode | 0x1); 3798 mode = 3799 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3800 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3801 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3802 mode | 0x1); 3803 } 3804 3805 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3806 cp = &sc->pciide_channels[channel]; 3807 if (pciide_chansetup(sc, channel, interface) == 0) 3808 continue; 3809 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3810 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3811 printf("%s: %s channel ignored (disabled)\n", 3812 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3813 continue; 3814 } 3815 if (PDC_IS_265(sc)) 3816 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3817 pdc20265_pci_intr); 3818 else 3819 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3820 pdc202xx_pci_intr); 3821 if (cp->hw_ok == 0) 3822 continue; 3823 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3824 st &= ~(PDC_IS_262(sc) ? 3825 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3826 pciide_map_compat_intr(pa, cp, channel, interface); 3827 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3828 } 3829 if (!PDC_IS_268(sc)) { 3830 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3831 "0x%x\n", st), DEBUG_PROBE); 3832 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3833 } 3834 return; 3835 } 3836 3837 void 3838 pdc202xx_setup_channel(chp) 3839 struct channel_softc *chp; 3840 { 3841 struct ata_drive_datas *drvp; 3842 int drive; 3843 pcireg_t mode, st; 3844 u_int32_t idedma_ctl, scr, atapi; 3845 struct pciide_channel *cp = (struct pciide_channel*)chp; 3846 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3847 int channel = chp->channel; 3848 3849 /* setup DMA if needed */ 3850 pciide_channel_dma_setup(cp); 3851 3852 idedma_ctl = 0; 3853 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3854 sc->sc_wdcdev.sc_dev.dv_xname, 3855 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3856 DEBUG_PROBE); 3857 3858 /* Per channel settings */ 3859 if (PDC_IS_262(sc)) { 3860 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3861 PDC262_U66); 3862 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3863 /* Trim UDMA mode */ 3864 if ((st & PDC262_STATE_80P(channel)) != 0 || 3865 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3866 chp->ch_drive[0].UDMA_mode <= 2) || 3867 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3868 chp->ch_drive[1].UDMA_mode <= 2)) { 3869 if (chp->ch_drive[0].UDMA_mode > 2) 3870 chp->ch_drive[0].UDMA_mode = 2; 3871 if (chp->ch_drive[1].UDMA_mode > 2) 3872 chp->ch_drive[1].UDMA_mode = 2; 3873 } 3874 /* Set U66 if needed */ 3875 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3876 chp->ch_drive[0].UDMA_mode > 2) || 3877 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3878 chp->ch_drive[1].UDMA_mode > 2)) 3879 scr |= PDC262_U66_EN(channel); 3880 else 3881 scr &= ~PDC262_U66_EN(channel); 3882 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3883 PDC262_U66, scr); 3884 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3885 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3886 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3887 PDC262_ATAPI(channel))), DEBUG_PROBE); 3888 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3889 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3890 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3891 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3892 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3893 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3894 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3895 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3896 atapi = 0; 3897 else 3898 atapi = PDC262_ATAPI_UDMA; 3899 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3900 PDC262_ATAPI(channel), atapi); 3901 } 3902 } 3903 for (drive = 0; drive < 2; drive++) { 3904 drvp = &chp->ch_drive[drive]; 3905 /* If no drive, skip */ 3906 if ((drvp->drive_flags & DRIVE) == 0) 3907 continue; 3908 mode = 0; 3909 if (drvp->drive_flags & DRIVE_UDMA) { 3910 /* use Ultra/DMA */ 3911 drvp->drive_flags &= ~DRIVE_DMA; 3912 mode = PDC2xx_TIM_SET_MB(mode, 3913 pdc2xx_udma_mb[drvp->UDMA_mode]); 3914 mode = PDC2xx_TIM_SET_MC(mode, 3915 pdc2xx_udma_mc[drvp->UDMA_mode]); 3916 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3917 } else if (drvp->drive_flags & DRIVE_DMA) { 3918 mode = PDC2xx_TIM_SET_MB(mode, 3919 pdc2xx_dma_mb[drvp->DMA_mode]); 3920 mode = PDC2xx_TIM_SET_MC(mode, 3921 pdc2xx_dma_mc[drvp->DMA_mode]); 3922 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3923 } else { 3924 mode = PDC2xx_TIM_SET_MB(mode, 3925 pdc2xx_dma_mb[0]); 3926 mode = PDC2xx_TIM_SET_MC(mode, 3927 pdc2xx_dma_mc[0]); 3928 } 3929 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3930 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3931 if (drvp->drive_flags & DRIVE_ATA) 3932 mode |= PDC2xx_TIM_PRE; 3933 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3934 if (drvp->PIO_mode >= 3) { 3935 mode |= PDC2xx_TIM_IORDY; 3936 if (drive == 0) 3937 mode |= PDC2xx_TIM_IORDYp; 3938 } 3939 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3940 "timings 0x%x\n", 3941 sc->sc_wdcdev.sc_dev.dv_xname, 3942 chp->channel, drive, mode), DEBUG_PROBE); 3943 pci_conf_write(sc->sc_pc, sc->sc_tag, 3944 PDC2xx_TIM(chp->channel, drive), mode); 3945 } 3946 if (idedma_ctl != 0) { 3947 /* Add software bits in status register */ 3948 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3949 IDEDMA_CTL, idedma_ctl); 3950 } 3951 pciide_print_modes(cp); 3952 } 3953 3954 void 3955 pdc20268_setup_channel(chp) 3956 struct channel_softc *chp; 3957 { 3958 struct ata_drive_datas *drvp; 3959 int drive; 3960 u_int32_t idedma_ctl; 3961 struct pciide_channel *cp = (struct pciide_channel*)chp; 3962 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3963 int u100; 3964 3965 /* setup DMA if needed */ 3966 pciide_channel_dma_setup(cp); 3967 3968 idedma_ctl = 0; 3969 3970 /* I don't know what this is for, FreeBSD does it ... */ 3971 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3972 IDEDMA_CMD + 0x1, 0x0b); 3973 3974 /* 3975 * I don't know what this is for; FreeBSD checks this ... this is not 3976 * cable type detect. 3977 */ 3978 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3979 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3980 3981 for (drive = 0; drive < 2; drive++) { 3982 drvp = &chp->ch_drive[drive]; 3983 /* If no drive, skip */ 3984 if ((drvp->drive_flags & DRIVE) == 0) 3985 continue; 3986 if (drvp->drive_flags & DRIVE_UDMA) { 3987 /* use Ultra/DMA */ 3988 drvp->drive_flags &= ~DRIVE_DMA; 3989 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3990 if (drvp->UDMA_mode > 2 && u100 == 0) 3991 drvp->UDMA_mode = 2; 3992 } else if (drvp->drive_flags & DRIVE_DMA) { 3993 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3994 } 3995 } 3996 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3997 if (idedma_ctl != 0) { 3998 /* Add software bits in status register */ 3999 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4000 IDEDMA_CTL, idedma_ctl); 4001 } 4002 pciide_print_modes(cp); 4003 } 4004 4005 int 4006 pdc202xx_pci_intr(arg) 4007 void *arg; 4008 { 4009 struct pciide_softc *sc = arg; 4010 struct pciide_channel *cp; 4011 struct channel_softc *wdc_cp; 4012 int i, rv, crv; 4013 u_int32_t scr; 4014 4015 rv = 0; 4016 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4017 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4018 cp = &sc->pciide_channels[i]; 4019 wdc_cp = &cp->wdc_channel; 4020 /* If a compat channel skip. */ 4021 if (cp->compat) 4022 continue; 4023 if (scr & PDC2xx_SCR_INT(i)) { 4024 crv = wdcintr(wdc_cp); 4025 if (crv == 0) 4026 printf("%s:%d: bogus intr (reg 0x%x)\n", 4027 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4028 else 4029 rv = 1; 4030 } 4031 } 4032 return rv; 4033 } 4034 4035 int 4036 pdc20265_pci_intr(arg) 4037 void *arg; 4038 { 4039 struct pciide_softc *sc = arg; 4040 struct pciide_channel *cp; 4041 struct channel_softc *wdc_cp; 4042 int i, rv, crv; 4043 u_int32_t dmastat; 4044 4045 rv = 0; 4046 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4047 cp = &sc->pciide_channels[i]; 4048 wdc_cp = &cp->wdc_channel; 4049 /* If a compat channel skip. */ 4050 if (cp->compat) 4051 continue; 4052 /* 4053 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4054 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4055 * So use it instead (requires 2 reg reads instead of 1, 4056 * but we can't do it another way). 4057 */ 4058 dmastat = bus_space_read_1(sc->sc_dma_iot, 4059 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4060 if((dmastat & IDEDMA_CTL_INTR) == 0) 4061 continue; 4062 crv = wdcintr(wdc_cp); 4063 if (crv == 0) 4064 printf("%s:%d: bogus intr\n", 4065 sc->sc_wdcdev.sc_dev.dv_xname, i); 4066 else 4067 rv = 1; 4068 } 4069 return rv; 4070 } 4071 4072 void 4073 opti_chip_map(sc, pa) 4074 struct pciide_softc *sc; 4075 struct pci_attach_args *pa; 4076 { 4077 struct pciide_channel *cp; 4078 bus_size_t cmdsize, ctlsize; 4079 pcireg_t interface; 4080 u_int8_t init_ctrl; 4081 int channel; 4082 4083 if (pciide_chipen(sc, pa) == 0) 4084 return; 4085 printf("%s: bus-master DMA support present", 4086 sc->sc_wdcdev.sc_dev.dv_xname); 4087 4088 /* 4089 * XXXSCW: 4090 * There seem to be a couple of buggy revisions/implementations 4091 * of the OPTi pciide chipset. This kludge seems to fix one of 4092 * the reported problems (PR/11644) but still fails for the 4093 * other (PR/13151), although the latter may be due to other 4094 * issues too... 4095 */ 4096 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4097 printf(" but disabled due to chip rev. <= 0x12"); 4098 sc->sc_dma_ok = 0; 4099 } else 4100 pciide_mapreg_dma(sc, pa); 4101 4102 printf("\n"); 4103 4104 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4105 WDC_CAPABILITY_MODE; 4106 sc->sc_wdcdev.PIO_cap = 4; 4107 if (sc->sc_dma_ok) { 4108 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4109 sc->sc_wdcdev.irqack = pciide_irqack; 4110 sc->sc_wdcdev.DMA_cap = 2; 4111 } 4112 sc->sc_wdcdev.set_modes = opti_setup_channel; 4113 4114 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4115 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4116 4117 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4118 OPTI_REG_INIT_CONTROL); 4119 4120 interface = PCI_INTERFACE(pa->pa_class); 4121 4122 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4123 cp = &sc->pciide_channels[channel]; 4124 if (pciide_chansetup(sc, channel, interface) == 0) 4125 continue; 4126 if (channel == 1 && 4127 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4128 printf("%s: %s channel ignored (disabled)\n", 4129 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4130 continue; 4131 } 4132 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4133 pciide_pci_intr); 4134 if (cp->hw_ok == 0) 4135 continue; 4136 pciide_map_compat_intr(pa, cp, channel, interface); 4137 if (cp->hw_ok == 0) 4138 continue; 4139 opti_setup_channel(&cp->wdc_channel); 4140 } 4141 } 4142 4143 void 4144 opti_setup_channel(chp) 4145 struct channel_softc *chp; 4146 { 4147 struct ata_drive_datas *drvp; 4148 struct pciide_channel *cp = (struct pciide_channel*)chp; 4149 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4150 int drive, spd; 4151 int mode[2]; 4152 u_int8_t rv, mr; 4153 4154 /* 4155 * The `Delay' and `Address Setup Time' fields of the 4156 * Miscellaneous Register are always zero initially. 4157 */ 4158 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4159 mr &= ~(OPTI_MISC_DELAY_MASK | 4160 OPTI_MISC_ADDR_SETUP_MASK | 4161 OPTI_MISC_INDEX_MASK); 4162 4163 /* Prime the control register before setting timing values */ 4164 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4165 4166 /* Determine the clockrate of the PCIbus the chip is attached to */ 4167 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4168 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4169 4170 /* setup DMA if needed */ 4171 pciide_channel_dma_setup(cp); 4172 4173 for (drive = 0; drive < 2; drive++) { 4174 drvp = &chp->ch_drive[drive]; 4175 /* If no drive, skip */ 4176 if ((drvp->drive_flags & DRIVE) == 0) { 4177 mode[drive] = -1; 4178 continue; 4179 } 4180 4181 if ((drvp->drive_flags & DRIVE_DMA)) { 4182 /* 4183 * Timings will be used for both PIO and DMA, 4184 * so adjust DMA mode if needed 4185 */ 4186 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4187 drvp->PIO_mode = drvp->DMA_mode + 2; 4188 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4189 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4190 drvp->PIO_mode - 2 : 0; 4191 if (drvp->DMA_mode == 0) 4192 drvp->PIO_mode = 0; 4193 4194 mode[drive] = drvp->DMA_mode + 5; 4195 } else 4196 mode[drive] = drvp->PIO_mode; 4197 4198 if (drive && mode[0] >= 0 && 4199 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4200 /* 4201 * Can't have two drives using different values 4202 * for `Address Setup Time'. 4203 * Slow down the faster drive to compensate. 4204 */ 4205 int d = (opti_tim_as[spd][mode[0]] > 4206 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4207 4208 mode[d] = mode[1-d]; 4209 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4210 chp->ch_drive[d].DMA_mode = 0; 4211 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4212 } 4213 } 4214 4215 for (drive = 0; drive < 2; drive++) { 4216 int m; 4217 if ((m = mode[drive]) < 0) 4218 continue; 4219 4220 /* Set the Address Setup Time and select appropriate index */ 4221 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4222 rv |= OPTI_MISC_INDEX(drive); 4223 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4224 4225 /* Set the pulse width and recovery timing parameters */ 4226 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4227 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4228 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4229 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4230 4231 /* Set the Enhanced Mode register appropriately */ 4232 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4233 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4234 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4235 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4236 } 4237 4238 /* Finally, enable the timings */ 4239 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4240 4241 pciide_print_modes(cp); 4242 } 4243 4244 #define ACARD_IS_850(sc) \ 4245 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4246 4247 void 4248 acard_chip_map(sc, pa) 4249 struct pciide_softc *sc; 4250 struct pci_attach_args *pa; 4251 { 4252 struct pciide_channel *cp; 4253 int i; 4254 pcireg_t interface; 4255 bus_size_t cmdsize, ctlsize; 4256 4257 if (pciide_chipen(sc, pa) == 0) 4258 return; 4259 4260 /* 4261 * when the chip is in native mode it identifies itself as a 4262 * 'misc mass storage'. Fake interface in this case. 4263 */ 4264 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4265 interface = PCI_INTERFACE(pa->pa_class); 4266 } else { 4267 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4268 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4269 } 4270 4271 printf("%s: bus-master DMA support present", 4272 sc->sc_wdcdev.sc_dev.dv_xname); 4273 pciide_mapreg_dma(sc, pa); 4274 printf("\n"); 4275 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4276 WDC_CAPABILITY_MODE; 4277 4278 if (sc->sc_dma_ok) { 4279 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4280 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4281 sc->sc_wdcdev.irqack = pciide_irqack; 4282 } 4283 sc->sc_wdcdev.PIO_cap = 4; 4284 sc->sc_wdcdev.DMA_cap = 2; 4285 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4286 4287 sc->sc_wdcdev.set_modes = acard_setup_channel; 4288 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4289 sc->sc_wdcdev.nchannels = 2; 4290 4291 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4292 cp = &sc->pciide_channels[i]; 4293 if (pciide_chansetup(sc, i, interface) == 0) 4294 continue; 4295 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4296 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4297 &ctlsize, pciide_pci_intr); 4298 } else { 4299 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4300 &cmdsize, &ctlsize); 4301 } 4302 if (cp->hw_ok == 0) 4303 return; 4304 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4305 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4306 wdcattach(&cp->wdc_channel); 4307 acard_setup_channel(&cp->wdc_channel); 4308 } 4309 if (!ACARD_IS_850(sc)) { 4310 u_int32_t reg; 4311 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4312 reg &= ~ATP860_CTRL_INT; 4313 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4314 } 4315 } 4316 4317 void 4318 acard_setup_channel(chp) 4319 struct channel_softc *chp; 4320 { 4321 struct ata_drive_datas *drvp; 4322 struct pciide_channel *cp = (struct pciide_channel*)chp; 4323 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4324 int channel = chp->channel; 4325 int drive; 4326 u_int32_t idetime, udma_mode; 4327 u_int32_t idedma_ctl; 4328 4329 /* setup DMA if needed */ 4330 pciide_channel_dma_setup(cp); 4331 4332 if (ACARD_IS_850(sc)) { 4333 idetime = 0; 4334 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4335 udma_mode &= ~ATP850_UDMA_MASK(channel); 4336 } else { 4337 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4338 idetime &= ~ATP860_SETTIME_MASK(channel); 4339 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4340 udma_mode &= ~ATP860_UDMA_MASK(channel); 4341 4342 /* check 80 pins cable */ 4343 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4344 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4345 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4346 & ATP860_CTRL_80P(chp->channel)) { 4347 if (chp->ch_drive[0].UDMA_mode > 2) 4348 chp->ch_drive[0].UDMA_mode = 2; 4349 if (chp->ch_drive[1].UDMA_mode > 2) 4350 chp->ch_drive[1].UDMA_mode = 2; 4351 } 4352 } 4353 } 4354 4355 idedma_ctl = 0; 4356 4357 /* Per drive settings */ 4358 for (drive = 0; drive < 2; drive++) { 4359 drvp = &chp->ch_drive[drive]; 4360 /* If no drive, skip */ 4361 if ((drvp->drive_flags & DRIVE) == 0) 4362 continue; 4363 /* add timing values, setup DMA if needed */ 4364 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4365 (drvp->drive_flags & DRIVE_UDMA)) { 4366 /* use Ultra/DMA */ 4367 if (ACARD_IS_850(sc)) { 4368 idetime |= ATP850_SETTIME(drive, 4369 acard_act_udma[drvp->UDMA_mode], 4370 acard_rec_udma[drvp->UDMA_mode]); 4371 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4372 acard_udma_conf[drvp->UDMA_mode]); 4373 } else { 4374 idetime |= ATP860_SETTIME(channel, drive, 4375 acard_act_udma[drvp->UDMA_mode], 4376 acard_rec_udma[drvp->UDMA_mode]); 4377 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4378 acard_udma_conf[drvp->UDMA_mode]); 4379 } 4380 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4381 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4382 (drvp->drive_flags & DRIVE_DMA)) { 4383 /* use Multiword DMA */ 4384 drvp->drive_flags &= ~DRIVE_UDMA; 4385 if (ACARD_IS_850(sc)) { 4386 idetime |= ATP850_SETTIME(drive, 4387 acard_act_dma[drvp->DMA_mode], 4388 acard_rec_dma[drvp->DMA_mode]); 4389 } else { 4390 idetime |= ATP860_SETTIME(channel, drive, 4391 acard_act_dma[drvp->DMA_mode], 4392 acard_rec_dma[drvp->DMA_mode]); 4393 } 4394 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4395 } else { 4396 /* PIO only */ 4397 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4398 if (ACARD_IS_850(sc)) { 4399 idetime |= ATP850_SETTIME(drive, 4400 acard_act_pio[drvp->PIO_mode], 4401 acard_rec_pio[drvp->PIO_mode]); 4402 } else { 4403 idetime |= ATP860_SETTIME(channel, drive, 4404 acard_act_pio[drvp->PIO_mode], 4405 acard_rec_pio[drvp->PIO_mode]); 4406 } 4407 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4408 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4409 | ATP8x0_CTRL_EN(channel)); 4410 } 4411 } 4412 4413 if (idedma_ctl != 0) { 4414 /* Add software bits in status register */ 4415 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4416 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4417 } 4418 pciide_print_modes(cp); 4419 4420 if (ACARD_IS_850(sc)) { 4421 pci_conf_write(sc->sc_pc, sc->sc_tag, 4422 ATP850_IDETIME(channel), idetime); 4423 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4424 } else { 4425 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4426 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4427 } 4428 } 4429 4430 int 4431 acard_pci_intr(arg) 4432 void *arg; 4433 { 4434 struct pciide_softc *sc = arg; 4435 struct pciide_channel *cp; 4436 struct channel_softc *wdc_cp; 4437 int rv = 0; 4438 int dmastat, i, crv; 4439 4440 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4441 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4442 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4443 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4444 continue; 4445 cp = &sc->pciide_channels[i]; 4446 wdc_cp = &cp->wdc_channel; 4447 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4448 (void)wdcintr(wdc_cp); 4449 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4450 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4451 continue; 4452 } 4453 crv = wdcintr(wdc_cp); 4454 if (crv == 0) 4455 printf("%s:%d: bogus intr\n", 4456 sc->sc_wdcdev.sc_dev.dv_xname, i); 4457 else if (crv == 1) 4458 rv = 1; 4459 else if (rv == 0) 4460 rv = crv; 4461 } 4462 return rv; 4463 } 4464 4465 static int 4466 sl82c105_bugchk(struct pci_attach_args *pa) 4467 { 4468 4469 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4470 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4471 return (0); 4472 4473 if (PCI_REVISION(pa->pa_class) <= 0x05) 4474 return (1); 4475 4476 return (0); 4477 } 4478 4479 void 4480 sl82c105_chip_map(sc, pa) 4481 struct pciide_softc *sc; 4482 struct pci_attach_args *pa; 4483 { 4484 struct pciide_channel *cp; 4485 bus_size_t cmdsize, ctlsize; 4486 pcireg_t interface, idecr; 4487 int channel; 4488 4489 if (pciide_chipen(sc, pa) == 0) 4490 return; 4491 4492 printf("%s: bus-master DMA support present", 4493 sc->sc_wdcdev.sc_dev.dv_xname); 4494 4495 /* 4496 * Check to see if we're part of the Winbond 83c553 Southbridge. 4497 * If so, we need to disable DMA on rev. <= 5 of that chip. 4498 */ 4499 if (pci_find_device(pa, sl82c105_bugchk)) { 4500 printf(" but disabled due to 83c553 rev. <= 0x05"); 4501 sc->sc_dma_ok = 0; 4502 } else 4503 pciide_mapreg_dma(sc, pa); 4504 printf("\n"); 4505 4506 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4507 WDC_CAPABILITY_MODE; 4508 sc->sc_wdcdev.PIO_cap = 4; 4509 if (sc->sc_dma_ok) { 4510 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4511 sc->sc_wdcdev.irqack = pciide_irqack; 4512 sc->sc_wdcdev.DMA_cap = 2; 4513 } 4514 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4515 4516 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4517 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4518 4519 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4520 4521 interface = PCI_INTERFACE(pa->pa_class); 4522 4523 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4524 cp = &sc->pciide_channels[channel]; 4525 if (pciide_chansetup(sc, channel, interface) == 0) 4526 continue; 4527 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4528 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4529 printf("%s: %s channel ignored (disabled)\n", 4530 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4531 continue; 4532 } 4533 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4534 pciide_pci_intr); 4535 if (cp->hw_ok == 0) 4536 continue; 4537 pciide_map_compat_intr(pa, cp, channel, interface); 4538 if (cp->hw_ok == 0) 4539 continue; 4540 sl82c105_setup_channel(&cp->wdc_channel); 4541 } 4542 } 4543 4544 void 4545 sl82c105_setup_channel(chp) 4546 struct channel_softc *chp; 4547 { 4548 struct ata_drive_datas *drvp; 4549 struct pciide_channel *cp = (struct pciide_channel*)chp; 4550 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4551 int pxdx_reg, drive; 4552 pcireg_t pxdx; 4553 4554 /* Set up DMA if needed. */ 4555 pciide_channel_dma_setup(cp); 4556 4557 for (drive = 0; drive < 2; drive++) { 4558 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4559 : SYMPH_P1D0CR) + (drive * 4); 4560 4561 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4562 4563 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4564 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4565 4566 drvp = &chp->ch_drive[drive]; 4567 /* If no drive, skip. */ 4568 if ((drvp->drive_flags & DRIVE) == 0) { 4569 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4570 continue; 4571 } 4572 4573 if (drvp->drive_flags & DRIVE_DMA) { 4574 /* 4575 * Timings will be used for both PIO and DMA, 4576 * so adjust DMA mode if needed. 4577 */ 4578 if (drvp->PIO_mode >= 3) { 4579 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4580 drvp->DMA_mode = drvp->PIO_mode - 2; 4581 if (drvp->DMA_mode < 1) { 4582 /* 4583 * Can't mix both PIO and DMA. 4584 * Disable DMA. 4585 */ 4586 drvp->drive_flags &= ~DRIVE_DMA; 4587 } 4588 } else { 4589 /* 4590 * Can't mix both PIO and DMA. Disable 4591 * DMA. 4592 */ 4593 drvp->drive_flags &= ~DRIVE_DMA; 4594 } 4595 } 4596 4597 if (drvp->drive_flags & DRIVE_DMA) { 4598 /* Use multi-word DMA. */ 4599 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4600 PxDx_CMD_ON_SHIFT; 4601 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4602 } else { 4603 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4604 PxDx_CMD_ON_SHIFT; 4605 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4606 } 4607 4608 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4609 4610 /* ...and set the mode for this drive. */ 4611 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4612 } 4613 4614 pciide_print_modes(cp); 4615 } 4616 4617 void 4618 serverworks_chip_map(sc, pa) 4619 struct pciide_softc *sc; 4620 struct pci_attach_args *pa; 4621 { 4622 struct pciide_channel *cp; 4623 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4624 pcitag_t pcib_tag; 4625 int channel; 4626 bus_size_t cmdsize, ctlsize; 4627 4628 if (pciide_chipen(sc, pa) == 0) 4629 return; 4630 4631 printf("%s: bus-master DMA support present", 4632 sc->sc_wdcdev.sc_dev.dv_xname); 4633 pciide_mapreg_dma(sc, pa); 4634 printf("\n"); 4635 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4636 WDC_CAPABILITY_MODE; 4637 4638 if (sc->sc_dma_ok) { 4639 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4640 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4641 sc->sc_wdcdev.irqack = pciide_irqack; 4642 } 4643 sc->sc_wdcdev.PIO_cap = 4; 4644 sc->sc_wdcdev.DMA_cap = 2; 4645 switch (sc->sc_pp->ide_product) { 4646 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4647 sc->sc_wdcdev.UDMA_cap = 2; 4648 break; 4649 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4650 if (PCI_REVISION(pa->pa_class) < 0x92) 4651 sc->sc_wdcdev.UDMA_cap = 4; 4652 else 4653 sc->sc_wdcdev.UDMA_cap = 5; 4654 break; 4655 } 4656 4657 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4658 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4659 sc->sc_wdcdev.nchannels = 2; 4660 4661 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4662 cp = &sc->pciide_channels[channel]; 4663 if (pciide_chansetup(sc, channel, interface) == 0) 4664 continue; 4665 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4666 serverworks_pci_intr); 4667 if (cp->hw_ok == 0) 4668 return; 4669 pciide_map_compat_intr(pa, cp, channel, interface); 4670 if (cp->hw_ok == 0) 4671 return; 4672 serverworks_setup_channel(&cp->wdc_channel); 4673 } 4674 4675 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4676 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4677 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4678 } 4679 4680 void 4681 serverworks_setup_channel(chp) 4682 struct channel_softc *chp; 4683 { 4684 struct ata_drive_datas *drvp; 4685 struct pciide_channel *cp = (struct pciide_channel*)chp; 4686 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4687 int channel = chp->channel; 4688 int drive, unit; 4689 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4690 u_int32_t idedma_ctl; 4691 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4692 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4693 4694 /* setup DMA if needed */ 4695 pciide_channel_dma_setup(cp); 4696 4697 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4698 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4699 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4700 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4701 4702 pio_time &= ~(0xffff << (16 * channel)); 4703 dma_time &= ~(0xffff << (16 * channel)); 4704 pio_mode &= ~(0xff << (8 * channel + 16)); 4705 udma_mode &= ~(0xff << (8 * channel + 16)); 4706 udma_mode &= ~(3 << (2 * channel)); 4707 4708 idedma_ctl = 0; 4709 4710 /* Per drive settings */ 4711 for (drive = 0; drive < 2; drive++) { 4712 drvp = &chp->ch_drive[drive]; 4713 /* If no drive, skip */ 4714 if ((drvp->drive_flags & DRIVE) == 0) 4715 continue; 4716 unit = drive + 2 * channel; 4717 /* add timing values, setup DMA if needed */ 4718 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4719 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4720 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4721 (drvp->drive_flags & DRIVE_UDMA)) { 4722 /* use Ultra/DMA, check for 80-pin cable */ 4723 if (drvp->UDMA_mode > 2 && 4724 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4725 drvp->UDMA_mode = 2; 4726 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4727 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4728 udma_mode |= 1 << unit; 4729 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4730 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4731 (drvp->drive_flags & DRIVE_DMA)) { 4732 /* use Multiword DMA */ 4733 drvp->drive_flags &= ~DRIVE_UDMA; 4734 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4735 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4736 } else { 4737 /* PIO only */ 4738 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4739 } 4740 } 4741 4742 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4743 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4744 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4745 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4746 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4747 4748 if (idedma_ctl != 0) { 4749 /* Add software bits in status register */ 4750 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4751 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4752 } 4753 pciide_print_modes(cp); 4754 } 4755 4756 int 4757 serverworks_pci_intr(arg) 4758 void *arg; 4759 { 4760 struct pciide_softc *sc = arg; 4761 struct pciide_channel *cp; 4762 struct channel_softc *wdc_cp; 4763 int rv = 0; 4764 int dmastat, i, crv; 4765 4766 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4767 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4768 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4769 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4770 IDEDMA_CTL_INTR) 4771 continue; 4772 cp = &sc->pciide_channels[i]; 4773 wdc_cp = &cp->wdc_channel; 4774 crv = wdcintr(wdc_cp); 4775 if (crv == 0) { 4776 printf("%s:%d: bogus intr\n", 4777 sc->sc_wdcdev.sc_dev.dv_xname, i); 4778 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4779 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4780 } else 4781 rv = 1; 4782 } 4783 return rv; 4784 } 4785
Indexes created Thu Oct 02 10:09:58 GMT 2025