pciide.c revision 1.107.2.6
1 /* $NetBSD: pciide.c,v 1.107.2.6 2001/10/22 20:41:27 nathanw Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/pciide_acard_reg.h> 119 #include <dev/pci/cy82c693var.h> 120 121 #include "opt_pciide.h" 122 123 /* inlines for reading/writing 8-bit PCI registers */ 124 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 125 int)); 126 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 127 int, u_int8_t)); 128 129 static __inline u_int8_t 130 pciide_pci_read(pc, pa, reg) 131 pci_chipset_tag_t pc; 132 pcitag_t pa; 133 int reg; 134 { 135 136 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 137 ((reg & 0x03) * 8) & 0xff); 138 } 139 140 static __inline void 141 pciide_pci_write(pc, pa, reg, val) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 u_int8_t val; 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 156 157 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 void piix_setup_channel __P((struct channel_softc*)); 159 void piix3_4_setup_channel __P((struct channel_softc*)); 160 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 161 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 162 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 164 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void amd7x6_setup_channel __P((struct channel_softc*)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 void cmd646_9_irqack __P((struct channel_softc *)); 177 178 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cy693_setup_channel __P((struct channel_softc*)); 180 181 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void sis_setup_channel __P((struct channel_softc*)); 183 static int sis_hostbr_match __P(( struct pci_attach_args *)); 184 185 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void acer_setup_channel __P((struct channel_softc*)); 187 int acer_pci_intr __P((void *)); 188 static int acer_isabr_match __P(( struct pci_attach_args *)); 189 190 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void pdc202xx_setup_channel __P((struct channel_softc*)); 192 int pdc202xx_pci_intr __P((void *)); 193 int pdc20265_pci_intr __P((void *)); 194 195 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void opti_setup_channel __P((struct channel_softc*)); 197 198 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void hpt_setup_channel __P((struct channel_softc*)); 200 int hpt_pci_intr __P((void *)); 201 202 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void acard_setup_channel __P((struct channel_softc*)); 204 int acard_pci_intr __P((void *)); 205 206 #ifdef PCIIDE_WINBOND_ENABLE 207 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 #endif 209 210 void pciide_channel_dma_setup __P((struct pciide_channel *)); 211 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 212 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 213 void pciide_dma_start __P((void*, int, int)); 214 int pciide_dma_finish __P((void*, int, int, int)); 215 void pciide_irqack __P((struct channel_softc *)); 216 void pciide_print_modes __P((struct pciide_channel *)); 217 218 struct pciide_product_desc { 219 u_int32_t ide_product; 220 int ide_flags; 221 const char *ide_name; 222 /* map and setup chip, probe drives */ 223 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 224 }; 225 226 /* Flags for ide_flags */ 227 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 228 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 229 230 /* Default product description for devices not known from this controller */ 231 const struct pciide_product_desc default_product_desc = { 232 0, 233 0, 234 "Generic PCI IDE controller", 235 default_chip_map, 236 }; 237 238 const struct pciide_product_desc pciide_intel_products[] = { 239 { PCI_PRODUCT_INTEL_82092AA, 240 0, 241 "Intel 82092AA IDE controller", 242 default_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82371FB_IDE, 245 0, 246 "Intel 82371FB IDE controller (PIIX)", 247 piix_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_82371SB_IDE, 250 0, 251 "Intel 82371SB IDE Interface (PIIX3)", 252 piix_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82371AB_IDE, 255 0, 256 "Intel 82371AB IDE controller (PIIX4)", 257 piix_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82440MX_IDE, 260 0, 261 "Intel 82440MX IDE controller", 262 piix_chip_map 263 }, 264 { PCI_PRODUCT_INTEL_82801AA_IDE, 265 0, 266 "Intel 82801AA IDE Controller (ICH)", 267 piix_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82801AB_IDE, 270 0, 271 "Intel 82801AB IDE Controller (ICH0)", 272 piix_chip_map, 273 }, 274 { PCI_PRODUCT_INTEL_82801BA_IDE, 275 0, 276 "Intel 82801BA IDE Controller (ICH2)", 277 piix_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_82801BAM_IDE, 280 0, 281 "Intel 82801BAM IDE Controller (ICH2)", 282 piix_chip_map, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 const struct pciide_product_desc pciide_amd_products[] = { 292 { PCI_PRODUCT_AMD_PBC756_IDE, 293 0, 294 "Advanced Micro Devices AMD756 IDE Controller", 295 amd7x6_chip_map 296 }, 297 { PCI_PRODUCT_AMD_PBC766_IDE, 298 0, 299 "Advanced Micro Devices AMD766 IDE Controller", 300 amd7x6_chip_map 301 }, 302 { 0, 303 0, 304 NULL, 305 NULL 306 } 307 }; 308 309 const struct pciide_product_desc pciide_cmd_products[] = { 310 { PCI_PRODUCT_CMDTECH_640, 311 0, 312 "CMD Technology PCI0640", 313 cmd_chip_map 314 }, 315 { PCI_PRODUCT_CMDTECH_643, 316 0, 317 "CMD Technology PCI0643", 318 cmd0643_9_chip_map, 319 }, 320 { PCI_PRODUCT_CMDTECH_646, 321 0, 322 "CMD Technology PCI0646", 323 cmd0643_9_chip_map, 324 }, 325 { PCI_PRODUCT_CMDTECH_648, 326 IDE_PCI_CLASS_OVERRIDE, 327 "CMD Technology PCI0648", 328 cmd0643_9_chip_map, 329 }, 330 { PCI_PRODUCT_CMDTECH_649, 331 IDE_PCI_CLASS_OVERRIDE, 332 "CMD Technology PCI0649", 333 cmd0643_9_chip_map, 334 }, 335 { 0, 336 0, 337 NULL, 338 NULL 339 } 340 }; 341 342 const struct pciide_product_desc pciide_via_products[] = { 343 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 344 0, 345 NULL, 346 apollo_chip_map, 347 }, 348 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 349 0, 350 NULL, 351 apollo_chip_map, 352 }, 353 { 0, 354 0, 355 NULL, 356 NULL 357 } 358 }; 359 360 const struct pciide_product_desc pciide_cypress_products[] = { 361 { PCI_PRODUCT_CONTAQ_82C693, 362 IDE_16BIT_IOSPACE, 363 "Cypress 82C693 IDE Controller", 364 cy693_chip_map, 365 }, 366 { 0, 367 0, 368 NULL, 369 NULL 370 } 371 }; 372 373 const struct pciide_product_desc pciide_sis_products[] = { 374 { PCI_PRODUCT_SIS_5597_IDE, 375 0, 376 "Silicon Integrated System 5597/5598 IDE controller", 377 sis_chip_map, 378 }, 379 { 0, 380 0, 381 NULL, 382 NULL 383 } 384 }; 385 386 const struct pciide_product_desc pciide_acer_products[] = { 387 { PCI_PRODUCT_ALI_M5229, 388 0, 389 "Acer Labs M5229 UDMA IDE Controller", 390 acer_chip_map, 391 }, 392 { 0, 393 0, 394 NULL, 395 NULL 396 } 397 }; 398 399 const struct pciide_product_desc pciide_promise_products[] = { 400 { PCI_PRODUCT_PROMISE_ULTRA33, 401 IDE_PCI_CLASS_OVERRIDE, 402 "Promise Ultra33/ATA Bus Master IDE Accelerator", 403 pdc202xx_chip_map, 404 }, 405 { PCI_PRODUCT_PROMISE_ULTRA66, 406 IDE_PCI_CLASS_OVERRIDE, 407 "Promise Ultra66/ATA Bus Master IDE Accelerator", 408 pdc202xx_chip_map, 409 }, 410 { PCI_PRODUCT_PROMISE_ULTRA100, 411 IDE_PCI_CLASS_OVERRIDE, 412 "Promise Ultra100/ATA Bus Master IDE Accelerator", 413 pdc202xx_chip_map, 414 }, 415 { PCI_PRODUCT_PROMISE_ULTRA100X, 416 IDE_PCI_CLASS_OVERRIDE, 417 "Promise Ultra100/ATA Bus Master IDE Accelerator", 418 pdc202xx_chip_map, 419 }, 420 { 0, 421 0, 422 NULL, 423 NULL 424 } 425 }; 426 427 const struct pciide_product_desc pciide_opti_products[] = { 428 { PCI_PRODUCT_OPTI_82C621, 429 0, 430 "OPTi 82c621 PCI IDE controller", 431 opti_chip_map, 432 }, 433 { PCI_PRODUCT_OPTI_82C568, 434 0, 435 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 436 opti_chip_map, 437 }, 438 { PCI_PRODUCT_OPTI_82D568, 439 0, 440 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 441 opti_chip_map, 442 }, 443 { 0, 444 0, 445 NULL, 446 NULL 447 } 448 }; 449 450 const struct pciide_product_desc pciide_triones_products[] = { 451 { PCI_PRODUCT_TRIONES_HPT366, 452 IDE_PCI_CLASS_OVERRIDE, 453 NULL, 454 hpt_chip_map, 455 }, 456 { 0, 457 0, 458 NULL, 459 NULL 460 } 461 }; 462 463 const struct pciide_product_desc pciide_acard_products[] = { 464 { PCI_PRODUCT_ACARD_ATP850U, 465 IDE_PCI_CLASS_OVERRIDE, 466 "Acard ATP850U Ultra33 IDE Controller", 467 acard_chip_map, 468 }, 469 { PCI_PRODUCT_ACARD_ATP860, 470 IDE_PCI_CLASS_OVERRIDE, 471 "Acard ATP860 Ultra66 IDE Controller", 472 acard_chip_map, 473 }, 474 { PCI_PRODUCT_ACARD_ATP860A, 475 IDE_PCI_CLASS_OVERRIDE, 476 "Acard ATP860-A Ultra66 IDE Controller", 477 acard_chip_map, 478 }, 479 { 0, 480 0, 481 NULL, 482 NULL 483 } 484 }; 485 486 #ifdef PCIIDE_SERVERWORKS_ENABLE 487 const struct pciide_product_desc pciide_serverworks_products[] = { 488 { PCI_PRODUCT_SERVERWORKS_IDE, 489 0, 490 "ServerWorks ROSB4 IDE Controller", 491 piix_chip_map, 492 }, 493 { 0, 494 0, 495 NULL, 496 } 497 }; 498 #endif 499 500 #ifdef PCIIDE_WINBOND_ENABLE 501 const struct pciide_product_desc pciide_winbond_products[] = { 502 { PCI_PRODUCT_WINBOND_W83C553F_1, 503 0, 504 "Winbond W83C553F IDE controller", 505 winbond_chip_map, 506 }, 507 { 0, 508 0, 509 NULL, 510 } 511 }; 512 #endif 513 514 struct pciide_vendor_desc { 515 u_int32_t ide_vendor; 516 const struct pciide_product_desc *ide_products; 517 }; 518 519 const struct pciide_vendor_desc pciide_vendors[] = { 520 { PCI_VENDOR_INTEL, pciide_intel_products }, 521 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 522 { PCI_VENDOR_VIATECH, pciide_via_products }, 523 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 524 { PCI_VENDOR_SIS, pciide_sis_products }, 525 { PCI_VENDOR_ALI, pciide_acer_products }, 526 { PCI_VENDOR_PROMISE, pciide_promise_products }, 527 { PCI_VENDOR_AMD, pciide_amd_products }, 528 { PCI_VENDOR_OPTI, pciide_opti_products }, 529 { PCI_VENDOR_TRIONES, pciide_triones_products }, 530 { PCI_VENDOR_ACARD, pciide_acard_products }, 531 #ifdef PCIIDE_SERVERWORKS_ENABLE 532 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 533 #endif 534 #ifdef PCIIDE_WINBOND_ENABLE 535 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 536 #endif 537 { 0, NULL } 538 }; 539 540 /* options passed via the 'flags' config keyword */ 541 #define PCIIDE_OPTIONS_DMA 0x01 542 #define PCIIDE_OPTIONS_NODMA 0x02 543 544 int pciide_match __P((struct device *, struct cfdata *, void *)); 545 void pciide_attach __P((struct device *, struct device *, void *)); 546 547 struct cfattach pciide_ca = { 548 sizeof(struct pciide_softc), pciide_match, pciide_attach 549 }; 550 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 551 int pciide_mapregs_compat __P(( struct pci_attach_args *, 552 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 553 int pciide_mapregs_native __P((struct pci_attach_args *, 554 struct pciide_channel *, bus_size_t *, bus_size_t *, 555 int (*pci_intr) __P((void *)))); 556 void pciide_mapreg_dma __P((struct pciide_softc *, 557 struct pci_attach_args *)); 558 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 559 void pciide_mapchan __P((struct pci_attach_args *, 560 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 561 int (*pci_intr) __P((void *)))); 562 int pciide_chan_candisable __P((struct pciide_channel *)); 563 void pciide_map_compat_intr __P(( struct pci_attach_args *, 564 struct pciide_channel *, int, int)); 565 int pciide_compat_intr __P((void *)); 566 int pciide_pci_intr __P((void *)); 567 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 568 569 const struct pciide_product_desc * 570 pciide_lookup_product(id) 571 u_int32_t id; 572 { 573 const struct pciide_product_desc *pp; 574 const struct pciide_vendor_desc *vp; 575 576 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 577 if (PCI_VENDOR(id) == vp->ide_vendor) 578 break; 579 580 if ((pp = vp->ide_products) == NULL) 581 return NULL; 582 583 for (; pp->chip_map != NULL; pp++) 584 if (PCI_PRODUCT(id) == pp->ide_product) 585 break; 586 587 if (pp->chip_map == NULL) 588 return NULL; 589 return pp; 590 } 591 592 int 593 pciide_match(parent, match, aux) 594 struct device *parent; 595 struct cfdata *match; 596 void *aux; 597 { 598 struct pci_attach_args *pa = aux; 599 const struct pciide_product_desc *pp; 600 601 /* 602 * Check the ID register to see that it's a PCI IDE controller. 603 * If it is, we assume that we can deal with it; it _should_ 604 * work in a standardized way... 605 */ 606 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 607 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 608 return (1); 609 } 610 611 /* 612 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 613 * controllers. Let see if we can deal with it anyway. 614 */ 615 pp = pciide_lookup_product(pa->pa_id); 616 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 617 return (1); 618 } 619 620 return (0); 621 } 622 623 void 624 pciide_attach(parent, self, aux) 625 struct device *parent, *self; 626 void *aux; 627 { 628 struct pci_attach_args *pa = aux; 629 pci_chipset_tag_t pc = pa->pa_pc; 630 pcitag_t tag = pa->pa_tag; 631 struct pciide_softc *sc = (struct pciide_softc *)self; 632 pcireg_t csr; 633 char devinfo[256]; 634 const char *displaydev; 635 636 sc->sc_pp = pciide_lookup_product(pa->pa_id); 637 if (sc->sc_pp == NULL) { 638 sc->sc_pp = &default_product_desc; 639 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 640 displaydev = devinfo; 641 } else 642 displaydev = sc->sc_pp->ide_name; 643 644 /* if displaydev == NULL, printf is done in chip-specific map */ 645 if (displaydev) 646 printf(": %s (rev. 0x%02x)\n", displaydev, 647 PCI_REVISION(pa->pa_class)); 648 649 sc->sc_pc = pa->pa_pc; 650 sc->sc_tag = pa->pa_tag; 651 #ifdef WDCDEBUG 652 if (wdcdebug_pciide_mask & DEBUG_PROBE) 653 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 654 #endif 655 sc->sc_pp->chip_map(sc, pa); 656 657 if (sc->sc_dma_ok) { 658 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 659 csr |= PCI_COMMAND_MASTER_ENABLE; 660 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 661 } 662 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 663 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 664 } 665 666 /* tell wether the chip is enabled or not */ 667 int 668 pciide_chipen(sc, pa) 669 struct pciide_softc *sc; 670 struct pci_attach_args *pa; 671 { 672 pcireg_t csr; 673 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 674 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 675 PCI_COMMAND_STATUS_REG); 676 printf("%s: device disabled (at %s)\n", 677 sc->sc_wdcdev.sc_dev.dv_xname, 678 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 679 "device" : "bridge"); 680 return 0; 681 } 682 return 1; 683 } 684 685 int 686 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 687 struct pci_attach_args *pa; 688 struct pciide_channel *cp; 689 int compatchan; 690 bus_size_t *cmdsizep, *ctlsizep; 691 { 692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 693 struct channel_softc *wdc_cp = &cp->wdc_channel; 694 695 cp->compat = 1; 696 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 697 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 698 699 wdc_cp->cmd_iot = pa->pa_iot; 700 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 701 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 702 printf("%s: couldn't map %s channel cmd regs\n", 703 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 704 return (0); 705 } 706 707 wdc_cp->ctl_iot = pa->pa_iot; 708 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 709 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 710 printf("%s: couldn't map %s channel ctl regs\n", 711 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 712 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 713 PCIIDE_COMPAT_CMD_SIZE); 714 return (0); 715 } 716 717 return (1); 718 } 719 720 int 721 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 722 struct pci_attach_args * pa; 723 struct pciide_channel *cp; 724 bus_size_t *cmdsizep, *ctlsizep; 725 int (*pci_intr) __P((void *)); 726 { 727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 728 struct channel_softc *wdc_cp = &cp->wdc_channel; 729 const char *intrstr; 730 pci_intr_handle_t intrhandle; 731 732 cp->compat = 0; 733 734 if (sc->sc_pci_ih == NULL) { 735 if (pci_intr_map(pa, &intrhandle) != 0) { 736 printf("%s: couldn't map native-PCI interrupt\n", 737 sc->sc_wdcdev.sc_dev.dv_xname); 738 return 0; 739 } 740 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 741 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 742 intrhandle, IPL_BIO, pci_intr, sc); 743 if (sc->sc_pci_ih != NULL) { 744 printf("%s: using %s for native-PCI interrupt\n", 745 sc->sc_wdcdev.sc_dev.dv_xname, 746 intrstr ? intrstr : "unknown interrupt"); 747 } else { 748 printf("%s: couldn't establish native-PCI interrupt", 749 sc->sc_wdcdev.sc_dev.dv_xname); 750 if (intrstr != NULL) 751 printf(" at %s", intrstr); 752 printf("\n"); 753 return 0; 754 } 755 } 756 cp->ih = sc->sc_pci_ih; 757 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 758 PCI_MAPREG_TYPE_IO, 0, 759 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 760 printf("%s: couldn't map %s channel cmd regs\n", 761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 762 return 0; 763 } 764 765 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 766 PCI_MAPREG_TYPE_IO, 0, 767 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 768 printf("%s: couldn't map %s channel ctl regs\n", 769 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 770 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 771 return 0; 772 } 773 /* 774 * In native mode, 4 bytes of I/O space are mapped for the control 775 * register, the control register is at offset 2. Pass the generic 776 * code a handle for only one byte at the rigth offset. 777 */ 778 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 779 &wdc_cp->ctl_ioh) != 0) { 780 printf("%s: unable to subregion %s channel ctl regs\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 782 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 783 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 784 return 0; 785 } 786 return (1); 787 } 788 789 void 790 pciide_mapreg_dma(sc, pa) 791 struct pciide_softc *sc; 792 struct pci_attach_args *pa; 793 { 794 pcireg_t maptype; 795 bus_addr_t addr; 796 797 /* 798 * Map DMA registers 799 * 800 * Note that sc_dma_ok is the right variable to test to see if 801 * DMA can be done. If the interface doesn't support DMA, 802 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 803 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 804 * non-zero if the interface supports DMA and the registers 805 * could be mapped. 806 * 807 * XXX Note that despite the fact that the Bus Master IDE specs 808 * XXX say that "The bus master IDE function uses 16 bytes of IO 809 * XXX space," some controllers (at least the United 810 * XXX Microelectronics UM8886BF) place it in memory space. 811 */ 812 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 813 PCIIDE_REG_BUS_MASTER_DMA); 814 815 switch (maptype) { 816 case PCI_MAPREG_TYPE_IO: 817 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 818 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 819 &addr, NULL, NULL) == 0); 820 if (sc->sc_dma_ok == 0) { 821 printf(", but unused (couldn't query registers)"); 822 break; 823 } 824 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 825 && addr >= 0x10000) { 826 sc->sc_dma_ok = 0; 827 printf(", but unused (registers at unsafe address " 828 "%#lx)", (unsigned long)addr); 829 break; 830 } 831 /* FALLTHROUGH */ 832 833 case PCI_MAPREG_MEM_TYPE_32BIT: 834 sc->sc_dma_ok = (pci_mapreg_map(pa, 835 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 836 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 837 sc->sc_dmat = pa->pa_dmat; 838 if (sc->sc_dma_ok == 0) { 839 printf(", but unused (couldn't map registers)"); 840 } else { 841 sc->sc_wdcdev.dma_arg = sc; 842 sc->sc_wdcdev.dma_init = pciide_dma_init; 843 sc->sc_wdcdev.dma_start = pciide_dma_start; 844 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 845 } 846 847 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 848 PCIIDE_OPTIONS_NODMA) { 849 printf(", but unused (forced off by config file)"); 850 sc->sc_dma_ok = 0; 851 } 852 break; 853 854 default: 855 sc->sc_dma_ok = 0; 856 printf(", but unsupported register maptype (0x%x)", maptype); 857 } 858 } 859 860 int 861 pciide_compat_intr(arg) 862 void *arg; 863 { 864 struct pciide_channel *cp = arg; 865 866 #ifdef DIAGNOSTIC 867 /* should only be called for a compat channel */ 868 if (cp->compat == 0) 869 panic("pciide compat intr called for non-compat chan %p\n", cp); 870 #endif 871 return (wdcintr(&cp->wdc_channel)); 872 } 873 874 int 875 pciide_pci_intr(arg) 876 void *arg; 877 { 878 struct pciide_softc *sc = arg; 879 struct pciide_channel *cp; 880 struct channel_softc *wdc_cp; 881 int i, rv, crv; 882 883 rv = 0; 884 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 885 cp = &sc->pciide_channels[i]; 886 wdc_cp = &cp->wdc_channel; 887 888 /* If a compat channel skip. */ 889 if (cp->compat) 890 continue; 891 /* if this channel not waiting for intr, skip */ 892 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 893 continue; 894 895 crv = wdcintr(wdc_cp); 896 if (crv == 0) 897 ; /* leave rv alone */ 898 else if (crv == 1) 899 rv = 1; /* claim the intr */ 900 else if (rv == 0) /* crv should be -1 in this case */ 901 rv = crv; /* if we've done no better, take it */ 902 } 903 return (rv); 904 } 905 906 void 907 pciide_channel_dma_setup(cp) 908 struct pciide_channel *cp; 909 { 910 int drive; 911 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 912 struct ata_drive_datas *drvp; 913 914 for (drive = 0; drive < 2; drive++) { 915 drvp = &cp->wdc_channel.ch_drive[drive]; 916 /* If no drive, skip */ 917 if ((drvp->drive_flags & DRIVE) == 0) 918 continue; 919 /* setup DMA if needed */ 920 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 921 (drvp->drive_flags & DRIVE_UDMA) == 0) || 922 sc->sc_dma_ok == 0) { 923 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 924 continue; 925 } 926 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 927 != 0) { 928 /* Abort DMA setup */ 929 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 930 continue; 931 } 932 } 933 } 934 935 int 936 pciide_dma_table_setup(sc, channel, drive) 937 struct pciide_softc *sc; 938 int channel, drive; 939 { 940 bus_dma_segment_t seg; 941 int error, rseg; 942 const bus_size_t dma_table_size = 943 sizeof(struct idedma_table) * NIDEDMA_TABLES; 944 struct pciide_dma_maps *dma_maps = 945 &sc->pciide_channels[channel].dma_maps[drive]; 946 947 /* If table was already allocated, just return */ 948 if (dma_maps->dma_table) 949 return 0; 950 951 /* Allocate memory for the DMA tables and map it */ 952 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 953 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 954 BUS_DMA_NOWAIT)) != 0) { 955 printf("%s:%d: unable to allocate table DMA for " 956 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 957 channel, drive, error); 958 return error; 959 } 960 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 961 dma_table_size, 962 (caddr_t *)&dma_maps->dma_table, 963 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 964 printf("%s:%d: unable to map table DMA for" 965 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 966 channel, drive, error); 967 return error; 968 } 969 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 970 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 971 (unsigned long)seg.ds_addr), DEBUG_PROBE); 972 973 /* Create and load table DMA map for this disk */ 974 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 975 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 976 &dma_maps->dmamap_table)) != 0) { 977 printf("%s:%d: unable to create table DMA map for " 978 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 979 channel, drive, error); 980 return error; 981 } 982 if ((error = bus_dmamap_load(sc->sc_dmat, 983 dma_maps->dmamap_table, 984 dma_maps->dma_table, 985 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 986 printf("%s:%d: unable to load table DMA map for " 987 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 988 channel, drive, error); 989 return error; 990 } 991 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 992 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 993 DEBUG_PROBE); 994 /* Create a xfer DMA map for this drive */ 995 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 996 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 997 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 998 &dma_maps->dmamap_xfer)) != 0) { 999 printf("%s:%d: unable to create xfer DMA map for " 1000 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1001 channel, drive, error); 1002 return error; 1003 } 1004 return 0; 1005 } 1006 1007 int 1008 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1009 void *v; 1010 int channel, drive; 1011 void *databuf; 1012 size_t datalen; 1013 int flags; 1014 { 1015 struct pciide_softc *sc = v; 1016 int error, seg; 1017 struct pciide_dma_maps *dma_maps = 1018 &sc->pciide_channels[channel].dma_maps[drive]; 1019 1020 error = bus_dmamap_load(sc->sc_dmat, 1021 dma_maps->dmamap_xfer, 1022 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1023 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1024 if (error) { 1025 printf("%s:%d: unable to load xfer DMA map for" 1026 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1027 channel, drive, error); 1028 return error; 1029 } 1030 1031 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1032 dma_maps->dmamap_xfer->dm_mapsize, 1033 (flags & WDC_DMA_READ) ? 1034 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1035 1036 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1037 #ifdef DIAGNOSTIC 1038 /* A segment must not cross a 64k boundary */ 1039 { 1040 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1041 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1042 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1043 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1044 printf("pciide_dma: segment %d physical addr 0x%lx" 1045 " len 0x%lx not properly aligned\n", 1046 seg, phys, len); 1047 panic("pciide_dma: buf align"); 1048 } 1049 } 1050 #endif 1051 dma_maps->dma_table[seg].base_addr = 1052 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1053 dma_maps->dma_table[seg].byte_count = 1054 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1055 IDEDMA_BYTE_COUNT_MASK); 1056 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1057 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1058 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1059 1060 } 1061 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1062 htole32(IDEDMA_BYTE_COUNT_EOT); 1063 1064 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1065 dma_maps->dmamap_table->dm_mapsize, 1066 BUS_DMASYNC_PREWRITE); 1067 1068 /* Maps are ready. Start DMA function */ 1069 #ifdef DIAGNOSTIC 1070 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1071 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1072 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1073 panic("pciide_dma_init: table align"); 1074 } 1075 #endif 1076 1077 /* Clear status bits */ 1078 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1079 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1080 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1081 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1082 /* Write table addr */ 1083 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1084 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1085 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1086 /* set read/write */ 1087 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1088 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1089 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1090 /* remember flags */ 1091 dma_maps->dma_flags = flags; 1092 return 0; 1093 } 1094 1095 void 1096 pciide_dma_start(v, channel, drive) 1097 void *v; 1098 int channel, drive; 1099 { 1100 struct pciide_softc *sc = v; 1101 1102 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1103 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1104 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1105 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1106 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1107 } 1108 1109 int 1110 pciide_dma_finish(v, channel, drive, force) 1111 void *v; 1112 int channel, drive; 1113 int force; 1114 { 1115 struct pciide_softc *sc = v; 1116 u_int8_t status; 1117 int error = 0; 1118 struct pciide_dma_maps *dma_maps = 1119 &sc->pciide_channels[channel].dma_maps[drive]; 1120 1121 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1122 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1123 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1124 DEBUG_XFERS); 1125 1126 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1127 return WDC_DMAST_NOIRQ; 1128 1129 /* stop DMA channel */ 1130 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1131 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1132 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1133 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1134 1135 /* Unload the map of the data buffer */ 1136 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1137 dma_maps->dmamap_xfer->dm_mapsize, 1138 (dma_maps->dma_flags & WDC_DMA_READ) ? 1139 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1140 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1141 1142 if ((status & IDEDMA_CTL_ERR) != 0) { 1143 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1144 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1145 error |= WDC_DMAST_ERR; 1146 } 1147 1148 if ((status & IDEDMA_CTL_INTR) == 0) { 1149 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1150 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1151 drive, status); 1152 error |= WDC_DMAST_NOIRQ; 1153 } 1154 1155 if ((status & IDEDMA_CTL_ACT) != 0) { 1156 /* data underrun, may be a valid condition for ATAPI */ 1157 error |= WDC_DMAST_UNDER; 1158 } 1159 return error; 1160 } 1161 1162 void 1163 pciide_irqack(chp) 1164 struct channel_softc *chp; 1165 { 1166 struct pciide_channel *cp = (struct pciide_channel*)chp; 1167 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1168 1169 /* clear status bits in IDE DMA registers */ 1170 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1171 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1172 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1173 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1174 } 1175 1176 /* some common code used by several chip_map */ 1177 int 1178 pciide_chansetup(sc, channel, interface) 1179 struct pciide_softc *sc; 1180 int channel; 1181 pcireg_t interface; 1182 { 1183 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1184 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1185 cp->name = PCIIDE_CHANNEL_NAME(channel); 1186 cp->wdc_channel.channel = channel; 1187 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1188 cp->wdc_channel.ch_queue = 1189 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1190 if (cp->wdc_channel.ch_queue == NULL) { 1191 printf("%s %s channel: " 1192 "can't allocate memory for command queue", 1193 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1194 return 0; 1195 } 1196 printf("%s: %s channel %s to %s mode\n", 1197 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1198 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1199 "configured" : "wired", 1200 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1201 "native-PCI" : "compatibility"); 1202 return 1; 1203 } 1204 1205 /* some common code used by several chip channel_map */ 1206 void 1207 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1208 struct pci_attach_args *pa; 1209 struct pciide_channel *cp; 1210 pcireg_t interface; 1211 bus_size_t *cmdsizep, *ctlsizep; 1212 int (*pci_intr) __P((void *)); 1213 { 1214 struct channel_softc *wdc_cp = &cp->wdc_channel; 1215 1216 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1217 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1218 pci_intr); 1219 else 1220 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1221 wdc_cp->channel, cmdsizep, ctlsizep); 1222 1223 if (cp->hw_ok == 0) 1224 return; 1225 wdc_cp->data32iot = wdc_cp->cmd_iot; 1226 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1227 wdcattach(wdc_cp); 1228 } 1229 1230 /* 1231 * Generic code to call to know if a channel can be disabled. Return 1 1232 * if channel can be disabled, 0 if not 1233 */ 1234 int 1235 pciide_chan_candisable(cp) 1236 struct pciide_channel *cp; 1237 { 1238 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1239 struct channel_softc *wdc_cp = &cp->wdc_channel; 1240 1241 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1242 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1243 printf("%s: disabling %s channel (no drives)\n", 1244 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1245 cp->hw_ok = 0; 1246 return 1; 1247 } 1248 return 0; 1249 } 1250 1251 /* 1252 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1253 * Set hw_ok=0 on failure 1254 */ 1255 void 1256 pciide_map_compat_intr(pa, cp, compatchan, interface) 1257 struct pci_attach_args *pa; 1258 struct pciide_channel *cp; 1259 int compatchan, interface; 1260 { 1261 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1262 struct channel_softc *wdc_cp = &cp->wdc_channel; 1263 1264 if (cp->hw_ok == 0) 1265 return; 1266 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1267 return; 1268 1269 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1270 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1271 pa, compatchan, pciide_compat_intr, cp); 1272 if (cp->ih == NULL) { 1273 #endif 1274 printf("%s: no compatibility interrupt for use by %s " 1275 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1276 cp->hw_ok = 0; 1277 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1278 } 1279 #endif 1280 } 1281 1282 void 1283 pciide_print_modes(cp) 1284 struct pciide_channel *cp; 1285 { 1286 wdc_print_modes(&cp->wdc_channel); 1287 } 1288 1289 void 1290 default_chip_map(sc, pa) 1291 struct pciide_softc *sc; 1292 struct pci_attach_args *pa; 1293 { 1294 struct pciide_channel *cp; 1295 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1296 pcireg_t csr; 1297 int channel, drive; 1298 struct ata_drive_datas *drvp; 1299 u_int8_t idedma_ctl; 1300 bus_size_t cmdsize, ctlsize; 1301 char *failreason; 1302 1303 if (pciide_chipen(sc, pa) == 0) 1304 return; 1305 1306 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1307 printf("%s: bus-master DMA support present", 1308 sc->sc_wdcdev.sc_dev.dv_xname); 1309 if (sc->sc_pp == &default_product_desc && 1310 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1311 PCIIDE_OPTIONS_DMA) == 0) { 1312 printf(", but unused (no driver support)"); 1313 sc->sc_dma_ok = 0; 1314 } else { 1315 pciide_mapreg_dma(sc, pa); 1316 if (sc->sc_dma_ok != 0) 1317 printf(", used without full driver " 1318 "support"); 1319 } 1320 } else { 1321 printf("%s: hardware does not support DMA", 1322 sc->sc_wdcdev.sc_dev.dv_xname); 1323 sc->sc_dma_ok = 0; 1324 } 1325 printf("\n"); 1326 if (sc->sc_dma_ok) { 1327 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1328 sc->sc_wdcdev.irqack = pciide_irqack; 1329 } 1330 sc->sc_wdcdev.PIO_cap = 0; 1331 sc->sc_wdcdev.DMA_cap = 0; 1332 1333 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1334 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1335 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1336 1337 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1338 cp = &sc->pciide_channels[channel]; 1339 if (pciide_chansetup(sc, channel, interface) == 0) 1340 continue; 1341 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1342 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1343 &ctlsize, pciide_pci_intr); 1344 } else { 1345 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1346 channel, &cmdsize, &ctlsize); 1347 } 1348 if (cp->hw_ok == 0) 1349 continue; 1350 /* 1351 * Check to see if something appears to be there. 1352 */ 1353 failreason = NULL; 1354 if (!wdcprobe(&cp->wdc_channel)) { 1355 failreason = "not responding; disabled or no drives?"; 1356 goto next; 1357 } 1358 /* 1359 * Now, make sure it's actually attributable to this PCI IDE 1360 * channel by trying to access the channel again while the 1361 * PCI IDE controller's I/O space is disabled. (If the 1362 * channel no longer appears to be there, it belongs to 1363 * this controller.) YUCK! 1364 */ 1365 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1366 PCI_COMMAND_STATUS_REG); 1367 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1368 csr & ~PCI_COMMAND_IO_ENABLE); 1369 if (wdcprobe(&cp->wdc_channel)) 1370 failreason = "other hardware responding at addresses"; 1371 pci_conf_write(sc->sc_pc, sc->sc_tag, 1372 PCI_COMMAND_STATUS_REG, csr); 1373 next: 1374 if (failreason) { 1375 printf("%s: %s channel ignored (%s)\n", 1376 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1377 failreason); 1378 cp->hw_ok = 0; 1379 bus_space_unmap(cp->wdc_channel.cmd_iot, 1380 cp->wdc_channel.cmd_ioh, cmdsize); 1381 bus_space_unmap(cp->wdc_channel.ctl_iot, 1382 cp->wdc_channel.ctl_ioh, ctlsize); 1383 } else { 1384 pciide_map_compat_intr(pa, cp, channel, interface); 1385 } 1386 if (cp->hw_ok) { 1387 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1388 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1389 wdcattach(&cp->wdc_channel); 1390 } 1391 } 1392 1393 if (sc->sc_dma_ok == 0) 1394 return; 1395 1396 /* Allocate DMA maps */ 1397 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1398 idedma_ctl = 0; 1399 cp = &sc->pciide_channels[channel]; 1400 for (drive = 0; drive < 2; drive++) { 1401 drvp = &cp->wdc_channel.ch_drive[drive]; 1402 /* If no drive, skip */ 1403 if ((drvp->drive_flags & DRIVE) == 0) 1404 continue; 1405 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1406 continue; 1407 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1408 /* Abort DMA setup */ 1409 printf("%s:%d:%d: can't allocate DMA maps, " 1410 "using PIO transfers\n", 1411 sc->sc_wdcdev.sc_dev.dv_xname, 1412 channel, drive); 1413 drvp->drive_flags &= ~DRIVE_DMA; 1414 } 1415 printf("%s:%d:%d: using DMA data transfers\n", 1416 sc->sc_wdcdev.sc_dev.dv_xname, 1417 channel, drive); 1418 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1419 } 1420 if (idedma_ctl != 0) { 1421 /* Add software bits in status register */ 1422 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1423 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1424 idedma_ctl); 1425 } 1426 } 1427 } 1428 1429 void 1430 piix_chip_map(sc, pa) 1431 struct pciide_softc *sc; 1432 struct pci_attach_args *pa; 1433 { 1434 struct pciide_channel *cp; 1435 int channel; 1436 u_int32_t idetim; 1437 bus_size_t cmdsize, ctlsize; 1438 1439 if (pciide_chipen(sc, pa) == 0) 1440 return; 1441 1442 printf("%s: bus-master DMA support present", 1443 sc->sc_wdcdev.sc_dev.dv_xname); 1444 pciide_mapreg_dma(sc, pa); 1445 printf("\n"); 1446 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1447 WDC_CAPABILITY_MODE; 1448 if (sc->sc_dma_ok) { 1449 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1450 sc->sc_wdcdev.irqack = pciide_irqack; 1451 switch(sc->sc_pp->ide_product) { 1452 case PCI_PRODUCT_INTEL_82371AB_IDE: 1453 case PCI_PRODUCT_INTEL_82440MX_IDE: 1454 case PCI_PRODUCT_INTEL_82801AA_IDE: 1455 case PCI_PRODUCT_INTEL_82801AB_IDE: 1456 case PCI_PRODUCT_INTEL_82801BA_IDE: 1457 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1458 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1459 } 1460 } 1461 sc->sc_wdcdev.PIO_cap = 4; 1462 sc->sc_wdcdev.DMA_cap = 2; 1463 switch(sc->sc_pp->ide_product) { 1464 case PCI_PRODUCT_INTEL_82801AA_IDE: 1465 sc->sc_wdcdev.UDMA_cap = 4; 1466 break; 1467 case PCI_PRODUCT_INTEL_82801BA_IDE: 1468 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1469 sc->sc_wdcdev.UDMA_cap = 5; 1470 break; 1471 default: 1472 sc->sc_wdcdev.UDMA_cap = 2; 1473 } 1474 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1475 sc->sc_wdcdev.set_modes = piix_setup_channel; 1476 else 1477 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1478 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1479 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1480 1481 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1482 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1483 DEBUG_PROBE); 1484 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1485 WDCDEBUG_PRINT((", sidetim=0x%x", 1486 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1487 DEBUG_PROBE); 1488 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1489 WDCDEBUG_PRINT((", udamreg 0x%x", 1490 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1491 DEBUG_PROBE); 1492 } 1493 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1494 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1495 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1496 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1497 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1498 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1499 DEBUG_PROBE); 1500 } 1501 1502 } 1503 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1504 1505 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1506 cp = &sc->pciide_channels[channel]; 1507 /* PIIX is compat-only */ 1508 if (pciide_chansetup(sc, channel, 0) == 0) 1509 continue; 1510 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1511 if ((PIIX_IDETIM_READ(idetim, channel) & 1512 PIIX_IDETIM_IDE) == 0) { 1513 printf("%s: %s channel ignored (disabled)\n", 1514 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1515 continue; 1516 } 1517 /* PIIX are compat-only pciide devices */ 1518 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1519 if (cp->hw_ok == 0) 1520 continue; 1521 if (pciide_chan_candisable(cp)) { 1522 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1523 channel); 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1525 idetim); 1526 } 1527 pciide_map_compat_intr(pa, cp, channel, 0); 1528 if (cp->hw_ok == 0) 1529 continue; 1530 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1531 } 1532 1533 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1534 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1535 DEBUG_PROBE); 1536 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1537 WDCDEBUG_PRINT((", sidetim=0x%x", 1538 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1539 DEBUG_PROBE); 1540 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1541 WDCDEBUG_PRINT((", udamreg 0x%x", 1542 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1543 DEBUG_PROBE); 1544 } 1545 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1549 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1550 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1551 DEBUG_PROBE); 1552 } 1553 } 1554 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1555 } 1556 1557 void 1558 piix_setup_channel(chp) 1559 struct channel_softc *chp; 1560 { 1561 u_int8_t mode[2], drive; 1562 u_int32_t oidetim, idetim, idedma_ctl; 1563 struct pciide_channel *cp = (struct pciide_channel*)chp; 1564 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1565 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1566 1567 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1568 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1569 idedma_ctl = 0; 1570 1571 /* set up new idetim: Enable IDE registers decode */ 1572 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1573 chp->channel); 1574 1575 /* setup DMA */ 1576 pciide_channel_dma_setup(cp); 1577 1578 /* 1579 * Here we have to mess up with drives mode: PIIX can't have 1580 * different timings for master and slave drives. 1581 * We need to find the best combination. 1582 */ 1583 1584 /* If both drives supports DMA, take the lower mode */ 1585 if ((drvp[0].drive_flags & DRIVE_DMA) && 1586 (drvp[1].drive_flags & DRIVE_DMA)) { 1587 mode[0] = mode[1] = 1588 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1589 drvp[0].DMA_mode = mode[0]; 1590 drvp[1].DMA_mode = mode[1]; 1591 goto ok; 1592 } 1593 /* 1594 * If only one drive supports DMA, use its mode, and 1595 * put the other one in PIO mode 0 if mode not compatible 1596 */ 1597 if (drvp[0].drive_flags & DRIVE_DMA) { 1598 mode[0] = drvp[0].DMA_mode; 1599 mode[1] = drvp[1].PIO_mode; 1600 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1601 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1602 mode[1] = drvp[1].PIO_mode = 0; 1603 goto ok; 1604 } 1605 if (drvp[1].drive_flags & DRIVE_DMA) { 1606 mode[1] = drvp[1].DMA_mode; 1607 mode[0] = drvp[0].PIO_mode; 1608 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1609 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1610 mode[0] = drvp[0].PIO_mode = 0; 1611 goto ok; 1612 } 1613 /* 1614 * If both drives are not DMA, takes the lower mode, unless 1615 * one of them is PIO mode < 2 1616 */ 1617 if (drvp[0].PIO_mode < 2) { 1618 mode[0] = drvp[0].PIO_mode = 0; 1619 mode[1] = drvp[1].PIO_mode; 1620 } else if (drvp[1].PIO_mode < 2) { 1621 mode[1] = drvp[1].PIO_mode = 0; 1622 mode[0] = drvp[0].PIO_mode; 1623 } else { 1624 mode[0] = mode[1] = 1625 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1626 drvp[0].PIO_mode = mode[0]; 1627 drvp[1].PIO_mode = mode[1]; 1628 } 1629 ok: /* The modes are setup */ 1630 for (drive = 0; drive < 2; drive++) { 1631 if (drvp[drive].drive_flags & DRIVE_DMA) { 1632 idetim |= piix_setup_idetim_timings( 1633 mode[drive], 1, chp->channel); 1634 goto end; 1635 } 1636 } 1637 /* If we are there, none of the drives are DMA */ 1638 if (mode[0] >= 2) 1639 idetim |= piix_setup_idetim_timings( 1640 mode[0], 0, chp->channel); 1641 else 1642 idetim |= piix_setup_idetim_timings( 1643 mode[1], 0, chp->channel); 1644 end: /* 1645 * timing mode is now set up in the controller. Enable 1646 * it per-drive 1647 */ 1648 for (drive = 0; drive < 2; drive++) { 1649 /* If no drive, skip */ 1650 if ((drvp[drive].drive_flags & DRIVE) == 0) 1651 continue; 1652 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1653 if (drvp[drive].drive_flags & DRIVE_DMA) 1654 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1655 } 1656 if (idedma_ctl != 0) { 1657 /* Add software bits in status register */ 1658 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1659 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1660 idedma_ctl); 1661 } 1662 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1663 pciide_print_modes(cp); 1664 } 1665 1666 void 1667 piix3_4_setup_channel(chp) 1668 struct channel_softc *chp; 1669 { 1670 struct ata_drive_datas *drvp; 1671 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1672 struct pciide_channel *cp = (struct pciide_channel*)chp; 1673 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1674 int drive; 1675 int channel = chp->channel; 1676 1677 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1678 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1679 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1680 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1681 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1682 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1683 PIIX_SIDETIM_RTC_MASK(channel)); 1684 1685 idedma_ctl = 0; 1686 /* If channel disabled, no need to go further */ 1687 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1688 return; 1689 /* set up new idetim: Enable IDE registers decode */ 1690 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1691 1692 /* setup DMA if needed */ 1693 pciide_channel_dma_setup(cp); 1694 1695 for (drive = 0; drive < 2; drive++) { 1696 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1697 PIIX_UDMATIM_SET(0x3, channel, drive)); 1698 drvp = &chp->ch_drive[drive]; 1699 /* If no drive, skip */ 1700 if ((drvp->drive_flags & DRIVE) == 0) 1701 continue; 1702 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1703 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1704 goto pio; 1705 1706 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1707 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1708 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1709 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1710 ideconf |= PIIX_CONFIG_PINGPONG; 1711 } 1712 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1713 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1714 /* setup Ultra/100 */ 1715 if (drvp->UDMA_mode > 2 && 1716 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1717 drvp->UDMA_mode = 2; 1718 if (drvp->UDMA_mode > 4) { 1719 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1720 } else { 1721 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1722 if (drvp->UDMA_mode > 2) { 1723 ideconf |= PIIX_CONFIG_UDMA66(channel, 1724 drive); 1725 } else { 1726 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1727 drive); 1728 } 1729 } 1730 } 1731 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1732 /* setup Ultra/66 */ 1733 if (drvp->UDMA_mode > 2 && 1734 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1735 drvp->UDMA_mode = 2; 1736 if (drvp->UDMA_mode > 2) 1737 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1738 else 1739 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1740 } 1741 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1742 (drvp->drive_flags & DRIVE_UDMA)) { 1743 /* use Ultra/DMA */ 1744 drvp->drive_flags &= ~DRIVE_DMA; 1745 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1746 udmareg |= PIIX_UDMATIM_SET( 1747 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1748 } else { 1749 /* use Multiword DMA */ 1750 drvp->drive_flags &= ~DRIVE_UDMA; 1751 if (drive == 0) { 1752 idetim |= piix_setup_idetim_timings( 1753 drvp->DMA_mode, 1, channel); 1754 } else { 1755 sidetim |= piix_setup_sidetim_timings( 1756 drvp->DMA_mode, 1, channel); 1757 idetim =PIIX_IDETIM_SET(idetim, 1758 PIIX_IDETIM_SITRE, channel); 1759 } 1760 } 1761 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1762 1763 pio: /* use PIO mode */ 1764 idetim |= piix_setup_idetim_drvs(drvp); 1765 if (drive == 0) { 1766 idetim |= piix_setup_idetim_timings( 1767 drvp->PIO_mode, 0, channel); 1768 } else { 1769 sidetim |= piix_setup_sidetim_timings( 1770 drvp->PIO_mode, 0, channel); 1771 idetim =PIIX_IDETIM_SET(idetim, 1772 PIIX_IDETIM_SITRE, channel); 1773 } 1774 } 1775 if (idedma_ctl != 0) { 1776 /* Add software bits in status register */ 1777 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1778 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1779 idedma_ctl); 1780 } 1781 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1782 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1783 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1784 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1785 pciide_print_modes(cp); 1786 } 1787 1788 1789 /* setup ISP and RTC fields, based on mode */ 1790 static u_int32_t 1791 piix_setup_idetim_timings(mode, dma, channel) 1792 u_int8_t mode; 1793 u_int8_t dma; 1794 u_int8_t channel; 1795 { 1796 1797 if (dma) 1798 return PIIX_IDETIM_SET(0, 1799 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1800 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1801 channel); 1802 else 1803 return PIIX_IDETIM_SET(0, 1804 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1805 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1806 channel); 1807 } 1808 1809 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1810 static u_int32_t 1811 piix_setup_idetim_drvs(drvp) 1812 struct ata_drive_datas *drvp; 1813 { 1814 u_int32_t ret = 0; 1815 struct channel_softc *chp = drvp->chnl_softc; 1816 u_int8_t channel = chp->channel; 1817 u_int8_t drive = drvp->drive; 1818 1819 /* 1820 * If drive is using UDMA, timings setups are independant 1821 * So just check DMA and PIO here. 1822 */ 1823 if (drvp->drive_flags & DRIVE_DMA) { 1824 /* if mode = DMA mode 0, use compatible timings */ 1825 if ((drvp->drive_flags & DRIVE_DMA) && 1826 drvp->DMA_mode == 0) { 1827 drvp->PIO_mode = 0; 1828 return ret; 1829 } 1830 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1831 /* 1832 * PIO and DMA timings are the same, use fast timings for PIO 1833 * too, else use compat timings. 1834 */ 1835 if ((piix_isp_pio[drvp->PIO_mode] != 1836 piix_isp_dma[drvp->DMA_mode]) || 1837 (piix_rtc_pio[drvp->PIO_mode] != 1838 piix_rtc_dma[drvp->DMA_mode])) 1839 drvp->PIO_mode = 0; 1840 /* if PIO mode <= 2, use compat timings for PIO */ 1841 if (drvp->PIO_mode <= 2) { 1842 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1843 channel); 1844 return ret; 1845 } 1846 } 1847 1848 /* 1849 * Now setup PIO modes. If mode < 2, use compat timings. 1850 * Else enable fast timings. Enable IORDY and prefetch/post 1851 * if PIO mode >= 3. 1852 */ 1853 1854 if (drvp->PIO_mode < 2) 1855 return ret; 1856 1857 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1858 if (drvp->PIO_mode >= 3) { 1859 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1860 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1861 } 1862 return ret; 1863 } 1864 1865 /* setup values in SIDETIM registers, based on mode */ 1866 static u_int32_t 1867 piix_setup_sidetim_timings(mode, dma, channel) 1868 u_int8_t mode; 1869 u_int8_t dma; 1870 u_int8_t channel; 1871 { 1872 if (dma) 1873 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1874 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1875 else 1876 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1877 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1878 } 1879 1880 void 1881 amd7x6_chip_map(sc, pa) 1882 struct pciide_softc *sc; 1883 struct pci_attach_args *pa; 1884 { 1885 struct pciide_channel *cp; 1886 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1887 int channel; 1888 pcireg_t chanenable; 1889 bus_size_t cmdsize, ctlsize; 1890 1891 if (pciide_chipen(sc, pa) == 0) 1892 return; 1893 printf("%s: bus-master DMA support present", 1894 sc->sc_wdcdev.sc_dev.dv_xname); 1895 pciide_mapreg_dma(sc, pa); 1896 printf("\n"); 1897 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1898 WDC_CAPABILITY_MODE; 1899 if (sc->sc_dma_ok) { 1900 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1901 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1902 sc->sc_wdcdev.irqack = pciide_irqack; 1903 } 1904 sc->sc_wdcdev.PIO_cap = 4; 1905 sc->sc_wdcdev.DMA_cap = 2; 1906 1907 if (sc->sc_pp->ide_product == PCI_PRODUCT_AMD_PBC766_IDE) 1908 sc->sc_wdcdev.UDMA_cap = 5; 1909 else 1910 sc->sc_wdcdev.UDMA_cap = 4; 1911 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1912 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1913 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1914 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1915 1916 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1917 DEBUG_PROBE); 1918 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1919 cp = &sc->pciide_channels[channel]; 1920 if (pciide_chansetup(sc, channel, interface) == 0) 1921 continue; 1922 1923 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1924 printf("%s: %s channel ignored (disabled)\n", 1925 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1926 continue; 1927 } 1928 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1929 pciide_pci_intr); 1930 1931 if (pciide_chan_candisable(cp)) 1932 chanenable &= ~AMD7X6_CHAN_EN(channel); 1933 pciide_map_compat_intr(pa, cp, channel, interface); 1934 if (cp->hw_ok == 0) 1935 continue; 1936 1937 amd7x6_setup_channel(&cp->wdc_channel); 1938 } 1939 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1940 chanenable); 1941 return; 1942 } 1943 1944 void 1945 amd7x6_setup_channel(chp) 1946 struct channel_softc *chp; 1947 { 1948 u_int32_t udmatim_reg, datatim_reg; 1949 u_int8_t idedma_ctl; 1950 int mode, drive; 1951 struct ata_drive_datas *drvp; 1952 struct pciide_channel *cp = (struct pciide_channel*)chp; 1953 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1954 #ifndef PCIIDE_AMD756_ENABLEDMA 1955 int rev = PCI_REVISION( 1956 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1957 #endif 1958 1959 idedma_ctl = 0; 1960 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1961 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1962 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1963 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1964 1965 /* setup DMA if needed */ 1966 pciide_channel_dma_setup(cp); 1967 1968 for (drive = 0; drive < 2; drive++) { 1969 drvp = &chp->ch_drive[drive]; 1970 /* If no drive, skip */ 1971 if ((drvp->drive_flags & DRIVE) == 0) 1972 continue; 1973 /* add timing values, setup DMA if needed */ 1974 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1975 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1976 mode = drvp->PIO_mode; 1977 goto pio; 1978 } 1979 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1980 (drvp->drive_flags & DRIVE_UDMA)) { 1981 /* use Ultra/DMA */ 1982 drvp->drive_flags &= ~DRIVE_DMA; 1983 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 1984 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 1985 AMD7X6_UDMA_TIME(chp->channel, drive, 1986 amd7x6_udma_tim[drvp->UDMA_mode]); 1987 /* can use PIO timings, MW DMA unused */ 1988 mode = drvp->PIO_mode; 1989 } else { 1990 /* use Multiword DMA, but only if revision is OK */ 1991 drvp->drive_flags &= ~DRIVE_UDMA; 1992 #ifndef PCIIDE_AMD756_ENABLEDMA 1993 /* 1994 * The workaround doesn't seem to be necessary 1995 * with all drives, so it can be disabled by 1996 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1997 * triggered. 1998 */ 1999 if (sc->sc_pp->ide_product == 2000 PCI_PRODUCT_AMD_PBC756_IDE && 2001 AMD756_CHIPREV_DISABLEDMA(rev)) { 2002 printf("%s:%d:%d: multi-word DMA disabled due " 2003 "to chip revision\n", 2004 sc->sc_wdcdev.sc_dev.dv_xname, 2005 chp->channel, drive); 2006 mode = drvp->PIO_mode; 2007 drvp->drive_flags &= ~DRIVE_DMA; 2008 goto pio; 2009 } 2010 #endif 2011 /* mode = min(pio, dma+2) */ 2012 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2013 mode = drvp->PIO_mode; 2014 else 2015 mode = drvp->DMA_mode + 2; 2016 } 2017 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2018 2019 pio: /* setup PIO mode */ 2020 if (mode <= 2) { 2021 drvp->DMA_mode = 0; 2022 drvp->PIO_mode = 0; 2023 mode = 0; 2024 } else { 2025 drvp->PIO_mode = mode; 2026 drvp->DMA_mode = mode - 2; 2027 } 2028 datatim_reg |= 2029 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2030 amd7x6_pio_set[mode]) | 2031 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2032 amd7x6_pio_rec[mode]); 2033 } 2034 if (idedma_ctl != 0) { 2035 /* Add software bits in status register */ 2036 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2037 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2038 idedma_ctl); 2039 } 2040 pciide_print_modes(cp); 2041 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2042 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2043 } 2044 2045 void 2046 apollo_chip_map(sc, pa) 2047 struct pciide_softc *sc; 2048 struct pci_attach_args *pa; 2049 { 2050 struct pciide_channel *cp; 2051 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2052 int channel; 2053 u_int32_t ideconf; 2054 bus_size_t cmdsize, ctlsize; 2055 pcitag_t pcib_tag; 2056 pcireg_t pcib_id, pcib_class; 2057 2058 if (pciide_chipen(sc, pa) == 0) 2059 return; 2060 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2061 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2062 /* and read ID and rev of the ISA bridge */ 2063 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2064 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2065 printf(": VIA Technologies "); 2066 switch (PCI_PRODUCT(pcib_id)) { 2067 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2068 printf("VT82C586 (Apollo VP) "); 2069 if(PCI_REVISION(pcib_class) >= 0x02) { 2070 printf("ATA33 controller\n"); 2071 sc->sc_wdcdev.UDMA_cap = 2; 2072 } else { 2073 printf("controller\n"); 2074 sc->sc_wdcdev.UDMA_cap = 0; 2075 } 2076 break; 2077 case PCI_PRODUCT_VIATECH_VT82C596A: 2078 printf("VT82C596A (Apollo Pro) "); 2079 if (PCI_REVISION(pcib_class) >= 0x12) { 2080 printf("ATA66 controller\n"); 2081 sc->sc_wdcdev.UDMA_cap = 4; 2082 } else { 2083 printf("ATA33 controller\n"); 2084 sc->sc_wdcdev.UDMA_cap = 2; 2085 } 2086 break; 2087 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2088 printf("VT82C686A (Apollo KX133) "); 2089 if (PCI_REVISION(pcib_class) >= 0x40) { 2090 printf("ATA100 controller\n"); 2091 sc->sc_wdcdev.UDMA_cap = 5; 2092 } else { 2093 printf("ATA66 controller\n"); 2094 sc->sc_wdcdev.UDMA_cap = 4; 2095 } 2096 break; 2097 default: 2098 printf("unknown ATA controller\n"); 2099 sc->sc_wdcdev.UDMA_cap = 0; 2100 } 2101 2102 printf("%s: bus-master DMA support present", 2103 sc->sc_wdcdev.sc_dev.dv_xname); 2104 pciide_mapreg_dma(sc, pa); 2105 printf("\n"); 2106 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2107 WDC_CAPABILITY_MODE; 2108 if (sc->sc_dma_ok) { 2109 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2110 sc->sc_wdcdev.irqack = pciide_irqack; 2111 if (sc->sc_wdcdev.UDMA_cap > 0) 2112 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2113 } 2114 sc->sc_wdcdev.PIO_cap = 4; 2115 sc->sc_wdcdev.DMA_cap = 2; 2116 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2117 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2118 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2119 2120 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2121 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2122 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2123 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2124 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2125 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2126 DEBUG_PROBE); 2127 2128 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2129 cp = &sc->pciide_channels[channel]; 2130 if (pciide_chansetup(sc, channel, interface) == 0) 2131 continue; 2132 2133 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2134 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2135 printf("%s: %s channel ignored (disabled)\n", 2136 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2137 continue; 2138 } 2139 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2140 pciide_pci_intr); 2141 if (cp->hw_ok == 0) 2142 continue; 2143 if (pciide_chan_candisable(cp)) { 2144 ideconf &= ~APO_IDECONF_EN(channel); 2145 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2146 ideconf); 2147 } 2148 pciide_map_compat_intr(pa, cp, channel, interface); 2149 2150 if (cp->hw_ok == 0) 2151 continue; 2152 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2153 } 2154 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2155 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2156 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2157 } 2158 2159 void 2160 apollo_setup_channel(chp) 2161 struct channel_softc *chp; 2162 { 2163 u_int32_t udmatim_reg, datatim_reg; 2164 u_int8_t idedma_ctl; 2165 int mode, drive; 2166 struct ata_drive_datas *drvp; 2167 struct pciide_channel *cp = (struct pciide_channel*)chp; 2168 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2169 2170 idedma_ctl = 0; 2171 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2172 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2173 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2174 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2175 2176 /* setup DMA if needed */ 2177 pciide_channel_dma_setup(cp); 2178 2179 for (drive = 0; drive < 2; drive++) { 2180 drvp = &chp->ch_drive[drive]; 2181 /* If no drive, skip */ 2182 if ((drvp->drive_flags & DRIVE) == 0) 2183 continue; 2184 /* add timing values, setup DMA if needed */ 2185 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2186 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2187 mode = drvp->PIO_mode; 2188 goto pio; 2189 } 2190 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2191 (drvp->drive_flags & DRIVE_UDMA)) { 2192 /* use Ultra/DMA */ 2193 drvp->drive_flags &= ~DRIVE_DMA; 2194 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2195 APO_UDMA_EN_MTH(chp->channel, drive); 2196 if (sc->sc_wdcdev.UDMA_cap == 5) { 2197 /* 686b */ 2198 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2199 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2200 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2201 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2202 /* 596b or 686a */ 2203 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2204 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2205 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2206 } else { 2207 /* 596a or 586b */ 2208 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2209 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2210 } 2211 /* can use PIO timings, MW DMA unused */ 2212 mode = drvp->PIO_mode; 2213 } else { 2214 /* use Multiword DMA */ 2215 drvp->drive_flags &= ~DRIVE_UDMA; 2216 /* mode = min(pio, dma+2) */ 2217 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2218 mode = drvp->PIO_mode; 2219 else 2220 mode = drvp->DMA_mode + 2; 2221 } 2222 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2223 2224 pio: /* setup PIO mode */ 2225 if (mode <= 2) { 2226 drvp->DMA_mode = 0; 2227 drvp->PIO_mode = 0; 2228 mode = 0; 2229 } else { 2230 drvp->PIO_mode = mode; 2231 drvp->DMA_mode = mode - 2; 2232 } 2233 datatim_reg |= 2234 APO_DATATIM_PULSE(chp->channel, drive, 2235 apollo_pio_set[mode]) | 2236 APO_DATATIM_RECOV(chp->channel, drive, 2237 apollo_pio_rec[mode]); 2238 } 2239 if (idedma_ctl != 0) { 2240 /* Add software bits in status register */ 2241 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2242 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2243 idedma_ctl); 2244 } 2245 pciide_print_modes(cp); 2246 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2247 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2248 } 2249 2250 void 2251 cmd_channel_map(pa, sc, channel) 2252 struct pci_attach_args *pa; 2253 struct pciide_softc *sc; 2254 int channel; 2255 { 2256 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2257 bus_size_t cmdsize, ctlsize; 2258 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2259 int interface; 2260 2261 /* 2262 * The 0648/0649 can be told to identify as a RAID controller. 2263 * In this case, we have to fake interface 2264 */ 2265 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2266 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2267 PCIIDE_INTERFACE_SETTABLE(1); 2268 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2269 CMD_CONF_DSA1) 2270 interface |= PCIIDE_INTERFACE_PCI(0) | 2271 PCIIDE_INTERFACE_PCI(1); 2272 } else { 2273 interface = PCI_INTERFACE(pa->pa_class); 2274 } 2275 2276 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2277 cp->name = PCIIDE_CHANNEL_NAME(channel); 2278 cp->wdc_channel.channel = channel; 2279 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2280 2281 if (channel > 0) { 2282 cp->wdc_channel.ch_queue = 2283 sc->pciide_channels[0].wdc_channel.ch_queue; 2284 } else { 2285 cp->wdc_channel.ch_queue = 2286 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2287 } 2288 if (cp->wdc_channel.ch_queue == NULL) { 2289 printf("%s %s channel: " 2290 "can't allocate memory for command queue", 2291 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2292 return; 2293 } 2294 2295 printf("%s: %s channel %s to %s mode\n", 2296 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2297 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2298 "configured" : "wired", 2299 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2300 "native-PCI" : "compatibility"); 2301 2302 /* 2303 * with a CMD PCI64x, if we get here, the first channel is enabled: 2304 * there's no way to disable the first channel without disabling 2305 * the whole device 2306 */ 2307 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2308 printf("%s: %s channel ignored (disabled)\n", 2309 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2310 return; 2311 } 2312 2313 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2314 if (cp->hw_ok == 0) 2315 return; 2316 if (channel == 1) { 2317 if (pciide_chan_candisable(cp)) { 2318 ctrl &= ~CMD_CTRL_2PORT; 2319 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2320 CMD_CTRL, ctrl); 2321 } 2322 } 2323 pciide_map_compat_intr(pa, cp, channel, interface); 2324 } 2325 2326 int 2327 cmd_pci_intr(arg) 2328 void *arg; 2329 { 2330 struct pciide_softc *sc = arg; 2331 struct pciide_channel *cp; 2332 struct channel_softc *wdc_cp; 2333 int i, rv, crv; 2334 u_int32_t priirq, secirq; 2335 2336 rv = 0; 2337 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2338 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2339 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2340 cp = &sc->pciide_channels[i]; 2341 wdc_cp = &cp->wdc_channel; 2342 /* If a compat channel skip. */ 2343 if (cp->compat) 2344 continue; 2345 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2346 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2347 crv = wdcintr(wdc_cp); 2348 if (crv == 0) 2349 printf("%s:%d: bogus intr\n", 2350 sc->sc_wdcdev.sc_dev.dv_xname, i); 2351 else 2352 rv = 1; 2353 } 2354 } 2355 return rv; 2356 } 2357 2358 void 2359 cmd_chip_map(sc, pa) 2360 struct pciide_softc *sc; 2361 struct pci_attach_args *pa; 2362 { 2363 int channel; 2364 2365 /* 2366 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2367 * and base adresses registers can be disabled at 2368 * hardware level. In this case, the device is wired 2369 * in compat mode and its first channel is always enabled, 2370 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2371 * In fact, it seems that the first channel of the CMD PCI0640 2372 * can't be disabled. 2373 */ 2374 2375 #ifdef PCIIDE_CMD064x_DISABLE 2376 if (pciide_chipen(sc, pa) == 0) 2377 return; 2378 #endif 2379 2380 printf("%s: hardware does not support DMA\n", 2381 sc->sc_wdcdev.sc_dev.dv_xname); 2382 sc->sc_dma_ok = 0; 2383 2384 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2385 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2386 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2387 2388 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2389 cmd_channel_map(pa, sc, channel); 2390 } 2391 } 2392 2393 void 2394 cmd0643_9_chip_map(sc, pa) 2395 struct pciide_softc *sc; 2396 struct pci_attach_args *pa; 2397 { 2398 struct pciide_channel *cp; 2399 int channel; 2400 int rev = PCI_REVISION( 2401 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2402 2403 /* 2404 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2405 * and base adresses registers can be disabled at 2406 * hardware level. In this case, the device is wired 2407 * in compat mode and its first channel is always enabled, 2408 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2409 * In fact, it seems that the first channel of the CMD PCI0640 2410 * can't be disabled. 2411 */ 2412 2413 #ifdef PCIIDE_CMD064x_DISABLE 2414 if (pciide_chipen(sc, pa) == 0) 2415 return; 2416 #endif 2417 printf("%s: bus-master DMA support present", 2418 sc->sc_wdcdev.sc_dev.dv_xname); 2419 pciide_mapreg_dma(sc, pa); 2420 printf("\n"); 2421 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2422 WDC_CAPABILITY_MODE; 2423 if (sc->sc_dma_ok) { 2424 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2425 switch (sc->sc_pp->ide_product) { 2426 case PCI_PRODUCT_CMDTECH_649: 2427 case PCI_PRODUCT_CMDTECH_648: 2428 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2429 sc->sc_wdcdev.UDMA_cap = 4; 2430 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2431 break; 2432 case PCI_PRODUCT_CMDTECH_646: 2433 if (rev >= CMD0646U2_REV) { 2434 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2435 sc->sc_wdcdev.UDMA_cap = 2; 2436 } else if (rev >= CMD0646U_REV) { 2437 /* 2438 * Linux's driver claims that the 646U is broken 2439 * with UDMA. Only enable it if we know what we're 2440 * doing 2441 */ 2442 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2443 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2444 sc->sc_wdcdev.UDMA_cap = 2; 2445 #endif 2446 /* explicitely disable UDMA */ 2447 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2448 CMD_UDMATIM(0), 0); 2449 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2450 CMD_UDMATIM(1), 0); 2451 } 2452 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2453 break; 2454 default: 2455 sc->sc_wdcdev.irqack = pciide_irqack; 2456 } 2457 } 2458 2459 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2460 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2461 sc->sc_wdcdev.PIO_cap = 4; 2462 sc->sc_wdcdev.DMA_cap = 2; 2463 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2464 2465 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2466 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2467 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2468 DEBUG_PROBE); 2469 2470 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2471 cp = &sc->pciide_channels[channel]; 2472 cmd_channel_map(pa, sc, channel); 2473 if (cp->hw_ok == 0) 2474 continue; 2475 cmd0643_9_setup_channel(&cp->wdc_channel); 2476 } 2477 /* 2478 * note - this also makes sure we clear the irq disable and reset 2479 * bits 2480 */ 2481 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2482 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2483 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2484 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2485 DEBUG_PROBE); 2486 } 2487 2488 void 2489 cmd0643_9_setup_channel(chp) 2490 struct channel_softc *chp; 2491 { 2492 struct ata_drive_datas *drvp; 2493 u_int8_t tim; 2494 u_int32_t idedma_ctl, udma_reg; 2495 int drive; 2496 struct pciide_channel *cp = (struct pciide_channel*)chp; 2497 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2498 2499 idedma_ctl = 0; 2500 /* setup DMA if needed */ 2501 pciide_channel_dma_setup(cp); 2502 2503 for (drive = 0; drive < 2; drive++) { 2504 drvp = &chp->ch_drive[drive]; 2505 /* If no drive, skip */ 2506 if ((drvp->drive_flags & DRIVE) == 0) 2507 continue; 2508 /* add timing values, setup DMA if needed */ 2509 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2510 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2511 if (drvp->drive_flags & DRIVE_UDMA) { 2512 /* UltraDMA on a 646U2, 0648 or 0649 */ 2513 drvp->drive_flags &= ~DRIVE_DMA; 2514 udma_reg = pciide_pci_read(sc->sc_pc, 2515 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2516 if (drvp->UDMA_mode > 2 && 2517 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2518 CMD_BICSR) & 2519 CMD_BICSR_80(chp->channel)) == 0) 2520 drvp->UDMA_mode = 2; 2521 if (drvp->UDMA_mode > 2) 2522 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2523 else if (sc->sc_wdcdev.UDMA_cap > 2) 2524 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2525 udma_reg |= CMD_UDMATIM_UDMA(drive); 2526 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2527 CMD_UDMATIM_TIM_OFF(drive)); 2528 udma_reg |= 2529 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2530 CMD_UDMATIM_TIM_OFF(drive)); 2531 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2532 CMD_UDMATIM(chp->channel), udma_reg); 2533 } else { 2534 /* 2535 * use Multiword DMA. 2536 * Timings will be used for both PIO and DMA, 2537 * so adjust DMA mode if needed 2538 * if we have a 0646U2/8/9, turn off UDMA 2539 */ 2540 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2541 udma_reg = pciide_pci_read(sc->sc_pc, 2542 sc->sc_tag, 2543 CMD_UDMATIM(chp->channel)); 2544 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2545 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2546 CMD_UDMATIM(chp->channel), 2547 udma_reg); 2548 } 2549 if (drvp->PIO_mode >= 3 && 2550 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2551 drvp->DMA_mode = drvp->PIO_mode - 2; 2552 } 2553 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2554 } 2555 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2556 } 2557 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2558 CMD_DATA_TIM(chp->channel, drive), tim); 2559 } 2560 if (idedma_ctl != 0) { 2561 /* Add software bits in status register */ 2562 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2563 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2564 idedma_ctl); 2565 } 2566 pciide_print_modes(cp); 2567 } 2568 2569 void 2570 cmd646_9_irqack(chp) 2571 struct channel_softc *chp; 2572 { 2573 u_int32_t priirq, secirq; 2574 struct pciide_channel *cp = (struct pciide_channel*)chp; 2575 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2576 2577 if (chp->channel == 0) { 2578 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2579 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2580 } else { 2581 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2582 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2583 } 2584 pciide_irqack(chp); 2585 } 2586 2587 void 2588 cy693_chip_map(sc, pa) 2589 struct pciide_softc *sc; 2590 struct pci_attach_args *pa; 2591 { 2592 struct pciide_channel *cp; 2593 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2594 bus_size_t cmdsize, ctlsize; 2595 2596 if (pciide_chipen(sc, pa) == 0) 2597 return; 2598 /* 2599 * this chip has 2 PCI IDE functions, one for primary and one for 2600 * secondary. So we need to call pciide_mapregs_compat() with 2601 * the real channel 2602 */ 2603 if (pa->pa_function == 1) { 2604 sc->sc_cy_compatchan = 0; 2605 } else if (pa->pa_function == 2) { 2606 sc->sc_cy_compatchan = 1; 2607 } else { 2608 printf("%s: unexpected PCI function %d\n", 2609 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2610 return; 2611 } 2612 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2613 printf("%s: bus-master DMA support present", 2614 sc->sc_wdcdev.sc_dev.dv_xname); 2615 pciide_mapreg_dma(sc, pa); 2616 } else { 2617 printf("%s: hardware does not support DMA", 2618 sc->sc_wdcdev.sc_dev.dv_xname); 2619 sc->sc_dma_ok = 0; 2620 } 2621 printf("\n"); 2622 2623 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2624 if (sc->sc_cy_handle == NULL) { 2625 printf("%s: unable to map hyperCache control registers\n", 2626 sc->sc_wdcdev.sc_dev.dv_xname); 2627 sc->sc_dma_ok = 0; 2628 } 2629 2630 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2631 WDC_CAPABILITY_MODE; 2632 if (sc->sc_dma_ok) { 2633 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2634 sc->sc_wdcdev.irqack = pciide_irqack; 2635 } 2636 sc->sc_wdcdev.PIO_cap = 4; 2637 sc->sc_wdcdev.DMA_cap = 2; 2638 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2639 2640 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2641 sc->sc_wdcdev.nchannels = 1; 2642 2643 /* Only one channel for this chip; if we are here it's enabled */ 2644 cp = &sc->pciide_channels[0]; 2645 sc->wdc_chanarray[0] = &cp->wdc_channel; 2646 cp->name = PCIIDE_CHANNEL_NAME(0); 2647 cp->wdc_channel.channel = 0; 2648 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2649 cp->wdc_channel.ch_queue = 2650 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2651 if (cp->wdc_channel.ch_queue == NULL) { 2652 printf("%s primary channel: " 2653 "can't allocate memory for command queue", 2654 sc->sc_wdcdev.sc_dev.dv_xname); 2655 return; 2656 } 2657 printf("%s: primary channel %s to ", 2658 sc->sc_wdcdev.sc_dev.dv_xname, 2659 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2660 "configured" : "wired"); 2661 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2662 printf("native-PCI"); 2663 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2664 pciide_pci_intr); 2665 } else { 2666 printf("compatibility"); 2667 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2668 &cmdsize, &ctlsize); 2669 } 2670 printf(" mode\n"); 2671 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2672 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2673 wdcattach(&cp->wdc_channel); 2674 if (pciide_chan_candisable(cp)) { 2675 pci_conf_write(sc->sc_pc, sc->sc_tag, 2676 PCI_COMMAND_STATUS_REG, 0); 2677 } 2678 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2679 if (cp->hw_ok == 0) 2680 return; 2681 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2682 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2683 cy693_setup_channel(&cp->wdc_channel); 2684 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2685 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2686 } 2687 2688 void 2689 cy693_setup_channel(chp) 2690 struct channel_softc *chp; 2691 { 2692 struct ata_drive_datas *drvp; 2693 int drive; 2694 u_int32_t cy_cmd_ctrl; 2695 u_int32_t idedma_ctl; 2696 struct pciide_channel *cp = (struct pciide_channel*)chp; 2697 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2698 int dma_mode = -1; 2699 2700 cy_cmd_ctrl = idedma_ctl = 0; 2701 2702 /* setup DMA if needed */ 2703 pciide_channel_dma_setup(cp); 2704 2705 for (drive = 0; drive < 2; drive++) { 2706 drvp = &chp->ch_drive[drive]; 2707 /* If no drive, skip */ 2708 if ((drvp->drive_flags & DRIVE) == 0) 2709 continue; 2710 /* add timing values, setup DMA if needed */ 2711 if (drvp->drive_flags & DRIVE_DMA) { 2712 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2713 /* use Multiword DMA */ 2714 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2715 dma_mode = drvp->DMA_mode; 2716 } 2717 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2718 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2719 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2720 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2721 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2722 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2723 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2724 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2725 } 2726 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2727 chp->ch_drive[0].DMA_mode = dma_mode; 2728 chp->ch_drive[1].DMA_mode = dma_mode; 2729 2730 if (dma_mode == -1) 2731 dma_mode = 0; 2732 2733 if (sc->sc_cy_handle != NULL) { 2734 /* Note: `multiple' is implied. */ 2735 cy82c693_write(sc->sc_cy_handle, 2736 (sc->sc_cy_compatchan == 0) ? 2737 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2738 } 2739 2740 pciide_print_modes(cp); 2741 2742 if (idedma_ctl != 0) { 2743 /* Add software bits in status register */ 2744 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2745 IDEDMA_CTL, idedma_ctl); 2746 } 2747 } 2748 2749 static int 2750 sis_hostbr_match(pa) 2751 struct pci_attach_args *pa; 2752 { 2753 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2754 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2755 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2756 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2757 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2758 } 2759 2760 void 2761 sis_chip_map(sc, pa) 2762 struct pciide_softc *sc; 2763 struct pci_attach_args *pa; 2764 { 2765 struct pciide_channel *cp; 2766 int channel; 2767 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2768 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2769 pcireg_t rev = PCI_REVISION(pa->pa_class); 2770 bus_size_t cmdsize, ctlsize; 2771 pcitag_t pchb_tag; 2772 pcireg_t pchb_id, pchb_class; 2773 2774 if (pciide_chipen(sc, pa) == 0) 2775 return; 2776 printf("%s: bus-master DMA support present", 2777 sc->sc_wdcdev.sc_dev.dv_xname); 2778 pciide_mapreg_dma(sc, pa); 2779 printf("\n"); 2780 2781 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2782 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2783 /* and read ID and rev of the ISA bridge */ 2784 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2785 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2786 2787 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2788 WDC_CAPABILITY_MODE; 2789 if (sc->sc_dma_ok) { 2790 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2791 sc->sc_wdcdev.irqack = pciide_irqack; 2792 /* 2793 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2794 * have problems with UDMA (info provided by Christos) 2795 */ 2796 if (rev >= 0xd0 && 2797 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2798 PCI_REVISION(pchb_class) >= 0x03)) 2799 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2800 } 2801 2802 sc->sc_wdcdev.PIO_cap = 4; 2803 sc->sc_wdcdev.DMA_cap = 2; 2804 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2805 /* 2806 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2807 * chipsets. 2808 */ 2809 sc->sc_wdcdev.UDMA_cap = 2810 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2811 sc->sc_wdcdev.set_modes = sis_setup_channel; 2812 2813 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2814 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2815 2816 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2817 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2818 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2819 2820 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2821 cp = &sc->pciide_channels[channel]; 2822 if (pciide_chansetup(sc, channel, interface) == 0) 2823 continue; 2824 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2825 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2826 printf("%s: %s channel ignored (disabled)\n", 2827 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2828 continue; 2829 } 2830 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2831 pciide_pci_intr); 2832 if (cp->hw_ok == 0) 2833 continue; 2834 if (pciide_chan_candisable(cp)) { 2835 if (channel == 0) 2836 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2837 else 2838 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2839 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2840 sis_ctr0); 2841 } 2842 pciide_map_compat_intr(pa, cp, channel, interface); 2843 if (cp->hw_ok == 0) 2844 continue; 2845 sis_setup_channel(&cp->wdc_channel); 2846 } 2847 } 2848 2849 void 2850 sis_setup_channel(chp) 2851 struct channel_softc *chp; 2852 { 2853 struct ata_drive_datas *drvp; 2854 int drive; 2855 u_int32_t sis_tim; 2856 u_int32_t idedma_ctl; 2857 struct pciide_channel *cp = (struct pciide_channel*)chp; 2858 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2859 2860 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2861 "channel %d 0x%x\n", chp->channel, 2862 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2863 DEBUG_PROBE); 2864 sis_tim = 0; 2865 idedma_ctl = 0; 2866 /* setup DMA if needed */ 2867 pciide_channel_dma_setup(cp); 2868 2869 for (drive = 0; drive < 2; drive++) { 2870 drvp = &chp->ch_drive[drive]; 2871 /* If no drive, skip */ 2872 if ((drvp->drive_flags & DRIVE) == 0) 2873 continue; 2874 /* add timing values, setup DMA if needed */ 2875 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2876 (drvp->drive_flags & DRIVE_UDMA) == 0) 2877 goto pio; 2878 2879 if (drvp->drive_flags & DRIVE_UDMA) { 2880 /* use Ultra/DMA */ 2881 drvp->drive_flags &= ~DRIVE_DMA; 2882 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2883 SIS_TIM_UDMA_TIME_OFF(drive); 2884 sis_tim |= SIS_TIM_UDMA_EN(drive); 2885 } else { 2886 /* 2887 * use Multiword DMA 2888 * Timings will be used for both PIO and DMA, 2889 * so adjust DMA mode if needed 2890 */ 2891 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2892 drvp->PIO_mode = drvp->DMA_mode + 2; 2893 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2894 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2895 drvp->PIO_mode - 2 : 0; 2896 if (drvp->DMA_mode == 0) 2897 drvp->PIO_mode = 0; 2898 } 2899 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2900 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2901 SIS_TIM_ACT_OFF(drive); 2902 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2903 SIS_TIM_REC_OFF(drive); 2904 } 2905 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2906 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2907 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2908 if (idedma_ctl != 0) { 2909 /* Add software bits in status register */ 2910 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2911 IDEDMA_CTL, idedma_ctl); 2912 } 2913 pciide_print_modes(cp); 2914 } 2915 2916 static int 2917 acer_isabr_match(pa) 2918 struct pci_attach_args *pa; 2919 { 2920 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 2921 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 2922 } 2923 2924 void 2925 acer_chip_map(sc, pa) 2926 struct pciide_softc *sc; 2927 struct pci_attach_args *pa; 2928 { 2929 struct pci_attach_args isa_pa; 2930 struct pciide_channel *cp; 2931 int channel; 2932 pcireg_t cr, interface; 2933 bus_size_t cmdsize, ctlsize; 2934 pcireg_t rev = PCI_REVISION(pa->pa_class); 2935 2936 if (pciide_chipen(sc, pa) == 0) 2937 return; 2938 printf("%s: bus-master DMA support present", 2939 sc->sc_wdcdev.sc_dev.dv_xname); 2940 pciide_mapreg_dma(sc, pa); 2941 printf("\n"); 2942 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2943 WDC_CAPABILITY_MODE; 2944 if (sc->sc_dma_ok) { 2945 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2946 if (rev >= 0x20) { 2947 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2948 if (rev >= 0xC4) 2949 sc->sc_wdcdev.UDMA_cap = 5; 2950 else if (rev >= 0xC2) 2951 sc->sc_wdcdev.UDMA_cap = 4; 2952 else 2953 sc->sc_wdcdev.UDMA_cap = 2; 2954 } 2955 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2956 sc->sc_wdcdev.irqack = pciide_irqack; 2957 } 2958 2959 sc->sc_wdcdev.PIO_cap = 4; 2960 sc->sc_wdcdev.DMA_cap = 2; 2961 sc->sc_wdcdev.set_modes = acer_setup_channel; 2962 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2963 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2964 2965 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2966 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2967 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2968 2969 /* Enable "microsoft register bits" R/W. */ 2970 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2971 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2972 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2973 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2974 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2975 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2976 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2977 ~ACER_CHANSTATUSREGS_RO); 2978 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2979 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2980 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2981 /* Don't use cr, re-read the real register content instead */ 2982 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2983 PCI_CLASS_REG)); 2984 2985 /* From linux: enable "Cable Detection" */ 2986 if (rev >= 0xC2) { 2987 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 2988 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 2989 | ACER_0x4B_CDETECT); 2990 /* set south-bridge's enable bit, m1533, 0x79 */ 2991 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 2992 printf("%s: can't find PCI/ISA bridge, downgrading " 2993 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 2994 sc->sc_wdcdev.UDMA_cap = 2; 2995 } else { 2996 if (rev == 0xC2) 2997 /* 1543C-B0 (m1533, 0x79, bit 2) */ 2998 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 2999 ACER_0x79, 3000 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3001 ACER_0x79) 3002 | ACER_0x79_REVC2_EN); 3003 else 3004 /* 1553/1535 (m1533, 0x79, bit 1) */ 3005 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3006 ACER_0x79, 3007 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3008 ACER_0x79) 3009 | ACER_0x79_EN); 3010 } 3011 } 3012 3013 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3014 cp = &sc->pciide_channels[channel]; 3015 if (pciide_chansetup(sc, channel, interface) == 0) 3016 continue; 3017 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3018 printf("%s: %s channel ignored (disabled)\n", 3019 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3020 continue; 3021 } 3022 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3023 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3024 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3025 if (cp->hw_ok == 0) 3026 continue; 3027 if (pciide_chan_candisable(cp)) { 3028 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3029 pci_conf_write(sc->sc_pc, sc->sc_tag, 3030 PCI_CLASS_REG, cr); 3031 } 3032 pciide_map_compat_intr(pa, cp, channel, interface); 3033 acer_setup_channel(&cp->wdc_channel); 3034 } 3035 } 3036 3037 void 3038 acer_setup_channel(chp) 3039 struct channel_softc *chp; 3040 { 3041 struct ata_drive_datas *drvp; 3042 int drive; 3043 u_int32_t acer_fifo_udma; 3044 u_int32_t idedma_ctl; 3045 struct pciide_channel *cp = (struct pciide_channel*)chp; 3046 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3047 3048 idedma_ctl = 0; 3049 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3050 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3051 acer_fifo_udma), DEBUG_PROBE); 3052 /* setup DMA if needed */ 3053 pciide_channel_dma_setup(cp); 3054 3055 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3056 DRIVE_UDMA) { /* check 80 pins cable */ 3057 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3058 ACER_0x4A_80PIN(chp->channel)) { 3059 if (chp->ch_drive[0].UDMA_mode > 2) 3060 chp->ch_drive[0].UDMA_mode = 2; 3061 if (chp->ch_drive[1].UDMA_mode > 2) 3062 chp->ch_drive[1].UDMA_mode = 2; 3063 } 3064 } 3065 3066 for (drive = 0; drive < 2; drive++) { 3067 drvp = &chp->ch_drive[drive]; 3068 /* If no drive, skip */ 3069 if ((drvp->drive_flags & DRIVE) == 0) 3070 continue; 3071 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3072 "channel %d drive %d 0x%x\n", chp->channel, drive, 3073 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3074 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3075 /* clear FIFO/DMA mode */ 3076 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3077 ACER_UDMA_EN(chp->channel, drive) | 3078 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3079 3080 /* add timing values, setup DMA if needed */ 3081 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3082 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3083 acer_fifo_udma |= 3084 ACER_FTH_OPL(chp->channel, drive, 0x1); 3085 goto pio; 3086 } 3087 3088 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3089 if (drvp->drive_flags & DRIVE_UDMA) { 3090 /* use Ultra/DMA */ 3091 drvp->drive_flags &= ~DRIVE_DMA; 3092 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3093 acer_fifo_udma |= 3094 ACER_UDMA_TIM(chp->channel, drive, 3095 acer_udma[drvp->UDMA_mode]); 3096 /* XXX disable if one drive < UDMA3 ? */ 3097 if (drvp->UDMA_mode >= 3) { 3098 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3099 ACER_0x4B, 3100 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3101 ACER_0x4B) | ACER_0x4B_UDMA66); 3102 } 3103 } else { 3104 /* 3105 * use Multiword DMA 3106 * Timings will be used for both PIO and DMA, 3107 * so adjust DMA mode if needed 3108 */ 3109 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3110 drvp->PIO_mode = drvp->DMA_mode + 2; 3111 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3112 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3113 drvp->PIO_mode - 2 : 0; 3114 if (drvp->DMA_mode == 0) 3115 drvp->PIO_mode = 0; 3116 } 3117 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3118 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3119 ACER_IDETIM(chp->channel, drive), 3120 acer_pio[drvp->PIO_mode]); 3121 } 3122 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3123 acer_fifo_udma), DEBUG_PROBE); 3124 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3125 if (idedma_ctl != 0) { 3126 /* Add software bits in status register */ 3127 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3128 IDEDMA_CTL, idedma_ctl); 3129 } 3130 pciide_print_modes(cp); 3131 } 3132 3133 int 3134 acer_pci_intr(arg) 3135 void *arg; 3136 { 3137 struct pciide_softc *sc = arg; 3138 struct pciide_channel *cp; 3139 struct channel_softc *wdc_cp; 3140 int i, rv, crv; 3141 u_int32_t chids; 3142 3143 rv = 0; 3144 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3145 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3146 cp = &sc->pciide_channels[i]; 3147 wdc_cp = &cp->wdc_channel; 3148 /* If a compat channel skip. */ 3149 if (cp->compat) 3150 continue; 3151 if (chids & ACER_CHIDS_INT(i)) { 3152 crv = wdcintr(wdc_cp); 3153 if (crv == 0) 3154 printf("%s:%d: bogus intr\n", 3155 sc->sc_wdcdev.sc_dev.dv_xname, i); 3156 else 3157 rv = 1; 3158 } 3159 } 3160 return rv; 3161 } 3162 3163 void 3164 hpt_chip_map(sc, pa) 3165 struct pciide_softc *sc; 3166 struct pci_attach_args *pa; 3167 { 3168 struct pciide_channel *cp; 3169 int i, compatchan, revision; 3170 pcireg_t interface; 3171 bus_size_t cmdsize, ctlsize; 3172 3173 if (pciide_chipen(sc, pa) == 0) 3174 return; 3175 revision = PCI_REVISION(pa->pa_class); 3176 printf(": Triones/Highpoint "); 3177 if (revision == HPT370_REV) 3178 printf("HPT370 IDE Controller\n"); 3179 else if (revision == HPT370A_REV) 3180 printf("HPT370A IDE Controller\n"); 3181 else if (revision == HPT366_REV) 3182 printf("HPT366 IDE Controller\n"); 3183 else 3184 printf("unknown HPT IDE controller rev %d\n", revision); 3185 3186 /* 3187 * when the chip is in native mode it identifies itself as a 3188 * 'misc mass storage'. Fake interface in this case. 3189 */ 3190 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3191 interface = PCI_INTERFACE(pa->pa_class); 3192 } else { 3193 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3194 PCIIDE_INTERFACE_PCI(0); 3195 if (revision == HPT370_REV || revision == HPT370A_REV) 3196 interface |= PCIIDE_INTERFACE_PCI(1); 3197 } 3198 3199 printf("%s: bus-master DMA support present", 3200 sc->sc_wdcdev.sc_dev.dv_xname); 3201 pciide_mapreg_dma(sc, pa); 3202 printf("\n"); 3203 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3204 WDC_CAPABILITY_MODE; 3205 if (sc->sc_dma_ok) { 3206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3207 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3208 sc->sc_wdcdev.irqack = pciide_irqack; 3209 } 3210 sc->sc_wdcdev.PIO_cap = 4; 3211 sc->sc_wdcdev.DMA_cap = 2; 3212 3213 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3214 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3215 if (revision == HPT366_REV) { 3216 sc->sc_wdcdev.UDMA_cap = 4; 3217 /* 3218 * The 366 has 2 PCI IDE functions, one for primary and one 3219 * for secondary. So we need to call pciide_mapregs_compat() 3220 * with the real channel 3221 */ 3222 if (pa->pa_function == 0) { 3223 compatchan = 0; 3224 } else if (pa->pa_function == 1) { 3225 compatchan = 1; 3226 } else { 3227 printf("%s: unexpected PCI function %d\n", 3228 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3229 return; 3230 } 3231 sc->sc_wdcdev.nchannels = 1; 3232 } else { 3233 sc->sc_wdcdev.nchannels = 2; 3234 sc->sc_wdcdev.UDMA_cap = 5; 3235 } 3236 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3237 cp = &sc->pciide_channels[i]; 3238 if (sc->sc_wdcdev.nchannels > 1) { 3239 compatchan = i; 3240 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3241 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3242 printf("%s: %s channel ignored (disabled)\n", 3243 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3244 continue; 3245 } 3246 } 3247 if (pciide_chansetup(sc, i, interface) == 0) 3248 continue; 3249 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3250 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3251 &ctlsize, hpt_pci_intr); 3252 } else { 3253 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3254 &cmdsize, &ctlsize); 3255 } 3256 if (cp->hw_ok == 0) 3257 return; 3258 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3259 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3260 wdcattach(&cp->wdc_channel); 3261 hpt_setup_channel(&cp->wdc_channel); 3262 } 3263 if (revision == HPT370_REV || revision == HPT370A_REV) { 3264 /* 3265 * HPT370_REV has a bit to disable interrupts, make sure 3266 * to clear it 3267 */ 3268 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3269 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3270 ~HPT_CSEL_IRQDIS); 3271 } 3272 return; 3273 } 3274 3275 void 3276 hpt_setup_channel(chp) 3277 struct channel_softc *chp; 3278 { 3279 struct ata_drive_datas *drvp; 3280 int drive; 3281 int cable; 3282 u_int32_t before, after; 3283 u_int32_t idedma_ctl; 3284 struct pciide_channel *cp = (struct pciide_channel*)chp; 3285 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3286 3287 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3288 3289 /* setup DMA if needed */ 3290 pciide_channel_dma_setup(cp); 3291 3292 idedma_ctl = 0; 3293 3294 /* Per drive settings */ 3295 for (drive = 0; drive < 2; drive++) { 3296 drvp = &chp->ch_drive[drive]; 3297 /* If no drive, skip */ 3298 if ((drvp->drive_flags & DRIVE) == 0) 3299 continue; 3300 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3301 HPT_IDETIM(chp->channel, drive)); 3302 3303 /* add timing values, setup DMA if needed */ 3304 if (drvp->drive_flags & DRIVE_UDMA) { 3305 /* use Ultra/DMA */ 3306 drvp->drive_flags &= ~DRIVE_DMA; 3307 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3308 drvp->UDMA_mode > 2) 3309 drvp->UDMA_mode = 2; 3310 after = (sc->sc_wdcdev.nchannels == 2) ? 3311 hpt370_udma[drvp->UDMA_mode] : 3312 hpt366_udma[drvp->UDMA_mode]; 3313 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3314 } else if (drvp->drive_flags & DRIVE_DMA) { 3315 /* 3316 * use Multiword DMA. 3317 * Timings will be used for both PIO and DMA, so adjust 3318 * DMA mode if needed 3319 */ 3320 if (drvp->PIO_mode >= 3 && 3321 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3322 drvp->DMA_mode = drvp->PIO_mode - 2; 3323 } 3324 after = (sc->sc_wdcdev.nchannels == 2) ? 3325 hpt370_dma[drvp->DMA_mode] : 3326 hpt366_dma[drvp->DMA_mode]; 3327 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3328 } else { 3329 /* PIO only */ 3330 after = (sc->sc_wdcdev.nchannels == 2) ? 3331 hpt370_pio[drvp->PIO_mode] : 3332 hpt366_pio[drvp->PIO_mode]; 3333 } 3334 pci_conf_write(sc->sc_pc, sc->sc_tag, 3335 HPT_IDETIM(chp->channel, drive), after); 3336 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3337 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3338 after, before), DEBUG_PROBE); 3339 } 3340 if (idedma_ctl != 0) { 3341 /* Add software bits in status register */ 3342 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3343 IDEDMA_CTL, idedma_ctl); 3344 } 3345 pciide_print_modes(cp); 3346 } 3347 3348 int 3349 hpt_pci_intr(arg) 3350 void *arg; 3351 { 3352 struct pciide_softc *sc = arg; 3353 struct pciide_channel *cp; 3354 struct channel_softc *wdc_cp; 3355 int rv = 0; 3356 int dmastat, i, crv; 3357 3358 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3359 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3360 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3361 if((dmastat & IDEDMA_CTL_INTR) == 0) 3362 continue; 3363 cp = &sc->pciide_channels[i]; 3364 wdc_cp = &cp->wdc_channel; 3365 crv = wdcintr(wdc_cp); 3366 if (crv == 0) { 3367 printf("%s:%d: bogus intr\n", 3368 sc->sc_wdcdev.sc_dev.dv_xname, i); 3369 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3370 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3371 } else 3372 rv = 1; 3373 } 3374 return rv; 3375 } 3376 3377 3378 /* Macros to test product */ 3379 #define PDC_IS_262(sc) \ 3380 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3381 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3382 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3383 #define PDC_IS_265(sc) \ 3384 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3385 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3386 3387 void 3388 pdc202xx_chip_map(sc, pa) 3389 struct pciide_softc *sc; 3390 struct pci_attach_args *pa; 3391 { 3392 struct pciide_channel *cp; 3393 int channel; 3394 pcireg_t interface, st, mode; 3395 bus_size_t cmdsize, ctlsize; 3396 3397 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3398 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3399 DEBUG_PROBE); 3400 if (pciide_chipen(sc, pa) == 0) 3401 return; 3402 3403 /* turn off RAID mode */ 3404 st &= ~PDC2xx_STATE_IDERAID; 3405 3406 /* 3407 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3408 * mode. We have to fake interface 3409 */ 3410 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3411 if (st & PDC2xx_STATE_NATIVE) 3412 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3413 3414 printf("%s: bus-master DMA support present", 3415 sc->sc_wdcdev.sc_dev.dv_xname); 3416 pciide_mapreg_dma(sc, pa); 3417 printf("\n"); 3418 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3419 WDC_CAPABILITY_MODE; 3420 if (sc->sc_dma_ok) { 3421 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3422 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3423 sc->sc_wdcdev.irqack = pciide_irqack; 3424 } 3425 sc->sc_wdcdev.PIO_cap = 4; 3426 sc->sc_wdcdev.DMA_cap = 2; 3427 if (PDC_IS_265(sc)) 3428 sc->sc_wdcdev.UDMA_cap = 5; 3429 else if (PDC_IS_262(sc)) 3430 sc->sc_wdcdev.UDMA_cap = 4; 3431 else 3432 sc->sc_wdcdev.UDMA_cap = 2; 3433 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3434 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3435 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3436 3437 /* setup failsafe defaults */ 3438 mode = 0; 3439 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3440 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3441 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3442 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3443 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3444 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3445 "initial timings 0x%x, now 0x%x\n", channel, 3446 pci_conf_read(sc->sc_pc, sc->sc_tag, 3447 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3448 DEBUG_PROBE); 3449 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3450 mode | PDC2xx_TIM_IORDYp); 3451 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3452 "initial timings 0x%x, now 0x%x\n", channel, 3453 pci_conf_read(sc->sc_pc, sc->sc_tag, 3454 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3455 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3456 mode); 3457 } 3458 3459 mode = PDC2xx_SCR_DMA; 3460 if (PDC_IS_262(sc)) { 3461 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3462 } else { 3463 /* the BIOS set it up this way */ 3464 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3465 } 3466 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3467 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3468 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3469 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3470 DEBUG_PROBE); 3471 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3472 3473 /* controller initial state register is OK even without BIOS */ 3474 /* Set DMA mode to IDE DMA compatibility */ 3475 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3476 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3477 DEBUG_PROBE); 3478 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3479 mode | 0x1); 3480 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3481 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3482 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3483 mode | 0x1); 3484 3485 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3486 cp = &sc->pciide_channels[channel]; 3487 if (pciide_chansetup(sc, channel, interface) == 0) 3488 continue; 3489 if ((st & (PDC_IS_262(sc) ? 3490 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3491 printf("%s: %s channel ignored (disabled)\n", 3492 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3493 continue; 3494 } 3495 if (PDC_IS_265(sc)) 3496 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3497 pdc20265_pci_intr); 3498 else 3499 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3500 pdc202xx_pci_intr); 3501 if (cp->hw_ok == 0) 3502 continue; 3503 if (pciide_chan_candisable(cp)) 3504 st &= ~(PDC_IS_262(sc) ? 3505 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3506 pciide_map_compat_intr(pa, cp, channel, interface); 3507 pdc202xx_setup_channel(&cp->wdc_channel); 3508 } 3509 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3510 DEBUG_PROBE); 3511 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3512 return; 3513 } 3514 3515 void 3516 pdc202xx_setup_channel(chp) 3517 struct channel_softc *chp; 3518 { 3519 struct ata_drive_datas *drvp; 3520 int drive; 3521 pcireg_t mode, st; 3522 u_int32_t idedma_ctl, scr, atapi; 3523 struct pciide_channel *cp = (struct pciide_channel*)chp; 3524 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3525 int channel = chp->channel; 3526 3527 /* setup DMA if needed */ 3528 pciide_channel_dma_setup(cp); 3529 3530 idedma_ctl = 0; 3531 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3532 sc->sc_wdcdev.sc_dev.dv_xname, 3533 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3534 DEBUG_PROBE); 3535 3536 /* Per channel settings */ 3537 if (PDC_IS_262(sc)) { 3538 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3539 PDC262_U66); 3540 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3541 /* Trimm UDMA mode */ 3542 if ((st & PDC262_STATE_80P(channel)) != 0 || 3543 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3544 chp->ch_drive[0].UDMA_mode <= 2) || 3545 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3546 chp->ch_drive[1].UDMA_mode <= 2)) { 3547 if (chp->ch_drive[0].UDMA_mode > 2) 3548 chp->ch_drive[0].UDMA_mode = 2; 3549 if (chp->ch_drive[1].UDMA_mode > 2) 3550 chp->ch_drive[1].UDMA_mode = 2; 3551 } 3552 /* Set U66 if needed */ 3553 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3554 chp->ch_drive[0].UDMA_mode > 2) || 3555 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3556 chp->ch_drive[1].UDMA_mode > 2)) 3557 scr |= PDC262_U66_EN(channel); 3558 else 3559 scr &= ~PDC262_U66_EN(channel); 3560 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3561 PDC262_U66, scr); 3562 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3563 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3564 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3565 PDC262_ATAPI(channel))), DEBUG_PROBE); 3566 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3567 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3568 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3569 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3570 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3571 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3572 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3573 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3574 atapi = 0; 3575 else 3576 atapi = PDC262_ATAPI_UDMA; 3577 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3578 PDC262_ATAPI(channel), atapi); 3579 } 3580 } 3581 for (drive = 0; drive < 2; drive++) { 3582 drvp = &chp->ch_drive[drive]; 3583 /* If no drive, skip */ 3584 if ((drvp->drive_flags & DRIVE) == 0) 3585 continue; 3586 mode = 0; 3587 if (drvp->drive_flags & DRIVE_UDMA) { 3588 /* use Ultra/DMA */ 3589 drvp->drive_flags &= ~DRIVE_DMA; 3590 mode = PDC2xx_TIM_SET_MB(mode, 3591 pdc2xx_udma_mb[drvp->UDMA_mode]); 3592 mode = PDC2xx_TIM_SET_MC(mode, 3593 pdc2xx_udma_mc[drvp->UDMA_mode]); 3594 drvp->drive_flags &= ~DRIVE_DMA; 3595 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3596 } else if (drvp->drive_flags & DRIVE_DMA) { 3597 mode = PDC2xx_TIM_SET_MB(mode, 3598 pdc2xx_dma_mb[drvp->DMA_mode]); 3599 mode = PDC2xx_TIM_SET_MC(mode, 3600 pdc2xx_dma_mc[drvp->DMA_mode]); 3601 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3602 } else { 3603 mode = PDC2xx_TIM_SET_MB(mode, 3604 pdc2xx_dma_mb[0]); 3605 mode = PDC2xx_TIM_SET_MC(mode, 3606 pdc2xx_dma_mc[0]); 3607 } 3608 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3609 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3610 if (drvp->drive_flags & DRIVE_ATA) 3611 mode |= PDC2xx_TIM_PRE; 3612 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3613 if (drvp->PIO_mode >= 3) { 3614 mode |= PDC2xx_TIM_IORDY; 3615 if (drive == 0) 3616 mode |= PDC2xx_TIM_IORDYp; 3617 } 3618 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3619 "timings 0x%x\n", 3620 sc->sc_wdcdev.sc_dev.dv_xname, 3621 chp->channel, drive, mode), DEBUG_PROBE); 3622 pci_conf_write(sc->sc_pc, sc->sc_tag, 3623 PDC2xx_TIM(chp->channel, drive), mode); 3624 } 3625 if (idedma_ctl != 0) { 3626 /* Add software bits in status register */ 3627 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3628 IDEDMA_CTL, idedma_ctl); 3629 } 3630 pciide_print_modes(cp); 3631 } 3632 3633 int 3634 pdc202xx_pci_intr(arg) 3635 void *arg; 3636 { 3637 struct pciide_softc *sc = arg; 3638 struct pciide_channel *cp; 3639 struct channel_softc *wdc_cp; 3640 int i, rv, crv; 3641 u_int32_t scr; 3642 3643 rv = 0; 3644 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3645 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3646 cp = &sc->pciide_channels[i]; 3647 wdc_cp = &cp->wdc_channel; 3648 /* If a compat channel skip. */ 3649 if (cp->compat) 3650 continue; 3651 if (scr & PDC2xx_SCR_INT(i)) { 3652 crv = wdcintr(wdc_cp); 3653 if (crv == 0) 3654 printf("%s:%d: bogus intr (reg 0x%x)\n", 3655 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3656 else 3657 rv = 1; 3658 } 3659 } 3660 return rv; 3661 } 3662 3663 int 3664 pdc20265_pci_intr(arg) 3665 void *arg; 3666 { 3667 struct pciide_softc *sc = arg; 3668 struct pciide_channel *cp; 3669 struct channel_softc *wdc_cp; 3670 int i, rv, crv; 3671 u_int32_t dmastat; 3672 3673 rv = 0; 3674 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3675 cp = &sc->pciide_channels[i]; 3676 wdc_cp = &cp->wdc_channel; 3677 /* If a compat channel skip. */ 3678 if (cp->compat) 3679 continue; 3680 /* 3681 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3682 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3683 * So use it instead (requires 2 reg reads instead of 1, 3684 * but we can't do it another way). 3685 */ 3686 dmastat = bus_space_read_1(sc->sc_dma_iot, 3687 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3688 if((dmastat & IDEDMA_CTL_INTR) == 0) 3689 continue; 3690 crv = wdcintr(wdc_cp); 3691 if (crv == 0) 3692 printf("%s:%d: bogus intr\n", 3693 sc->sc_wdcdev.sc_dev.dv_xname, i); 3694 else 3695 rv = 1; 3696 } 3697 return rv; 3698 } 3699 3700 void 3701 opti_chip_map(sc, pa) 3702 struct pciide_softc *sc; 3703 struct pci_attach_args *pa; 3704 { 3705 struct pciide_channel *cp; 3706 bus_size_t cmdsize, ctlsize; 3707 pcireg_t interface; 3708 u_int8_t init_ctrl; 3709 int channel; 3710 3711 if (pciide_chipen(sc, pa) == 0) 3712 return; 3713 printf("%s: bus-master DMA support present", 3714 sc->sc_wdcdev.sc_dev.dv_xname); 3715 3716 /* 3717 * XXXSCW: 3718 * There seem to be a couple of buggy revisions/implementations 3719 * of the OPTi pciide chipset. This kludge seems to fix one of 3720 * the reported problems (PR/11644) but still fails for the 3721 * other (PR/13151), although the latter may be due to other 3722 * issues too... 3723 */ 3724 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3725 printf(" but disabled due to chip rev. <= 0x12"); 3726 sc->sc_dma_ok = 0; 3727 sc->sc_wdcdev.cap = 0; 3728 } else { 3729 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3730 pciide_mapreg_dma(sc, pa); 3731 } 3732 printf("\n"); 3733 3734 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3735 sc->sc_wdcdev.PIO_cap = 4; 3736 if (sc->sc_dma_ok) { 3737 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3738 sc->sc_wdcdev.irqack = pciide_irqack; 3739 sc->sc_wdcdev.DMA_cap = 2; 3740 } 3741 sc->sc_wdcdev.set_modes = opti_setup_channel; 3742 3743 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3744 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3745 3746 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3747 OPTI_REG_INIT_CONTROL); 3748 3749 interface = PCI_INTERFACE(pa->pa_class); 3750 3751 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3752 cp = &sc->pciide_channels[channel]; 3753 if (pciide_chansetup(sc, channel, interface) == 0) 3754 continue; 3755 if (channel == 1 && 3756 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3757 printf("%s: %s channel ignored (disabled)\n", 3758 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3759 continue; 3760 } 3761 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3762 pciide_pci_intr); 3763 if (cp->hw_ok == 0) 3764 continue; 3765 pciide_map_compat_intr(pa, cp, channel, interface); 3766 if (cp->hw_ok == 0) 3767 continue; 3768 opti_setup_channel(&cp->wdc_channel); 3769 } 3770 } 3771 3772 void 3773 opti_setup_channel(chp) 3774 struct channel_softc *chp; 3775 { 3776 struct ata_drive_datas *drvp; 3777 struct pciide_channel *cp = (struct pciide_channel*)chp; 3778 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3779 int drive, spd; 3780 int mode[2]; 3781 u_int8_t rv, mr; 3782 3783 /* 3784 * The `Delay' and `Address Setup Time' fields of the 3785 * Miscellaneous Register are always zero initially. 3786 */ 3787 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3788 mr &= ~(OPTI_MISC_DELAY_MASK | 3789 OPTI_MISC_ADDR_SETUP_MASK | 3790 OPTI_MISC_INDEX_MASK); 3791 3792 /* Prime the control register before setting timing values */ 3793 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3794 3795 /* Determine the clockrate of the PCIbus the chip is attached to */ 3796 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3797 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3798 3799 /* setup DMA if needed */ 3800 pciide_channel_dma_setup(cp); 3801 3802 for (drive = 0; drive < 2; drive++) { 3803 drvp = &chp->ch_drive[drive]; 3804 /* If no drive, skip */ 3805 if ((drvp->drive_flags & DRIVE) == 0) { 3806 mode[drive] = -1; 3807 continue; 3808 } 3809 3810 if ((drvp->drive_flags & DRIVE_DMA)) { 3811 /* 3812 * Timings will be used for both PIO and DMA, 3813 * so adjust DMA mode if needed 3814 */ 3815 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3816 drvp->PIO_mode = drvp->DMA_mode + 2; 3817 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3818 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3819 drvp->PIO_mode - 2 : 0; 3820 if (drvp->DMA_mode == 0) 3821 drvp->PIO_mode = 0; 3822 3823 mode[drive] = drvp->DMA_mode + 5; 3824 } else 3825 mode[drive] = drvp->PIO_mode; 3826 3827 if (drive && mode[0] >= 0 && 3828 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3829 /* 3830 * Can't have two drives using different values 3831 * for `Address Setup Time'. 3832 * Slow down the faster drive to compensate. 3833 */ 3834 int d = (opti_tim_as[spd][mode[0]] > 3835 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3836 3837 mode[d] = mode[1-d]; 3838 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3839 chp->ch_drive[d].DMA_mode = 0; 3840 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3841 } 3842 } 3843 3844 for (drive = 0; drive < 2; drive++) { 3845 int m; 3846 if ((m = mode[drive]) < 0) 3847 continue; 3848 3849 /* Set the Address Setup Time and select appropriate index */ 3850 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3851 rv |= OPTI_MISC_INDEX(drive); 3852 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3853 3854 /* Set the pulse width and recovery timing parameters */ 3855 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3856 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3857 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3858 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3859 3860 /* Set the Enhanced Mode register appropriately */ 3861 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3862 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3863 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3864 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3865 } 3866 3867 /* Finally, enable the timings */ 3868 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3869 3870 pciide_print_modes(cp); 3871 } 3872 3873 #define ACARD_IS_850(sc) \ 3874 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3875 3876 void 3877 acard_chip_map(sc, pa) 3878 struct pciide_softc *sc; 3879 struct pci_attach_args *pa; 3880 { 3881 struct pciide_channel *cp; 3882 int i; 3883 pcireg_t interface; 3884 bus_size_t cmdsize, ctlsize; 3885 3886 if (pciide_chipen(sc, pa) == 0) 3887 return; 3888 3889 /* 3890 * when the chip is in native mode it identifies itself as a 3891 * 'misc mass storage'. Fake interface in this case. 3892 */ 3893 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3894 interface = PCI_INTERFACE(pa->pa_class); 3895 } else { 3896 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3897 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3898 } 3899 3900 printf("%s: bus-master DMA support present", 3901 sc->sc_wdcdev.sc_dev.dv_xname); 3902 pciide_mapreg_dma(sc, pa); 3903 printf("\n"); 3904 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3905 WDC_CAPABILITY_MODE; 3906 3907 if (sc->sc_dma_ok) { 3908 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3909 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3910 sc->sc_wdcdev.irqack = pciide_irqack; 3911 } 3912 sc->sc_wdcdev.PIO_cap = 4; 3913 sc->sc_wdcdev.DMA_cap = 2; 3914 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3915 3916 sc->sc_wdcdev.set_modes = acard_setup_channel; 3917 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3918 sc->sc_wdcdev.nchannels = 2; 3919 3920 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3921 cp = &sc->pciide_channels[i]; 3922 if (pciide_chansetup(sc, i, interface) == 0) 3923 continue; 3924 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3925 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3926 &ctlsize, pciide_pci_intr); 3927 } else { 3928 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 3929 &cmdsize, &ctlsize); 3930 } 3931 if (cp->hw_ok == 0) 3932 return; 3933 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3934 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3935 wdcattach(&cp->wdc_channel); 3936 acard_setup_channel(&cp->wdc_channel); 3937 } 3938 if (!ACARD_IS_850(sc)) { 3939 u_int32_t reg; 3940 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3941 reg &= ~ATP860_CTRL_INT; 3942 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3943 } 3944 } 3945 3946 void 3947 acard_setup_channel(chp) 3948 struct channel_softc *chp; 3949 { 3950 struct ata_drive_datas *drvp; 3951 struct pciide_channel *cp = (struct pciide_channel*)chp; 3952 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3953 int channel = chp->channel; 3954 int drive; 3955 u_int32_t idetime, udma_mode; 3956 u_int32_t idedma_ctl; 3957 3958 /* setup DMA if needed */ 3959 pciide_channel_dma_setup(cp); 3960 3961 if (ACARD_IS_850(sc)) { 3962 idetime = 0; 3963 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3964 udma_mode &= ~ATP850_UDMA_MASK(channel); 3965 } else { 3966 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3967 idetime &= ~ATP860_SETTIME_MASK(channel); 3968 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3969 udma_mode &= ~ATP860_UDMA_MASK(channel); 3970 3971 /* check 80 pins cable */ 3972 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 3973 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 3974 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3975 & ATP860_CTRL_80P(chp->channel)) { 3976 if (chp->ch_drive[0].UDMA_mode > 2) 3977 chp->ch_drive[0].UDMA_mode = 2; 3978 if (chp->ch_drive[1].UDMA_mode > 2) 3979 chp->ch_drive[1].UDMA_mode = 2; 3980 } 3981 } 3982 } 3983 3984 idedma_ctl = 0; 3985 3986 /* Per drive settings */ 3987 for (drive = 0; drive < 2; drive++) { 3988 drvp = &chp->ch_drive[drive]; 3989 /* If no drive, skip */ 3990 if ((drvp->drive_flags & DRIVE) == 0) 3991 continue; 3992 /* add timing values, setup DMA if needed */ 3993 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3994 (drvp->drive_flags & DRIVE_UDMA)) { 3995 /* use Ultra/DMA */ 3996 if (ACARD_IS_850(sc)) { 3997 idetime |= ATP850_SETTIME(drive, 3998 acard_act_udma[drvp->UDMA_mode], 3999 acard_rec_udma[drvp->UDMA_mode]); 4000 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4001 acard_udma_conf[drvp->UDMA_mode]); 4002 } else { 4003 idetime |= ATP860_SETTIME(channel, drive, 4004 acard_act_udma[drvp->UDMA_mode], 4005 acard_rec_udma[drvp->UDMA_mode]); 4006 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4007 acard_udma_conf[drvp->UDMA_mode]); 4008 } 4009 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4010 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4011 (drvp->drive_flags & DRIVE_DMA)) { 4012 /* use Multiword DMA */ 4013 drvp->drive_flags &= ~DRIVE_UDMA; 4014 if (ACARD_IS_850(sc)) { 4015 idetime |= ATP850_SETTIME(drive, 4016 acard_act_dma[drvp->DMA_mode], 4017 acard_rec_dma[drvp->DMA_mode]); 4018 } else { 4019 idetime |= ATP860_SETTIME(channel, drive, 4020 acard_act_dma[drvp->DMA_mode], 4021 acard_rec_dma[drvp->DMA_mode]); 4022 } 4023 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4024 } else { 4025 /* PIO only */ 4026 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4027 if (ACARD_IS_850(sc)) { 4028 idetime |= ATP850_SETTIME(drive, 4029 acard_act_pio[drvp->PIO_mode], 4030 acard_rec_pio[drvp->PIO_mode]); 4031 } else { 4032 idetime |= ATP860_SETTIME(channel, drive, 4033 acard_act_pio[drvp->PIO_mode], 4034 acard_rec_pio[drvp->PIO_mode]); 4035 } 4036 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4037 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4038 | ATP8x0_CTRL_EN(channel)); 4039 } 4040 } 4041 4042 if (idedma_ctl != 0) { 4043 /* Add software bits in status register */ 4044 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4045 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4046 } 4047 pciide_print_modes(cp); 4048 4049 if (ACARD_IS_850(sc)) { 4050 pci_conf_write(sc->sc_pc, sc->sc_tag, 4051 ATP850_IDETIME(channel), idetime); 4052 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4053 } else { 4054 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4055 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4056 } 4057 } 4058 4059 int 4060 acard_pci_intr(arg) 4061 void *arg; 4062 { 4063 struct pciide_softc *sc = arg; 4064 struct pciide_channel *cp; 4065 struct channel_softc *wdc_cp; 4066 int rv = 0; 4067 int dmastat, i, crv; 4068 4069 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4070 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4071 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4072 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4073 continue; 4074 cp = &sc->pciide_channels[i]; 4075 wdc_cp = &cp->wdc_channel; 4076 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4077 (void)wdcintr(wdc_cp); 4078 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4079 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4080 continue; 4081 } 4082 crv = wdcintr(wdc_cp); 4083 if (crv == 0) 4084 printf("%s:%d: bogus intr\n", 4085 sc->sc_wdcdev.sc_dev.dv_xname, i); 4086 else if (crv == 1) 4087 rv = 1; 4088 else if (rv == 0) 4089 rv = crv; 4090 } 4091 return rv; 4092 } 4093
Indexes created Thu Oct 02 10:09:58 GMT 2025