pciide.c revision 1.115
1 /* $NetBSD: pciide.c,v 1.115 2001/05/06 14:32:35 fvdl Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/pciide_acard_reg.h> 119 #include <dev/pci/cy82c693var.h> 120 121 #include "opt_pciide.h" 122 123 /* inlines for reading/writing 8-bit PCI registers */ 124 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 125 int)); 126 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 127 int, u_int8_t)); 128 129 static __inline u_int8_t 130 pciide_pci_read(pc, pa, reg) 131 pci_chipset_tag_t pc; 132 pcitag_t pa; 133 int reg; 134 { 135 136 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 137 ((reg & 0x03) * 8) & 0xff); 138 } 139 140 static __inline void 141 pciide_pci_write(pc, pa, reg, val) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 u_int8_t val; 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 156 157 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 void piix_setup_channel __P((struct channel_softc*)); 159 void piix3_4_setup_channel __P((struct channel_softc*)); 160 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 161 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 162 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 164 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void amd756_setup_channel __P((struct channel_softc*)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 void cmd646_9_irqack __P((struct channel_softc *)); 177 178 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cy693_setup_channel __P((struct channel_softc*)); 180 181 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void sis_setup_channel __P((struct channel_softc*)); 183 184 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void acer_setup_channel __P((struct channel_softc*)); 186 int acer_pci_intr __P((void *)); 187 188 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void pdc202xx_setup_channel __P((struct channel_softc*)); 190 int pdc202xx_pci_intr __P((void *)); 191 int pdc20265_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void acard_setup_channel __P((struct channel_softc*)); 202 int acard_pci_intr __P((void *)); 203 204 void pciide_channel_dma_setup __P((struct pciide_channel *)); 205 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 206 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 207 void pciide_dma_start __P((void*, int, int)); 208 int pciide_dma_finish __P((void*, int, int, int)); 209 void pciide_irqack __P((struct channel_softc *)); 210 void pciide_print_modes __P((struct pciide_channel *)); 211 212 struct pciide_product_desc { 213 u_int32_t ide_product; 214 int ide_flags; 215 const char *ide_name; 216 /* map and setup chip, probe drives */ 217 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 218 }; 219 220 /* Flags for ide_flags */ 221 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 222 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 223 224 /* Default product description for devices not known from this controller */ 225 const struct pciide_product_desc default_product_desc = { 226 0, 227 0, 228 "Generic PCI IDE controller", 229 default_chip_map, 230 }; 231 232 const struct pciide_product_desc pciide_intel_products[] = { 233 { PCI_PRODUCT_INTEL_82092AA, 234 0, 235 "Intel 82092AA IDE controller", 236 default_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82371FB_IDE, 239 0, 240 "Intel 82371FB IDE controller (PIIX)", 241 piix_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_82371SB_IDE, 244 0, 245 "Intel 82371SB IDE Interface (PIIX3)", 246 piix_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82371AB_IDE, 249 0, 250 "Intel 82371AB IDE controller (PIIX4)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82440MX_IDE, 254 0, 255 "Intel 82440MX IDE controller", 256 piix_chip_map 257 }, 258 { PCI_PRODUCT_INTEL_82801AA_IDE, 259 0, 260 "Intel 82801AA IDE Controller (ICH)", 261 piix_chip_map, 262 }, 263 { PCI_PRODUCT_INTEL_82801AB_IDE, 264 0, 265 "Intel 82801AB IDE Controller (ICH0)", 266 piix_chip_map, 267 }, 268 { PCI_PRODUCT_INTEL_82801BA_IDE, 269 0, 270 "Intel 82801BA IDE Controller (ICH2)", 271 piix_chip_map, 272 }, 273 { PCI_PRODUCT_INTEL_82801BAM_IDE, 274 0, 275 "Intel 82801BAM IDE Controller (ICH2)", 276 piix_chip_map, 277 }, 278 { 0, 279 0, 280 NULL, 281 NULL 282 } 283 }; 284 285 const struct pciide_product_desc pciide_amd_products[] = { 286 { PCI_PRODUCT_AMD_PBC756_IDE, 287 0, 288 "Advanced Micro Devices AMD756 IDE Controller", 289 amd756_chip_map 290 }, 291 { 0, 292 0, 293 NULL, 294 NULL 295 } 296 }; 297 298 const struct pciide_product_desc pciide_cmd_products[] = { 299 { PCI_PRODUCT_CMDTECH_640, 300 0, 301 "CMD Technology PCI0640", 302 cmd_chip_map 303 }, 304 { PCI_PRODUCT_CMDTECH_643, 305 0, 306 "CMD Technology PCI0643", 307 cmd0643_9_chip_map, 308 }, 309 { PCI_PRODUCT_CMDTECH_646, 310 0, 311 "CMD Technology PCI0646", 312 cmd0643_9_chip_map, 313 }, 314 { PCI_PRODUCT_CMDTECH_648, 315 IDE_PCI_CLASS_OVERRIDE, 316 "CMD Technology PCI0648", 317 cmd0643_9_chip_map, 318 }, 319 { PCI_PRODUCT_CMDTECH_649, 320 IDE_PCI_CLASS_OVERRIDE, 321 "CMD Technology PCI0649", 322 cmd0643_9_chip_map, 323 }, 324 { 0, 325 0, 326 NULL, 327 NULL 328 } 329 }; 330 331 const struct pciide_product_desc pciide_via_products[] = { 332 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 333 0, 334 NULL, 335 apollo_chip_map, 336 }, 337 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 338 0, 339 NULL, 340 apollo_chip_map, 341 }, 342 { 0, 343 0, 344 NULL, 345 NULL 346 } 347 }; 348 349 const struct pciide_product_desc pciide_cypress_products[] = { 350 { PCI_PRODUCT_CONTAQ_82C693, 351 IDE_16BIT_IOSPACE, 352 "Cypress 82C693 IDE Controller", 353 cy693_chip_map, 354 }, 355 { 0, 356 0, 357 NULL, 358 NULL 359 } 360 }; 361 362 const struct pciide_product_desc pciide_sis_products[] = { 363 { PCI_PRODUCT_SIS_5597_IDE, 364 0, 365 "Silicon Integrated System 5597/5598 IDE controller", 366 sis_chip_map, 367 }, 368 { 0, 369 0, 370 NULL, 371 NULL 372 } 373 }; 374 375 const struct pciide_product_desc pciide_acer_products[] = { 376 { PCI_PRODUCT_ALI_M5229, 377 0, 378 "Acer Labs M5229 UDMA IDE Controller", 379 acer_chip_map, 380 }, 381 { 0, 382 0, 383 NULL, 384 NULL 385 } 386 }; 387 388 const struct pciide_product_desc pciide_promise_products[] = { 389 { PCI_PRODUCT_PROMISE_ULTRA33, 390 IDE_PCI_CLASS_OVERRIDE, 391 "Promise Ultra33/ATA Bus Master IDE Accelerator", 392 pdc202xx_chip_map, 393 }, 394 { PCI_PRODUCT_PROMISE_ULTRA66, 395 IDE_PCI_CLASS_OVERRIDE, 396 "Promise Ultra66/ATA Bus Master IDE Accelerator", 397 pdc202xx_chip_map, 398 }, 399 { PCI_PRODUCT_PROMISE_ULTRA100, 400 IDE_PCI_CLASS_OVERRIDE, 401 "Promise Ultra100/ATA Bus Master IDE Accelerator", 402 pdc202xx_chip_map, 403 }, 404 { PCI_PRODUCT_PROMISE_ULTRA100X, 405 IDE_PCI_CLASS_OVERRIDE, 406 "Promise Ultra100/ATA Bus Master IDE Accelerator", 407 pdc202xx_chip_map, 408 }, 409 { 0, 410 0, 411 NULL, 412 NULL 413 } 414 }; 415 416 const struct pciide_product_desc pciide_opti_products[] = { 417 { PCI_PRODUCT_OPTI_82C621, 418 0, 419 "OPTi 82c621 PCI IDE controller", 420 opti_chip_map, 421 }, 422 { PCI_PRODUCT_OPTI_82C568, 423 0, 424 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 425 opti_chip_map, 426 }, 427 { PCI_PRODUCT_OPTI_82D568, 428 0, 429 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 430 opti_chip_map, 431 }, 432 { 0, 433 0, 434 NULL, 435 NULL 436 } 437 }; 438 439 const struct pciide_product_desc pciide_triones_products[] = { 440 { PCI_PRODUCT_TRIONES_HPT366, 441 IDE_PCI_CLASS_OVERRIDE, 442 NULL, 443 hpt_chip_map, 444 }, 445 { 0, 446 0, 447 NULL, 448 NULL 449 } 450 }; 451 452 const struct pciide_product_desc pciide_acard_products[] = { 453 { PCI_PRODUCT_ACARD_ATP850U, 454 IDE_PCI_CLASS_OVERRIDE, 455 "Acard ATP850U Ultra33 IDE Controller", 456 acard_chip_map, 457 }, 458 { PCI_PRODUCT_ACARD_ATP860, 459 IDE_PCI_CLASS_OVERRIDE, 460 "Acard ATP860 Ultra66 IDE Controller", 461 acard_chip_map, 462 }, 463 { PCI_PRODUCT_ACARD_ATP860A, 464 IDE_PCI_CLASS_OVERRIDE, 465 "Acard ATP860-A Ultra66 IDE Controller", 466 acard_chip_map, 467 }, 468 { 0, 469 0, 470 NULL, 471 NULL 472 } 473 }; 474 475 struct pciide_vendor_desc { 476 u_int32_t ide_vendor; 477 const struct pciide_product_desc *ide_products; 478 }; 479 480 const struct pciide_vendor_desc pciide_vendors[] = { 481 { PCI_VENDOR_INTEL, pciide_intel_products }, 482 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 483 { PCI_VENDOR_VIATECH, pciide_via_products }, 484 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 485 { PCI_VENDOR_SIS, pciide_sis_products }, 486 { PCI_VENDOR_ALI, pciide_acer_products }, 487 { PCI_VENDOR_PROMISE, pciide_promise_products }, 488 { PCI_VENDOR_AMD, pciide_amd_products }, 489 { PCI_VENDOR_OPTI, pciide_opti_products }, 490 { PCI_VENDOR_TRIONES, pciide_triones_products }, 491 #ifdef PCIIDE_ACARD_ENABLE 492 { PCI_VENDOR_ACARD, pciide_acard_products }, 493 #endif 494 { 0, NULL } 495 }; 496 497 /* options passed via the 'flags' config keyword */ 498 #define PCIIDE_OPTIONS_DMA 0x01 499 500 int pciide_match __P((struct device *, struct cfdata *, void *)); 501 void pciide_attach __P((struct device *, struct device *, void *)); 502 503 struct cfattach pciide_ca = { 504 sizeof(struct pciide_softc), pciide_match, pciide_attach 505 }; 506 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 507 int pciide_mapregs_compat __P(( struct pci_attach_args *, 508 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 509 int pciide_mapregs_native __P((struct pci_attach_args *, 510 struct pciide_channel *, bus_size_t *, bus_size_t *, 511 int (*pci_intr) __P((void *)))); 512 void pciide_mapreg_dma __P((struct pciide_softc *, 513 struct pci_attach_args *)); 514 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 515 void pciide_mapchan __P((struct pci_attach_args *, 516 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 517 int (*pci_intr) __P((void *)))); 518 int pciide_chan_candisable __P((struct pciide_channel *)); 519 void pciide_map_compat_intr __P(( struct pci_attach_args *, 520 struct pciide_channel *, int, int)); 521 int pciide_print __P((void *, const char *pnp)); 522 int pciide_compat_intr __P((void *)); 523 int pciide_pci_intr __P((void *)); 524 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 525 526 const struct pciide_product_desc * 527 pciide_lookup_product(id) 528 u_int32_t id; 529 { 530 const struct pciide_product_desc *pp; 531 const struct pciide_vendor_desc *vp; 532 533 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 534 if (PCI_VENDOR(id) == vp->ide_vendor) 535 break; 536 537 if ((pp = vp->ide_products) == NULL) 538 return NULL; 539 540 for (; pp->chip_map != NULL; pp++) 541 if (PCI_PRODUCT(id) == pp->ide_product) 542 break; 543 544 if (pp->chip_map == NULL) 545 return NULL; 546 return pp; 547 } 548 549 int 550 pciide_match(parent, match, aux) 551 struct device *parent; 552 struct cfdata *match; 553 void *aux; 554 { 555 struct pci_attach_args *pa = aux; 556 const struct pciide_product_desc *pp; 557 558 /* 559 * Check the ID register to see that it's a PCI IDE controller. 560 * If it is, we assume that we can deal with it; it _should_ 561 * work in a standardized way... 562 */ 563 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 564 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 565 return (1); 566 } 567 568 /* 569 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 570 * controllers. Let see if we can deal with it anyway. 571 */ 572 pp = pciide_lookup_product(pa->pa_id); 573 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 574 return (1); 575 } 576 577 return (0); 578 } 579 580 void 581 pciide_attach(parent, self, aux) 582 struct device *parent, *self; 583 void *aux; 584 { 585 struct pci_attach_args *pa = aux; 586 pci_chipset_tag_t pc = pa->pa_pc; 587 pcitag_t tag = pa->pa_tag; 588 struct pciide_softc *sc = (struct pciide_softc *)self; 589 pcireg_t csr; 590 char devinfo[256]; 591 const char *displaydev; 592 593 sc->sc_pp = pciide_lookup_product(pa->pa_id); 594 if (sc->sc_pp == NULL) { 595 sc->sc_pp = &default_product_desc; 596 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 597 displaydev = devinfo; 598 } else 599 displaydev = sc->sc_pp->ide_name; 600 601 /* if displaydev == NULL, printf is done in chip-specific map */ 602 if (displaydev) 603 printf(": %s (rev. 0x%02x)\n", displaydev, 604 PCI_REVISION(pa->pa_class)); 605 606 sc->sc_pc = pa->pa_pc; 607 sc->sc_tag = pa->pa_tag; 608 #ifdef WDCDEBUG 609 if (wdcdebug_pciide_mask & DEBUG_PROBE) 610 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 611 #endif 612 sc->sc_pp->chip_map(sc, pa); 613 614 if (sc->sc_dma_ok) { 615 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 616 csr |= PCI_COMMAND_MASTER_ENABLE; 617 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 618 } 619 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 620 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 621 } 622 623 /* tell wether the chip is enabled or not */ 624 int 625 pciide_chipen(sc, pa) 626 struct pciide_softc *sc; 627 struct pci_attach_args *pa; 628 { 629 pcireg_t csr; 630 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 631 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 632 PCI_COMMAND_STATUS_REG); 633 printf("%s: device disabled (at %s)\n", 634 sc->sc_wdcdev.sc_dev.dv_xname, 635 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 636 "device" : "bridge"); 637 return 0; 638 } 639 return 1; 640 } 641 642 int 643 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 644 struct pci_attach_args *pa; 645 struct pciide_channel *cp; 646 int compatchan; 647 bus_size_t *cmdsizep, *ctlsizep; 648 { 649 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 650 struct channel_softc *wdc_cp = &cp->wdc_channel; 651 652 cp->compat = 1; 653 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 654 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 655 656 wdc_cp->cmd_iot = pa->pa_iot; 657 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 658 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 659 printf("%s: couldn't map %s channel cmd regs\n", 660 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 661 return (0); 662 } 663 664 wdc_cp->ctl_iot = pa->pa_iot; 665 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 666 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 667 printf("%s: couldn't map %s channel ctl regs\n", 668 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 669 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 670 PCIIDE_COMPAT_CMD_SIZE); 671 return (0); 672 } 673 674 return (1); 675 } 676 677 int 678 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 679 struct pci_attach_args * pa; 680 struct pciide_channel *cp; 681 bus_size_t *cmdsizep, *ctlsizep; 682 int (*pci_intr) __P((void *)); 683 { 684 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 685 struct channel_softc *wdc_cp = &cp->wdc_channel; 686 const char *intrstr; 687 pci_intr_handle_t intrhandle; 688 689 cp->compat = 0; 690 691 if (sc->sc_pci_ih == NULL) { 692 if (pci_intr_map(pa, &intrhandle) != 0) { 693 printf("%s: couldn't map native-PCI interrupt\n", 694 sc->sc_wdcdev.sc_dev.dv_xname); 695 return 0; 696 } 697 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 698 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 699 intrhandle, IPL_BIO, pci_intr, sc); 700 if (sc->sc_pci_ih != NULL) { 701 printf("%s: using %s for native-PCI interrupt\n", 702 sc->sc_wdcdev.sc_dev.dv_xname, 703 intrstr ? intrstr : "unknown interrupt"); 704 } else { 705 printf("%s: couldn't establish native-PCI interrupt", 706 sc->sc_wdcdev.sc_dev.dv_xname); 707 if (intrstr != NULL) 708 printf(" at %s", intrstr); 709 printf("\n"); 710 return 0; 711 } 712 } 713 cp->ih = sc->sc_pci_ih; 714 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 715 PCI_MAPREG_TYPE_IO, 0, 716 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 717 printf("%s: couldn't map %s channel cmd regs\n", 718 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 719 return 0; 720 } 721 722 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 723 PCI_MAPREG_TYPE_IO, 0, 724 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 725 printf("%s: couldn't map %s channel ctl regs\n", 726 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 727 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 728 return 0; 729 } 730 /* 731 * In native mode, 4 bytes of I/O space are mapped for the control 732 * register, the control register is at offset 2. Pass the generic 733 * code a handle for only one byte at the rigth offset. 734 */ 735 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 736 &wdc_cp->ctl_ioh) != 0) { 737 printf("%s: unable to subregion %s channel ctl regs\n", 738 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 739 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 740 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 741 return 0; 742 } 743 return (1); 744 } 745 746 void 747 pciide_mapreg_dma(sc, pa) 748 struct pciide_softc *sc; 749 struct pci_attach_args *pa; 750 { 751 pcireg_t maptype; 752 bus_addr_t addr; 753 754 /* 755 * Map DMA registers 756 * 757 * Note that sc_dma_ok is the right variable to test to see if 758 * DMA can be done. If the interface doesn't support DMA, 759 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 760 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 761 * non-zero if the interface supports DMA and the registers 762 * could be mapped. 763 * 764 * XXX Note that despite the fact that the Bus Master IDE specs 765 * XXX say that "The bus master IDE function uses 16 bytes of IO 766 * XXX space," some controllers (at least the United 767 * XXX Microelectronics UM8886BF) place it in memory space. 768 */ 769 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 770 PCIIDE_REG_BUS_MASTER_DMA); 771 772 switch (maptype) { 773 case PCI_MAPREG_TYPE_IO: 774 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 775 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 776 &addr, NULL, NULL) == 0); 777 if (sc->sc_dma_ok == 0) { 778 printf(", but unused (couldn't query registers)"); 779 break; 780 } 781 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 782 && addr >= 0x10000) { 783 sc->sc_dma_ok = 0; 784 printf(", but unused (registers at unsafe address %#lx)", (unsigned long)addr); 785 break; 786 } 787 /* FALLTHROUGH */ 788 789 case PCI_MAPREG_MEM_TYPE_32BIT: 790 sc->sc_dma_ok = (pci_mapreg_map(pa, 791 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 792 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 793 sc->sc_dmat = pa->pa_dmat; 794 if (sc->sc_dma_ok == 0) { 795 printf(", but unused (couldn't map registers)"); 796 } else { 797 sc->sc_wdcdev.dma_arg = sc; 798 sc->sc_wdcdev.dma_init = pciide_dma_init; 799 sc->sc_wdcdev.dma_start = pciide_dma_start; 800 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 801 } 802 break; 803 804 default: 805 sc->sc_dma_ok = 0; 806 printf(", but unsupported register maptype (0x%x)", maptype); 807 } 808 } 809 810 int 811 pciide_compat_intr(arg) 812 void *arg; 813 { 814 struct pciide_channel *cp = arg; 815 816 #ifdef DIAGNOSTIC 817 /* should only be called for a compat channel */ 818 if (cp->compat == 0) 819 panic("pciide compat intr called for non-compat chan %p\n", cp); 820 #endif 821 return (wdcintr(&cp->wdc_channel)); 822 } 823 824 int 825 pciide_pci_intr(arg) 826 void *arg; 827 { 828 struct pciide_softc *sc = arg; 829 struct pciide_channel *cp; 830 struct channel_softc *wdc_cp; 831 int i, rv, crv; 832 833 rv = 0; 834 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 835 cp = &sc->pciide_channels[i]; 836 wdc_cp = &cp->wdc_channel; 837 838 /* If a compat channel skip. */ 839 if (cp->compat) 840 continue; 841 /* if this channel not waiting for intr, skip */ 842 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 843 continue; 844 845 crv = wdcintr(wdc_cp); 846 if (crv == 0) 847 ; /* leave rv alone */ 848 else if (crv == 1) 849 rv = 1; /* claim the intr */ 850 else if (rv == 0) /* crv should be -1 in this case */ 851 rv = crv; /* if we've done no better, take it */ 852 } 853 return (rv); 854 } 855 856 void 857 pciide_channel_dma_setup(cp) 858 struct pciide_channel *cp; 859 { 860 int drive; 861 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 862 struct ata_drive_datas *drvp; 863 864 for (drive = 0; drive < 2; drive++) { 865 drvp = &cp->wdc_channel.ch_drive[drive]; 866 /* If no drive, skip */ 867 if ((drvp->drive_flags & DRIVE) == 0) 868 continue; 869 /* setup DMA if needed */ 870 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 871 (drvp->drive_flags & DRIVE_UDMA) == 0) || 872 sc->sc_dma_ok == 0) { 873 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 874 continue; 875 } 876 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 877 != 0) { 878 /* Abort DMA setup */ 879 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 880 continue; 881 } 882 } 883 } 884 885 int 886 pciide_dma_table_setup(sc, channel, drive) 887 struct pciide_softc *sc; 888 int channel, drive; 889 { 890 bus_dma_segment_t seg; 891 int error, rseg; 892 const bus_size_t dma_table_size = 893 sizeof(struct idedma_table) * NIDEDMA_TABLES; 894 struct pciide_dma_maps *dma_maps = 895 &sc->pciide_channels[channel].dma_maps[drive]; 896 897 /* If table was already allocated, just return */ 898 if (dma_maps->dma_table) 899 return 0; 900 901 /* Allocate memory for the DMA tables and map it */ 902 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 903 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 904 BUS_DMA_NOWAIT)) != 0) { 905 printf("%s:%d: unable to allocate table DMA for " 906 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 907 channel, drive, error); 908 return error; 909 } 910 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 911 dma_table_size, 912 (caddr_t *)&dma_maps->dma_table, 913 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 914 printf("%s:%d: unable to map table DMA for" 915 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 916 channel, drive, error); 917 return error; 918 } 919 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 920 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 921 (unsigned long)seg.ds_addr), DEBUG_PROBE); 922 923 /* Create and load table DMA map for this disk */ 924 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 925 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 926 &dma_maps->dmamap_table)) != 0) { 927 printf("%s:%d: unable to create table DMA map for " 928 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 929 channel, drive, error); 930 return error; 931 } 932 if ((error = bus_dmamap_load(sc->sc_dmat, 933 dma_maps->dmamap_table, 934 dma_maps->dma_table, 935 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 936 printf("%s:%d: unable to load table DMA map for " 937 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 938 channel, drive, error); 939 return error; 940 } 941 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 942 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 943 DEBUG_PROBE); 944 /* Create a xfer DMA map for this drive */ 945 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 946 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 947 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 948 &dma_maps->dmamap_xfer)) != 0) { 949 printf("%s:%d: unable to create xfer DMA map for " 950 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 951 channel, drive, error); 952 return error; 953 } 954 return 0; 955 } 956 957 int 958 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 959 void *v; 960 int channel, drive; 961 void *databuf; 962 size_t datalen; 963 int flags; 964 { 965 struct pciide_softc *sc = v; 966 int error, seg; 967 struct pciide_dma_maps *dma_maps = 968 &sc->pciide_channels[channel].dma_maps[drive]; 969 970 error = bus_dmamap_load(sc->sc_dmat, 971 dma_maps->dmamap_xfer, 972 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING); 973 if (error) { 974 printf("%s:%d: unable to load xfer DMA map for" 975 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 976 channel, drive, error); 977 return error; 978 } 979 980 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 981 dma_maps->dmamap_xfer->dm_mapsize, 982 (flags & WDC_DMA_READ) ? 983 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 984 985 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 986 #ifdef DIAGNOSTIC 987 /* A segment must not cross a 64k boundary */ 988 { 989 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 990 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 991 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 992 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 993 printf("pciide_dma: segment %d physical addr 0x%lx" 994 " len 0x%lx not properly aligned\n", 995 seg, phys, len); 996 panic("pciide_dma: buf align"); 997 } 998 } 999 #endif 1000 dma_maps->dma_table[seg].base_addr = 1001 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1002 dma_maps->dma_table[seg].byte_count = 1003 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1004 IDEDMA_BYTE_COUNT_MASK); 1005 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1006 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1007 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1008 1009 } 1010 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1011 htole32(IDEDMA_BYTE_COUNT_EOT); 1012 1013 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1014 dma_maps->dmamap_table->dm_mapsize, 1015 BUS_DMASYNC_PREWRITE); 1016 1017 /* Maps are ready. Start DMA function */ 1018 #ifdef DIAGNOSTIC 1019 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1020 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1021 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1022 panic("pciide_dma_init: table align"); 1023 } 1024 #endif 1025 1026 /* Clear status bits */ 1027 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1028 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1029 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1030 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1031 /* Write table addr */ 1032 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1033 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1034 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1035 /* set read/write */ 1036 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1037 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1038 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1039 /* remember flags */ 1040 dma_maps->dma_flags = flags; 1041 return 0; 1042 } 1043 1044 void 1045 pciide_dma_start(v, channel, drive) 1046 void *v; 1047 int channel, drive; 1048 { 1049 struct pciide_softc *sc = v; 1050 1051 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1052 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1053 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1054 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1055 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1056 } 1057 1058 int 1059 pciide_dma_finish(v, channel, drive, force) 1060 void *v; 1061 int channel, drive; 1062 int force; 1063 { 1064 struct pciide_softc *sc = v; 1065 u_int8_t status; 1066 int error = 0; 1067 struct pciide_dma_maps *dma_maps = 1068 &sc->pciide_channels[channel].dma_maps[drive]; 1069 1070 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1071 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1072 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1073 DEBUG_XFERS); 1074 1075 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1076 return WDC_DMAST_NOIRQ; 1077 1078 /* stop DMA channel */ 1079 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1080 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1081 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1082 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1083 1084 /* Unload the map of the data buffer */ 1085 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1086 dma_maps->dmamap_xfer->dm_mapsize, 1087 (dma_maps->dma_flags & WDC_DMA_READ) ? 1088 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1089 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1090 1091 if ((status & IDEDMA_CTL_ERR) != 0) { 1092 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1093 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1094 error |= WDC_DMAST_ERR; 1095 } 1096 1097 if ((status & IDEDMA_CTL_INTR) == 0) { 1098 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1099 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1100 drive, status); 1101 error |= WDC_DMAST_NOIRQ; 1102 } 1103 1104 if ((status & IDEDMA_CTL_ACT) != 0) { 1105 /* data underrun, may be a valid condition for ATAPI */ 1106 error |= WDC_DMAST_UNDER; 1107 } 1108 return error; 1109 } 1110 1111 void 1112 pciide_irqack(chp) 1113 struct channel_softc *chp; 1114 { 1115 struct pciide_channel *cp = (struct pciide_channel*)chp; 1116 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1117 1118 /* clear status bits in IDE DMA registers */ 1119 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1120 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1121 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1122 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1123 } 1124 1125 /* some common code used by several chip_map */ 1126 int 1127 pciide_chansetup(sc, channel, interface) 1128 struct pciide_softc *sc; 1129 int channel; 1130 pcireg_t interface; 1131 { 1132 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1133 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1134 cp->name = PCIIDE_CHANNEL_NAME(channel); 1135 cp->wdc_channel.channel = channel; 1136 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1137 cp->wdc_channel.ch_queue = 1138 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1139 if (cp->wdc_channel.ch_queue == NULL) { 1140 printf("%s %s channel: " 1141 "can't allocate memory for command queue", 1142 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1143 return 0; 1144 } 1145 printf("%s: %s channel %s to %s mode\n", 1146 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1147 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1148 "configured" : "wired", 1149 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1150 "native-PCI" : "compatibility"); 1151 return 1; 1152 } 1153 1154 /* some common code used by several chip channel_map */ 1155 void 1156 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1157 struct pci_attach_args *pa; 1158 struct pciide_channel *cp; 1159 pcireg_t interface; 1160 bus_size_t *cmdsizep, *ctlsizep; 1161 int (*pci_intr) __P((void *)); 1162 { 1163 struct channel_softc *wdc_cp = &cp->wdc_channel; 1164 1165 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1166 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1167 pci_intr); 1168 else 1169 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1170 wdc_cp->channel, cmdsizep, ctlsizep); 1171 1172 if (cp->hw_ok == 0) 1173 return; 1174 wdc_cp->data32iot = wdc_cp->cmd_iot; 1175 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1176 wdcattach(wdc_cp); 1177 } 1178 1179 /* 1180 * Generic code to call to know if a channel can be disabled. Return 1 1181 * if channel can be disabled, 0 if not 1182 */ 1183 int 1184 pciide_chan_candisable(cp) 1185 struct pciide_channel *cp; 1186 { 1187 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1188 struct channel_softc *wdc_cp = &cp->wdc_channel; 1189 1190 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1191 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1192 printf("%s: disabling %s channel (no drives)\n", 1193 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1194 cp->hw_ok = 0; 1195 return 1; 1196 } 1197 return 0; 1198 } 1199 1200 /* 1201 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1202 * Set hw_ok=0 on failure 1203 */ 1204 void 1205 pciide_map_compat_intr(pa, cp, compatchan, interface) 1206 struct pci_attach_args *pa; 1207 struct pciide_channel *cp; 1208 int compatchan, interface; 1209 { 1210 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1211 struct channel_softc *wdc_cp = &cp->wdc_channel; 1212 1213 if (cp->hw_ok == 0) 1214 return; 1215 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1216 return; 1217 1218 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1219 pa, compatchan, pciide_compat_intr, cp); 1220 if (cp->ih == NULL) { 1221 printf("%s: no compatibility interrupt for use by %s " 1222 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1223 cp->hw_ok = 0; 1224 } 1225 } 1226 1227 void 1228 pciide_print_modes(cp) 1229 struct pciide_channel *cp; 1230 { 1231 wdc_print_modes(&cp->wdc_channel); 1232 } 1233 1234 void 1235 default_chip_map(sc, pa) 1236 struct pciide_softc *sc; 1237 struct pci_attach_args *pa; 1238 { 1239 struct pciide_channel *cp; 1240 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1241 pcireg_t csr; 1242 int channel, drive; 1243 struct ata_drive_datas *drvp; 1244 u_int8_t idedma_ctl; 1245 bus_size_t cmdsize, ctlsize; 1246 char *failreason; 1247 1248 if (pciide_chipen(sc, pa) == 0) 1249 return; 1250 1251 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1252 printf("%s: bus-master DMA support present", 1253 sc->sc_wdcdev.sc_dev.dv_xname); 1254 if (sc->sc_pp == &default_product_desc && 1255 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1256 PCIIDE_OPTIONS_DMA) == 0) { 1257 printf(", but unused (no driver support)"); 1258 sc->sc_dma_ok = 0; 1259 } else { 1260 pciide_mapreg_dma(sc, pa); 1261 if (sc->sc_dma_ok != 0) 1262 printf(", used without full driver " 1263 "support"); 1264 } 1265 } else { 1266 printf("%s: hardware does not support DMA", 1267 sc->sc_wdcdev.sc_dev.dv_xname); 1268 sc->sc_dma_ok = 0; 1269 } 1270 printf("\n"); 1271 if (sc->sc_dma_ok) { 1272 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1273 sc->sc_wdcdev.irqack = pciide_irqack; 1274 } 1275 sc->sc_wdcdev.PIO_cap = 0; 1276 sc->sc_wdcdev.DMA_cap = 0; 1277 1278 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1279 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1280 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1281 1282 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1283 cp = &sc->pciide_channels[channel]; 1284 if (pciide_chansetup(sc, channel, interface) == 0) 1285 continue; 1286 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1287 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1288 &ctlsize, pciide_pci_intr); 1289 } else { 1290 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1291 channel, &cmdsize, &ctlsize); 1292 } 1293 if (cp->hw_ok == 0) 1294 continue; 1295 /* 1296 * Check to see if something appears to be there. 1297 */ 1298 failreason = NULL; 1299 if (!wdcprobe(&cp->wdc_channel)) { 1300 failreason = "not responding; disabled or no drives?"; 1301 goto next; 1302 } 1303 /* 1304 * Now, make sure it's actually attributable to this PCI IDE 1305 * channel by trying to access the channel again while the 1306 * PCI IDE controller's I/O space is disabled. (If the 1307 * channel no longer appears to be there, it belongs to 1308 * this controller.) YUCK! 1309 */ 1310 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1311 PCI_COMMAND_STATUS_REG); 1312 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1313 csr & ~PCI_COMMAND_IO_ENABLE); 1314 if (wdcprobe(&cp->wdc_channel)) 1315 failreason = "other hardware responding at addresses"; 1316 pci_conf_write(sc->sc_pc, sc->sc_tag, 1317 PCI_COMMAND_STATUS_REG, csr); 1318 next: 1319 if (failreason) { 1320 printf("%s: %s channel ignored (%s)\n", 1321 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1322 failreason); 1323 cp->hw_ok = 0; 1324 bus_space_unmap(cp->wdc_channel.cmd_iot, 1325 cp->wdc_channel.cmd_ioh, cmdsize); 1326 bus_space_unmap(cp->wdc_channel.ctl_iot, 1327 cp->wdc_channel.ctl_ioh, ctlsize); 1328 } else { 1329 pciide_map_compat_intr(pa, cp, channel, interface); 1330 } 1331 if (cp->hw_ok) { 1332 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1333 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1334 wdcattach(&cp->wdc_channel); 1335 } 1336 } 1337 1338 if (sc->sc_dma_ok == 0) 1339 return; 1340 1341 /* Allocate DMA maps */ 1342 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1343 idedma_ctl = 0; 1344 cp = &sc->pciide_channels[channel]; 1345 for (drive = 0; drive < 2; drive++) { 1346 drvp = &cp->wdc_channel.ch_drive[drive]; 1347 /* If no drive, skip */ 1348 if ((drvp->drive_flags & DRIVE) == 0) 1349 continue; 1350 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1351 continue; 1352 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1353 /* Abort DMA setup */ 1354 printf("%s:%d:%d: can't allocate DMA maps, " 1355 "using PIO transfers\n", 1356 sc->sc_wdcdev.sc_dev.dv_xname, 1357 channel, drive); 1358 drvp->drive_flags &= ~DRIVE_DMA; 1359 } 1360 printf("%s:%d:%d: using DMA data transfers\n", 1361 sc->sc_wdcdev.sc_dev.dv_xname, 1362 channel, drive); 1363 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1364 } 1365 if (idedma_ctl != 0) { 1366 /* Add software bits in status register */ 1367 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1368 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1369 idedma_ctl); 1370 } 1371 } 1372 } 1373 1374 void 1375 piix_chip_map(sc, pa) 1376 struct pciide_softc *sc; 1377 struct pci_attach_args *pa; 1378 { 1379 struct pciide_channel *cp; 1380 int channel; 1381 u_int32_t idetim; 1382 bus_size_t cmdsize, ctlsize; 1383 1384 if (pciide_chipen(sc, pa) == 0) 1385 return; 1386 1387 printf("%s: bus-master DMA support present", 1388 sc->sc_wdcdev.sc_dev.dv_xname); 1389 pciide_mapreg_dma(sc, pa); 1390 printf("\n"); 1391 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1392 WDC_CAPABILITY_MODE; 1393 if (sc->sc_dma_ok) { 1394 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1395 sc->sc_wdcdev.irqack = pciide_irqack; 1396 switch(sc->sc_pp->ide_product) { 1397 case PCI_PRODUCT_INTEL_82371AB_IDE: 1398 case PCI_PRODUCT_INTEL_82440MX_IDE: 1399 case PCI_PRODUCT_INTEL_82801AA_IDE: 1400 case PCI_PRODUCT_INTEL_82801AB_IDE: 1401 case PCI_PRODUCT_INTEL_82801BA_IDE: 1402 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1403 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1404 } 1405 } 1406 sc->sc_wdcdev.PIO_cap = 4; 1407 sc->sc_wdcdev.DMA_cap = 2; 1408 switch(sc->sc_pp->ide_product) { 1409 case PCI_PRODUCT_INTEL_82801AA_IDE: 1410 sc->sc_wdcdev.UDMA_cap = 4; 1411 break; 1412 case PCI_PRODUCT_INTEL_82801BA_IDE: 1413 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1414 sc->sc_wdcdev.UDMA_cap = 5; 1415 break; 1416 default: 1417 sc->sc_wdcdev.UDMA_cap = 2; 1418 } 1419 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1420 sc->sc_wdcdev.set_modes = piix_setup_channel; 1421 else 1422 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1423 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1424 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1425 1426 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1427 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1428 DEBUG_PROBE); 1429 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1430 WDCDEBUG_PRINT((", sidetim=0x%x", 1431 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1432 DEBUG_PROBE); 1433 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1434 WDCDEBUG_PRINT((", udamreg 0x%x", 1435 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1436 DEBUG_PROBE); 1437 } 1438 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1439 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1440 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1441 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1442 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1443 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1444 DEBUG_PROBE); 1445 } 1446 1447 } 1448 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1449 1450 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1451 cp = &sc->pciide_channels[channel]; 1452 /* PIIX is compat-only */ 1453 if (pciide_chansetup(sc, channel, 0) == 0) 1454 continue; 1455 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1456 if ((PIIX_IDETIM_READ(idetim, channel) & 1457 PIIX_IDETIM_IDE) == 0) { 1458 printf("%s: %s channel ignored (disabled)\n", 1459 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1460 continue; 1461 } 1462 /* PIIX are compat-only pciide devices */ 1463 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1464 if (cp->hw_ok == 0) 1465 continue; 1466 if (pciide_chan_candisable(cp)) { 1467 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1468 channel); 1469 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1470 idetim); 1471 } 1472 pciide_map_compat_intr(pa, cp, channel, 0); 1473 if (cp->hw_ok == 0) 1474 continue; 1475 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1476 } 1477 1478 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1479 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1480 DEBUG_PROBE); 1481 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1482 WDCDEBUG_PRINT((", sidetim=0x%x", 1483 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1484 DEBUG_PROBE); 1485 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1486 WDCDEBUG_PRINT((", udamreg 0x%x", 1487 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1488 DEBUG_PROBE); 1489 } 1490 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1491 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1492 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1493 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1494 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1495 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1496 DEBUG_PROBE); 1497 } 1498 } 1499 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1500 } 1501 1502 void 1503 piix_setup_channel(chp) 1504 struct channel_softc *chp; 1505 { 1506 u_int8_t mode[2], drive; 1507 u_int32_t oidetim, idetim, idedma_ctl; 1508 struct pciide_channel *cp = (struct pciide_channel*)chp; 1509 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1510 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1511 1512 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1513 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1514 idedma_ctl = 0; 1515 1516 /* set up new idetim: Enable IDE registers decode */ 1517 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1518 chp->channel); 1519 1520 /* setup DMA */ 1521 pciide_channel_dma_setup(cp); 1522 1523 /* 1524 * Here we have to mess up with drives mode: PIIX can't have 1525 * different timings for master and slave drives. 1526 * We need to find the best combination. 1527 */ 1528 1529 /* If both drives supports DMA, take the lower mode */ 1530 if ((drvp[0].drive_flags & DRIVE_DMA) && 1531 (drvp[1].drive_flags & DRIVE_DMA)) { 1532 mode[0] = mode[1] = 1533 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1534 drvp[0].DMA_mode = mode[0]; 1535 drvp[1].DMA_mode = mode[1]; 1536 goto ok; 1537 } 1538 /* 1539 * If only one drive supports DMA, use its mode, and 1540 * put the other one in PIO mode 0 if mode not compatible 1541 */ 1542 if (drvp[0].drive_flags & DRIVE_DMA) { 1543 mode[0] = drvp[0].DMA_mode; 1544 mode[1] = drvp[1].PIO_mode; 1545 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1546 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1547 mode[1] = drvp[1].PIO_mode = 0; 1548 goto ok; 1549 } 1550 if (drvp[1].drive_flags & DRIVE_DMA) { 1551 mode[1] = drvp[1].DMA_mode; 1552 mode[0] = drvp[0].PIO_mode; 1553 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1554 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1555 mode[0] = drvp[0].PIO_mode = 0; 1556 goto ok; 1557 } 1558 /* 1559 * If both drives are not DMA, takes the lower mode, unless 1560 * one of them is PIO mode < 2 1561 */ 1562 if (drvp[0].PIO_mode < 2) { 1563 mode[0] = drvp[0].PIO_mode = 0; 1564 mode[1] = drvp[1].PIO_mode; 1565 } else if (drvp[1].PIO_mode < 2) { 1566 mode[1] = drvp[1].PIO_mode = 0; 1567 mode[0] = drvp[0].PIO_mode; 1568 } else { 1569 mode[0] = mode[1] = 1570 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1571 drvp[0].PIO_mode = mode[0]; 1572 drvp[1].PIO_mode = mode[1]; 1573 } 1574 ok: /* The modes are setup */ 1575 for (drive = 0; drive < 2; drive++) { 1576 if (drvp[drive].drive_flags & DRIVE_DMA) { 1577 idetim |= piix_setup_idetim_timings( 1578 mode[drive], 1, chp->channel); 1579 goto end; 1580 } 1581 } 1582 /* If we are there, none of the drives are DMA */ 1583 if (mode[0] >= 2) 1584 idetim |= piix_setup_idetim_timings( 1585 mode[0], 0, chp->channel); 1586 else 1587 idetim |= piix_setup_idetim_timings( 1588 mode[1], 0, chp->channel); 1589 end: /* 1590 * timing mode is now set up in the controller. Enable 1591 * it per-drive 1592 */ 1593 for (drive = 0; drive < 2; drive++) { 1594 /* If no drive, skip */ 1595 if ((drvp[drive].drive_flags & DRIVE) == 0) 1596 continue; 1597 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1598 if (drvp[drive].drive_flags & DRIVE_DMA) 1599 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1600 } 1601 if (idedma_ctl != 0) { 1602 /* Add software bits in status register */ 1603 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1604 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1605 idedma_ctl); 1606 } 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1608 pciide_print_modes(cp); 1609 } 1610 1611 void 1612 piix3_4_setup_channel(chp) 1613 struct channel_softc *chp; 1614 { 1615 struct ata_drive_datas *drvp; 1616 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1617 struct pciide_channel *cp = (struct pciide_channel*)chp; 1618 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1619 int drive; 1620 int channel = chp->channel; 1621 1622 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1623 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1624 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1625 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1626 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1627 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1628 PIIX_SIDETIM_RTC_MASK(channel)); 1629 1630 idedma_ctl = 0; 1631 /* If channel disabled, no need to go further */ 1632 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1633 return; 1634 /* set up new idetim: Enable IDE registers decode */ 1635 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1636 1637 /* setup DMA if needed */ 1638 pciide_channel_dma_setup(cp); 1639 1640 for (drive = 0; drive < 2; drive++) { 1641 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1642 PIIX_UDMATIM_SET(0x3, channel, drive)); 1643 drvp = &chp->ch_drive[drive]; 1644 /* If no drive, skip */ 1645 if ((drvp->drive_flags & DRIVE) == 0) 1646 continue; 1647 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1648 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1649 goto pio; 1650 1651 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1652 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1653 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1654 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1655 ideconf |= PIIX_CONFIG_PINGPONG; 1656 } 1657 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1658 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1659 /* setup Ultra/100 */ 1660 if (drvp->UDMA_mode > 2 && 1661 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1662 drvp->UDMA_mode = 2; 1663 if (drvp->UDMA_mode > 4) { 1664 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1665 } else { 1666 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1667 if (drvp->UDMA_mode > 2) { 1668 ideconf |= PIIX_CONFIG_UDMA66(channel, 1669 drive); 1670 } else { 1671 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1672 drive); 1673 } 1674 } 1675 } 1676 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1677 /* setup Ultra/66 */ 1678 if (drvp->UDMA_mode > 2 && 1679 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1680 drvp->UDMA_mode = 2; 1681 if (drvp->UDMA_mode > 2) 1682 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1683 else 1684 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1685 } 1686 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1687 (drvp->drive_flags & DRIVE_UDMA)) { 1688 /* use Ultra/DMA */ 1689 drvp->drive_flags &= ~DRIVE_DMA; 1690 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1691 udmareg |= PIIX_UDMATIM_SET( 1692 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1693 } else { 1694 /* use Multiword DMA */ 1695 drvp->drive_flags &= ~DRIVE_UDMA; 1696 if (drive == 0) { 1697 idetim |= piix_setup_idetim_timings( 1698 drvp->DMA_mode, 1, channel); 1699 } else { 1700 sidetim |= piix_setup_sidetim_timings( 1701 drvp->DMA_mode, 1, channel); 1702 idetim =PIIX_IDETIM_SET(idetim, 1703 PIIX_IDETIM_SITRE, channel); 1704 } 1705 } 1706 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1707 1708 pio: /* use PIO mode */ 1709 idetim |= piix_setup_idetim_drvs(drvp); 1710 if (drive == 0) { 1711 idetim |= piix_setup_idetim_timings( 1712 drvp->PIO_mode, 0, channel); 1713 } else { 1714 sidetim |= piix_setup_sidetim_timings( 1715 drvp->PIO_mode, 0, channel); 1716 idetim =PIIX_IDETIM_SET(idetim, 1717 PIIX_IDETIM_SITRE, channel); 1718 } 1719 } 1720 if (idedma_ctl != 0) { 1721 /* Add software bits in status register */ 1722 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1723 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1724 idedma_ctl); 1725 } 1726 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1727 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1728 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1729 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1730 pciide_print_modes(cp); 1731 } 1732 1733 1734 /* setup ISP and RTC fields, based on mode */ 1735 static u_int32_t 1736 piix_setup_idetim_timings(mode, dma, channel) 1737 u_int8_t mode; 1738 u_int8_t dma; 1739 u_int8_t channel; 1740 { 1741 1742 if (dma) 1743 return PIIX_IDETIM_SET(0, 1744 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1745 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1746 channel); 1747 else 1748 return PIIX_IDETIM_SET(0, 1749 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1750 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1751 channel); 1752 } 1753 1754 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1755 static u_int32_t 1756 piix_setup_idetim_drvs(drvp) 1757 struct ata_drive_datas *drvp; 1758 { 1759 u_int32_t ret = 0; 1760 struct channel_softc *chp = drvp->chnl_softc; 1761 u_int8_t channel = chp->channel; 1762 u_int8_t drive = drvp->drive; 1763 1764 /* 1765 * If drive is using UDMA, timings setups are independant 1766 * So just check DMA and PIO here. 1767 */ 1768 if (drvp->drive_flags & DRIVE_DMA) { 1769 /* if mode = DMA mode 0, use compatible timings */ 1770 if ((drvp->drive_flags & DRIVE_DMA) && 1771 drvp->DMA_mode == 0) { 1772 drvp->PIO_mode = 0; 1773 return ret; 1774 } 1775 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1776 /* 1777 * PIO and DMA timings are the same, use fast timings for PIO 1778 * too, else use compat timings. 1779 */ 1780 if ((piix_isp_pio[drvp->PIO_mode] != 1781 piix_isp_dma[drvp->DMA_mode]) || 1782 (piix_rtc_pio[drvp->PIO_mode] != 1783 piix_rtc_dma[drvp->DMA_mode])) 1784 drvp->PIO_mode = 0; 1785 /* if PIO mode <= 2, use compat timings for PIO */ 1786 if (drvp->PIO_mode <= 2) { 1787 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1788 channel); 1789 return ret; 1790 } 1791 } 1792 1793 /* 1794 * Now setup PIO modes. If mode < 2, use compat timings. 1795 * Else enable fast timings. Enable IORDY and prefetch/post 1796 * if PIO mode >= 3. 1797 */ 1798 1799 if (drvp->PIO_mode < 2) 1800 return ret; 1801 1802 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1803 if (drvp->PIO_mode >= 3) { 1804 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1805 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1806 } 1807 return ret; 1808 } 1809 1810 /* setup values in SIDETIM registers, based on mode */ 1811 static u_int32_t 1812 piix_setup_sidetim_timings(mode, dma, channel) 1813 u_int8_t mode; 1814 u_int8_t dma; 1815 u_int8_t channel; 1816 { 1817 if (dma) 1818 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1819 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1820 else 1821 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1822 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1823 } 1824 1825 void 1826 amd756_chip_map(sc, pa) 1827 struct pciide_softc *sc; 1828 struct pci_attach_args *pa; 1829 { 1830 struct pciide_channel *cp; 1831 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1832 int channel; 1833 pcireg_t chanenable; 1834 bus_size_t cmdsize, ctlsize; 1835 1836 if (pciide_chipen(sc, pa) == 0) 1837 return; 1838 printf("%s: bus-master DMA support present", 1839 sc->sc_wdcdev.sc_dev.dv_xname); 1840 pciide_mapreg_dma(sc, pa); 1841 printf("\n"); 1842 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1843 WDC_CAPABILITY_MODE; 1844 if (sc->sc_dma_ok) { 1845 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1846 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1847 sc->sc_wdcdev.irqack = pciide_irqack; 1848 } 1849 sc->sc_wdcdev.PIO_cap = 4; 1850 sc->sc_wdcdev.DMA_cap = 2; 1851 sc->sc_wdcdev.UDMA_cap = 4; 1852 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1853 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1854 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1855 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1856 1857 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1858 DEBUG_PROBE); 1859 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1860 cp = &sc->pciide_channels[channel]; 1861 if (pciide_chansetup(sc, channel, interface) == 0) 1862 continue; 1863 1864 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1865 printf("%s: %s channel ignored (disabled)\n", 1866 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1867 continue; 1868 } 1869 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1870 pciide_pci_intr); 1871 1872 if (pciide_chan_candisable(cp)) 1873 chanenable &= ~AMD756_CHAN_EN(channel); 1874 pciide_map_compat_intr(pa, cp, channel, interface); 1875 if (cp->hw_ok == 0) 1876 continue; 1877 1878 amd756_setup_channel(&cp->wdc_channel); 1879 } 1880 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1881 chanenable); 1882 return; 1883 } 1884 1885 void 1886 amd756_setup_channel(chp) 1887 struct channel_softc *chp; 1888 { 1889 u_int32_t udmatim_reg, datatim_reg; 1890 u_int8_t idedma_ctl; 1891 int mode, drive; 1892 struct ata_drive_datas *drvp; 1893 struct pciide_channel *cp = (struct pciide_channel*)chp; 1894 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1895 #ifndef PCIIDE_AMD756_ENABLEDMA 1896 int rev = PCI_REVISION( 1897 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1898 #endif 1899 1900 idedma_ctl = 0; 1901 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1902 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1903 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1904 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1905 1906 /* setup DMA if needed */ 1907 pciide_channel_dma_setup(cp); 1908 1909 for (drive = 0; drive < 2; drive++) { 1910 drvp = &chp->ch_drive[drive]; 1911 /* If no drive, skip */ 1912 if ((drvp->drive_flags & DRIVE) == 0) 1913 continue; 1914 /* add timing values, setup DMA if needed */ 1915 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1916 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1917 mode = drvp->PIO_mode; 1918 goto pio; 1919 } 1920 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1921 (drvp->drive_flags & DRIVE_UDMA)) { 1922 /* use Ultra/DMA */ 1923 drvp->drive_flags &= ~DRIVE_DMA; 1924 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1925 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1926 AMD756_UDMA_TIME(chp->channel, drive, 1927 amd756_udma_tim[drvp->UDMA_mode]); 1928 /* can use PIO timings, MW DMA unused */ 1929 mode = drvp->PIO_mode; 1930 } else { 1931 /* use Multiword DMA, but only if revision is OK */ 1932 drvp->drive_flags &= ~DRIVE_UDMA; 1933 #ifndef PCIIDE_AMD756_ENABLEDMA 1934 /* 1935 * The workaround doesn't seem to be necessary 1936 * with all drives, so it can be disabled by 1937 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1938 * triggered. 1939 */ 1940 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1941 printf("%s:%d:%d: multi-word DMA disabled due " 1942 "to chip revision\n", 1943 sc->sc_wdcdev.sc_dev.dv_xname, 1944 chp->channel, drive); 1945 mode = drvp->PIO_mode; 1946 drvp->drive_flags &= ~DRIVE_DMA; 1947 goto pio; 1948 } 1949 #endif 1950 /* mode = min(pio, dma+2) */ 1951 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1952 mode = drvp->PIO_mode; 1953 else 1954 mode = drvp->DMA_mode + 2; 1955 } 1956 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1957 1958 pio: /* setup PIO mode */ 1959 if (mode <= 2) { 1960 drvp->DMA_mode = 0; 1961 drvp->PIO_mode = 0; 1962 mode = 0; 1963 } else { 1964 drvp->PIO_mode = mode; 1965 drvp->DMA_mode = mode - 2; 1966 } 1967 datatim_reg |= 1968 AMD756_DATATIM_PULSE(chp->channel, drive, 1969 amd756_pio_set[mode]) | 1970 AMD756_DATATIM_RECOV(chp->channel, drive, 1971 amd756_pio_rec[mode]); 1972 } 1973 if (idedma_ctl != 0) { 1974 /* Add software bits in status register */ 1975 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1976 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1977 idedma_ctl); 1978 } 1979 pciide_print_modes(cp); 1980 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1981 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1982 } 1983 1984 void 1985 apollo_chip_map(sc, pa) 1986 struct pciide_softc *sc; 1987 struct pci_attach_args *pa; 1988 { 1989 struct pciide_channel *cp; 1990 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1991 int channel; 1992 u_int32_t ideconf; 1993 bus_size_t cmdsize, ctlsize; 1994 pcitag_t pcib_tag; 1995 pcireg_t pcib_id, pcib_class; 1996 1997 if (pciide_chipen(sc, pa) == 0) 1998 return; 1999 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2000 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2001 /* and read ID and rev of the ISA bridge */ 2002 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2003 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2004 printf(": VIA Technologies "); 2005 switch (PCI_PRODUCT(pcib_id)) { 2006 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2007 printf("VT82C586 (Apollo VP) "); 2008 if(PCI_REVISION(pcib_class) >= 0x02) { 2009 printf("ATA33 controller\n"); 2010 sc->sc_wdcdev.UDMA_cap = 2; 2011 } else { 2012 printf("controller\n"); 2013 sc->sc_wdcdev.UDMA_cap = 0; 2014 } 2015 break; 2016 case PCI_PRODUCT_VIATECH_VT82C596A: 2017 printf("VT82C596A (Apollo Pro) "); 2018 if (PCI_REVISION(pcib_class) >= 0x12) { 2019 printf("ATA66 controller\n"); 2020 sc->sc_wdcdev.UDMA_cap = 4; 2021 } else { 2022 printf("ATA33 controller\n"); 2023 sc->sc_wdcdev.UDMA_cap = 2; 2024 } 2025 break; 2026 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2027 printf("VT82C686A (Apollo KX133) "); 2028 if (PCI_REVISION(pcib_class) >= 0x40) { 2029 printf("ATA100 controller\n"); 2030 sc->sc_wdcdev.UDMA_cap = 5; 2031 } else { 2032 printf("ATA66 controller\n"); 2033 sc->sc_wdcdev.UDMA_cap = 4; 2034 } 2035 break; 2036 default: 2037 printf("unknown ATA controller\n"); 2038 sc->sc_wdcdev.UDMA_cap = 0; 2039 } 2040 2041 printf("%s: bus-master DMA support present", 2042 sc->sc_wdcdev.sc_dev.dv_xname); 2043 pciide_mapreg_dma(sc, pa); 2044 printf("\n"); 2045 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2046 WDC_CAPABILITY_MODE; 2047 if (sc->sc_dma_ok) { 2048 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2049 sc->sc_wdcdev.irqack = pciide_irqack; 2050 if (sc->sc_wdcdev.UDMA_cap > 0) 2051 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2052 } 2053 sc->sc_wdcdev.PIO_cap = 4; 2054 sc->sc_wdcdev.DMA_cap = 2; 2055 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2056 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2057 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2058 2059 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2060 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2061 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2062 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2063 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2064 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2065 DEBUG_PROBE); 2066 2067 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2068 cp = &sc->pciide_channels[channel]; 2069 if (pciide_chansetup(sc, channel, interface) == 0) 2070 continue; 2071 2072 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2073 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2074 printf("%s: %s channel ignored (disabled)\n", 2075 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2076 continue; 2077 } 2078 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2079 pciide_pci_intr); 2080 if (cp->hw_ok == 0) 2081 continue; 2082 if (pciide_chan_candisable(cp)) { 2083 ideconf &= ~APO_IDECONF_EN(channel); 2084 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2085 ideconf); 2086 } 2087 pciide_map_compat_intr(pa, cp, channel, interface); 2088 2089 if (cp->hw_ok == 0) 2090 continue; 2091 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2092 } 2093 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2094 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2095 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2096 } 2097 2098 void 2099 apollo_setup_channel(chp) 2100 struct channel_softc *chp; 2101 { 2102 u_int32_t udmatim_reg, datatim_reg; 2103 u_int8_t idedma_ctl; 2104 int mode, drive; 2105 struct ata_drive_datas *drvp; 2106 struct pciide_channel *cp = (struct pciide_channel*)chp; 2107 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2108 2109 idedma_ctl = 0; 2110 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2111 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2112 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2113 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2114 2115 /* setup DMA if needed */ 2116 pciide_channel_dma_setup(cp); 2117 2118 for (drive = 0; drive < 2; drive++) { 2119 drvp = &chp->ch_drive[drive]; 2120 /* If no drive, skip */ 2121 if ((drvp->drive_flags & DRIVE) == 0) 2122 continue; 2123 /* add timing values, setup DMA if needed */ 2124 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2125 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2126 mode = drvp->PIO_mode; 2127 goto pio; 2128 } 2129 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2130 (drvp->drive_flags & DRIVE_UDMA)) { 2131 /* use Ultra/DMA */ 2132 drvp->drive_flags &= ~DRIVE_DMA; 2133 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2134 APO_UDMA_EN_MTH(chp->channel, drive); 2135 if (sc->sc_wdcdev.UDMA_cap == 5) { 2136 /* 686b */ 2137 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2138 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2139 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2140 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2141 /* 596b or 686a */ 2142 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2143 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2144 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2145 } else { 2146 /* 596a or 586b */ 2147 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2148 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2149 } 2150 /* can use PIO timings, MW DMA unused */ 2151 mode = drvp->PIO_mode; 2152 } else { 2153 /* use Multiword DMA */ 2154 drvp->drive_flags &= ~DRIVE_UDMA; 2155 /* mode = min(pio, dma+2) */ 2156 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2157 mode = drvp->PIO_mode; 2158 else 2159 mode = drvp->DMA_mode + 2; 2160 } 2161 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2162 2163 pio: /* setup PIO mode */ 2164 if (mode <= 2) { 2165 drvp->DMA_mode = 0; 2166 drvp->PIO_mode = 0; 2167 mode = 0; 2168 } else { 2169 drvp->PIO_mode = mode; 2170 drvp->DMA_mode = mode - 2; 2171 } 2172 datatim_reg |= 2173 APO_DATATIM_PULSE(chp->channel, drive, 2174 apollo_pio_set[mode]) | 2175 APO_DATATIM_RECOV(chp->channel, drive, 2176 apollo_pio_rec[mode]); 2177 } 2178 if (idedma_ctl != 0) { 2179 /* Add software bits in status register */ 2180 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2181 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2182 idedma_ctl); 2183 } 2184 pciide_print_modes(cp); 2185 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2186 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2187 } 2188 2189 void 2190 cmd_channel_map(pa, sc, channel) 2191 struct pci_attach_args *pa; 2192 struct pciide_softc *sc; 2193 int channel; 2194 { 2195 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2196 bus_size_t cmdsize, ctlsize; 2197 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2198 int interface; 2199 2200 /* 2201 * The 0648/0649 can be told to identify as a RAID controller. 2202 * In this case, we have to fake interface 2203 */ 2204 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2205 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2206 PCIIDE_INTERFACE_SETTABLE(1); 2207 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2208 CMD_CONF_DSA1) 2209 interface |= PCIIDE_INTERFACE_PCI(0) | 2210 PCIIDE_INTERFACE_PCI(1); 2211 } else { 2212 interface = PCI_INTERFACE(pa->pa_class); 2213 } 2214 2215 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2216 cp->name = PCIIDE_CHANNEL_NAME(channel); 2217 cp->wdc_channel.channel = channel; 2218 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2219 2220 if (channel > 0) { 2221 cp->wdc_channel.ch_queue = 2222 sc->pciide_channels[0].wdc_channel.ch_queue; 2223 } else { 2224 cp->wdc_channel.ch_queue = 2225 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2226 } 2227 if (cp->wdc_channel.ch_queue == NULL) { 2228 printf("%s %s channel: " 2229 "can't allocate memory for command queue", 2230 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2231 return; 2232 } 2233 2234 printf("%s: %s channel %s to %s mode\n", 2235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2236 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2237 "configured" : "wired", 2238 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2239 "native-PCI" : "compatibility"); 2240 2241 /* 2242 * with a CMD PCI64x, if we get here, the first channel is enabled: 2243 * there's no way to disable the first channel without disabling 2244 * the whole device 2245 */ 2246 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2247 printf("%s: %s channel ignored (disabled)\n", 2248 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2249 return; 2250 } 2251 2252 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2253 if (cp->hw_ok == 0) 2254 return; 2255 if (channel == 1) { 2256 if (pciide_chan_candisable(cp)) { 2257 ctrl &= ~CMD_CTRL_2PORT; 2258 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2259 CMD_CTRL, ctrl); 2260 } 2261 } 2262 pciide_map_compat_intr(pa, cp, channel, interface); 2263 } 2264 2265 int 2266 cmd_pci_intr(arg) 2267 void *arg; 2268 { 2269 struct pciide_softc *sc = arg; 2270 struct pciide_channel *cp; 2271 struct channel_softc *wdc_cp; 2272 int i, rv, crv; 2273 u_int32_t priirq, secirq; 2274 2275 rv = 0; 2276 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2277 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2278 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2279 cp = &sc->pciide_channels[i]; 2280 wdc_cp = &cp->wdc_channel; 2281 /* If a compat channel skip. */ 2282 if (cp->compat) 2283 continue; 2284 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2285 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2286 crv = wdcintr(wdc_cp); 2287 if (crv == 0) 2288 printf("%s:%d: bogus intr\n", 2289 sc->sc_wdcdev.sc_dev.dv_xname, i); 2290 else 2291 rv = 1; 2292 } 2293 } 2294 return rv; 2295 } 2296 2297 void 2298 cmd_chip_map(sc, pa) 2299 struct pciide_softc *sc; 2300 struct pci_attach_args *pa; 2301 { 2302 int channel; 2303 2304 /* 2305 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2306 * and base adresses registers can be disabled at 2307 * hardware level. In this case, the device is wired 2308 * in compat mode and its first channel is always enabled, 2309 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2310 * In fact, it seems that the first channel of the CMD PCI0640 2311 * can't be disabled. 2312 */ 2313 2314 #ifdef PCIIDE_CMD064x_DISABLE 2315 if (pciide_chipen(sc, pa) == 0) 2316 return; 2317 #endif 2318 2319 printf("%s: hardware does not support DMA\n", 2320 sc->sc_wdcdev.sc_dev.dv_xname); 2321 sc->sc_dma_ok = 0; 2322 2323 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2324 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2325 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2326 2327 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2328 cmd_channel_map(pa, sc, channel); 2329 } 2330 } 2331 2332 void 2333 cmd0643_9_chip_map(sc, pa) 2334 struct pciide_softc *sc; 2335 struct pci_attach_args *pa; 2336 { 2337 struct pciide_channel *cp; 2338 int channel; 2339 int rev = PCI_REVISION( 2340 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2341 2342 /* 2343 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2344 * and base adresses registers can be disabled at 2345 * hardware level. In this case, the device is wired 2346 * in compat mode and its first channel is always enabled, 2347 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2348 * In fact, it seems that the first channel of the CMD PCI0640 2349 * can't be disabled. 2350 */ 2351 2352 #ifdef PCIIDE_CMD064x_DISABLE 2353 if (pciide_chipen(sc, pa) == 0) 2354 return; 2355 #endif 2356 printf("%s: bus-master DMA support present", 2357 sc->sc_wdcdev.sc_dev.dv_xname); 2358 pciide_mapreg_dma(sc, pa); 2359 printf("\n"); 2360 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2361 WDC_CAPABILITY_MODE; 2362 if (sc->sc_dma_ok) { 2363 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2364 switch (sc->sc_pp->ide_product) { 2365 case PCI_PRODUCT_CMDTECH_649: 2366 case PCI_PRODUCT_CMDTECH_648: 2367 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2368 sc->sc_wdcdev.UDMA_cap = 4; 2369 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2370 break; 2371 case PCI_PRODUCT_CMDTECH_646: 2372 if (rev >= CMD0646U2_REV) { 2373 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2374 sc->sc_wdcdev.UDMA_cap = 2; 2375 } else if (rev >= CMD0646U_REV) { 2376 /* 2377 * Linux's driver claims that the 646U is broken 2378 * with UDMA. Only enable it if we know what we're 2379 * doing 2380 */ 2381 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2382 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2383 sc->sc_wdcdev.UDMA_cap = 2; 2384 #endif 2385 /* explicitely disable UDMA */ 2386 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2387 CMD_UDMATIM(0), 0); 2388 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2389 CMD_UDMATIM(1), 0); 2390 } 2391 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2392 break; 2393 default: 2394 sc->sc_wdcdev.irqack = pciide_irqack; 2395 } 2396 } 2397 2398 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2399 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2400 sc->sc_wdcdev.PIO_cap = 4; 2401 sc->sc_wdcdev.DMA_cap = 2; 2402 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2403 2404 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2405 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2406 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2407 DEBUG_PROBE); 2408 2409 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2410 cp = &sc->pciide_channels[channel]; 2411 cmd_channel_map(pa, sc, channel); 2412 if (cp->hw_ok == 0) 2413 continue; 2414 cmd0643_9_setup_channel(&cp->wdc_channel); 2415 } 2416 /* 2417 * note - this also makes sure we clear the irq disable and reset 2418 * bits 2419 */ 2420 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2421 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2422 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2423 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2424 DEBUG_PROBE); 2425 } 2426 2427 void 2428 cmd0643_9_setup_channel(chp) 2429 struct channel_softc *chp; 2430 { 2431 struct ata_drive_datas *drvp; 2432 u_int8_t tim; 2433 u_int32_t idedma_ctl, udma_reg; 2434 int drive; 2435 struct pciide_channel *cp = (struct pciide_channel*)chp; 2436 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2437 2438 idedma_ctl = 0; 2439 /* setup DMA if needed */ 2440 pciide_channel_dma_setup(cp); 2441 2442 for (drive = 0; drive < 2; drive++) { 2443 drvp = &chp->ch_drive[drive]; 2444 /* If no drive, skip */ 2445 if ((drvp->drive_flags & DRIVE) == 0) 2446 continue; 2447 /* add timing values, setup DMA if needed */ 2448 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2449 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2450 if (drvp->drive_flags & DRIVE_UDMA) { 2451 /* UltraDMA on a 646U2, 0648 or 0649 */ 2452 drvp->drive_flags &= ~DRIVE_DMA; 2453 udma_reg = pciide_pci_read(sc->sc_pc, 2454 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2455 if (drvp->UDMA_mode > 2 && 2456 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2457 CMD_BICSR) & 2458 CMD_BICSR_80(chp->channel)) == 0) 2459 drvp->UDMA_mode = 2; 2460 if (drvp->UDMA_mode > 2) 2461 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2462 else if (sc->sc_wdcdev.UDMA_cap > 2) 2463 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2464 udma_reg |= CMD_UDMATIM_UDMA(drive); 2465 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2466 CMD_UDMATIM_TIM_OFF(drive)); 2467 udma_reg |= 2468 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2469 CMD_UDMATIM_TIM_OFF(drive)); 2470 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2471 CMD_UDMATIM(chp->channel), udma_reg); 2472 } else { 2473 /* 2474 * use Multiword DMA. 2475 * Timings will be used for both PIO and DMA, 2476 * so adjust DMA mode if needed 2477 * if we have a 0646U2/8/9, turn off UDMA 2478 */ 2479 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2480 udma_reg = pciide_pci_read(sc->sc_pc, 2481 sc->sc_tag, 2482 CMD_UDMATIM(chp->channel)); 2483 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2484 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2485 CMD_UDMATIM(chp->channel), 2486 udma_reg); 2487 } 2488 if (drvp->PIO_mode >= 3 && 2489 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2490 drvp->DMA_mode = drvp->PIO_mode - 2; 2491 } 2492 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2493 } 2494 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2495 } 2496 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2497 CMD_DATA_TIM(chp->channel, drive), tim); 2498 } 2499 if (idedma_ctl != 0) { 2500 /* Add software bits in status register */ 2501 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2502 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2503 idedma_ctl); 2504 } 2505 pciide_print_modes(cp); 2506 } 2507 2508 void 2509 cmd646_9_irqack(chp) 2510 struct channel_softc *chp; 2511 { 2512 u_int32_t priirq, secirq; 2513 struct pciide_channel *cp = (struct pciide_channel*)chp; 2514 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2515 2516 if (chp->channel == 0) { 2517 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2518 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2519 } else { 2520 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2521 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2522 } 2523 pciide_irqack(chp); 2524 } 2525 2526 void 2527 cy693_chip_map(sc, pa) 2528 struct pciide_softc *sc; 2529 struct pci_attach_args *pa; 2530 { 2531 struct pciide_channel *cp; 2532 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2533 bus_size_t cmdsize, ctlsize; 2534 2535 if (pciide_chipen(sc, pa) == 0) 2536 return; 2537 /* 2538 * this chip has 2 PCI IDE functions, one for primary and one for 2539 * secondary. So we need to call pciide_mapregs_compat() with 2540 * the real channel 2541 */ 2542 if (pa->pa_function == 1) { 2543 sc->sc_cy_compatchan = 0; 2544 } else if (pa->pa_function == 2) { 2545 sc->sc_cy_compatchan = 1; 2546 } else { 2547 printf("%s: unexpected PCI function %d\n", 2548 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2549 return; 2550 } 2551 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2552 printf("%s: bus-master DMA support present", 2553 sc->sc_wdcdev.sc_dev.dv_xname); 2554 pciide_mapreg_dma(sc, pa); 2555 } else { 2556 printf("%s: hardware does not support DMA", 2557 sc->sc_wdcdev.sc_dev.dv_xname); 2558 sc->sc_dma_ok = 0; 2559 } 2560 printf("\n"); 2561 2562 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2563 if (sc->sc_cy_handle == NULL) { 2564 printf("%s: unable to map hyperCache control registers\n", 2565 sc->sc_wdcdev.sc_dev.dv_xname); 2566 sc->sc_dma_ok = 0; 2567 } 2568 2569 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2570 WDC_CAPABILITY_MODE; 2571 if (sc->sc_dma_ok) { 2572 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2573 sc->sc_wdcdev.irqack = pciide_irqack; 2574 } 2575 sc->sc_wdcdev.PIO_cap = 4; 2576 sc->sc_wdcdev.DMA_cap = 2; 2577 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2578 2579 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2580 sc->sc_wdcdev.nchannels = 1; 2581 2582 /* Only one channel for this chip; if we are here it's enabled */ 2583 cp = &sc->pciide_channels[0]; 2584 sc->wdc_chanarray[0] = &cp->wdc_channel; 2585 cp->name = PCIIDE_CHANNEL_NAME(0); 2586 cp->wdc_channel.channel = 0; 2587 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2588 cp->wdc_channel.ch_queue = 2589 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2590 if (cp->wdc_channel.ch_queue == NULL) { 2591 printf("%s primary channel: " 2592 "can't allocate memory for command queue", 2593 sc->sc_wdcdev.sc_dev.dv_xname); 2594 return; 2595 } 2596 printf("%s: primary channel %s to ", 2597 sc->sc_wdcdev.sc_dev.dv_xname, 2598 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2599 "configured" : "wired"); 2600 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2601 printf("native-PCI"); 2602 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2603 pciide_pci_intr); 2604 } else { 2605 printf("compatibility"); 2606 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2607 &cmdsize, &ctlsize); 2608 } 2609 printf(" mode\n"); 2610 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2611 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2612 wdcattach(&cp->wdc_channel); 2613 if (pciide_chan_candisable(cp)) { 2614 pci_conf_write(sc->sc_pc, sc->sc_tag, 2615 PCI_COMMAND_STATUS_REG, 0); 2616 } 2617 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2618 if (cp->hw_ok == 0) 2619 return; 2620 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2621 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2622 cy693_setup_channel(&cp->wdc_channel); 2623 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2624 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2625 } 2626 2627 void 2628 cy693_setup_channel(chp) 2629 struct channel_softc *chp; 2630 { 2631 struct ata_drive_datas *drvp; 2632 int drive; 2633 u_int32_t cy_cmd_ctrl; 2634 u_int32_t idedma_ctl; 2635 struct pciide_channel *cp = (struct pciide_channel*)chp; 2636 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2637 int dma_mode = -1; 2638 2639 cy_cmd_ctrl = idedma_ctl = 0; 2640 2641 /* setup DMA if needed */ 2642 pciide_channel_dma_setup(cp); 2643 2644 for (drive = 0; drive < 2; drive++) { 2645 drvp = &chp->ch_drive[drive]; 2646 /* If no drive, skip */ 2647 if ((drvp->drive_flags & DRIVE) == 0) 2648 continue; 2649 /* add timing values, setup DMA if needed */ 2650 if (drvp->drive_flags & DRIVE_DMA) { 2651 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2652 /* use Multiword DMA */ 2653 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2654 dma_mode = drvp->DMA_mode; 2655 } 2656 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2657 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2658 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2659 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2660 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2661 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2662 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2663 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2664 } 2665 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2666 chp->ch_drive[0].DMA_mode = dma_mode; 2667 chp->ch_drive[1].DMA_mode = dma_mode; 2668 2669 if (dma_mode == -1) 2670 dma_mode = 0; 2671 2672 if (sc->sc_cy_handle != NULL) { 2673 /* Note: `multiple' is implied. */ 2674 cy82c693_write(sc->sc_cy_handle, 2675 (sc->sc_cy_compatchan == 0) ? 2676 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2677 } 2678 2679 pciide_print_modes(cp); 2680 2681 if (idedma_ctl != 0) { 2682 /* Add software bits in status register */ 2683 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2684 IDEDMA_CTL, idedma_ctl); 2685 } 2686 } 2687 2688 void 2689 sis_chip_map(sc, pa) 2690 struct pciide_softc *sc; 2691 struct pci_attach_args *pa; 2692 { 2693 struct pciide_channel *cp; 2694 int channel; 2695 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2696 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2697 pcireg_t rev = PCI_REVISION(pa->pa_class); 2698 bus_size_t cmdsize, ctlsize; 2699 2700 if (pciide_chipen(sc, pa) == 0) 2701 return; 2702 printf("%s: bus-master DMA support present", 2703 sc->sc_wdcdev.sc_dev.dv_xname); 2704 pciide_mapreg_dma(sc, pa); 2705 printf("\n"); 2706 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2707 WDC_CAPABILITY_MODE; 2708 if (sc->sc_dma_ok) { 2709 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2710 sc->sc_wdcdev.irqack = pciide_irqack; 2711 if (rev > 0xd0) 2712 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2713 } 2714 2715 sc->sc_wdcdev.PIO_cap = 4; 2716 sc->sc_wdcdev.DMA_cap = 2; 2717 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2718 sc->sc_wdcdev.UDMA_cap = 2; 2719 sc->sc_wdcdev.set_modes = sis_setup_channel; 2720 2721 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2722 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2723 2724 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2725 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2726 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2727 2728 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2729 cp = &sc->pciide_channels[channel]; 2730 if (pciide_chansetup(sc, channel, interface) == 0) 2731 continue; 2732 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2733 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2734 printf("%s: %s channel ignored (disabled)\n", 2735 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2736 continue; 2737 } 2738 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2739 pciide_pci_intr); 2740 if (cp->hw_ok == 0) 2741 continue; 2742 if (pciide_chan_candisable(cp)) { 2743 if (channel == 0) 2744 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2745 else 2746 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2747 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2748 sis_ctr0); 2749 } 2750 pciide_map_compat_intr(pa, cp, channel, interface); 2751 if (cp->hw_ok == 0) 2752 continue; 2753 sis_setup_channel(&cp->wdc_channel); 2754 } 2755 } 2756 2757 void 2758 sis_setup_channel(chp) 2759 struct channel_softc *chp; 2760 { 2761 struct ata_drive_datas *drvp; 2762 int drive; 2763 u_int32_t sis_tim; 2764 u_int32_t idedma_ctl; 2765 struct pciide_channel *cp = (struct pciide_channel*)chp; 2766 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2767 2768 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2769 "channel %d 0x%x\n", chp->channel, 2770 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2771 DEBUG_PROBE); 2772 sis_tim = 0; 2773 idedma_ctl = 0; 2774 /* setup DMA if needed */ 2775 pciide_channel_dma_setup(cp); 2776 2777 for (drive = 0; drive < 2; drive++) { 2778 drvp = &chp->ch_drive[drive]; 2779 /* If no drive, skip */ 2780 if ((drvp->drive_flags & DRIVE) == 0) 2781 continue; 2782 /* add timing values, setup DMA if needed */ 2783 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2784 (drvp->drive_flags & DRIVE_UDMA) == 0) 2785 goto pio; 2786 2787 if (drvp->drive_flags & DRIVE_UDMA) { 2788 /* use Ultra/DMA */ 2789 drvp->drive_flags &= ~DRIVE_DMA; 2790 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2791 SIS_TIM_UDMA_TIME_OFF(drive); 2792 sis_tim |= SIS_TIM_UDMA_EN(drive); 2793 } else { 2794 /* 2795 * use Multiword DMA 2796 * Timings will be used for both PIO and DMA, 2797 * so adjust DMA mode if needed 2798 */ 2799 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2800 drvp->PIO_mode = drvp->DMA_mode + 2; 2801 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2802 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2803 drvp->PIO_mode - 2 : 0; 2804 if (drvp->DMA_mode == 0) 2805 drvp->PIO_mode = 0; 2806 } 2807 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2808 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2809 SIS_TIM_ACT_OFF(drive); 2810 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2811 SIS_TIM_REC_OFF(drive); 2812 } 2813 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2814 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2815 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2816 if (idedma_ctl != 0) { 2817 /* Add software bits in status register */ 2818 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2819 IDEDMA_CTL, idedma_ctl); 2820 } 2821 pciide_print_modes(cp); 2822 } 2823 2824 void 2825 acer_chip_map(sc, pa) 2826 struct pciide_softc *sc; 2827 struct pci_attach_args *pa; 2828 { 2829 struct pciide_channel *cp; 2830 int channel; 2831 pcireg_t cr, interface; 2832 bus_size_t cmdsize, ctlsize; 2833 pcireg_t rev = PCI_REVISION(pa->pa_class); 2834 2835 if (pciide_chipen(sc, pa) == 0) 2836 return; 2837 printf("%s: bus-master DMA support present", 2838 sc->sc_wdcdev.sc_dev.dv_xname); 2839 pciide_mapreg_dma(sc, pa); 2840 printf("\n"); 2841 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2842 WDC_CAPABILITY_MODE; 2843 if (sc->sc_dma_ok) { 2844 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2845 if (rev >= 0x20) 2846 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2847 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2848 sc->sc_wdcdev.irqack = pciide_irqack; 2849 } 2850 2851 sc->sc_wdcdev.PIO_cap = 4; 2852 sc->sc_wdcdev.DMA_cap = 2; 2853 sc->sc_wdcdev.UDMA_cap = 2; 2854 sc->sc_wdcdev.set_modes = acer_setup_channel; 2855 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2856 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2857 2858 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2859 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2860 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2861 2862 /* Enable "microsoft register bits" R/W. */ 2863 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2864 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2865 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2866 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2867 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2868 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2869 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2870 ~ACER_CHANSTATUSREGS_RO); 2871 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2872 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2873 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2874 /* Don't use cr, re-read the real register content instead */ 2875 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2876 PCI_CLASS_REG)); 2877 2878 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2879 cp = &sc->pciide_channels[channel]; 2880 if (pciide_chansetup(sc, channel, interface) == 0) 2881 continue; 2882 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2883 printf("%s: %s channel ignored (disabled)\n", 2884 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2885 continue; 2886 } 2887 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2888 acer_pci_intr); 2889 if (cp->hw_ok == 0) 2890 continue; 2891 if (pciide_chan_candisable(cp)) { 2892 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2893 pci_conf_write(sc->sc_pc, sc->sc_tag, 2894 PCI_CLASS_REG, cr); 2895 } 2896 pciide_map_compat_intr(pa, cp, channel, interface); 2897 acer_setup_channel(&cp->wdc_channel); 2898 } 2899 } 2900 2901 void 2902 acer_setup_channel(chp) 2903 struct channel_softc *chp; 2904 { 2905 struct ata_drive_datas *drvp; 2906 int drive; 2907 u_int32_t acer_fifo_udma; 2908 u_int32_t idedma_ctl; 2909 struct pciide_channel *cp = (struct pciide_channel*)chp; 2910 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2911 2912 idedma_ctl = 0; 2913 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2914 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2915 acer_fifo_udma), DEBUG_PROBE); 2916 /* setup DMA if needed */ 2917 pciide_channel_dma_setup(cp); 2918 2919 for (drive = 0; drive < 2; drive++) { 2920 drvp = &chp->ch_drive[drive]; 2921 /* If no drive, skip */ 2922 if ((drvp->drive_flags & DRIVE) == 0) 2923 continue; 2924 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2925 "channel %d drive %d 0x%x\n", chp->channel, drive, 2926 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2927 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2928 /* clear FIFO/DMA mode */ 2929 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2930 ACER_UDMA_EN(chp->channel, drive) | 2931 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2932 2933 /* add timing values, setup DMA if needed */ 2934 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2935 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2936 acer_fifo_udma |= 2937 ACER_FTH_OPL(chp->channel, drive, 0x1); 2938 goto pio; 2939 } 2940 2941 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2942 if (drvp->drive_flags & DRIVE_UDMA) { 2943 /* use Ultra/DMA */ 2944 drvp->drive_flags &= ~DRIVE_DMA; 2945 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2946 acer_fifo_udma |= 2947 ACER_UDMA_TIM(chp->channel, drive, 2948 acer_udma[drvp->UDMA_mode]); 2949 } else { 2950 /* 2951 * use Multiword DMA 2952 * Timings will be used for both PIO and DMA, 2953 * so adjust DMA mode if needed 2954 */ 2955 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2956 drvp->PIO_mode = drvp->DMA_mode + 2; 2957 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2958 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2959 drvp->PIO_mode - 2 : 0; 2960 if (drvp->DMA_mode == 0) 2961 drvp->PIO_mode = 0; 2962 } 2963 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2964 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2965 ACER_IDETIM(chp->channel, drive), 2966 acer_pio[drvp->PIO_mode]); 2967 } 2968 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2969 acer_fifo_udma), DEBUG_PROBE); 2970 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2971 if (idedma_ctl != 0) { 2972 /* Add software bits in status register */ 2973 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2974 IDEDMA_CTL, idedma_ctl); 2975 } 2976 pciide_print_modes(cp); 2977 } 2978 2979 int 2980 acer_pci_intr(arg) 2981 void *arg; 2982 { 2983 struct pciide_softc *sc = arg; 2984 struct pciide_channel *cp; 2985 struct channel_softc *wdc_cp; 2986 int i, rv, crv; 2987 u_int32_t chids; 2988 2989 rv = 0; 2990 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2991 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2992 cp = &sc->pciide_channels[i]; 2993 wdc_cp = &cp->wdc_channel; 2994 /* If a compat channel skip. */ 2995 if (cp->compat) 2996 continue; 2997 if (chids & ACER_CHIDS_INT(i)) { 2998 crv = wdcintr(wdc_cp); 2999 if (crv == 0) 3000 printf("%s:%d: bogus intr\n", 3001 sc->sc_wdcdev.sc_dev.dv_xname, i); 3002 else 3003 rv = 1; 3004 } 3005 } 3006 return rv; 3007 } 3008 3009 void 3010 hpt_chip_map(sc, pa) 3011 struct pciide_softc *sc; 3012 struct pci_attach_args *pa; 3013 { 3014 struct pciide_channel *cp; 3015 int i, compatchan, revision; 3016 pcireg_t interface; 3017 bus_size_t cmdsize, ctlsize; 3018 3019 if (pciide_chipen(sc, pa) == 0) 3020 return; 3021 revision = PCI_REVISION(pa->pa_class); 3022 printf(": Triones/Highpoint "); 3023 if (revision == HPT370_REV) 3024 printf("HPT370 IDE Controller\n"); 3025 else 3026 printf("HPT366 IDE Controller\n"); 3027 3028 /* 3029 * when the chip is in native mode it identifies itself as a 3030 * 'misc mass storage'. Fake interface in this case. 3031 */ 3032 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3033 interface = PCI_INTERFACE(pa->pa_class); 3034 } else { 3035 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3036 PCIIDE_INTERFACE_PCI(0); 3037 if (revision == HPT370_REV) 3038 interface |= PCIIDE_INTERFACE_PCI(1); 3039 } 3040 3041 printf("%s: bus-master DMA support present", 3042 sc->sc_wdcdev.sc_dev.dv_xname); 3043 pciide_mapreg_dma(sc, pa); 3044 printf("\n"); 3045 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3046 WDC_CAPABILITY_MODE; 3047 if (sc->sc_dma_ok) { 3048 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3049 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3050 sc->sc_wdcdev.irqack = pciide_irqack; 3051 } 3052 sc->sc_wdcdev.PIO_cap = 4; 3053 sc->sc_wdcdev.DMA_cap = 2; 3054 3055 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3056 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3057 if (revision == HPT366_REV) { 3058 sc->sc_wdcdev.UDMA_cap = 4; 3059 /* 3060 * The 366 has 2 PCI IDE functions, one for primary and one 3061 * for secondary. So we need to call pciide_mapregs_compat() 3062 * with the real channel 3063 */ 3064 if (pa->pa_function == 0) { 3065 compatchan = 0; 3066 } else if (pa->pa_function == 1) { 3067 compatchan = 1; 3068 } else { 3069 printf("%s: unexpected PCI function %d\n", 3070 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3071 return; 3072 } 3073 sc->sc_wdcdev.nchannels = 1; 3074 } else { 3075 sc->sc_wdcdev.nchannels = 2; 3076 sc->sc_wdcdev.UDMA_cap = 5; 3077 } 3078 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3079 cp = &sc->pciide_channels[i]; 3080 if (sc->sc_wdcdev.nchannels > 1) { 3081 compatchan = i; 3082 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3083 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3084 printf("%s: %s channel ignored (disabled)\n", 3085 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3086 continue; 3087 } 3088 } 3089 if (pciide_chansetup(sc, i, interface) == 0) 3090 continue; 3091 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3092 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3093 &ctlsize, hpt_pci_intr); 3094 } else { 3095 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3096 &cmdsize, &ctlsize); 3097 } 3098 if (cp->hw_ok == 0) 3099 return; 3100 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3101 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3102 wdcattach(&cp->wdc_channel); 3103 hpt_setup_channel(&cp->wdc_channel); 3104 } 3105 if (revision == HPT370_REV) { 3106 /* 3107 * HPT370_REV has a bit to disable interrupts, make sure 3108 * to clear it 3109 */ 3110 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3111 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3112 ~HPT_CSEL_IRQDIS); 3113 } 3114 return; 3115 } 3116 3117 void 3118 hpt_setup_channel(chp) 3119 struct channel_softc *chp; 3120 { 3121 struct ata_drive_datas *drvp; 3122 int drive; 3123 int cable; 3124 u_int32_t before, after; 3125 u_int32_t idedma_ctl; 3126 struct pciide_channel *cp = (struct pciide_channel*)chp; 3127 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3128 3129 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3130 3131 /* setup DMA if needed */ 3132 pciide_channel_dma_setup(cp); 3133 3134 idedma_ctl = 0; 3135 3136 /* Per drive settings */ 3137 for (drive = 0; drive < 2; drive++) { 3138 drvp = &chp->ch_drive[drive]; 3139 /* If no drive, skip */ 3140 if ((drvp->drive_flags & DRIVE) == 0) 3141 continue; 3142 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3143 HPT_IDETIM(chp->channel, drive)); 3144 3145 /* add timing values, setup DMA if needed */ 3146 if (drvp->drive_flags & DRIVE_UDMA) { 3147 /* use Ultra/DMA */ 3148 drvp->drive_flags &= ~DRIVE_DMA; 3149 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3150 drvp->UDMA_mode > 2) 3151 drvp->UDMA_mode = 2; 3152 after = (sc->sc_wdcdev.nchannels == 2) ? 3153 hpt370_udma[drvp->UDMA_mode] : 3154 hpt366_udma[drvp->UDMA_mode]; 3155 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3156 } else if (drvp->drive_flags & DRIVE_DMA) { 3157 /* 3158 * use Multiword DMA. 3159 * Timings will be used for both PIO and DMA, so adjust 3160 * DMA mode if needed 3161 */ 3162 if (drvp->PIO_mode >= 3 && 3163 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3164 drvp->DMA_mode = drvp->PIO_mode - 2; 3165 } 3166 after = (sc->sc_wdcdev.nchannels == 2) ? 3167 hpt370_dma[drvp->DMA_mode] : 3168 hpt366_dma[drvp->DMA_mode]; 3169 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3170 } else { 3171 /* PIO only */ 3172 after = (sc->sc_wdcdev.nchannels == 2) ? 3173 hpt370_pio[drvp->PIO_mode] : 3174 hpt366_pio[drvp->PIO_mode]; 3175 } 3176 pci_conf_write(sc->sc_pc, sc->sc_tag, 3177 HPT_IDETIM(chp->channel, drive), after); 3178 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3179 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3180 after, before), DEBUG_PROBE); 3181 } 3182 if (idedma_ctl != 0) { 3183 /* Add software bits in status register */ 3184 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3185 IDEDMA_CTL, idedma_ctl); 3186 } 3187 pciide_print_modes(cp); 3188 } 3189 3190 int 3191 hpt_pci_intr(arg) 3192 void *arg; 3193 { 3194 struct pciide_softc *sc = arg; 3195 struct pciide_channel *cp; 3196 struct channel_softc *wdc_cp; 3197 int rv = 0; 3198 int dmastat, i, crv; 3199 3200 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3201 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3202 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3203 if((dmastat & IDEDMA_CTL_INTR) == 0) 3204 continue; 3205 cp = &sc->pciide_channels[i]; 3206 wdc_cp = &cp->wdc_channel; 3207 crv = wdcintr(wdc_cp); 3208 if (crv == 0) { 3209 printf("%s:%d: bogus intr\n", 3210 sc->sc_wdcdev.sc_dev.dv_xname, i); 3211 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3212 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3213 } else 3214 rv = 1; 3215 } 3216 return rv; 3217 } 3218 3219 3220 /* Macros to test product */ 3221 #define PDC_IS_262(sc) \ 3222 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3223 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3224 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3225 #define PDC_IS_265(sc) \ 3226 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3227 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3228 3229 void 3230 pdc202xx_chip_map(sc, pa) 3231 struct pciide_softc *sc; 3232 struct pci_attach_args *pa; 3233 { 3234 struct pciide_channel *cp; 3235 int channel; 3236 pcireg_t interface, st, mode; 3237 bus_size_t cmdsize, ctlsize; 3238 3239 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3240 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3241 DEBUG_PROBE); 3242 if (pciide_chipen(sc, pa) == 0) 3243 return; 3244 3245 /* turn off RAID mode */ 3246 st &= ~PDC2xx_STATE_IDERAID; 3247 3248 /* 3249 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3250 * mode. We have to fake interface 3251 */ 3252 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3253 if (st & PDC2xx_STATE_NATIVE) 3254 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3255 3256 printf("%s: bus-master DMA support present", 3257 sc->sc_wdcdev.sc_dev.dv_xname); 3258 pciide_mapreg_dma(sc, pa); 3259 printf("\n"); 3260 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3261 WDC_CAPABILITY_MODE; 3262 if (sc->sc_dma_ok) { 3263 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3264 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3265 sc->sc_wdcdev.irqack = pciide_irqack; 3266 } 3267 sc->sc_wdcdev.PIO_cap = 4; 3268 sc->sc_wdcdev.DMA_cap = 2; 3269 if (PDC_IS_265(sc)) 3270 sc->sc_wdcdev.UDMA_cap = 5; 3271 else if (PDC_IS_262(sc)) 3272 sc->sc_wdcdev.UDMA_cap = 4; 3273 else 3274 sc->sc_wdcdev.UDMA_cap = 2; 3275 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3276 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3277 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3278 3279 /* setup failsafe defaults */ 3280 mode = 0; 3281 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3282 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3283 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3284 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3285 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3286 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3287 "initial timings 0x%x, now 0x%x\n", channel, 3288 pci_conf_read(sc->sc_pc, sc->sc_tag, 3289 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3290 DEBUG_PROBE); 3291 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3292 mode | PDC2xx_TIM_IORDYp); 3293 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3294 "initial timings 0x%x, now 0x%x\n", channel, 3295 pci_conf_read(sc->sc_pc, sc->sc_tag, 3296 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3297 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3298 mode); 3299 } 3300 3301 mode = PDC2xx_SCR_DMA; 3302 if (PDC_IS_262(sc)) { 3303 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3304 } else { 3305 /* the BIOS set it up this way */ 3306 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3307 } 3308 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3309 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3310 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3311 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3312 DEBUG_PROBE); 3313 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3314 3315 /* controller initial state register is OK even without BIOS */ 3316 /* Set DMA mode to IDE DMA compatibility */ 3317 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3318 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3319 DEBUG_PROBE); 3320 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3321 mode | 0x1); 3322 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3323 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3324 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3325 mode | 0x1); 3326 3327 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3328 cp = &sc->pciide_channels[channel]; 3329 if (pciide_chansetup(sc, channel, interface) == 0) 3330 continue; 3331 if ((st & (PDC_IS_262(sc) ? 3332 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3333 printf("%s: %s channel ignored (disabled)\n", 3334 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3335 continue; 3336 } 3337 if (PDC_IS_265(sc)) 3338 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3339 pdc20265_pci_intr); 3340 else 3341 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3342 pdc202xx_pci_intr); 3343 if (cp->hw_ok == 0) 3344 continue; 3345 if (pciide_chan_candisable(cp)) 3346 st &= ~(PDC_IS_262(sc) ? 3347 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3348 pciide_map_compat_intr(pa, cp, channel, interface); 3349 pdc202xx_setup_channel(&cp->wdc_channel); 3350 } 3351 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3352 DEBUG_PROBE); 3353 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3354 return; 3355 } 3356 3357 void 3358 pdc202xx_setup_channel(chp) 3359 struct channel_softc *chp; 3360 { 3361 struct ata_drive_datas *drvp; 3362 int drive; 3363 pcireg_t mode, st; 3364 u_int32_t idedma_ctl, scr, atapi; 3365 struct pciide_channel *cp = (struct pciide_channel*)chp; 3366 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3367 int channel = chp->channel; 3368 3369 /* setup DMA if needed */ 3370 pciide_channel_dma_setup(cp); 3371 3372 idedma_ctl = 0; 3373 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3374 sc->sc_wdcdev.sc_dev.dv_xname, 3375 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3376 DEBUG_PROBE); 3377 3378 /* Per channel settings */ 3379 if (PDC_IS_262(sc)) { 3380 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3381 PDC262_U66); 3382 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3383 /* Trimm UDMA mode */ 3384 if ((st & PDC262_STATE_80P(channel)) != 0 || 3385 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3386 chp->ch_drive[0].UDMA_mode <= 2) || 3387 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3388 chp->ch_drive[1].UDMA_mode <= 2)) { 3389 if (chp->ch_drive[0].UDMA_mode > 2) 3390 chp->ch_drive[0].UDMA_mode = 2; 3391 if (chp->ch_drive[1].UDMA_mode > 2) 3392 chp->ch_drive[1].UDMA_mode = 2; 3393 } 3394 /* Set U66 if needed */ 3395 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3396 chp->ch_drive[0].UDMA_mode > 2) || 3397 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3398 chp->ch_drive[1].UDMA_mode > 2)) 3399 scr |= PDC262_U66_EN(channel); 3400 else 3401 scr &= ~PDC262_U66_EN(channel); 3402 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3403 PDC262_U66, scr); 3404 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3405 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3406 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3407 PDC262_ATAPI(channel))), DEBUG_PROBE); 3408 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3409 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3410 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3411 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3412 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3413 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3414 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3415 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3416 atapi = 0; 3417 else 3418 atapi = PDC262_ATAPI_UDMA; 3419 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3420 PDC262_ATAPI(channel), atapi); 3421 } 3422 } 3423 for (drive = 0; drive < 2; drive++) { 3424 drvp = &chp->ch_drive[drive]; 3425 /* If no drive, skip */ 3426 if ((drvp->drive_flags & DRIVE) == 0) 3427 continue; 3428 mode = 0; 3429 if (drvp->drive_flags & DRIVE_UDMA) { 3430 /* use Ultra/DMA */ 3431 drvp->drive_flags &= ~DRIVE_DMA; 3432 mode = PDC2xx_TIM_SET_MB(mode, 3433 pdc2xx_udma_mb[drvp->UDMA_mode]); 3434 mode = PDC2xx_TIM_SET_MC(mode, 3435 pdc2xx_udma_mc[drvp->UDMA_mode]); 3436 drvp->drive_flags &= ~DRIVE_DMA; 3437 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3438 } else if (drvp->drive_flags & DRIVE_DMA) { 3439 mode = PDC2xx_TIM_SET_MB(mode, 3440 pdc2xx_dma_mb[drvp->DMA_mode]); 3441 mode = PDC2xx_TIM_SET_MC(mode, 3442 pdc2xx_dma_mc[drvp->DMA_mode]); 3443 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3444 } else { 3445 mode = PDC2xx_TIM_SET_MB(mode, 3446 pdc2xx_dma_mb[0]); 3447 mode = PDC2xx_TIM_SET_MC(mode, 3448 pdc2xx_dma_mc[0]); 3449 } 3450 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3451 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3452 if (drvp->drive_flags & DRIVE_ATA) 3453 mode |= PDC2xx_TIM_PRE; 3454 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3455 if (drvp->PIO_mode >= 3) { 3456 mode |= PDC2xx_TIM_IORDY; 3457 if (drive == 0) 3458 mode |= PDC2xx_TIM_IORDYp; 3459 } 3460 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3461 "timings 0x%x\n", 3462 sc->sc_wdcdev.sc_dev.dv_xname, 3463 chp->channel, drive, mode), DEBUG_PROBE); 3464 pci_conf_write(sc->sc_pc, sc->sc_tag, 3465 PDC2xx_TIM(chp->channel, drive), mode); 3466 } 3467 if (idedma_ctl != 0) { 3468 /* Add software bits in status register */ 3469 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3470 IDEDMA_CTL, idedma_ctl); 3471 } 3472 pciide_print_modes(cp); 3473 } 3474 3475 int 3476 pdc202xx_pci_intr(arg) 3477 void *arg; 3478 { 3479 struct pciide_softc *sc = arg; 3480 struct pciide_channel *cp; 3481 struct channel_softc *wdc_cp; 3482 int i, rv, crv; 3483 u_int32_t scr; 3484 3485 rv = 0; 3486 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3487 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3488 cp = &sc->pciide_channels[i]; 3489 wdc_cp = &cp->wdc_channel; 3490 /* If a compat channel skip. */ 3491 if (cp->compat) 3492 continue; 3493 if (scr & PDC2xx_SCR_INT(i)) { 3494 crv = wdcintr(wdc_cp); 3495 if (crv == 0) 3496 printf("%s:%d: bogus intr (reg 0x%x)\n", 3497 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3498 else 3499 rv = 1; 3500 } 3501 } 3502 return rv; 3503 } 3504 3505 int 3506 pdc20265_pci_intr(arg) 3507 void *arg; 3508 { 3509 struct pciide_softc *sc = arg; 3510 struct pciide_channel *cp; 3511 struct channel_softc *wdc_cp; 3512 int i, rv, crv; 3513 u_int32_t dmastat; 3514 3515 rv = 0; 3516 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3517 cp = &sc->pciide_channels[i]; 3518 wdc_cp = &cp->wdc_channel; 3519 /* If a compat channel skip. */ 3520 if (cp->compat) 3521 continue; 3522 /* 3523 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3524 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3525 * So use it instead (requires 2 reg reads instead of 1, 3526 * but we can't do it another way). 3527 */ 3528 dmastat = bus_space_read_1(sc->sc_dma_iot, 3529 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3530 if((dmastat & IDEDMA_CTL_INTR) == 0) 3531 continue; 3532 crv = wdcintr(wdc_cp); 3533 if (crv == 0) 3534 printf("%s:%d: bogus intr\n", 3535 sc->sc_wdcdev.sc_dev.dv_xname, i); 3536 else 3537 rv = 1; 3538 } 3539 return rv; 3540 } 3541 3542 void 3543 opti_chip_map(sc, pa) 3544 struct pciide_softc *sc; 3545 struct pci_attach_args *pa; 3546 { 3547 struct pciide_channel *cp; 3548 bus_size_t cmdsize, ctlsize; 3549 pcireg_t interface; 3550 u_int8_t init_ctrl; 3551 int channel; 3552 3553 if (pciide_chipen(sc, pa) == 0) 3554 return; 3555 printf("%s: bus-master DMA support present", 3556 sc->sc_wdcdev.sc_dev.dv_xname); 3557 pciide_mapreg_dma(sc, pa); 3558 printf("\n"); 3559 3560 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3561 WDC_CAPABILITY_MODE; 3562 sc->sc_wdcdev.PIO_cap = 4; 3563 if (sc->sc_dma_ok) { 3564 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3565 sc->sc_wdcdev.irqack = pciide_irqack; 3566 sc->sc_wdcdev.DMA_cap = 2; 3567 } 3568 sc->sc_wdcdev.set_modes = opti_setup_channel; 3569 3570 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3571 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3572 3573 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3574 OPTI_REG_INIT_CONTROL); 3575 3576 interface = PCI_INTERFACE(pa->pa_class); 3577 3578 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3579 cp = &sc->pciide_channels[channel]; 3580 if (pciide_chansetup(sc, channel, interface) == 0) 3581 continue; 3582 if (channel == 1 && 3583 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3584 printf("%s: %s channel ignored (disabled)\n", 3585 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3586 continue; 3587 } 3588 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3589 pciide_pci_intr); 3590 if (cp->hw_ok == 0) 3591 continue; 3592 pciide_map_compat_intr(pa, cp, channel, interface); 3593 if (cp->hw_ok == 0) 3594 continue; 3595 opti_setup_channel(&cp->wdc_channel); 3596 } 3597 } 3598 3599 void 3600 opti_setup_channel(chp) 3601 struct channel_softc *chp; 3602 { 3603 struct ata_drive_datas *drvp; 3604 struct pciide_channel *cp = (struct pciide_channel*)chp; 3605 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3606 int drive, spd; 3607 int mode[2]; 3608 u_int8_t rv, mr; 3609 3610 /* 3611 * The `Delay' and `Address Setup Time' fields of the 3612 * Miscellaneous Register are always zero initially. 3613 */ 3614 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3615 mr &= ~(OPTI_MISC_DELAY_MASK | 3616 OPTI_MISC_ADDR_SETUP_MASK | 3617 OPTI_MISC_INDEX_MASK); 3618 3619 /* Prime the control register before setting timing values */ 3620 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3621 3622 /* Determine the clockrate of the PCIbus the chip is attached to */ 3623 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3624 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3625 3626 /* setup DMA if needed */ 3627 pciide_channel_dma_setup(cp); 3628 3629 for (drive = 0; drive < 2; drive++) { 3630 drvp = &chp->ch_drive[drive]; 3631 /* If no drive, skip */ 3632 if ((drvp->drive_flags & DRIVE) == 0) { 3633 mode[drive] = -1; 3634 continue; 3635 } 3636 3637 if ((drvp->drive_flags & DRIVE_DMA)) { 3638 /* 3639 * Timings will be used for both PIO and DMA, 3640 * so adjust DMA mode if needed 3641 */ 3642 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3643 drvp->PIO_mode = drvp->DMA_mode + 2; 3644 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3645 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3646 drvp->PIO_mode - 2 : 0; 3647 if (drvp->DMA_mode == 0) 3648 drvp->PIO_mode = 0; 3649 3650 mode[drive] = drvp->DMA_mode + 5; 3651 } else 3652 mode[drive] = drvp->PIO_mode; 3653 3654 if (drive && mode[0] >= 0 && 3655 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3656 /* 3657 * Can't have two drives using different values 3658 * for `Address Setup Time'. 3659 * Slow down the faster drive to compensate. 3660 */ 3661 int d = (opti_tim_as[spd][mode[0]] > 3662 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3663 3664 mode[d] = mode[1-d]; 3665 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3666 chp->ch_drive[d].DMA_mode = 0; 3667 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3668 } 3669 } 3670 3671 for (drive = 0; drive < 2; drive++) { 3672 int m; 3673 if ((m = mode[drive]) < 0) 3674 continue; 3675 3676 /* Set the Address Setup Time and select appropriate index */ 3677 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3678 rv |= OPTI_MISC_INDEX(drive); 3679 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3680 3681 /* Set the pulse width and recovery timing parameters */ 3682 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3683 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3684 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3685 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3686 3687 /* Set the Enhanced Mode register appropriately */ 3688 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3689 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3690 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3691 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3692 } 3693 3694 /* Finally, enable the timings */ 3695 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3696 3697 pciide_print_modes(cp); 3698 } 3699 3700 #define ACARD_IS_850(sc) \ 3701 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3702 3703 void 3704 acard_chip_map(sc, pa) 3705 struct pciide_softc *sc; 3706 struct pci_attach_args *pa; 3707 { 3708 struct pciide_channel *cp; 3709 int i, compatchan; 3710 pcireg_t interface; 3711 bus_size_t cmdsize, ctlsize; 3712 3713 if (pciide_chipen(sc, pa) == 0) 3714 return; 3715 3716 /* 3717 * when the chip is in native mode it identifies itself as a 3718 * 'misc mass storage'. Fake interface in this case. 3719 */ 3720 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3721 interface = PCI_INTERFACE(pa->pa_class); 3722 } else { 3723 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3724 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3725 } 3726 3727 printf("%s: bus-master DMA support present", 3728 sc->sc_wdcdev.sc_dev.dv_xname); 3729 pciide_mapreg_dma(sc, pa); 3730 printf("\n"); 3731 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3732 WDC_CAPABILITY_MODE; 3733 3734 if (sc->sc_dma_ok) { 3735 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3736 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3737 sc->sc_wdcdev.irqack = pciide_irqack; 3738 } 3739 sc->sc_wdcdev.PIO_cap = 4; 3740 sc->sc_wdcdev.DMA_cap = 2; 3741 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3742 3743 sc->sc_wdcdev.set_modes = acard_setup_channel; 3744 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3745 sc->sc_wdcdev.nchannels = 2; 3746 3747 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3748 cp = &sc->pciide_channels[i]; 3749 if (pciide_chansetup(sc, i, interface) == 0) 3750 continue; 3751 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3752 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3753 &ctlsize, pciide_pci_intr); 3754 } else { 3755 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3756 &cmdsize, &ctlsize); 3757 } 3758 if (cp->hw_ok == 0) 3759 return; 3760 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3761 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3762 wdcattach(&cp->wdc_channel); 3763 acard_setup_channel(&cp->wdc_channel); 3764 } 3765 if (!ACARD_IS_850(sc)) { 3766 u_int32_t reg; 3767 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3768 reg &= ~ATP860_CTRL_INT; 3769 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3770 } 3771 } 3772 3773 void 3774 acard_setup_channel(chp) 3775 struct channel_softc *chp; 3776 { 3777 struct ata_drive_datas *drvp; 3778 struct pciide_channel *cp = (struct pciide_channel*)chp; 3779 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3780 int channel = chp->channel; 3781 int drive; 3782 u_int32_t idetime, udma_mode; 3783 u_int32_t idedma_ctl; 3784 3785 /* setup DMA if needed */ 3786 pciide_channel_dma_setup(cp); 3787 3788 if (ACARD_IS_850(sc)) { 3789 idetime = 0; 3790 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3791 udma_mode &= ~ATP850_UDMA_MASK(channel); 3792 } else { 3793 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3794 idetime &= ~ATP860_SETTIME_MASK(channel); 3795 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3796 udma_mode &= ~ATP860_UDMA_MASK(channel); 3797 } 3798 3799 idedma_ctl = 0; 3800 3801 /* Per drive settings */ 3802 for (drive = 0; drive < 2; drive++) { 3803 drvp = &chp->ch_drive[drive]; 3804 /* If no drive, skip */ 3805 if ((drvp->drive_flags & DRIVE) == 0) 3806 continue; 3807 /* add timing values, setup DMA if needed */ 3808 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3809 (drvp->drive_flags & DRIVE_UDMA)) { 3810 /* use Ultra/DMA */ 3811 if (ACARD_IS_850(sc)) { 3812 idetime |= ATP850_SETTIME(drive, 3813 acard_act_udma[drvp->UDMA_mode], 3814 acard_rec_udma[drvp->UDMA_mode]); 3815 udma_mode |= ATP850_UDMA_MODE(channel, drive, 3816 acard_udma_conf[drvp->UDMA_mode]); 3817 } else { 3818 idetime |= ATP860_SETTIME(channel, drive, 3819 acard_act_udma[drvp->UDMA_mode], 3820 acard_rec_udma[drvp->UDMA_mode]); 3821 udma_mode |= ATP860_UDMA_MODE(channel, drive, 3822 acard_udma_conf[drvp->UDMA_mode]); 3823 } 3824 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3825 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 3826 (drvp->drive_flags & DRIVE_DMA)) { 3827 /* use Multiword DMA */ 3828 drvp->drive_flags &= ~DRIVE_UDMA; 3829 if (ACARD_IS_850(sc)) { 3830 idetime |= ATP850_SETTIME(drive, 3831 acard_act_dma[drvp->DMA_mode], 3832 acard_rec_dma[drvp->DMA_mode]); 3833 } else { 3834 idetime |= ATP860_SETTIME(channel, drive, 3835 acard_act_dma[drvp->DMA_mode], 3836 acard_rec_dma[drvp->DMA_mode]); 3837 } 3838 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3839 } else { 3840 /* PIO only */ 3841 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 3842 if (ACARD_IS_850(sc)) { 3843 idetime |= ATP850_SETTIME(drive, 3844 acard_act_pio[drvp->PIO_mode], 3845 acard_rec_pio[drvp->PIO_mode]); 3846 } else { 3847 idetime |= ATP860_SETTIME(channel, drive, 3848 acard_act_pio[drvp->PIO_mode], 3849 acard_rec_pio[drvp->PIO_mode]); 3850 } 3851 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 3852 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3853 | ATP8x0_CTRL_EN(channel)); 3854 } 3855 } 3856 3857 if (idedma_ctl != 0) { 3858 /* Add software bits in status register */ 3859 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3860 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 3861 } 3862 pciide_print_modes(cp); 3863 3864 if (ACARD_IS_850(sc)) { 3865 pci_conf_write(sc->sc_pc, sc->sc_tag, 3866 ATP850_IDETIME(channel), idetime); 3867 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 3868 } else { 3869 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 3870 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 3871 } 3872 } 3873 3874 int 3875 acard_pci_intr(arg) 3876 void *arg; 3877 { 3878 struct pciide_softc *sc = arg; 3879 struct pciide_channel *cp; 3880 struct channel_softc *wdc_cp; 3881 int rv = 0; 3882 int dmastat, i, crv; 3883 3884 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3885 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3886 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3887 if ((dmastat & IDEDMA_CTL_INTR) == 0) 3888 continue; 3889 cp = &sc->pciide_channels[i]; 3890 wdc_cp = &cp->wdc_channel; 3891 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 3892 (void)wdcintr(wdc_cp); 3893 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3894 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3895 continue; 3896 } 3897 crv = wdcintr(wdc_cp); 3898 if (crv == 0) 3899 printf("%s:%d: bogus intr\n", 3900 sc->sc_wdcdev.sc_dev.dv_xname, i); 3901 else if (crv == 1) 3902 rv = 1; 3903 else if (rv == 0) 3904 rv = crv; 3905 } 3906 return rv; 3907 } 3908
Indexes created Thu Oct 02 10:09:58 GMT 2025