pciide.c revision 1.117
1 /* $NetBSD: pciide.c,v 1.117 2001/05/14 20:41:27 matt Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/pciide_acard_reg.h> 119 #include <dev/pci/cy82c693var.h> 120 121 #include "opt_pciide.h" 122 123 /* inlines for reading/writing 8-bit PCI registers */ 124 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 125 int)); 126 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 127 int, u_int8_t)); 128 129 static __inline u_int8_t 130 pciide_pci_read(pc, pa, reg) 131 pci_chipset_tag_t pc; 132 pcitag_t pa; 133 int reg; 134 { 135 136 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 137 ((reg & 0x03) * 8) & 0xff); 138 } 139 140 static __inline void 141 pciide_pci_write(pc, pa, reg, val) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 u_int8_t val; 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 156 157 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 void piix_setup_channel __P((struct channel_softc*)); 159 void piix3_4_setup_channel __P((struct channel_softc*)); 160 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 161 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 162 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 164 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void amd7x6_setup_channel __P((struct channel_softc*)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 void cmd646_9_irqack __P((struct channel_softc *)); 177 178 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cy693_setup_channel __P((struct channel_softc*)); 180 181 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void sis_setup_channel __P((struct channel_softc*)); 183 184 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void acer_setup_channel __P((struct channel_softc*)); 186 int acer_pci_intr __P((void *)); 187 188 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void pdc202xx_setup_channel __P((struct channel_softc*)); 190 int pdc202xx_pci_intr __P((void *)); 191 int pdc20265_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void acard_setup_channel __P((struct channel_softc*)); 202 int acard_pci_intr __P((void *)); 203 204 #ifdef PCIIDE_WINBOND_ENABLE 205 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 #endif 207 208 void pciide_channel_dma_setup __P((struct pciide_channel *)); 209 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 210 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 211 void pciide_dma_start __P((void*, int, int)); 212 int pciide_dma_finish __P((void*, int, int, int)); 213 void pciide_irqack __P((struct channel_softc *)); 214 void pciide_print_modes __P((struct pciide_channel *)); 215 216 struct pciide_product_desc { 217 u_int32_t ide_product; 218 int ide_flags; 219 const char *ide_name; 220 /* map and setup chip, probe drives */ 221 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 222 }; 223 224 /* Flags for ide_flags */ 225 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 226 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 227 228 /* Default product description for devices not known from this controller */ 229 const struct pciide_product_desc default_product_desc = { 230 0, 231 0, 232 "Generic PCI IDE controller", 233 default_chip_map, 234 }; 235 236 const struct pciide_product_desc pciide_intel_products[] = { 237 { PCI_PRODUCT_INTEL_82092AA, 238 0, 239 "Intel 82092AA IDE controller", 240 default_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82371FB_IDE, 243 0, 244 "Intel 82371FB IDE controller (PIIX)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82371SB_IDE, 248 0, 249 "Intel 82371SB IDE Interface (PIIX3)", 250 piix_chip_map, 251 }, 252 { PCI_PRODUCT_INTEL_82371AB_IDE, 253 0, 254 "Intel 82371AB IDE controller (PIIX4)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82440MX_IDE, 258 0, 259 "Intel 82440MX IDE controller", 260 piix_chip_map 261 }, 262 { PCI_PRODUCT_INTEL_82801AA_IDE, 263 0, 264 "Intel 82801AA IDE Controller (ICH)", 265 piix_chip_map, 266 }, 267 { PCI_PRODUCT_INTEL_82801AB_IDE, 268 0, 269 "Intel 82801AB IDE Controller (ICH0)", 270 piix_chip_map, 271 }, 272 { PCI_PRODUCT_INTEL_82801BA_IDE, 273 0, 274 "Intel 82801BA IDE Controller (ICH2)", 275 piix_chip_map, 276 }, 277 { PCI_PRODUCT_INTEL_82801BAM_IDE, 278 0, 279 "Intel 82801BAM IDE Controller (ICH2)", 280 piix_chip_map, 281 }, 282 { 0, 283 0, 284 NULL, 285 NULL 286 } 287 }; 288 289 const struct pciide_product_desc pciide_amd_products[] = { 290 { PCI_PRODUCT_AMD_PBC756_IDE, 291 0, 292 "Advanced Micro Devices AMD756 IDE Controller", 293 amd7x6_chip_map 294 }, 295 { PCI_PRODUCT_AMD_PBC766_IDE, 296 0, 297 "Advanced Micro Devices AMD766 IDE Controller", 298 amd7x6_chip_map 299 }, 300 { 0, 301 0, 302 NULL, 303 NULL 304 } 305 }; 306 307 const struct pciide_product_desc pciide_cmd_products[] = { 308 { PCI_PRODUCT_CMDTECH_640, 309 0, 310 "CMD Technology PCI0640", 311 cmd_chip_map 312 }, 313 { PCI_PRODUCT_CMDTECH_643, 314 0, 315 "CMD Technology PCI0643", 316 cmd0643_9_chip_map, 317 }, 318 { PCI_PRODUCT_CMDTECH_646, 319 0, 320 "CMD Technology PCI0646", 321 cmd0643_9_chip_map, 322 }, 323 { PCI_PRODUCT_CMDTECH_648, 324 IDE_PCI_CLASS_OVERRIDE, 325 "CMD Technology PCI0648", 326 cmd0643_9_chip_map, 327 }, 328 { PCI_PRODUCT_CMDTECH_649, 329 IDE_PCI_CLASS_OVERRIDE, 330 "CMD Technology PCI0649", 331 cmd0643_9_chip_map, 332 }, 333 { 0, 334 0, 335 NULL, 336 NULL 337 } 338 }; 339 340 const struct pciide_product_desc pciide_via_products[] = { 341 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 342 0, 343 NULL, 344 apollo_chip_map, 345 }, 346 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 347 0, 348 NULL, 349 apollo_chip_map, 350 }, 351 { 0, 352 0, 353 NULL, 354 NULL 355 } 356 }; 357 358 const struct pciide_product_desc pciide_cypress_products[] = { 359 { PCI_PRODUCT_CONTAQ_82C693, 360 IDE_16BIT_IOSPACE, 361 "Cypress 82C693 IDE Controller", 362 cy693_chip_map, 363 }, 364 { 0, 365 0, 366 NULL, 367 NULL 368 } 369 }; 370 371 const struct pciide_product_desc pciide_sis_products[] = { 372 { PCI_PRODUCT_SIS_5597_IDE, 373 0, 374 "Silicon Integrated System 5597/5598 IDE controller", 375 sis_chip_map, 376 }, 377 { 0, 378 0, 379 NULL, 380 NULL 381 } 382 }; 383 384 const struct pciide_product_desc pciide_acer_products[] = { 385 { PCI_PRODUCT_ALI_M5229, 386 0, 387 "Acer Labs M5229 UDMA IDE Controller", 388 acer_chip_map, 389 }, 390 { 0, 391 0, 392 NULL, 393 NULL 394 } 395 }; 396 397 const struct pciide_product_desc pciide_promise_products[] = { 398 { PCI_PRODUCT_PROMISE_ULTRA33, 399 IDE_PCI_CLASS_OVERRIDE, 400 "Promise Ultra33/ATA Bus Master IDE Accelerator", 401 pdc202xx_chip_map, 402 }, 403 { PCI_PRODUCT_PROMISE_ULTRA66, 404 IDE_PCI_CLASS_OVERRIDE, 405 "Promise Ultra66/ATA Bus Master IDE Accelerator", 406 pdc202xx_chip_map, 407 }, 408 { PCI_PRODUCT_PROMISE_ULTRA100, 409 IDE_PCI_CLASS_OVERRIDE, 410 "Promise Ultra100/ATA Bus Master IDE Accelerator", 411 pdc202xx_chip_map, 412 }, 413 { PCI_PRODUCT_PROMISE_ULTRA100X, 414 IDE_PCI_CLASS_OVERRIDE, 415 "Promise Ultra100/ATA Bus Master IDE Accelerator", 416 pdc202xx_chip_map, 417 }, 418 { 0, 419 0, 420 NULL, 421 NULL 422 } 423 }; 424 425 const struct pciide_product_desc pciide_opti_products[] = { 426 { PCI_PRODUCT_OPTI_82C621, 427 0, 428 "OPTi 82c621 PCI IDE controller", 429 opti_chip_map, 430 }, 431 { PCI_PRODUCT_OPTI_82C568, 432 0, 433 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 434 opti_chip_map, 435 }, 436 { PCI_PRODUCT_OPTI_82D568, 437 0, 438 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 439 opti_chip_map, 440 }, 441 { 0, 442 0, 443 NULL, 444 NULL 445 } 446 }; 447 448 const struct pciide_product_desc pciide_triones_products[] = { 449 { PCI_PRODUCT_TRIONES_HPT366, 450 IDE_PCI_CLASS_OVERRIDE, 451 NULL, 452 hpt_chip_map, 453 }, 454 { 0, 455 0, 456 NULL, 457 NULL 458 } 459 }; 460 461 const struct pciide_product_desc pciide_acard_products[] = { 462 { PCI_PRODUCT_ACARD_ATP850U, 463 IDE_PCI_CLASS_OVERRIDE, 464 "Acard ATP850U Ultra33 IDE Controller", 465 acard_chip_map, 466 }, 467 { PCI_PRODUCT_ACARD_ATP860, 468 IDE_PCI_CLASS_OVERRIDE, 469 "Acard ATP860 Ultra66 IDE Controller", 470 acard_chip_map, 471 }, 472 { PCI_PRODUCT_ACARD_ATP860A, 473 IDE_PCI_CLASS_OVERRIDE, 474 "Acard ATP860-A Ultra66 IDE Controller", 475 acard_chip_map, 476 }, 477 { 0, 478 0, 479 NULL, 480 NULL 481 } 482 }; 483 484 #ifdef PCIIDE_SERVERWORKS_ENABLE 485 const struct pciide_product_desc pciide_serverworks_products[] = { 486 { PCI_PRODUCT_SERVERWORKS_IDE, 487 0, 488 "ServerWorks ROSB4 IDE Controller", 489 piix_chip_map, 490 }, 491 { 0, 492 0, 493 NULL, 494 } 495 }; 496 #endif 497 498 #ifdef PCIIDE_WINBOND_ENABLE 499 const struct pciide_product_desc pciide_winbond_products[] = { 500 { PCI_PRODUCT_WINBOND_W83C553F_1, 501 0, 502 "Winbond W83C553F IDE controller", 503 winbond_chip_map, 504 }, 505 { 0, 506 0, 507 NULL, 508 } 509 }; 510 #endif 511 512 struct pciide_vendor_desc { 513 u_int32_t ide_vendor; 514 const struct pciide_product_desc *ide_products; 515 }; 516 517 const struct pciide_vendor_desc pciide_vendors[] = { 518 { PCI_VENDOR_INTEL, pciide_intel_products }, 519 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 520 { PCI_VENDOR_VIATECH, pciide_via_products }, 521 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 522 { PCI_VENDOR_SIS, pciide_sis_products }, 523 { PCI_VENDOR_ALI, pciide_acer_products }, 524 { PCI_VENDOR_PROMISE, pciide_promise_products }, 525 { PCI_VENDOR_AMD, pciide_amd_products }, 526 { PCI_VENDOR_OPTI, pciide_opti_products }, 527 { PCI_VENDOR_TRIONES, pciide_triones_products }, 528 #ifdef PCIIDE_ACARD_ENABLE 529 { PCI_VENDOR_ACARD, pciide_acard_products }, 530 #endif 531 #ifdef PCIIDE_SERVERWORKS_ENABLE 532 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 533 #endif 534 #ifdef PCIIDE_WINBOND_ENABLE 535 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 536 #endif 537 { 0, NULL } 538 }; 539 540 /* options passed via the 'flags' config keyword */ 541 #define PCIIDE_OPTIONS_DMA 0x01 542 543 int pciide_match __P((struct device *, struct cfdata *, void *)); 544 void pciide_attach __P((struct device *, struct device *, void *)); 545 546 struct cfattach pciide_ca = { 547 sizeof(struct pciide_softc), pciide_match, pciide_attach 548 }; 549 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 550 int pciide_mapregs_compat __P(( struct pci_attach_args *, 551 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 552 int pciide_mapregs_native __P((struct pci_attach_args *, 553 struct pciide_channel *, bus_size_t *, bus_size_t *, 554 int (*pci_intr) __P((void *)))); 555 void pciide_mapreg_dma __P((struct pciide_softc *, 556 struct pci_attach_args *)); 557 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 558 void pciide_mapchan __P((struct pci_attach_args *, 559 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 560 int (*pci_intr) __P((void *)))); 561 int pciide_chan_candisable __P((struct pciide_channel *)); 562 void pciide_map_compat_intr __P(( struct pci_attach_args *, 563 struct pciide_channel *, int, int)); 564 int pciide_print __P((void *, const char *pnp)); 565 int pciide_compat_intr __P((void *)); 566 int pciide_pci_intr __P((void *)); 567 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 568 569 const struct pciide_product_desc * 570 pciide_lookup_product(id) 571 u_int32_t id; 572 { 573 const struct pciide_product_desc *pp; 574 const struct pciide_vendor_desc *vp; 575 576 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 577 if (PCI_VENDOR(id) == vp->ide_vendor) 578 break; 579 580 if ((pp = vp->ide_products) == NULL) 581 return NULL; 582 583 for (; pp->chip_map != NULL; pp++) 584 if (PCI_PRODUCT(id) == pp->ide_product) 585 break; 586 587 if (pp->chip_map == NULL) 588 return NULL; 589 return pp; 590 } 591 592 int 593 pciide_match(parent, match, aux) 594 struct device *parent; 595 struct cfdata *match; 596 void *aux; 597 { 598 struct pci_attach_args *pa = aux; 599 const struct pciide_product_desc *pp; 600 601 /* 602 * Check the ID register to see that it's a PCI IDE controller. 603 * If it is, we assume that we can deal with it; it _should_ 604 * work in a standardized way... 605 */ 606 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 607 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 608 return (1); 609 } 610 611 /* 612 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 613 * controllers. Let see if we can deal with it anyway. 614 */ 615 pp = pciide_lookup_product(pa->pa_id); 616 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 617 return (1); 618 } 619 620 return (0); 621 } 622 623 void 624 pciide_attach(parent, self, aux) 625 struct device *parent, *self; 626 void *aux; 627 { 628 struct pci_attach_args *pa = aux; 629 pci_chipset_tag_t pc = pa->pa_pc; 630 pcitag_t tag = pa->pa_tag; 631 struct pciide_softc *sc = (struct pciide_softc *)self; 632 pcireg_t csr; 633 char devinfo[256]; 634 const char *displaydev; 635 636 sc->sc_pp = pciide_lookup_product(pa->pa_id); 637 if (sc->sc_pp == NULL) { 638 sc->sc_pp = &default_product_desc; 639 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 640 displaydev = devinfo; 641 } else 642 displaydev = sc->sc_pp->ide_name; 643 644 /* if displaydev == NULL, printf is done in chip-specific map */ 645 if (displaydev) 646 printf(": %s (rev. 0x%02x)\n", displaydev, 647 PCI_REVISION(pa->pa_class)); 648 649 sc->sc_pc = pa->pa_pc; 650 sc->sc_tag = pa->pa_tag; 651 #ifdef WDCDEBUG 652 if (wdcdebug_pciide_mask & DEBUG_PROBE) 653 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 654 #endif 655 sc->sc_pp->chip_map(sc, pa); 656 657 if (sc->sc_dma_ok) { 658 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 659 csr |= PCI_COMMAND_MASTER_ENABLE; 660 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 661 } 662 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 663 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 664 } 665 666 /* tell wether the chip is enabled or not */ 667 int 668 pciide_chipen(sc, pa) 669 struct pciide_softc *sc; 670 struct pci_attach_args *pa; 671 { 672 pcireg_t csr; 673 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 674 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 675 PCI_COMMAND_STATUS_REG); 676 printf("%s: device disabled (at %s)\n", 677 sc->sc_wdcdev.sc_dev.dv_xname, 678 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 679 "device" : "bridge"); 680 return 0; 681 } 682 return 1; 683 } 684 685 int 686 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 687 struct pci_attach_args *pa; 688 struct pciide_channel *cp; 689 int compatchan; 690 bus_size_t *cmdsizep, *ctlsizep; 691 { 692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 693 struct channel_softc *wdc_cp = &cp->wdc_channel; 694 695 cp->compat = 1; 696 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 697 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 698 699 wdc_cp->cmd_iot = pa->pa_iot; 700 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 701 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 702 printf("%s: couldn't map %s channel cmd regs\n", 703 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 704 return (0); 705 } 706 707 wdc_cp->ctl_iot = pa->pa_iot; 708 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 709 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 710 printf("%s: couldn't map %s channel ctl regs\n", 711 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 712 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 713 PCIIDE_COMPAT_CMD_SIZE); 714 return (0); 715 } 716 717 return (1); 718 } 719 720 int 721 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 722 struct pci_attach_args * pa; 723 struct pciide_channel *cp; 724 bus_size_t *cmdsizep, *ctlsizep; 725 int (*pci_intr) __P((void *)); 726 { 727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 728 struct channel_softc *wdc_cp = &cp->wdc_channel; 729 const char *intrstr; 730 pci_intr_handle_t intrhandle; 731 732 cp->compat = 0; 733 734 if (sc->sc_pci_ih == NULL) { 735 if (pci_intr_map(pa, &intrhandle) != 0) { 736 printf("%s: couldn't map native-PCI interrupt\n", 737 sc->sc_wdcdev.sc_dev.dv_xname); 738 return 0; 739 } 740 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 741 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 742 intrhandle, IPL_BIO, pci_intr, sc); 743 if (sc->sc_pci_ih != NULL) { 744 printf("%s: using %s for native-PCI interrupt\n", 745 sc->sc_wdcdev.sc_dev.dv_xname, 746 intrstr ? intrstr : "unknown interrupt"); 747 } else { 748 printf("%s: couldn't establish native-PCI interrupt", 749 sc->sc_wdcdev.sc_dev.dv_xname); 750 if (intrstr != NULL) 751 printf(" at %s", intrstr); 752 printf("\n"); 753 return 0; 754 } 755 } 756 cp->ih = sc->sc_pci_ih; 757 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 758 PCI_MAPREG_TYPE_IO, 0, 759 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 760 printf("%s: couldn't map %s channel cmd regs\n", 761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 762 return 0; 763 } 764 765 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 766 PCI_MAPREG_TYPE_IO, 0, 767 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 768 printf("%s: couldn't map %s channel ctl regs\n", 769 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 770 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 771 return 0; 772 } 773 /* 774 * In native mode, 4 bytes of I/O space are mapped for the control 775 * register, the control register is at offset 2. Pass the generic 776 * code a handle for only one byte at the rigth offset. 777 */ 778 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 779 &wdc_cp->ctl_ioh) != 0) { 780 printf("%s: unable to subregion %s channel ctl regs\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 782 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 783 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 784 return 0; 785 } 786 return (1); 787 } 788 789 void 790 pciide_mapreg_dma(sc, pa) 791 struct pciide_softc *sc; 792 struct pci_attach_args *pa; 793 { 794 pcireg_t maptype; 795 bus_addr_t addr; 796 797 /* 798 * Map DMA registers 799 * 800 * Note that sc_dma_ok is the right variable to test to see if 801 * DMA can be done. If the interface doesn't support DMA, 802 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 803 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 804 * non-zero if the interface supports DMA and the registers 805 * could be mapped. 806 * 807 * XXX Note that despite the fact that the Bus Master IDE specs 808 * XXX say that "The bus master IDE function uses 16 bytes of IO 809 * XXX space," some controllers (at least the United 810 * XXX Microelectronics UM8886BF) place it in memory space. 811 */ 812 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 813 PCIIDE_REG_BUS_MASTER_DMA); 814 815 switch (maptype) { 816 case PCI_MAPREG_TYPE_IO: 817 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 818 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 819 &addr, NULL, NULL) == 0); 820 if (sc->sc_dma_ok == 0) { 821 printf(", but unused (couldn't query registers)"); 822 break; 823 } 824 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 825 && addr >= 0x10000) { 826 sc->sc_dma_ok = 0; 827 printf(", but unused (registers at unsafe address %#lx)", (unsigned long)addr); 828 break; 829 } 830 /* FALLTHROUGH */ 831 832 case PCI_MAPREG_MEM_TYPE_32BIT: 833 sc->sc_dma_ok = (pci_mapreg_map(pa, 834 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 835 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 836 sc->sc_dmat = pa->pa_dmat; 837 if (sc->sc_dma_ok == 0) { 838 printf(", but unused (couldn't map registers)"); 839 } else { 840 sc->sc_wdcdev.dma_arg = sc; 841 sc->sc_wdcdev.dma_init = pciide_dma_init; 842 sc->sc_wdcdev.dma_start = pciide_dma_start; 843 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 844 } 845 break; 846 847 default: 848 sc->sc_dma_ok = 0; 849 printf(", but unsupported register maptype (0x%x)", maptype); 850 } 851 } 852 853 int 854 pciide_compat_intr(arg) 855 void *arg; 856 { 857 struct pciide_channel *cp = arg; 858 859 #ifdef DIAGNOSTIC 860 /* should only be called for a compat channel */ 861 if (cp->compat == 0) 862 panic("pciide compat intr called for non-compat chan %p\n", cp); 863 #endif 864 return (wdcintr(&cp->wdc_channel)); 865 } 866 867 int 868 pciide_pci_intr(arg) 869 void *arg; 870 { 871 struct pciide_softc *sc = arg; 872 struct pciide_channel *cp; 873 struct channel_softc *wdc_cp; 874 int i, rv, crv; 875 876 rv = 0; 877 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 878 cp = &sc->pciide_channels[i]; 879 wdc_cp = &cp->wdc_channel; 880 881 /* If a compat channel skip. */ 882 if (cp->compat) 883 continue; 884 /* if this channel not waiting for intr, skip */ 885 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 886 continue; 887 888 crv = wdcintr(wdc_cp); 889 if (crv == 0) 890 ; /* leave rv alone */ 891 else if (crv == 1) 892 rv = 1; /* claim the intr */ 893 else if (rv == 0) /* crv should be -1 in this case */ 894 rv = crv; /* if we've done no better, take it */ 895 } 896 return (rv); 897 } 898 899 void 900 pciide_channel_dma_setup(cp) 901 struct pciide_channel *cp; 902 { 903 int drive; 904 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 905 struct ata_drive_datas *drvp; 906 907 for (drive = 0; drive < 2; drive++) { 908 drvp = &cp->wdc_channel.ch_drive[drive]; 909 /* If no drive, skip */ 910 if ((drvp->drive_flags & DRIVE) == 0) 911 continue; 912 /* setup DMA if needed */ 913 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 914 (drvp->drive_flags & DRIVE_UDMA) == 0) || 915 sc->sc_dma_ok == 0) { 916 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 917 continue; 918 } 919 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 920 != 0) { 921 /* Abort DMA setup */ 922 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 923 continue; 924 } 925 } 926 } 927 928 int 929 pciide_dma_table_setup(sc, channel, drive) 930 struct pciide_softc *sc; 931 int channel, drive; 932 { 933 bus_dma_segment_t seg; 934 int error, rseg; 935 const bus_size_t dma_table_size = 936 sizeof(struct idedma_table) * NIDEDMA_TABLES; 937 struct pciide_dma_maps *dma_maps = 938 &sc->pciide_channels[channel].dma_maps[drive]; 939 940 /* If table was already allocated, just return */ 941 if (dma_maps->dma_table) 942 return 0; 943 944 /* Allocate memory for the DMA tables and map it */ 945 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 946 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 947 BUS_DMA_NOWAIT)) != 0) { 948 printf("%s:%d: unable to allocate table DMA for " 949 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 950 channel, drive, error); 951 return error; 952 } 953 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 954 dma_table_size, 955 (caddr_t *)&dma_maps->dma_table, 956 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 957 printf("%s:%d: unable to map table DMA for" 958 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 959 channel, drive, error); 960 return error; 961 } 962 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 963 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 964 (unsigned long)seg.ds_addr), DEBUG_PROBE); 965 966 /* Create and load table DMA map for this disk */ 967 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 968 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 969 &dma_maps->dmamap_table)) != 0) { 970 printf("%s:%d: unable to create table DMA map for " 971 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 972 channel, drive, error); 973 return error; 974 } 975 if ((error = bus_dmamap_load(sc->sc_dmat, 976 dma_maps->dmamap_table, 977 dma_maps->dma_table, 978 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 979 printf("%s:%d: unable to load table DMA map for " 980 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 981 channel, drive, error); 982 return error; 983 } 984 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 985 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 986 DEBUG_PROBE); 987 /* Create a xfer DMA map for this drive */ 988 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 989 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 990 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 991 &dma_maps->dmamap_xfer)) != 0) { 992 printf("%s:%d: unable to create xfer DMA map for " 993 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 994 channel, drive, error); 995 return error; 996 } 997 return 0; 998 } 999 1000 int 1001 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1002 void *v; 1003 int channel, drive; 1004 void *databuf; 1005 size_t datalen; 1006 int flags; 1007 { 1008 struct pciide_softc *sc = v; 1009 int error, seg; 1010 struct pciide_dma_maps *dma_maps = 1011 &sc->pciide_channels[channel].dma_maps[drive]; 1012 1013 error = bus_dmamap_load(sc->sc_dmat, 1014 dma_maps->dmamap_xfer, 1015 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING); 1016 if (error) { 1017 printf("%s:%d: unable to load xfer DMA map for" 1018 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1019 channel, drive, error); 1020 return error; 1021 } 1022 1023 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1024 dma_maps->dmamap_xfer->dm_mapsize, 1025 (flags & WDC_DMA_READ) ? 1026 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1027 1028 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1029 #ifdef DIAGNOSTIC 1030 /* A segment must not cross a 64k boundary */ 1031 { 1032 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1033 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1034 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1035 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1036 printf("pciide_dma: segment %d physical addr 0x%lx" 1037 " len 0x%lx not properly aligned\n", 1038 seg, phys, len); 1039 panic("pciide_dma: buf align"); 1040 } 1041 } 1042 #endif 1043 dma_maps->dma_table[seg].base_addr = 1044 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1045 dma_maps->dma_table[seg].byte_count = 1046 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1047 IDEDMA_BYTE_COUNT_MASK); 1048 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1049 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1050 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1051 1052 } 1053 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1054 htole32(IDEDMA_BYTE_COUNT_EOT); 1055 1056 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1057 dma_maps->dmamap_table->dm_mapsize, 1058 BUS_DMASYNC_PREWRITE); 1059 1060 /* Maps are ready. Start DMA function */ 1061 #ifdef DIAGNOSTIC 1062 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1063 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1064 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1065 panic("pciide_dma_init: table align"); 1066 } 1067 #endif 1068 1069 /* Clear status bits */ 1070 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1071 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1072 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1073 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1074 /* Write table addr */ 1075 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1076 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1077 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1078 /* set read/write */ 1079 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1080 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1081 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1082 /* remember flags */ 1083 dma_maps->dma_flags = flags; 1084 return 0; 1085 } 1086 1087 void 1088 pciide_dma_start(v, channel, drive) 1089 void *v; 1090 int channel, drive; 1091 { 1092 struct pciide_softc *sc = v; 1093 1094 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1095 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1096 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1097 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1098 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1099 } 1100 1101 int 1102 pciide_dma_finish(v, channel, drive, force) 1103 void *v; 1104 int channel, drive; 1105 int force; 1106 { 1107 struct pciide_softc *sc = v; 1108 u_int8_t status; 1109 int error = 0; 1110 struct pciide_dma_maps *dma_maps = 1111 &sc->pciide_channels[channel].dma_maps[drive]; 1112 1113 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1114 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1115 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1116 DEBUG_XFERS); 1117 1118 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1119 return WDC_DMAST_NOIRQ; 1120 1121 /* stop DMA channel */ 1122 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1123 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1124 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1125 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1126 1127 /* Unload the map of the data buffer */ 1128 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1129 dma_maps->dmamap_xfer->dm_mapsize, 1130 (dma_maps->dma_flags & WDC_DMA_READ) ? 1131 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1132 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1133 1134 if ((status & IDEDMA_CTL_ERR) != 0) { 1135 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1136 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1137 error |= WDC_DMAST_ERR; 1138 } 1139 1140 if ((status & IDEDMA_CTL_INTR) == 0) { 1141 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1142 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1143 drive, status); 1144 error |= WDC_DMAST_NOIRQ; 1145 } 1146 1147 if ((status & IDEDMA_CTL_ACT) != 0) { 1148 /* data underrun, may be a valid condition for ATAPI */ 1149 error |= WDC_DMAST_UNDER; 1150 } 1151 return error; 1152 } 1153 1154 void 1155 pciide_irqack(chp) 1156 struct channel_softc *chp; 1157 { 1158 struct pciide_channel *cp = (struct pciide_channel*)chp; 1159 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1160 1161 /* clear status bits in IDE DMA registers */ 1162 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1163 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1164 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1165 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1166 } 1167 1168 /* some common code used by several chip_map */ 1169 int 1170 pciide_chansetup(sc, channel, interface) 1171 struct pciide_softc *sc; 1172 int channel; 1173 pcireg_t interface; 1174 { 1175 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1176 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1177 cp->name = PCIIDE_CHANNEL_NAME(channel); 1178 cp->wdc_channel.channel = channel; 1179 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1180 cp->wdc_channel.ch_queue = 1181 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1182 if (cp->wdc_channel.ch_queue == NULL) { 1183 printf("%s %s channel: " 1184 "can't allocate memory for command queue", 1185 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1186 return 0; 1187 } 1188 printf("%s: %s channel %s to %s mode\n", 1189 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1190 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1191 "configured" : "wired", 1192 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1193 "native-PCI" : "compatibility"); 1194 return 1; 1195 } 1196 1197 /* some common code used by several chip channel_map */ 1198 void 1199 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1200 struct pci_attach_args *pa; 1201 struct pciide_channel *cp; 1202 pcireg_t interface; 1203 bus_size_t *cmdsizep, *ctlsizep; 1204 int (*pci_intr) __P((void *)); 1205 { 1206 struct channel_softc *wdc_cp = &cp->wdc_channel; 1207 1208 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1209 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1210 pci_intr); 1211 else 1212 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1213 wdc_cp->channel, cmdsizep, ctlsizep); 1214 1215 if (cp->hw_ok == 0) 1216 return; 1217 wdc_cp->data32iot = wdc_cp->cmd_iot; 1218 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1219 wdcattach(wdc_cp); 1220 } 1221 1222 /* 1223 * Generic code to call to know if a channel can be disabled. Return 1 1224 * if channel can be disabled, 0 if not 1225 */ 1226 int 1227 pciide_chan_candisable(cp) 1228 struct pciide_channel *cp; 1229 { 1230 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1231 struct channel_softc *wdc_cp = &cp->wdc_channel; 1232 1233 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1234 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1235 printf("%s: disabling %s channel (no drives)\n", 1236 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1237 cp->hw_ok = 0; 1238 return 1; 1239 } 1240 return 0; 1241 } 1242 1243 /* 1244 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1245 * Set hw_ok=0 on failure 1246 */ 1247 void 1248 pciide_map_compat_intr(pa, cp, compatchan, interface) 1249 struct pci_attach_args *pa; 1250 struct pciide_channel *cp; 1251 int compatchan, interface; 1252 { 1253 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1254 struct channel_softc *wdc_cp = &cp->wdc_channel; 1255 1256 if (cp->hw_ok == 0) 1257 return; 1258 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1259 return; 1260 1261 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1262 pa, compatchan, pciide_compat_intr, cp); 1263 if (cp->ih == NULL) { 1264 printf("%s: no compatibility interrupt for use by %s " 1265 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1266 cp->hw_ok = 0; 1267 } 1268 } 1269 1270 void 1271 pciide_print_modes(cp) 1272 struct pciide_channel *cp; 1273 { 1274 wdc_print_modes(&cp->wdc_channel); 1275 } 1276 1277 void 1278 default_chip_map(sc, pa) 1279 struct pciide_softc *sc; 1280 struct pci_attach_args *pa; 1281 { 1282 struct pciide_channel *cp; 1283 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1284 pcireg_t csr; 1285 int channel, drive; 1286 struct ata_drive_datas *drvp; 1287 u_int8_t idedma_ctl; 1288 bus_size_t cmdsize, ctlsize; 1289 char *failreason; 1290 1291 if (pciide_chipen(sc, pa) == 0) 1292 return; 1293 1294 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1295 printf("%s: bus-master DMA support present", 1296 sc->sc_wdcdev.sc_dev.dv_xname); 1297 if (sc->sc_pp == &default_product_desc && 1298 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1299 PCIIDE_OPTIONS_DMA) == 0) { 1300 printf(", but unused (no driver support)"); 1301 sc->sc_dma_ok = 0; 1302 } else { 1303 pciide_mapreg_dma(sc, pa); 1304 if (sc->sc_dma_ok != 0) 1305 printf(", used without full driver " 1306 "support"); 1307 } 1308 } else { 1309 printf("%s: hardware does not support DMA", 1310 sc->sc_wdcdev.sc_dev.dv_xname); 1311 sc->sc_dma_ok = 0; 1312 } 1313 printf("\n"); 1314 if (sc->sc_dma_ok) { 1315 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1316 sc->sc_wdcdev.irqack = pciide_irqack; 1317 } 1318 sc->sc_wdcdev.PIO_cap = 0; 1319 sc->sc_wdcdev.DMA_cap = 0; 1320 1321 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1322 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1323 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1324 1325 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1326 cp = &sc->pciide_channels[channel]; 1327 if (pciide_chansetup(sc, channel, interface) == 0) 1328 continue; 1329 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1330 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1331 &ctlsize, pciide_pci_intr); 1332 } else { 1333 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1334 channel, &cmdsize, &ctlsize); 1335 } 1336 if (cp->hw_ok == 0) 1337 continue; 1338 /* 1339 * Check to see if something appears to be there. 1340 */ 1341 failreason = NULL; 1342 if (!wdcprobe(&cp->wdc_channel)) { 1343 failreason = "not responding; disabled or no drives?"; 1344 goto next; 1345 } 1346 /* 1347 * Now, make sure it's actually attributable to this PCI IDE 1348 * channel by trying to access the channel again while the 1349 * PCI IDE controller's I/O space is disabled. (If the 1350 * channel no longer appears to be there, it belongs to 1351 * this controller.) YUCK! 1352 */ 1353 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1354 PCI_COMMAND_STATUS_REG); 1355 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1356 csr & ~PCI_COMMAND_IO_ENABLE); 1357 if (wdcprobe(&cp->wdc_channel)) 1358 failreason = "other hardware responding at addresses"; 1359 pci_conf_write(sc->sc_pc, sc->sc_tag, 1360 PCI_COMMAND_STATUS_REG, csr); 1361 next: 1362 if (failreason) { 1363 printf("%s: %s channel ignored (%s)\n", 1364 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1365 failreason); 1366 cp->hw_ok = 0; 1367 bus_space_unmap(cp->wdc_channel.cmd_iot, 1368 cp->wdc_channel.cmd_ioh, cmdsize); 1369 bus_space_unmap(cp->wdc_channel.ctl_iot, 1370 cp->wdc_channel.ctl_ioh, ctlsize); 1371 } else { 1372 pciide_map_compat_intr(pa, cp, channel, interface); 1373 } 1374 if (cp->hw_ok) { 1375 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1376 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1377 wdcattach(&cp->wdc_channel); 1378 } 1379 } 1380 1381 if (sc->sc_dma_ok == 0) 1382 return; 1383 1384 /* Allocate DMA maps */ 1385 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1386 idedma_ctl = 0; 1387 cp = &sc->pciide_channels[channel]; 1388 for (drive = 0; drive < 2; drive++) { 1389 drvp = &cp->wdc_channel.ch_drive[drive]; 1390 /* If no drive, skip */ 1391 if ((drvp->drive_flags & DRIVE) == 0) 1392 continue; 1393 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1394 continue; 1395 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1396 /* Abort DMA setup */ 1397 printf("%s:%d:%d: can't allocate DMA maps, " 1398 "using PIO transfers\n", 1399 sc->sc_wdcdev.sc_dev.dv_xname, 1400 channel, drive); 1401 drvp->drive_flags &= ~DRIVE_DMA; 1402 } 1403 printf("%s:%d:%d: using DMA data transfers\n", 1404 sc->sc_wdcdev.sc_dev.dv_xname, 1405 channel, drive); 1406 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1407 } 1408 if (idedma_ctl != 0) { 1409 /* Add software bits in status register */ 1410 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1411 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1412 idedma_ctl); 1413 } 1414 } 1415 } 1416 1417 void 1418 piix_chip_map(sc, pa) 1419 struct pciide_softc *sc; 1420 struct pci_attach_args *pa; 1421 { 1422 struct pciide_channel *cp; 1423 int channel; 1424 u_int32_t idetim; 1425 bus_size_t cmdsize, ctlsize; 1426 1427 if (pciide_chipen(sc, pa) == 0) 1428 return; 1429 1430 printf("%s: bus-master DMA support present", 1431 sc->sc_wdcdev.sc_dev.dv_xname); 1432 pciide_mapreg_dma(sc, pa); 1433 printf("\n"); 1434 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1435 WDC_CAPABILITY_MODE; 1436 if (sc->sc_dma_ok) { 1437 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1438 sc->sc_wdcdev.irqack = pciide_irqack; 1439 switch(sc->sc_pp->ide_product) { 1440 case PCI_PRODUCT_INTEL_82371AB_IDE: 1441 case PCI_PRODUCT_INTEL_82440MX_IDE: 1442 case PCI_PRODUCT_INTEL_82801AA_IDE: 1443 case PCI_PRODUCT_INTEL_82801AB_IDE: 1444 case PCI_PRODUCT_INTEL_82801BA_IDE: 1445 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1446 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1447 } 1448 } 1449 sc->sc_wdcdev.PIO_cap = 4; 1450 sc->sc_wdcdev.DMA_cap = 2; 1451 switch(sc->sc_pp->ide_product) { 1452 case PCI_PRODUCT_INTEL_82801AA_IDE: 1453 sc->sc_wdcdev.UDMA_cap = 4; 1454 break; 1455 case PCI_PRODUCT_INTEL_82801BA_IDE: 1456 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1457 sc->sc_wdcdev.UDMA_cap = 5; 1458 break; 1459 default: 1460 sc->sc_wdcdev.UDMA_cap = 2; 1461 } 1462 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1463 sc->sc_wdcdev.set_modes = piix_setup_channel; 1464 else 1465 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1466 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1467 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1468 1469 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1470 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1471 DEBUG_PROBE); 1472 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1473 WDCDEBUG_PRINT((", sidetim=0x%x", 1474 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1475 DEBUG_PROBE); 1476 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1477 WDCDEBUG_PRINT((", udamreg 0x%x", 1478 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1479 DEBUG_PROBE); 1480 } 1481 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1482 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1483 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1485 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1486 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1487 DEBUG_PROBE); 1488 } 1489 1490 } 1491 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1492 1493 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1494 cp = &sc->pciide_channels[channel]; 1495 /* PIIX is compat-only */ 1496 if (pciide_chansetup(sc, channel, 0) == 0) 1497 continue; 1498 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1499 if ((PIIX_IDETIM_READ(idetim, channel) & 1500 PIIX_IDETIM_IDE) == 0) { 1501 printf("%s: %s channel ignored (disabled)\n", 1502 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1503 continue; 1504 } 1505 /* PIIX are compat-only pciide devices */ 1506 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1507 if (cp->hw_ok == 0) 1508 continue; 1509 if (pciide_chan_candisable(cp)) { 1510 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1511 channel); 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1513 idetim); 1514 } 1515 pciide_map_compat_intr(pa, cp, channel, 0); 1516 if (cp->hw_ok == 0) 1517 continue; 1518 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1519 } 1520 1521 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1522 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1523 DEBUG_PROBE); 1524 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1525 WDCDEBUG_PRINT((", sidetim=0x%x", 1526 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1527 DEBUG_PROBE); 1528 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1529 WDCDEBUG_PRINT((", udamreg 0x%x", 1530 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1531 DEBUG_PROBE); 1532 } 1533 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1534 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1535 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1536 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1537 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1538 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1539 DEBUG_PROBE); 1540 } 1541 } 1542 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1543 } 1544 1545 void 1546 piix_setup_channel(chp) 1547 struct channel_softc *chp; 1548 { 1549 u_int8_t mode[2], drive; 1550 u_int32_t oidetim, idetim, idedma_ctl; 1551 struct pciide_channel *cp = (struct pciide_channel*)chp; 1552 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1553 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1554 1555 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1556 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1557 idedma_ctl = 0; 1558 1559 /* set up new idetim: Enable IDE registers decode */ 1560 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1561 chp->channel); 1562 1563 /* setup DMA */ 1564 pciide_channel_dma_setup(cp); 1565 1566 /* 1567 * Here we have to mess up with drives mode: PIIX can't have 1568 * different timings for master and slave drives. 1569 * We need to find the best combination. 1570 */ 1571 1572 /* If both drives supports DMA, take the lower mode */ 1573 if ((drvp[0].drive_flags & DRIVE_DMA) && 1574 (drvp[1].drive_flags & DRIVE_DMA)) { 1575 mode[0] = mode[1] = 1576 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1577 drvp[0].DMA_mode = mode[0]; 1578 drvp[1].DMA_mode = mode[1]; 1579 goto ok; 1580 } 1581 /* 1582 * If only one drive supports DMA, use its mode, and 1583 * put the other one in PIO mode 0 if mode not compatible 1584 */ 1585 if (drvp[0].drive_flags & DRIVE_DMA) { 1586 mode[0] = drvp[0].DMA_mode; 1587 mode[1] = drvp[1].PIO_mode; 1588 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1589 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1590 mode[1] = drvp[1].PIO_mode = 0; 1591 goto ok; 1592 } 1593 if (drvp[1].drive_flags & DRIVE_DMA) { 1594 mode[1] = drvp[1].DMA_mode; 1595 mode[0] = drvp[0].PIO_mode; 1596 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1597 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1598 mode[0] = drvp[0].PIO_mode = 0; 1599 goto ok; 1600 } 1601 /* 1602 * If both drives are not DMA, takes the lower mode, unless 1603 * one of them is PIO mode < 2 1604 */ 1605 if (drvp[0].PIO_mode < 2) { 1606 mode[0] = drvp[0].PIO_mode = 0; 1607 mode[1] = drvp[1].PIO_mode; 1608 } else if (drvp[1].PIO_mode < 2) { 1609 mode[1] = drvp[1].PIO_mode = 0; 1610 mode[0] = drvp[0].PIO_mode; 1611 } else { 1612 mode[0] = mode[1] = 1613 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1614 drvp[0].PIO_mode = mode[0]; 1615 drvp[1].PIO_mode = mode[1]; 1616 } 1617 ok: /* The modes are setup */ 1618 for (drive = 0; drive < 2; drive++) { 1619 if (drvp[drive].drive_flags & DRIVE_DMA) { 1620 idetim |= piix_setup_idetim_timings( 1621 mode[drive], 1, chp->channel); 1622 goto end; 1623 } 1624 } 1625 /* If we are there, none of the drives are DMA */ 1626 if (mode[0] >= 2) 1627 idetim |= piix_setup_idetim_timings( 1628 mode[0], 0, chp->channel); 1629 else 1630 idetim |= piix_setup_idetim_timings( 1631 mode[1], 0, chp->channel); 1632 end: /* 1633 * timing mode is now set up in the controller. Enable 1634 * it per-drive 1635 */ 1636 for (drive = 0; drive < 2; drive++) { 1637 /* If no drive, skip */ 1638 if ((drvp[drive].drive_flags & DRIVE) == 0) 1639 continue; 1640 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1641 if (drvp[drive].drive_flags & DRIVE_DMA) 1642 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1643 } 1644 if (idedma_ctl != 0) { 1645 /* Add software bits in status register */ 1646 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1647 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1648 idedma_ctl); 1649 } 1650 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1651 pciide_print_modes(cp); 1652 } 1653 1654 void 1655 piix3_4_setup_channel(chp) 1656 struct channel_softc *chp; 1657 { 1658 struct ata_drive_datas *drvp; 1659 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1660 struct pciide_channel *cp = (struct pciide_channel*)chp; 1661 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1662 int drive; 1663 int channel = chp->channel; 1664 1665 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1666 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1667 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1668 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1669 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1670 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1671 PIIX_SIDETIM_RTC_MASK(channel)); 1672 1673 idedma_ctl = 0; 1674 /* If channel disabled, no need to go further */ 1675 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1676 return; 1677 /* set up new idetim: Enable IDE registers decode */ 1678 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1679 1680 /* setup DMA if needed */ 1681 pciide_channel_dma_setup(cp); 1682 1683 for (drive = 0; drive < 2; drive++) { 1684 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1685 PIIX_UDMATIM_SET(0x3, channel, drive)); 1686 drvp = &chp->ch_drive[drive]; 1687 /* If no drive, skip */ 1688 if ((drvp->drive_flags & DRIVE) == 0) 1689 continue; 1690 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1691 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1692 goto pio; 1693 1694 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1695 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1696 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1697 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1698 ideconf |= PIIX_CONFIG_PINGPONG; 1699 } 1700 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1701 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1702 /* setup Ultra/100 */ 1703 if (drvp->UDMA_mode > 2 && 1704 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1705 drvp->UDMA_mode = 2; 1706 if (drvp->UDMA_mode > 4) { 1707 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1708 } else { 1709 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1710 if (drvp->UDMA_mode > 2) { 1711 ideconf |= PIIX_CONFIG_UDMA66(channel, 1712 drive); 1713 } else { 1714 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1715 drive); 1716 } 1717 } 1718 } 1719 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1720 /* setup Ultra/66 */ 1721 if (drvp->UDMA_mode > 2 && 1722 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1723 drvp->UDMA_mode = 2; 1724 if (drvp->UDMA_mode > 2) 1725 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1726 else 1727 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1728 } 1729 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1730 (drvp->drive_flags & DRIVE_UDMA)) { 1731 /* use Ultra/DMA */ 1732 drvp->drive_flags &= ~DRIVE_DMA; 1733 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1734 udmareg |= PIIX_UDMATIM_SET( 1735 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1736 } else { 1737 /* use Multiword DMA */ 1738 drvp->drive_flags &= ~DRIVE_UDMA; 1739 if (drive == 0) { 1740 idetim |= piix_setup_idetim_timings( 1741 drvp->DMA_mode, 1, channel); 1742 } else { 1743 sidetim |= piix_setup_sidetim_timings( 1744 drvp->DMA_mode, 1, channel); 1745 idetim =PIIX_IDETIM_SET(idetim, 1746 PIIX_IDETIM_SITRE, channel); 1747 } 1748 } 1749 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1750 1751 pio: /* use PIO mode */ 1752 idetim |= piix_setup_idetim_drvs(drvp); 1753 if (drive == 0) { 1754 idetim |= piix_setup_idetim_timings( 1755 drvp->PIO_mode, 0, channel); 1756 } else { 1757 sidetim |= piix_setup_sidetim_timings( 1758 drvp->PIO_mode, 0, channel); 1759 idetim =PIIX_IDETIM_SET(idetim, 1760 PIIX_IDETIM_SITRE, channel); 1761 } 1762 } 1763 if (idedma_ctl != 0) { 1764 /* Add software bits in status register */ 1765 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1766 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1767 idedma_ctl); 1768 } 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1770 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1771 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1772 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1773 pciide_print_modes(cp); 1774 } 1775 1776 1777 /* setup ISP and RTC fields, based on mode */ 1778 static u_int32_t 1779 piix_setup_idetim_timings(mode, dma, channel) 1780 u_int8_t mode; 1781 u_int8_t dma; 1782 u_int8_t channel; 1783 { 1784 1785 if (dma) 1786 return PIIX_IDETIM_SET(0, 1787 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1788 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1789 channel); 1790 else 1791 return PIIX_IDETIM_SET(0, 1792 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1793 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1794 channel); 1795 } 1796 1797 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1798 static u_int32_t 1799 piix_setup_idetim_drvs(drvp) 1800 struct ata_drive_datas *drvp; 1801 { 1802 u_int32_t ret = 0; 1803 struct channel_softc *chp = drvp->chnl_softc; 1804 u_int8_t channel = chp->channel; 1805 u_int8_t drive = drvp->drive; 1806 1807 /* 1808 * If drive is using UDMA, timings setups are independant 1809 * So just check DMA and PIO here. 1810 */ 1811 if (drvp->drive_flags & DRIVE_DMA) { 1812 /* if mode = DMA mode 0, use compatible timings */ 1813 if ((drvp->drive_flags & DRIVE_DMA) && 1814 drvp->DMA_mode == 0) { 1815 drvp->PIO_mode = 0; 1816 return ret; 1817 } 1818 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1819 /* 1820 * PIO and DMA timings are the same, use fast timings for PIO 1821 * too, else use compat timings. 1822 */ 1823 if ((piix_isp_pio[drvp->PIO_mode] != 1824 piix_isp_dma[drvp->DMA_mode]) || 1825 (piix_rtc_pio[drvp->PIO_mode] != 1826 piix_rtc_dma[drvp->DMA_mode])) 1827 drvp->PIO_mode = 0; 1828 /* if PIO mode <= 2, use compat timings for PIO */ 1829 if (drvp->PIO_mode <= 2) { 1830 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1831 channel); 1832 return ret; 1833 } 1834 } 1835 1836 /* 1837 * Now setup PIO modes. If mode < 2, use compat timings. 1838 * Else enable fast timings. Enable IORDY and prefetch/post 1839 * if PIO mode >= 3. 1840 */ 1841 1842 if (drvp->PIO_mode < 2) 1843 return ret; 1844 1845 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1846 if (drvp->PIO_mode >= 3) { 1847 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1848 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1849 } 1850 return ret; 1851 } 1852 1853 /* setup values in SIDETIM registers, based on mode */ 1854 static u_int32_t 1855 piix_setup_sidetim_timings(mode, dma, channel) 1856 u_int8_t mode; 1857 u_int8_t dma; 1858 u_int8_t channel; 1859 { 1860 if (dma) 1861 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1862 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1863 else 1864 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1865 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1866 } 1867 1868 void 1869 amd7x6_chip_map(sc, pa) 1870 struct pciide_softc *sc; 1871 struct pci_attach_args *pa; 1872 { 1873 struct pciide_channel *cp; 1874 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1875 int channel; 1876 pcireg_t chanenable; 1877 bus_size_t cmdsize, ctlsize; 1878 1879 if (pciide_chipen(sc, pa) == 0) 1880 return; 1881 printf("%s: bus-master DMA support present", 1882 sc->sc_wdcdev.sc_dev.dv_xname); 1883 pciide_mapreg_dma(sc, pa); 1884 printf("\n"); 1885 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1886 WDC_CAPABILITY_MODE; 1887 if (sc->sc_dma_ok) { 1888 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1889 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1890 sc->sc_wdcdev.irqack = pciide_irqack; 1891 } 1892 sc->sc_wdcdev.PIO_cap = 4; 1893 sc->sc_wdcdev.DMA_cap = 2; 1894 1895 if (sc->sc_pp->ide_product == PCI_PRODUCT_AMD_PBC766_IDE) 1896 sc->sc_wdcdev.UDMA_cap = 5; 1897 else 1898 sc->sc_wdcdev.UDMA_cap = 4; 1899 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1900 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1901 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1902 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1903 1904 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1905 DEBUG_PROBE); 1906 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1907 cp = &sc->pciide_channels[channel]; 1908 if (pciide_chansetup(sc, channel, interface) == 0) 1909 continue; 1910 1911 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1912 printf("%s: %s channel ignored (disabled)\n", 1913 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1914 continue; 1915 } 1916 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1917 pciide_pci_intr); 1918 1919 if (pciide_chan_candisable(cp)) 1920 chanenable &= ~AMD7X6_CHAN_EN(channel); 1921 pciide_map_compat_intr(pa, cp, channel, interface); 1922 if (cp->hw_ok == 0) 1923 continue; 1924 1925 amd7x6_setup_channel(&cp->wdc_channel); 1926 } 1927 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1928 chanenable); 1929 return; 1930 } 1931 1932 void 1933 amd7x6_setup_channel(chp) 1934 struct channel_softc *chp; 1935 { 1936 u_int32_t udmatim_reg, datatim_reg; 1937 u_int8_t idedma_ctl; 1938 int mode, drive; 1939 struct ata_drive_datas *drvp; 1940 struct pciide_channel *cp = (struct pciide_channel*)chp; 1941 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1942 #ifndef PCIIDE_AMD756_ENABLEDMA 1943 int rev = PCI_REVISION( 1944 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1945 #endif 1946 1947 idedma_ctl = 0; 1948 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1949 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1950 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1951 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1952 1953 /* setup DMA if needed */ 1954 pciide_channel_dma_setup(cp); 1955 1956 for (drive = 0; drive < 2; drive++) { 1957 drvp = &chp->ch_drive[drive]; 1958 /* If no drive, skip */ 1959 if ((drvp->drive_flags & DRIVE) == 0) 1960 continue; 1961 /* add timing values, setup DMA if needed */ 1962 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1963 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1964 mode = drvp->PIO_mode; 1965 goto pio; 1966 } 1967 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1968 (drvp->drive_flags & DRIVE_UDMA)) { 1969 /* use Ultra/DMA */ 1970 drvp->drive_flags &= ~DRIVE_DMA; 1971 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 1972 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 1973 AMD7X6_UDMA_TIME(chp->channel, drive, 1974 amd7x6_udma_tim[drvp->UDMA_mode]); 1975 /* can use PIO timings, MW DMA unused */ 1976 mode = drvp->PIO_mode; 1977 } else { 1978 /* use Multiword DMA, but only if revision is OK */ 1979 drvp->drive_flags &= ~DRIVE_UDMA; 1980 #ifndef PCIIDE_AMD756_ENABLEDMA 1981 /* 1982 * The workaround doesn't seem to be necessary 1983 * with all drives, so it can be disabled by 1984 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1985 * triggered. 1986 */ 1987 if (sc->sc_pp->ide_product == 1988 PCI_PRODUCT_AMD_PBC756_IDE && 1989 AMD756_CHIPREV_DISABLEDMA(rev)) { 1990 printf("%s:%d:%d: multi-word DMA disabled due " 1991 "to chip revision\n", 1992 sc->sc_wdcdev.sc_dev.dv_xname, 1993 chp->channel, drive); 1994 mode = drvp->PIO_mode; 1995 drvp->drive_flags &= ~DRIVE_DMA; 1996 goto pio; 1997 } 1998 #endif 1999 /* mode = min(pio, dma+2) */ 2000 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2001 mode = drvp->PIO_mode; 2002 else 2003 mode = drvp->DMA_mode + 2; 2004 } 2005 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2006 2007 pio: /* setup PIO mode */ 2008 if (mode <= 2) { 2009 drvp->DMA_mode = 0; 2010 drvp->PIO_mode = 0; 2011 mode = 0; 2012 } else { 2013 drvp->PIO_mode = mode; 2014 drvp->DMA_mode = mode - 2; 2015 } 2016 datatim_reg |= 2017 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2018 amd7x6_pio_set[mode]) | 2019 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2020 amd7x6_pio_rec[mode]); 2021 } 2022 if (idedma_ctl != 0) { 2023 /* Add software bits in status register */ 2024 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2025 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2026 idedma_ctl); 2027 } 2028 pciide_print_modes(cp); 2029 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2030 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2031 } 2032 2033 void 2034 apollo_chip_map(sc, pa) 2035 struct pciide_softc *sc; 2036 struct pci_attach_args *pa; 2037 { 2038 struct pciide_channel *cp; 2039 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2040 int channel; 2041 u_int32_t ideconf; 2042 bus_size_t cmdsize, ctlsize; 2043 pcitag_t pcib_tag; 2044 pcireg_t pcib_id, pcib_class; 2045 2046 if (pciide_chipen(sc, pa) == 0) 2047 return; 2048 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2049 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2050 /* and read ID and rev of the ISA bridge */ 2051 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2052 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2053 printf(": VIA Technologies "); 2054 switch (PCI_PRODUCT(pcib_id)) { 2055 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2056 printf("VT82C586 (Apollo VP) "); 2057 if(PCI_REVISION(pcib_class) >= 0x02) { 2058 printf("ATA33 controller\n"); 2059 sc->sc_wdcdev.UDMA_cap = 2; 2060 } else { 2061 printf("controller\n"); 2062 sc->sc_wdcdev.UDMA_cap = 0; 2063 } 2064 break; 2065 case PCI_PRODUCT_VIATECH_VT82C596A: 2066 printf("VT82C596A (Apollo Pro) "); 2067 if (PCI_REVISION(pcib_class) >= 0x12) { 2068 printf("ATA66 controller\n"); 2069 sc->sc_wdcdev.UDMA_cap = 4; 2070 } else { 2071 printf("ATA33 controller\n"); 2072 sc->sc_wdcdev.UDMA_cap = 2; 2073 } 2074 break; 2075 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2076 printf("VT82C686A (Apollo KX133) "); 2077 if (PCI_REVISION(pcib_class) >= 0x40) { 2078 printf("ATA100 controller\n"); 2079 sc->sc_wdcdev.UDMA_cap = 5; 2080 } else { 2081 printf("ATA66 controller\n"); 2082 sc->sc_wdcdev.UDMA_cap = 4; 2083 } 2084 break; 2085 default: 2086 printf("unknown ATA controller\n"); 2087 sc->sc_wdcdev.UDMA_cap = 0; 2088 } 2089 2090 printf("%s: bus-master DMA support present", 2091 sc->sc_wdcdev.sc_dev.dv_xname); 2092 pciide_mapreg_dma(sc, pa); 2093 printf("\n"); 2094 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2095 WDC_CAPABILITY_MODE; 2096 if (sc->sc_dma_ok) { 2097 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2098 sc->sc_wdcdev.irqack = pciide_irqack; 2099 if (sc->sc_wdcdev.UDMA_cap > 0) 2100 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2101 } 2102 sc->sc_wdcdev.PIO_cap = 4; 2103 sc->sc_wdcdev.DMA_cap = 2; 2104 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2105 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2106 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2107 2108 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2109 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2110 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2111 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2112 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2113 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2114 DEBUG_PROBE); 2115 2116 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2117 cp = &sc->pciide_channels[channel]; 2118 if (pciide_chansetup(sc, channel, interface) == 0) 2119 continue; 2120 2121 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2122 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2123 printf("%s: %s channel ignored (disabled)\n", 2124 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2125 continue; 2126 } 2127 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2128 pciide_pci_intr); 2129 if (cp->hw_ok == 0) 2130 continue; 2131 if (pciide_chan_candisable(cp)) { 2132 ideconf &= ~APO_IDECONF_EN(channel); 2133 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2134 ideconf); 2135 } 2136 pciide_map_compat_intr(pa, cp, channel, interface); 2137 2138 if (cp->hw_ok == 0) 2139 continue; 2140 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2141 } 2142 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2143 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2144 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2145 } 2146 2147 void 2148 apollo_setup_channel(chp) 2149 struct channel_softc *chp; 2150 { 2151 u_int32_t udmatim_reg, datatim_reg; 2152 u_int8_t idedma_ctl; 2153 int mode, drive; 2154 struct ata_drive_datas *drvp; 2155 struct pciide_channel *cp = (struct pciide_channel*)chp; 2156 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2157 2158 idedma_ctl = 0; 2159 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2160 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2161 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2162 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2163 2164 /* setup DMA if needed */ 2165 pciide_channel_dma_setup(cp); 2166 2167 for (drive = 0; drive < 2; drive++) { 2168 drvp = &chp->ch_drive[drive]; 2169 /* If no drive, skip */ 2170 if ((drvp->drive_flags & DRIVE) == 0) 2171 continue; 2172 /* add timing values, setup DMA if needed */ 2173 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2174 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2175 mode = drvp->PIO_mode; 2176 goto pio; 2177 } 2178 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2179 (drvp->drive_flags & DRIVE_UDMA)) { 2180 /* use Ultra/DMA */ 2181 drvp->drive_flags &= ~DRIVE_DMA; 2182 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2183 APO_UDMA_EN_MTH(chp->channel, drive); 2184 if (sc->sc_wdcdev.UDMA_cap == 5) { 2185 /* 686b */ 2186 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2187 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2188 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2189 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2190 /* 596b or 686a */ 2191 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2192 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2193 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2194 } else { 2195 /* 596a or 586b */ 2196 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2197 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2198 } 2199 /* can use PIO timings, MW DMA unused */ 2200 mode = drvp->PIO_mode; 2201 } else { 2202 /* use Multiword DMA */ 2203 drvp->drive_flags &= ~DRIVE_UDMA; 2204 /* mode = min(pio, dma+2) */ 2205 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2206 mode = drvp->PIO_mode; 2207 else 2208 mode = drvp->DMA_mode + 2; 2209 } 2210 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2211 2212 pio: /* setup PIO mode */ 2213 if (mode <= 2) { 2214 drvp->DMA_mode = 0; 2215 drvp->PIO_mode = 0; 2216 mode = 0; 2217 } else { 2218 drvp->PIO_mode = mode; 2219 drvp->DMA_mode = mode - 2; 2220 } 2221 datatim_reg |= 2222 APO_DATATIM_PULSE(chp->channel, drive, 2223 apollo_pio_set[mode]) | 2224 APO_DATATIM_RECOV(chp->channel, drive, 2225 apollo_pio_rec[mode]); 2226 } 2227 if (idedma_ctl != 0) { 2228 /* Add software bits in status register */ 2229 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2230 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2231 idedma_ctl); 2232 } 2233 pciide_print_modes(cp); 2234 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2235 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2236 } 2237 2238 void 2239 cmd_channel_map(pa, sc, channel) 2240 struct pci_attach_args *pa; 2241 struct pciide_softc *sc; 2242 int channel; 2243 { 2244 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2245 bus_size_t cmdsize, ctlsize; 2246 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2247 int interface; 2248 2249 /* 2250 * The 0648/0649 can be told to identify as a RAID controller. 2251 * In this case, we have to fake interface 2252 */ 2253 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2254 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2255 PCIIDE_INTERFACE_SETTABLE(1); 2256 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2257 CMD_CONF_DSA1) 2258 interface |= PCIIDE_INTERFACE_PCI(0) | 2259 PCIIDE_INTERFACE_PCI(1); 2260 } else { 2261 interface = PCI_INTERFACE(pa->pa_class); 2262 } 2263 2264 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2265 cp->name = PCIIDE_CHANNEL_NAME(channel); 2266 cp->wdc_channel.channel = channel; 2267 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2268 2269 if (channel > 0) { 2270 cp->wdc_channel.ch_queue = 2271 sc->pciide_channels[0].wdc_channel.ch_queue; 2272 } else { 2273 cp->wdc_channel.ch_queue = 2274 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2275 } 2276 if (cp->wdc_channel.ch_queue == NULL) { 2277 printf("%s %s channel: " 2278 "can't allocate memory for command queue", 2279 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2280 return; 2281 } 2282 2283 printf("%s: %s channel %s to %s mode\n", 2284 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2285 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2286 "configured" : "wired", 2287 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2288 "native-PCI" : "compatibility"); 2289 2290 /* 2291 * with a CMD PCI64x, if we get here, the first channel is enabled: 2292 * there's no way to disable the first channel without disabling 2293 * the whole device 2294 */ 2295 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2296 printf("%s: %s channel ignored (disabled)\n", 2297 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2298 return; 2299 } 2300 2301 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2302 if (cp->hw_ok == 0) 2303 return; 2304 if (channel == 1) { 2305 if (pciide_chan_candisable(cp)) { 2306 ctrl &= ~CMD_CTRL_2PORT; 2307 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2308 CMD_CTRL, ctrl); 2309 } 2310 } 2311 pciide_map_compat_intr(pa, cp, channel, interface); 2312 } 2313 2314 int 2315 cmd_pci_intr(arg) 2316 void *arg; 2317 { 2318 struct pciide_softc *sc = arg; 2319 struct pciide_channel *cp; 2320 struct channel_softc *wdc_cp; 2321 int i, rv, crv; 2322 u_int32_t priirq, secirq; 2323 2324 rv = 0; 2325 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2326 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2327 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2328 cp = &sc->pciide_channels[i]; 2329 wdc_cp = &cp->wdc_channel; 2330 /* If a compat channel skip. */ 2331 if (cp->compat) 2332 continue; 2333 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2334 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2335 crv = wdcintr(wdc_cp); 2336 if (crv == 0) 2337 printf("%s:%d: bogus intr\n", 2338 sc->sc_wdcdev.sc_dev.dv_xname, i); 2339 else 2340 rv = 1; 2341 } 2342 } 2343 return rv; 2344 } 2345 2346 void 2347 cmd_chip_map(sc, pa) 2348 struct pciide_softc *sc; 2349 struct pci_attach_args *pa; 2350 { 2351 int channel; 2352 2353 /* 2354 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2355 * and base adresses registers can be disabled at 2356 * hardware level. In this case, the device is wired 2357 * in compat mode and its first channel is always enabled, 2358 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2359 * In fact, it seems that the first channel of the CMD PCI0640 2360 * can't be disabled. 2361 */ 2362 2363 #ifdef PCIIDE_CMD064x_DISABLE 2364 if (pciide_chipen(sc, pa) == 0) 2365 return; 2366 #endif 2367 2368 printf("%s: hardware does not support DMA\n", 2369 sc->sc_wdcdev.sc_dev.dv_xname); 2370 sc->sc_dma_ok = 0; 2371 2372 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2373 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2374 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2375 2376 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2377 cmd_channel_map(pa, sc, channel); 2378 } 2379 } 2380 2381 void 2382 cmd0643_9_chip_map(sc, pa) 2383 struct pciide_softc *sc; 2384 struct pci_attach_args *pa; 2385 { 2386 struct pciide_channel *cp; 2387 int channel; 2388 int rev = PCI_REVISION( 2389 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2390 2391 /* 2392 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2393 * and base adresses registers can be disabled at 2394 * hardware level. In this case, the device is wired 2395 * in compat mode and its first channel is always enabled, 2396 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2397 * In fact, it seems that the first channel of the CMD PCI0640 2398 * can't be disabled. 2399 */ 2400 2401 #ifdef PCIIDE_CMD064x_DISABLE 2402 if (pciide_chipen(sc, pa) == 0) 2403 return; 2404 #endif 2405 printf("%s: bus-master DMA support present", 2406 sc->sc_wdcdev.sc_dev.dv_xname); 2407 pciide_mapreg_dma(sc, pa); 2408 printf("\n"); 2409 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2410 WDC_CAPABILITY_MODE; 2411 if (sc->sc_dma_ok) { 2412 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2413 switch (sc->sc_pp->ide_product) { 2414 case PCI_PRODUCT_CMDTECH_649: 2415 case PCI_PRODUCT_CMDTECH_648: 2416 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2417 sc->sc_wdcdev.UDMA_cap = 4; 2418 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2419 break; 2420 case PCI_PRODUCT_CMDTECH_646: 2421 if (rev >= CMD0646U2_REV) { 2422 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2423 sc->sc_wdcdev.UDMA_cap = 2; 2424 } else if (rev >= CMD0646U_REV) { 2425 /* 2426 * Linux's driver claims that the 646U is broken 2427 * with UDMA. Only enable it if we know what we're 2428 * doing 2429 */ 2430 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2431 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2432 sc->sc_wdcdev.UDMA_cap = 2; 2433 #endif 2434 /* explicitely disable UDMA */ 2435 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2436 CMD_UDMATIM(0), 0); 2437 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2438 CMD_UDMATIM(1), 0); 2439 } 2440 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2441 break; 2442 default: 2443 sc->sc_wdcdev.irqack = pciide_irqack; 2444 } 2445 } 2446 2447 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2448 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2449 sc->sc_wdcdev.PIO_cap = 4; 2450 sc->sc_wdcdev.DMA_cap = 2; 2451 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2452 2453 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2454 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2455 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2456 DEBUG_PROBE); 2457 2458 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2459 cp = &sc->pciide_channels[channel]; 2460 cmd_channel_map(pa, sc, channel); 2461 if (cp->hw_ok == 0) 2462 continue; 2463 cmd0643_9_setup_channel(&cp->wdc_channel); 2464 } 2465 /* 2466 * note - this also makes sure we clear the irq disable and reset 2467 * bits 2468 */ 2469 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2470 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2471 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2472 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2473 DEBUG_PROBE); 2474 } 2475 2476 void 2477 cmd0643_9_setup_channel(chp) 2478 struct channel_softc *chp; 2479 { 2480 struct ata_drive_datas *drvp; 2481 u_int8_t tim; 2482 u_int32_t idedma_ctl, udma_reg; 2483 int drive; 2484 struct pciide_channel *cp = (struct pciide_channel*)chp; 2485 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2486 2487 idedma_ctl = 0; 2488 /* setup DMA if needed */ 2489 pciide_channel_dma_setup(cp); 2490 2491 for (drive = 0; drive < 2; drive++) { 2492 drvp = &chp->ch_drive[drive]; 2493 /* If no drive, skip */ 2494 if ((drvp->drive_flags & DRIVE) == 0) 2495 continue; 2496 /* add timing values, setup DMA if needed */ 2497 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2498 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2499 if (drvp->drive_flags & DRIVE_UDMA) { 2500 /* UltraDMA on a 646U2, 0648 or 0649 */ 2501 drvp->drive_flags &= ~DRIVE_DMA; 2502 udma_reg = pciide_pci_read(sc->sc_pc, 2503 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2504 if (drvp->UDMA_mode > 2 && 2505 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2506 CMD_BICSR) & 2507 CMD_BICSR_80(chp->channel)) == 0) 2508 drvp->UDMA_mode = 2; 2509 if (drvp->UDMA_mode > 2) 2510 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2511 else if (sc->sc_wdcdev.UDMA_cap > 2) 2512 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2513 udma_reg |= CMD_UDMATIM_UDMA(drive); 2514 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2515 CMD_UDMATIM_TIM_OFF(drive)); 2516 udma_reg |= 2517 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2518 CMD_UDMATIM_TIM_OFF(drive)); 2519 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2520 CMD_UDMATIM(chp->channel), udma_reg); 2521 } else { 2522 /* 2523 * use Multiword DMA. 2524 * Timings will be used for both PIO and DMA, 2525 * so adjust DMA mode if needed 2526 * if we have a 0646U2/8/9, turn off UDMA 2527 */ 2528 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2529 udma_reg = pciide_pci_read(sc->sc_pc, 2530 sc->sc_tag, 2531 CMD_UDMATIM(chp->channel)); 2532 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2533 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2534 CMD_UDMATIM(chp->channel), 2535 udma_reg); 2536 } 2537 if (drvp->PIO_mode >= 3 && 2538 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2539 drvp->DMA_mode = drvp->PIO_mode - 2; 2540 } 2541 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2542 } 2543 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2544 } 2545 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2546 CMD_DATA_TIM(chp->channel, drive), tim); 2547 } 2548 if (idedma_ctl != 0) { 2549 /* Add software bits in status register */ 2550 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2551 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2552 idedma_ctl); 2553 } 2554 pciide_print_modes(cp); 2555 } 2556 2557 void 2558 cmd646_9_irqack(chp) 2559 struct channel_softc *chp; 2560 { 2561 u_int32_t priirq, secirq; 2562 struct pciide_channel *cp = (struct pciide_channel*)chp; 2563 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2564 2565 if (chp->channel == 0) { 2566 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2567 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2568 } else { 2569 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2570 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2571 } 2572 pciide_irqack(chp); 2573 } 2574 2575 void 2576 cy693_chip_map(sc, pa) 2577 struct pciide_softc *sc; 2578 struct pci_attach_args *pa; 2579 { 2580 struct pciide_channel *cp; 2581 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2582 bus_size_t cmdsize, ctlsize; 2583 2584 if (pciide_chipen(sc, pa) == 0) 2585 return; 2586 /* 2587 * this chip has 2 PCI IDE functions, one for primary and one for 2588 * secondary. So we need to call pciide_mapregs_compat() with 2589 * the real channel 2590 */ 2591 if (pa->pa_function == 1) { 2592 sc->sc_cy_compatchan = 0; 2593 } else if (pa->pa_function == 2) { 2594 sc->sc_cy_compatchan = 1; 2595 } else { 2596 printf("%s: unexpected PCI function %d\n", 2597 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2598 return; 2599 } 2600 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2601 printf("%s: bus-master DMA support present", 2602 sc->sc_wdcdev.sc_dev.dv_xname); 2603 pciide_mapreg_dma(sc, pa); 2604 } else { 2605 printf("%s: hardware does not support DMA", 2606 sc->sc_wdcdev.sc_dev.dv_xname); 2607 sc->sc_dma_ok = 0; 2608 } 2609 printf("\n"); 2610 2611 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2612 if (sc->sc_cy_handle == NULL) { 2613 printf("%s: unable to map hyperCache control registers\n", 2614 sc->sc_wdcdev.sc_dev.dv_xname); 2615 sc->sc_dma_ok = 0; 2616 } 2617 2618 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2619 WDC_CAPABILITY_MODE; 2620 if (sc->sc_dma_ok) { 2621 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2622 sc->sc_wdcdev.irqack = pciide_irqack; 2623 } 2624 sc->sc_wdcdev.PIO_cap = 4; 2625 sc->sc_wdcdev.DMA_cap = 2; 2626 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2627 2628 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2629 sc->sc_wdcdev.nchannels = 1; 2630 2631 /* Only one channel for this chip; if we are here it's enabled */ 2632 cp = &sc->pciide_channels[0]; 2633 sc->wdc_chanarray[0] = &cp->wdc_channel; 2634 cp->name = PCIIDE_CHANNEL_NAME(0); 2635 cp->wdc_channel.channel = 0; 2636 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2637 cp->wdc_channel.ch_queue = 2638 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2639 if (cp->wdc_channel.ch_queue == NULL) { 2640 printf("%s primary channel: " 2641 "can't allocate memory for command queue", 2642 sc->sc_wdcdev.sc_dev.dv_xname); 2643 return; 2644 } 2645 printf("%s: primary channel %s to ", 2646 sc->sc_wdcdev.sc_dev.dv_xname, 2647 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2648 "configured" : "wired"); 2649 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2650 printf("native-PCI"); 2651 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2652 pciide_pci_intr); 2653 } else { 2654 printf("compatibility"); 2655 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2656 &cmdsize, &ctlsize); 2657 } 2658 printf(" mode\n"); 2659 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2660 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2661 wdcattach(&cp->wdc_channel); 2662 if (pciide_chan_candisable(cp)) { 2663 pci_conf_write(sc->sc_pc, sc->sc_tag, 2664 PCI_COMMAND_STATUS_REG, 0); 2665 } 2666 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2667 if (cp->hw_ok == 0) 2668 return; 2669 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2670 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2671 cy693_setup_channel(&cp->wdc_channel); 2672 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2673 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2674 } 2675 2676 void 2677 cy693_setup_channel(chp) 2678 struct channel_softc *chp; 2679 { 2680 struct ata_drive_datas *drvp; 2681 int drive; 2682 u_int32_t cy_cmd_ctrl; 2683 u_int32_t idedma_ctl; 2684 struct pciide_channel *cp = (struct pciide_channel*)chp; 2685 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2686 int dma_mode = -1; 2687 2688 cy_cmd_ctrl = idedma_ctl = 0; 2689 2690 /* setup DMA if needed */ 2691 pciide_channel_dma_setup(cp); 2692 2693 for (drive = 0; drive < 2; drive++) { 2694 drvp = &chp->ch_drive[drive]; 2695 /* If no drive, skip */ 2696 if ((drvp->drive_flags & DRIVE) == 0) 2697 continue; 2698 /* add timing values, setup DMA if needed */ 2699 if (drvp->drive_flags & DRIVE_DMA) { 2700 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2701 /* use Multiword DMA */ 2702 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2703 dma_mode = drvp->DMA_mode; 2704 } 2705 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2706 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2707 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2708 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2709 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2710 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2711 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2712 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2713 } 2714 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2715 chp->ch_drive[0].DMA_mode = dma_mode; 2716 chp->ch_drive[1].DMA_mode = dma_mode; 2717 2718 if (dma_mode == -1) 2719 dma_mode = 0; 2720 2721 if (sc->sc_cy_handle != NULL) { 2722 /* Note: `multiple' is implied. */ 2723 cy82c693_write(sc->sc_cy_handle, 2724 (sc->sc_cy_compatchan == 0) ? 2725 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2726 } 2727 2728 pciide_print_modes(cp); 2729 2730 if (idedma_ctl != 0) { 2731 /* Add software bits in status register */ 2732 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2733 IDEDMA_CTL, idedma_ctl); 2734 } 2735 } 2736 2737 void 2738 sis_chip_map(sc, pa) 2739 struct pciide_softc *sc; 2740 struct pci_attach_args *pa; 2741 { 2742 struct pciide_channel *cp; 2743 int channel; 2744 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2745 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2746 pcireg_t rev = PCI_REVISION(pa->pa_class); 2747 bus_size_t cmdsize, ctlsize; 2748 2749 if (pciide_chipen(sc, pa) == 0) 2750 return; 2751 printf("%s: bus-master DMA support present", 2752 sc->sc_wdcdev.sc_dev.dv_xname); 2753 pciide_mapreg_dma(sc, pa); 2754 printf("\n"); 2755 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2756 WDC_CAPABILITY_MODE; 2757 if (sc->sc_dma_ok) { 2758 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2759 sc->sc_wdcdev.irqack = pciide_irqack; 2760 if (rev > 0xd0) 2761 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2762 } 2763 2764 sc->sc_wdcdev.PIO_cap = 4; 2765 sc->sc_wdcdev.DMA_cap = 2; 2766 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2767 sc->sc_wdcdev.UDMA_cap = 2; 2768 sc->sc_wdcdev.set_modes = sis_setup_channel; 2769 2770 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2771 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2772 2773 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2774 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2775 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2776 2777 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2778 cp = &sc->pciide_channels[channel]; 2779 if (pciide_chansetup(sc, channel, interface) == 0) 2780 continue; 2781 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2782 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2783 printf("%s: %s channel ignored (disabled)\n", 2784 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2785 continue; 2786 } 2787 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2788 pciide_pci_intr); 2789 if (cp->hw_ok == 0) 2790 continue; 2791 if (pciide_chan_candisable(cp)) { 2792 if (channel == 0) 2793 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2794 else 2795 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2796 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2797 sis_ctr0); 2798 } 2799 pciide_map_compat_intr(pa, cp, channel, interface); 2800 if (cp->hw_ok == 0) 2801 continue; 2802 sis_setup_channel(&cp->wdc_channel); 2803 } 2804 } 2805 2806 void 2807 sis_setup_channel(chp) 2808 struct channel_softc *chp; 2809 { 2810 struct ata_drive_datas *drvp; 2811 int drive; 2812 u_int32_t sis_tim; 2813 u_int32_t idedma_ctl; 2814 struct pciide_channel *cp = (struct pciide_channel*)chp; 2815 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2816 2817 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2818 "channel %d 0x%x\n", chp->channel, 2819 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2820 DEBUG_PROBE); 2821 sis_tim = 0; 2822 idedma_ctl = 0; 2823 /* setup DMA if needed */ 2824 pciide_channel_dma_setup(cp); 2825 2826 for (drive = 0; drive < 2; drive++) { 2827 drvp = &chp->ch_drive[drive]; 2828 /* If no drive, skip */ 2829 if ((drvp->drive_flags & DRIVE) == 0) 2830 continue; 2831 /* add timing values, setup DMA if needed */ 2832 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2833 (drvp->drive_flags & DRIVE_UDMA) == 0) 2834 goto pio; 2835 2836 if (drvp->drive_flags & DRIVE_UDMA) { 2837 /* use Ultra/DMA */ 2838 drvp->drive_flags &= ~DRIVE_DMA; 2839 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2840 SIS_TIM_UDMA_TIME_OFF(drive); 2841 sis_tim |= SIS_TIM_UDMA_EN(drive); 2842 } else { 2843 /* 2844 * use Multiword DMA 2845 * Timings will be used for both PIO and DMA, 2846 * so adjust DMA mode if needed 2847 */ 2848 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2849 drvp->PIO_mode = drvp->DMA_mode + 2; 2850 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2851 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2852 drvp->PIO_mode - 2 : 0; 2853 if (drvp->DMA_mode == 0) 2854 drvp->PIO_mode = 0; 2855 } 2856 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2857 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2858 SIS_TIM_ACT_OFF(drive); 2859 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2860 SIS_TIM_REC_OFF(drive); 2861 } 2862 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2863 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2864 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2865 if (idedma_ctl != 0) { 2866 /* Add software bits in status register */ 2867 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2868 IDEDMA_CTL, idedma_ctl); 2869 } 2870 pciide_print_modes(cp); 2871 } 2872 2873 void 2874 acer_chip_map(sc, pa) 2875 struct pciide_softc *sc; 2876 struct pci_attach_args *pa; 2877 { 2878 struct pciide_channel *cp; 2879 int channel; 2880 pcireg_t cr, interface; 2881 bus_size_t cmdsize, ctlsize; 2882 pcireg_t rev = PCI_REVISION(pa->pa_class); 2883 2884 if (pciide_chipen(sc, pa) == 0) 2885 return; 2886 printf("%s: bus-master DMA support present", 2887 sc->sc_wdcdev.sc_dev.dv_xname); 2888 pciide_mapreg_dma(sc, pa); 2889 printf("\n"); 2890 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2891 WDC_CAPABILITY_MODE; 2892 if (sc->sc_dma_ok) { 2893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2894 if (rev >= 0x20) 2895 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2896 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2897 sc->sc_wdcdev.irqack = pciide_irqack; 2898 } 2899 2900 sc->sc_wdcdev.PIO_cap = 4; 2901 sc->sc_wdcdev.DMA_cap = 2; 2902 sc->sc_wdcdev.UDMA_cap = 2; 2903 sc->sc_wdcdev.set_modes = acer_setup_channel; 2904 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2905 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2906 2907 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2908 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2909 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2910 2911 /* Enable "microsoft register bits" R/W. */ 2912 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2913 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2914 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2915 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2916 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2917 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2918 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2919 ~ACER_CHANSTATUSREGS_RO); 2920 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2921 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2922 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2923 /* Don't use cr, re-read the real register content instead */ 2924 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2925 PCI_CLASS_REG)); 2926 2927 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2928 cp = &sc->pciide_channels[channel]; 2929 if (pciide_chansetup(sc, channel, interface) == 0) 2930 continue; 2931 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2932 printf("%s: %s channel ignored (disabled)\n", 2933 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2934 continue; 2935 } 2936 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2937 acer_pci_intr); 2938 if (cp->hw_ok == 0) 2939 continue; 2940 if (pciide_chan_candisable(cp)) { 2941 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2942 pci_conf_write(sc->sc_pc, sc->sc_tag, 2943 PCI_CLASS_REG, cr); 2944 } 2945 pciide_map_compat_intr(pa, cp, channel, interface); 2946 acer_setup_channel(&cp->wdc_channel); 2947 } 2948 } 2949 2950 void 2951 acer_setup_channel(chp) 2952 struct channel_softc *chp; 2953 { 2954 struct ata_drive_datas *drvp; 2955 int drive; 2956 u_int32_t acer_fifo_udma; 2957 u_int32_t idedma_ctl; 2958 struct pciide_channel *cp = (struct pciide_channel*)chp; 2959 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2960 2961 idedma_ctl = 0; 2962 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2963 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2964 acer_fifo_udma), DEBUG_PROBE); 2965 /* setup DMA if needed */ 2966 pciide_channel_dma_setup(cp); 2967 2968 for (drive = 0; drive < 2; drive++) { 2969 drvp = &chp->ch_drive[drive]; 2970 /* If no drive, skip */ 2971 if ((drvp->drive_flags & DRIVE) == 0) 2972 continue; 2973 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2974 "channel %d drive %d 0x%x\n", chp->channel, drive, 2975 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2976 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2977 /* clear FIFO/DMA mode */ 2978 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2979 ACER_UDMA_EN(chp->channel, drive) | 2980 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2981 2982 /* add timing values, setup DMA if needed */ 2983 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2984 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2985 acer_fifo_udma |= 2986 ACER_FTH_OPL(chp->channel, drive, 0x1); 2987 goto pio; 2988 } 2989 2990 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2991 if (drvp->drive_flags & DRIVE_UDMA) { 2992 /* use Ultra/DMA */ 2993 drvp->drive_flags &= ~DRIVE_DMA; 2994 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2995 acer_fifo_udma |= 2996 ACER_UDMA_TIM(chp->channel, drive, 2997 acer_udma[drvp->UDMA_mode]); 2998 } else { 2999 /* 3000 * use Multiword DMA 3001 * Timings will be used for both PIO and DMA, 3002 * so adjust DMA mode if needed 3003 */ 3004 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3005 drvp->PIO_mode = drvp->DMA_mode + 2; 3006 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3007 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3008 drvp->PIO_mode - 2 : 0; 3009 if (drvp->DMA_mode == 0) 3010 drvp->PIO_mode = 0; 3011 } 3012 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3013 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3014 ACER_IDETIM(chp->channel, drive), 3015 acer_pio[drvp->PIO_mode]); 3016 } 3017 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3018 acer_fifo_udma), DEBUG_PROBE); 3019 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3020 if (idedma_ctl != 0) { 3021 /* Add software bits in status register */ 3022 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3023 IDEDMA_CTL, idedma_ctl); 3024 } 3025 pciide_print_modes(cp); 3026 } 3027 3028 int 3029 acer_pci_intr(arg) 3030 void *arg; 3031 { 3032 struct pciide_softc *sc = arg; 3033 struct pciide_channel *cp; 3034 struct channel_softc *wdc_cp; 3035 int i, rv, crv; 3036 u_int32_t chids; 3037 3038 rv = 0; 3039 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3040 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3041 cp = &sc->pciide_channels[i]; 3042 wdc_cp = &cp->wdc_channel; 3043 /* If a compat channel skip. */ 3044 if (cp->compat) 3045 continue; 3046 if (chids & ACER_CHIDS_INT(i)) { 3047 crv = wdcintr(wdc_cp); 3048 if (crv == 0) 3049 printf("%s:%d: bogus intr\n", 3050 sc->sc_wdcdev.sc_dev.dv_xname, i); 3051 else 3052 rv = 1; 3053 } 3054 } 3055 return rv; 3056 } 3057 3058 void 3059 hpt_chip_map(sc, pa) 3060 struct pciide_softc *sc; 3061 struct pci_attach_args *pa; 3062 { 3063 struct pciide_channel *cp; 3064 int i, compatchan, revision; 3065 pcireg_t interface; 3066 bus_size_t cmdsize, ctlsize; 3067 3068 if (pciide_chipen(sc, pa) == 0) 3069 return; 3070 revision = PCI_REVISION(pa->pa_class); 3071 printf(": Triones/Highpoint "); 3072 if (revision == HPT370_REV) 3073 printf("HPT370 IDE Controller\n"); 3074 else 3075 printf("HPT366 IDE Controller\n"); 3076 3077 /* 3078 * when the chip is in native mode it identifies itself as a 3079 * 'misc mass storage'. Fake interface in this case. 3080 */ 3081 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3082 interface = PCI_INTERFACE(pa->pa_class); 3083 } else { 3084 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3085 PCIIDE_INTERFACE_PCI(0); 3086 if (revision == HPT370_REV) 3087 interface |= PCIIDE_INTERFACE_PCI(1); 3088 } 3089 3090 printf("%s: bus-master DMA support present", 3091 sc->sc_wdcdev.sc_dev.dv_xname); 3092 pciide_mapreg_dma(sc, pa); 3093 printf("\n"); 3094 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3095 WDC_CAPABILITY_MODE; 3096 if (sc->sc_dma_ok) { 3097 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3098 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3099 sc->sc_wdcdev.irqack = pciide_irqack; 3100 } 3101 sc->sc_wdcdev.PIO_cap = 4; 3102 sc->sc_wdcdev.DMA_cap = 2; 3103 3104 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3105 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3106 if (revision == HPT366_REV) { 3107 sc->sc_wdcdev.UDMA_cap = 4; 3108 /* 3109 * The 366 has 2 PCI IDE functions, one for primary and one 3110 * for secondary. So we need to call pciide_mapregs_compat() 3111 * with the real channel 3112 */ 3113 if (pa->pa_function == 0) { 3114 compatchan = 0; 3115 } else if (pa->pa_function == 1) { 3116 compatchan = 1; 3117 } else { 3118 printf("%s: unexpected PCI function %d\n", 3119 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3120 return; 3121 } 3122 sc->sc_wdcdev.nchannels = 1; 3123 } else { 3124 sc->sc_wdcdev.nchannels = 2; 3125 sc->sc_wdcdev.UDMA_cap = 5; 3126 } 3127 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3128 cp = &sc->pciide_channels[i]; 3129 if (sc->sc_wdcdev.nchannels > 1) { 3130 compatchan = i; 3131 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3132 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3133 printf("%s: %s channel ignored (disabled)\n", 3134 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3135 continue; 3136 } 3137 } 3138 if (pciide_chansetup(sc, i, interface) == 0) 3139 continue; 3140 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3141 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3142 &ctlsize, hpt_pci_intr); 3143 } else { 3144 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3145 &cmdsize, &ctlsize); 3146 } 3147 if (cp->hw_ok == 0) 3148 return; 3149 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3150 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3151 wdcattach(&cp->wdc_channel); 3152 hpt_setup_channel(&cp->wdc_channel); 3153 } 3154 if (revision == HPT370_REV) { 3155 /* 3156 * HPT370_REV has a bit to disable interrupts, make sure 3157 * to clear it 3158 */ 3159 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3160 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3161 ~HPT_CSEL_IRQDIS); 3162 } 3163 return; 3164 } 3165 3166 void 3167 hpt_setup_channel(chp) 3168 struct channel_softc *chp; 3169 { 3170 struct ata_drive_datas *drvp; 3171 int drive; 3172 int cable; 3173 u_int32_t before, after; 3174 u_int32_t idedma_ctl; 3175 struct pciide_channel *cp = (struct pciide_channel*)chp; 3176 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3177 3178 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3179 3180 /* setup DMA if needed */ 3181 pciide_channel_dma_setup(cp); 3182 3183 idedma_ctl = 0; 3184 3185 /* Per drive settings */ 3186 for (drive = 0; drive < 2; drive++) { 3187 drvp = &chp->ch_drive[drive]; 3188 /* If no drive, skip */ 3189 if ((drvp->drive_flags & DRIVE) == 0) 3190 continue; 3191 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3192 HPT_IDETIM(chp->channel, drive)); 3193 3194 /* add timing values, setup DMA if needed */ 3195 if (drvp->drive_flags & DRIVE_UDMA) { 3196 /* use Ultra/DMA */ 3197 drvp->drive_flags &= ~DRIVE_DMA; 3198 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3199 drvp->UDMA_mode > 2) 3200 drvp->UDMA_mode = 2; 3201 after = (sc->sc_wdcdev.nchannels == 2) ? 3202 hpt370_udma[drvp->UDMA_mode] : 3203 hpt366_udma[drvp->UDMA_mode]; 3204 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3205 } else if (drvp->drive_flags & DRIVE_DMA) { 3206 /* 3207 * use Multiword DMA. 3208 * Timings will be used for both PIO and DMA, so adjust 3209 * DMA mode if needed 3210 */ 3211 if (drvp->PIO_mode >= 3 && 3212 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3213 drvp->DMA_mode = drvp->PIO_mode - 2; 3214 } 3215 after = (sc->sc_wdcdev.nchannels == 2) ? 3216 hpt370_dma[drvp->DMA_mode] : 3217 hpt366_dma[drvp->DMA_mode]; 3218 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3219 } else { 3220 /* PIO only */ 3221 after = (sc->sc_wdcdev.nchannels == 2) ? 3222 hpt370_pio[drvp->PIO_mode] : 3223 hpt366_pio[drvp->PIO_mode]; 3224 } 3225 pci_conf_write(sc->sc_pc, sc->sc_tag, 3226 HPT_IDETIM(chp->channel, drive), after); 3227 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3228 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3229 after, before), DEBUG_PROBE); 3230 } 3231 if (idedma_ctl != 0) { 3232 /* Add software bits in status register */ 3233 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3234 IDEDMA_CTL, idedma_ctl); 3235 } 3236 pciide_print_modes(cp); 3237 } 3238 3239 int 3240 hpt_pci_intr(arg) 3241 void *arg; 3242 { 3243 struct pciide_softc *sc = arg; 3244 struct pciide_channel *cp; 3245 struct channel_softc *wdc_cp; 3246 int rv = 0; 3247 int dmastat, i, crv; 3248 3249 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3250 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3251 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3252 if((dmastat & IDEDMA_CTL_INTR) == 0) 3253 continue; 3254 cp = &sc->pciide_channels[i]; 3255 wdc_cp = &cp->wdc_channel; 3256 crv = wdcintr(wdc_cp); 3257 if (crv == 0) { 3258 printf("%s:%d: bogus intr\n", 3259 sc->sc_wdcdev.sc_dev.dv_xname, i); 3260 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3261 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3262 } else 3263 rv = 1; 3264 } 3265 return rv; 3266 } 3267 3268 3269 /* Macros to test product */ 3270 #define PDC_IS_262(sc) \ 3271 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3272 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3273 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3274 #define PDC_IS_265(sc) \ 3275 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3276 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3277 3278 void 3279 pdc202xx_chip_map(sc, pa) 3280 struct pciide_softc *sc; 3281 struct pci_attach_args *pa; 3282 { 3283 struct pciide_channel *cp; 3284 int channel; 3285 pcireg_t interface, st, mode; 3286 bus_size_t cmdsize, ctlsize; 3287 3288 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3289 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3290 DEBUG_PROBE); 3291 if (pciide_chipen(sc, pa) == 0) 3292 return; 3293 3294 /* turn off RAID mode */ 3295 st &= ~PDC2xx_STATE_IDERAID; 3296 3297 /* 3298 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3299 * mode. We have to fake interface 3300 */ 3301 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3302 if (st & PDC2xx_STATE_NATIVE) 3303 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3304 3305 printf("%s: bus-master DMA support present", 3306 sc->sc_wdcdev.sc_dev.dv_xname); 3307 pciide_mapreg_dma(sc, pa); 3308 printf("\n"); 3309 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3310 WDC_CAPABILITY_MODE; 3311 if (sc->sc_dma_ok) { 3312 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3313 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3314 sc->sc_wdcdev.irqack = pciide_irqack; 3315 } 3316 sc->sc_wdcdev.PIO_cap = 4; 3317 sc->sc_wdcdev.DMA_cap = 2; 3318 if (PDC_IS_265(sc)) 3319 sc->sc_wdcdev.UDMA_cap = 5; 3320 else if (PDC_IS_262(sc)) 3321 sc->sc_wdcdev.UDMA_cap = 4; 3322 else 3323 sc->sc_wdcdev.UDMA_cap = 2; 3324 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3325 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3326 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3327 3328 /* setup failsafe defaults */ 3329 mode = 0; 3330 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3331 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3332 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3333 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3334 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3335 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3336 "initial timings 0x%x, now 0x%x\n", channel, 3337 pci_conf_read(sc->sc_pc, sc->sc_tag, 3338 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3339 DEBUG_PROBE); 3340 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3341 mode | PDC2xx_TIM_IORDYp); 3342 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3343 "initial timings 0x%x, now 0x%x\n", channel, 3344 pci_conf_read(sc->sc_pc, sc->sc_tag, 3345 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3346 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3347 mode); 3348 } 3349 3350 mode = PDC2xx_SCR_DMA; 3351 if (PDC_IS_262(sc)) { 3352 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3353 } else { 3354 /* the BIOS set it up this way */ 3355 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3356 } 3357 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3358 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3359 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3360 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3361 DEBUG_PROBE); 3362 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3363 3364 /* controller initial state register is OK even without BIOS */ 3365 /* Set DMA mode to IDE DMA compatibility */ 3366 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3367 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3368 DEBUG_PROBE); 3369 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3370 mode | 0x1); 3371 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3372 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3373 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3374 mode | 0x1); 3375 3376 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3377 cp = &sc->pciide_channels[channel]; 3378 if (pciide_chansetup(sc, channel, interface) == 0) 3379 continue; 3380 if ((st & (PDC_IS_262(sc) ? 3381 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3382 printf("%s: %s channel ignored (disabled)\n", 3383 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3384 continue; 3385 } 3386 if (PDC_IS_265(sc)) 3387 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3388 pdc20265_pci_intr); 3389 else 3390 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3391 pdc202xx_pci_intr); 3392 if (cp->hw_ok == 0) 3393 continue; 3394 if (pciide_chan_candisable(cp)) 3395 st &= ~(PDC_IS_262(sc) ? 3396 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3397 pciide_map_compat_intr(pa, cp, channel, interface); 3398 pdc202xx_setup_channel(&cp->wdc_channel); 3399 } 3400 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3401 DEBUG_PROBE); 3402 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3403 return; 3404 } 3405 3406 void 3407 pdc202xx_setup_channel(chp) 3408 struct channel_softc *chp; 3409 { 3410 struct ata_drive_datas *drvp; 3411 int drive; 3412 pcireg_t mode, st; 3413 u_int32_t idedma_ctl, scr, atapi; 3414 struct pciide_channel *cp = (struct pciide_channel*)chp; 3415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3416 int channel = chp->channel; 3417 3418 /* setup DMA if needed */ 3419 pciide_channel_dma_setup(cp); 3420 3421 idedma_ctl = 0; 3422 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3423 sc->sc_wdcdev.sc_dev.dv_xname, 3424 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3425 DEBUG_PROBE); 3426 3427 /* Per channel settings */ 3428 if (PDC_IS_262(sc)) { 3429 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3430 PDC262_U66); 3431 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3432 /* Trimm UDMA mode */ 3433 if ((st & PDC262_STATE_80P(channel)) != 0 || 3434 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3435 chp->ch_drive[0].UDMA_mode <= 2) || 3436 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3437 chp->ch_drive[1].UDMA_mode <= 2)) { 3438 if (chp->ch_drive[0].UDMA_mode > 2) 3439 chp->ch_drive[0].UDMA_mode = 2; 3440 if (chp->ch_drive[1].UDMA_mode > 2) 3441 chp->ch_drive[1].UDMA_mode = 2; 3442 } 3443 /* Set U66 if needed */ 3444 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3445 chp->ch_drive[0].UDMA_mode > 2) || 3446 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3447 chp->ch_drive[1].UDMA_mode > 2)) 3448 scr |= PDC262_U66_EN(channel); 3449 else 3450 scr &= ~PDC262_U66_EN(channel); 3451 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3452 PDC262_U66, scr); 3453 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3454 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3455 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3456 PDC262_ATAPI(channel))), DEBUG_PROBE); 3457 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3458 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3459 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3460 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3461 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3462 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3463 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3464 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3465 atapi = 0; 3466 else 3467 atapi = PDC262_ATAPI_UDMA; 3468 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3469 PDC262_ATAPI(channel), atapi); 3470 } 3471 } 3472 for (drive = 0; drive < 2; drive++) { 3473 drvp = &chp->ch_drive[drive]; 3474 /* If no drive, skip */ 3475 if ((drvp->drive_flags & DRIVE) == 0) 3476 continue; 3477 mode = 0; 3478 if (drvp->drive_flags & DRIVE_UDMA) { 3479 /* use Ultra/DMA */ 3480 drvp->drive_flags &= ~DRIVE_DMA; 3481 mode = PDC2xx_TIM_SET_MB(mode, 3482 pdc2xx_udma_mb[drvp->UDMA_mode]); 3483 mode = PDC2xx_TIM_SET_MC(mode, 3484 pdc2xx_udma_mc[drvp->UDMA_mode]); 3485 drvp->drive_flags &= ~DRIVE_DMA; 3486 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3487 } else if (drvp->drive_flags & DRIVE_DMA) { 3488 mode = PDC2xx_TIM_SET_MB(mode, 3489 pdc2xx_dma_mb[drvp->DMA_mode]); 3490 mode = PDC2xx_TIM_SET_MC(mode, 3491 pdc2xx_dma_mc[drvp->DMA_mode]); 3492 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3493 } else { 3494 mode = PDC2xx_TIM_SET_MB(mode, 3495 pdc2xx_dma_mb[0]); 3496 mode = PDC2xx_TIM_SET_MC(mode, 3497 pdc2xx_dma_mc[0]); 3498 } 3499 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3500 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3501 if (drvp->drive_flags & DRIVE_ATA) 3502 mode |= PDC2xx_TIM_PRE; 3503 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3504 if (drvp->PIO_mode >= 3) { 3505 mode |= PDC2xx_TIM_IORDY; 3506 if (drive == 0) 3507 mode |= PDC2xx_TIM_IORDYp; 3508 } 3509 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3510 "timings 0x%x\n", 3511 sc->sc_wdcdev.sc_dev.dv_xname, 3512 chp->channel, drive, mode), DEBUG_PROBE); 3513 pci_conf_write(sc->sc_pc, sc->sc_tag, 3514 PDC2xx_TIM(chp->channel, drive), mode); 3515 } 3516 if (idedma_ctl != 0) { 3517 /* Add software bits in status register */ 3518 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3519 IDEDMA_CTL, idedma_ctl); 3520 } 3521 pciide_print_modes(cp); 3522 } 3523 3524 int 3525 pdc202xx_pci_intr(arg) 3526 void *arg; 3527 { 3528 struct pciide_softc *sc = arg; 3529 struct pciide_channel *cp; 3530 struct channel_softc *wdc_cp; 3531 int i, rv, crv; 3532 u_int32_t scr; 3533 3534 rv = 0; 3535 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3536 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3537 cp = &sc->pciide_channels[i]; 3538 wdc_cp = &cp->wdc_channel; 3539 /* If a compat channel skip. */ 3540 if (cp->compat) 3541 continue; 3542 if (scr & PDC2xx_SCR_INT(i)) { 3543 crv = wdcintr(wdc_cp); 3544 if (crv == 0) 3545 printf("%s:%d: bogus intr (reg 0x%x)\n", 3546 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3547 else 3548 rv = 1; 3549 } 3550 } 3551 return rv; 3552 } 3553 3554 int 3555 pdc20265_pci_intr(arg) 3556 void *arg; 3557 { 3558 struct pciide_softc *sc = arg; 3559 struct pciide_channel *cp; 3560 struct channel_softc *wdc_cp; 3561 int i, rv, crv; 3562 u_int32_t dmastat; 3563 3564 rv = 0; 3565 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3566 cp = &sc->pciide_channels[i]; 3567 wdc_cp = &cp->wdc_channel; 3568 /* If a compat channel skip. */ 3569 if (cp->compat) 3570 continue; 3571 /* 3572 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3573 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3574 * So use it instead (requires 2 reg reads instead of 1, 3575 * but we can't do it another way). 3576 */ 3577 dmastat = bus_space_read_1(sc->sc_dma_iot, 3578 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3579 if((dmastat & IDEDMA_CTL_INTR) == 0) 3580 continue; 3581 crv = wdcintr(wdc_cp); 3582 if (crv == 0) 3583 printf("%s:%d: bogus intr\n", 3584 sc->sc_wdcdev.sc_dev.dv_xname, i); 3585 else 3586 rv = 1; 3587 } 3588 return rv; 3589 } 3590 3591 void 3592 opti_chip_map(sc, pa) 3593 struct pciide_softc *sc; 3594 struct pci_attach_args *pa; 3595 { 3596 struct pciide_channel *cp; 3597 bus_size_t cmdsize, ctlsize; 3598 pcireg_t interface; 3599 u_int8_t init_ctrl; 3600 int channel; 3601 3602 if (pciide_chipen(sc, pa) == 0) 3603 return; 3604 printf("%s: bus-master DMA support present", 3605 sc->sc_wdcdev.sc_dev.dv_xname); 3606 pciide_mapreg_dma(sc, pa); 3607 printf("\n"); 3608 3609 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3610 WDC_CAPABILITY_MODE; 3611 sc->sc_wdcdev.PIO_cap = 4; 3612 if (sc->sc_dma_ok) { 3613 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3614 sc->sc_wdcdev.irqack = pciide_irqack; 3615 sc->sc_wdcdev.DMA_cap = 2; 3616 } 3617 sc->sc_wdcdev.set_modes = opti_setup_channel; 3618 3619 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3620 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3621 3622 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3623 OPTI_REG_INIT_CONTROL); 3624 3625 interface = PCI_INTERFACE(pa->pa_class); 3626 3627 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3628 cp = &sc->pciide_channels[channel]; 3629 if (pciide_chansetup(sc, channel, interface) == 0) 3630 continue; 3631 if (channel == 1 && 3632 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3633 printf("%s: %s channel ignored (disabled)\n", 3634 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3635 continue; 3636 } 3637 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3638 pciide_pci_intr); 3639 if (cp->hw_ok == 0) 3640 continue; 3641 pciide_map_compat_intr(pa, cp, channel, interface); 3642 if (cp->hw_ok == 0) 3643 continue; 3644 opti_setup_channel(&cp->wdc_channel); 3645 } 3646 } 3647 3648 void 3649 opti_setup_channel(chp) 3650 struct channel_softc *chp; 3651 { 3652 struct ata_drive_datas *drvp; 3653 struct pciide_channel *cp = (struct pciide_channel*)chp; 3654 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3655 int drive, spd; 3656 int mode[2]; 3657 u_int8_t rv, mr; 3658 3659 /* 3660 * The `Delay' and `Address Setup Time' fields of the 3661 * Miscellaneous Register are always zero initially. 3662 */ 3663 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3664 mr &= ~(OPTI_MISC_DELAY_MASK | 3665 OPTI_MISC_ADDR_SETUP_MASK | 3666 OPTI_MISC_INDEX_MASK); 3667 3668 /* Prime the control register before setting timing values */ 3669 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3670 3671 /* Determine the clockrate of the PCIbus the chip is attached to */ 3672 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3673 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3674 3675 /* setup DMA if needed */ 3676 pciide_channel_dma_setup(cp); 3677 3678 for (drive = 0; drive < 2; drive++) { 3679 drvp = &chp->ch_drive[drive]; 3680 /* If no drive, skip */ 3681 if ((drvp->drive_flags & DRIVE) == 0) { 3682 mode[drive] = -1; 3683 continue; 3684 } 3685 3686 if ((drvp->drive_flags & DRIVE_DMA)) { 3687 /* 3688 * Timings will be used for both PIO and DMA, 3689 * so adjust DMA mode if needed 3690 */ 3691 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3692 drvp->PIO_mode = drvp->DMA_mode + 2; 3693 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3694 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3695 drvp->PIO_mode - 2 : 0; 3696 if (drvp->DMA_mode == 0) 3697 drvp->PIO_mode = 0; 3698 3699 mode[drive] = drvp->DMA_mode + 5; 3700 } else 3701 mode[drive] = drvp->PIO_mode; 3702 3703 if (drive && mode[0] >= 0 && 3704 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3705 /* 3706 * Can't have two drives using different values 3707 * for `Address Setup Time'. 3708 * Slow down the faster drive to compensate. 3709 */ 3710 int d = (opti_tim_as[spd][mode[0]] > 3711 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3712 3713 mode[d] = mode[1-d]; 3714 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3715 chp->ch_drive[d].DMA_mode = 0; 3716 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3717 } 3718 } 3719 3720 for (drive = 0; drive < 2; drive++) { 3721 int m; 3722 if ((m = mode[drive]) < 0) 3723 continue; 3724 3725 /* Set the Address Setup Time and select appropriate index */ 3726 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3727 rv |= OPTI_MISC_INDEX(drive); 3728 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3729 3730 /* Set the pulse width and recovery timing parameters */ 3731 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3732 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3733 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3734 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3735 3736 /* Set the Enhanced Mode register appropriately */ 3737 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3738 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3739 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3740 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3741 } 3742 3743 /* Finally, enable the timings */ 3744 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3745 3746 pciide_print_modes(cp); 3747 } 3748 3749 #define ACARD_IS_850(sc) \ 3750 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3751 3752 void 3753 acard_chip_map(sc, pa) 3754 struct pciide_softc *sc; 3755 struct pci_attach_args *pa; 3756 { 3757 struct pciide_channel *cp; 3758 int i, compatchan; 3759 pcireg_t interface; 3760 bus_size_t cmdsize, ctlsize; 3761 3762 if (pciide_chipen(sc, pa) == 0) 3763 return; 3764 3765 /* 3766 * when the chip is in native mode it identifies itself as a 3767 * 'misc mass storage'. Fake interface in this case. 3768 */ 3769 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3770 interface = PCI_INTERFACE(pa->pa_class); 3771 } else { 3772 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3773 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3774 } 3775 3776 printf("%s: bus-master DMA support present", 3777 sc->sc_wdcdev.sc_dev.dv_xname); 3778 pciide_mapreg_dma(sc, pa); 3779 printf("\n"); 3780 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3781 WDC_CAPABILITY_MODE; 3782 3783 if (sc->sc_dma_ok) { 3784 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3785 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3786 sc->sc_wdcdev.irqack = pciide_irqack; 3787 } 3788 sc->sc_wdcdev.PIO_cap = 4; 3789 sc->sc_wdcdev.DMA_cap = 2; 3790 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3791 3792 sc->sc_wdcdev.set_modes = acard_setup_channel; 3793 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3794 sc->sc_wdcdev.nchannels = 2; 3795 3796 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3797 cp = &sc->pciide_channels[i]; 3798 if (pciide_chansetup(sc, i, interface) == 0) 3799 continue; 3800 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3801 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3802 &ctlsize, pciide_pci_intr); 3803 } else { 3804 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3805 &cmdsize, &ctlsize); 3806 } 3807 if (cp->hw_ok == 0) 3808 return; 3809 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3810 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3811 wdcattach(&cp->wdc_channel); 3812 acard_setup_channel(&cp->wdc_channel); 3813 } 3814 if (!ACARD_IS_850(sc)) { 3815 u_int32_t reg; 3816 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3817 reg &= ~ATP860_CTRL_INT; 3818 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3819 } 3820 } 3821 3822 void 3823 acard_setup_channel(chp) 3824 struct channel_softc *chp; 3825 { 3826 struct ata_drive_datas *drvp; 3827 struct pciide_channel *cp = (struct pciide_channel*)chp; 3828 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3829 int channel = chp->channel; 3830 int drive; 3831 u_int32_t idetime, udma_mode; 3832 u_int32_t idedma_ctl; 3833 3834 /* setup DMA if needed */ 3835 pciide_channel_dma_setup(cp); 3836 3837 if (ACARD_IS_850(sc)) { 3838 idetime = 0; 3839 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3840 udma_mode &= ~ATP850_UDMA_MASK(channel); 3841 } else { 3842 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3843 idetime &= ~ATP860_SETTIME_MASK(channel); 3844 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3845 udma_mode &= ~ATP860_UDMA_MASK(channel); 3846 } 3847 3848 idedma_ctl = 0; 3849 3850 /* Per drive settings */ 3851 for (drive = 0; drive < 2; drive++) { 3852 drvp = &chp->ch_drive[drive]; 3853 /* If no drive, skip */ 3854 if ((drvp->drive_flags & DRIVE) == 0) 3855 continue; 3856 /* add timing values, setup DMA if needed */ 3857 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3858 (drvp->drive_flags & DRIVE_UDMA)) { 3859 /* use Ultra/DMA */ 3860 if (ACARD_IS_850(sc)) { 3861 idetime |= ATP850_SETTIME(drive, 3862 acard_act_udma[drvp->UDMA_mode], 3863 acard_rec_udma[drvp->UDMA_mode]); 3864 udma_mode |= ATP850_UDMA_MODE(channel, drive, 3865 acard_udma_conf[drvp->UDMA_mode]); 3866 } else { 3867 idetime |= ATP860_SETTIME(channel, drive, 3868 acard_act_udma[drvp->UDMA_mode], 3869 acard_rec_udma[drvp->UDMA_mode]); 3870 udma_mode |= ATP860_UDMA_MODE(channel, drive, 3871 acard_udma_conf[drvp->UDMA_mode]); 3872 } 3873 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3874 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 3875 (drvp->drive_flags & DRIVE_DMA)) { 3876 /* use Multiword DMA */ 3877 drvp->drive_flags &= ~DRIVE_UDMA; 3878 if (ACARD_IS_850(sc)) { 3879 idetime |= ATP850_SETTIME(drive, 3880 acard_act_dma[drvp->DMA_mode], 3881 acard_rec_dma[drvp->DMA_mode]); 3882 } else { 3883 idetime |= ATP860_SETTIME(channel, drive, 3884 acard_act_dma[drvp->DMA_mode], 3885 acard_rec_dma[drvp->DMA_mode]); 3886 } 3887 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3888 } else { 3889 /* PIO only */ 3890 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 3891 if (ACARD_IS_850(sc)) { 3892 idetime |= ATP850_SETTIME(drive, 3893 acard_act_pio[drvp->PIO_mode], 3894 acard_rec_pio[drvp->PIO_mode]); 3895 } else { 3896 idetime |= ATP860_SETTIME(channel, drive, 3897 acard_act_pio[drvp->PIO_mode], 3898 acard_rec_pio[drvp->PIO_mode]); 3899 } 3900 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 3901 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3902 | ATP8x0_CTRL_EN(channel)); 3903 } 3904 } 3905 3906 if (idedma_ctl != 0) { 3907 /* Add software bits in status register */ 3908 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3909 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 3910 } 3911 pciide_print_modes(cp); 3912 3913 if (ACARD_IS_850(sc)) { 3914 pci_conf_write(sc->sc_pc, sc->sc_tag, 3915 ATP850_IDETIME(channel), idetime); 3916 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 3917 } else { 3918 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 3919 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 3920 } 3921 } 3922 3923 int 3924 acard_pci_intr(arg) 3925 void *arg; 3926 { 3927 struct pciide_softc *sc = arg; 3928 struct pciide_channel *cp; 3929 struct channel_softc *wdc_cp; 3930 int rv = 0; 3931 int dmastat, i, crv; 3932 3933 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3934 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3935 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3936 if ((dmastat & IDEDMA_CTL_INTR) == 0) 3937 continue; 3938 cp = &sc->pciide_channels[i]; 3939 wdc_cp = &cp->wdc_channel; 3940 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 3941 (void)wdcintr(wdc_cp); 3942 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3943 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3944 continue; 3945 } 3946 crv = wdcintr(wdc_cp); 3947 if (crv == 0) 3948 printf("%s:%d: bogus intr\n", 3949 sc->sc_wdcdev.sc_dev.dv_xname, i); 3950 else if (crv == 1) 3951 rv = 1; 3952 else if (rv == 0) 3953 rv = crv; 3954 } 3955 return rv; 3956 } 3957
Indexes created Tue Sep 23 02:09:52 GMT 2025