pciide.c revision 1.120
1 /* $NetBSD: pciide.c,v 1.120 2001/06/13 09:55:25 scw Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/pciide_acard_reg.h> 119 #include <dev/pci/cy82c693var.h> 120 121 #include "opt_pciide.h" 122 123 /* inlines for reading/writing 8-bit PCI registers */ 124 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 125 int)); 126 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 127 int, u_int8_t)); 128 129 static __inline u_int8_t 130 pciide_pci_read(pc, pa, reg) 131 pci_chipset_tag_t pc; 132 pcitag_t pa; 133 int reg; 134 { 135 136 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 137 ((reg & 0x03) * 8) & 0xff); 138 } 139 140 static __inline void 141 pciide_pci_write(pc, pa, reg, val) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 u_int8_t val; 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 156 157 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 void piix_setup_channel __P((struct channel_softc*)); 159 void piix3_4_setup_channel __P((struct channel_softc*)); 160 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 161 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 162 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 164 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void amd7x6_setup_channel __P((struct channel_softc*)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 void cmd646_9_irqack __P((struct channel_softc *)); 177 178 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cy693_setup_channel __P((struct channel_softc*)); 180 181 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void sis_setup_channel __P((struct channel_softc*)); 183 184 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void acer_setup_channel __P((struct channel_softc*)); 186 int acer_pci_intr __P((void *)); 187 188 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void pdc202xx_setup_channel __P((struct channel_softc*)); 190 int pdc202xx_pci_intr __P((void *)); 191 int pdc20265_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void acard_setup_channel __P((struct channel_softc*)); 202 int acard_pci_intr __P((void *)); 203 204 #ifdef PCIIDE_WINBOND_ENABLE 205 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 #endif 207 208 void pciide_channel_dma_setup __P((struct pciide_channel *)); 209 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 210 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 211 void pciide_dma_start __P((void*, int, int)); 212 int pciide_dma_finish __P((void*, int, int, int)); 213 void pciide_irqack __P((struct channel_softc *)); 214 void pciide_print_modes __P((struct pciide_channel *)); 215 216 struct pciide_product_desc { 217 u_int32_t ide_product; 218 int ide_flags; 219 const char *ide_name; 220 /* map and setup chip, probe drives */ 221 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 222 }; 223 224 /* Flags for ide_flags */ 225 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 226 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 227 228 /* Default product description for devices not known from this controller */ 229 const struct pciide_product_desc default_product_desc = { 230 0, 231 0, 232 "Generic PCI IDE controller", 233 default_chip_map, 234 }; 235 236 const struct pciide_product_desc pciide_intel_products[] = { 237 { PCI_PRODUCT_INTEL_82092AA, 238 0, 239 "Intel 82092AA IDE controller", 240 default_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82371FB_IDE, 243 0, 244 "Intel 82371FB IDE controller (PIIX)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82371SB_IDE, 248 0, 249 "Intel 82371SB IDE Interface (PIIX3)", 250 piix_chip_map, 251 }, 252 { PCI_PRODUCT_INTEL_82371AB_IDE, 253 0, 254 "Intel 82371AB IDE controller (PIIX4)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82440MX_IDE, 258 0, 259 "Intel 82440MX IDE controller", 260 piix_chip_map 261 }, 262 { PCI_PRODUCT_INTEL_82801AA_IDE, 263 0, 264 "Intel 82801AA IDE Controller (ICH)", 265 piix_chip_map, 266 }, 267 { PCI_PRODUCT_INTEL_82801AB_IDE, 268 0, 269 "Intel 82801AB IDE Controller (ICH0)", 270 piix_chip_map, 271 }, 272 { PCI_PRODUCT_INTEL_82801BA_IDE, 273 0, 274 "Intel 82801BA IDE Controller (ICH2)", 275 piix_chip_map, 276 }, 277 { PCI_PRODUCT_INTEL_82801BAM_IDE, 278 0, 279 "Intel 82801BAM IDE Controller (ICH2)", 280 piix_chip_map, 281 }, 282 { 0, 283 0, 284 NULL, 285 NULL 286 } 287 }; 288 289 const struct pciide_product_desc pciide_amd_products[] = { 290 { PCI_PRODUCT_AMD_PBC756_IDE, 291 0, 292 "Advanced Micro Devices AMD756 IDE Controller", 293 amd7x6_chip_map 294 }, 295 { PCI_PRODUCT_AMD_PBC766_IDE, 296 0, 297 "Advanced Micro Devices AMD766 IDE Controller", 298 amd7x6_chip_map 299 }, 300 { 0, 301 0, 302 NULL, 303 NULL 304 } 305 }; 306 307 const struct pciide_product_desc pciide_cmd_products[] = { 308 { PCI_PRODUCT_CMDTECH_640, 309 0, 310 "CMD Technology PCI0640", 311 cmd_chip_map 312 }, 313 { PCI_PRODUCT_CMDTECH_643, 314 0, 315 "CMD Technology PCI0643", 316 cmd0643_9_chip_map, 317 }, 318 { PCI_PRODUCT_CMDTECH_646, 319 0, 320 "CMD Technology PCI0646", 321 cmd0643_9_chip_map, 322 }, 323 { PCI_PRODUCT_CMDTECH_648, 324 IDE_PCI_CLASS_OVERRIDE, 325 "CMD Technology PCI0648", 326 cmd0643_9_chip_map, 327 }, 328 { PCI_PRODUCT_CMDTECH_649, 329 IDE_PCI_CLASS_OVERRIDE, 330 "CMD Technology PCI0649", 331 cmd0643_9_chip_map, 332 }, 333 { 0, 334 0, 335 NULL, 336 NULL 337 } 338 }; 339 340 const struct pciide_product_desc pciide_via_products[] = { 341 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 342 0, 343 NULL, 344 apollo_chip_map, 345 }, 346 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 347 0, 348 NULL, 349 apollo_chip_map, 350 }, 351 { 0, 352 0, 353 NULL, 354 NULL 355 } 356 }; 357 358 const struct pciide_product_desc pciide_cypress_products[] = { 359 { PCI_PRODUCT_CONTAQ_82C693, 360 IDE_16BIT_IOSPACE, 361 "Cypress 82C693 IDE Controller", 362 cy693_chip_map, 363 }, 364 { 0, 365 0, 366 NULL, 367 NULL 368 } 369 }; 370 371 const struct pciide_product_desc pciide_sis_products[] = { 372 { PCI_PRODUCT_SIS_5597_IDE, 373 0, 374 "Silicon Integrated System 5597/5598 IDE controller", 375 sis_chip_map, 376 }, 377 { 0, 378 0, 379 NULL, 380 NULL 381 } 382 }; 383 384 const struct pciide_product_desc pciide_acer_products[] = { 385 { PCI_PRODUCT_ALI_M5229, 386 0, 387 "Acer Labs M5229 UDMA IDE Controller", 388 acer_chip_map, 389 }, 390 { 0, 391 0, 392 NULL, 393 NULL 394 } 395 }; 396 397 const struct pciide_product_desc pciide_promise_products[] = { 398 { PCI_PRODUCT_PROMISE_ULTRA33, 399 IDE_PCI_CLASS_OVERRIDE, 400 "Promise Ultra33/ATA Bus Master IDE Accelerator", 401 pdc202xx_chip_map, 402 }, 403 { PCI_PRODUCT_PROMISE_ULTRA66, 404 IDE_PCI_CLASS_OVERRIDE, 405 "Promise Ultra66/ATA Bus Master IDE Accelerator", 406 pdc202xx_chip_map, 407 }, 408 { PCI_PRODUCT_PROMISE_ULTRA100, 409 IDE_PCI_CLASS_OVERRIDE, 410 "Promise Ultra100/ATA Bus Master IDE Accelerator", 411 pdc202xx_chip_map, 412 }, 413 { PCI_PRODUCT_PROMISE_ULTRA100X, 414 IDE_PCI_CLASS_OVERRIDE, 415 "Promise Ultra100/ATA Bus Master IDE Accelerator", 416 pdc202xx_chip_map, 417 }, 418 { 0, 419 0, 420 NULL, 421 NULL 422 } 423 }; 424 425 const struct pciide_product_desc pciide_opti_products[] = { 426 { PCI_PRODUCT_OPTI_82C621, 427 0, 428 "OPTi 82c621 PCI IDE controller", 429 opti_chip_map, 430 }, 431 { PCI_PRODUCT_OPTI_82C568, 432 0, 433 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 434 opti_chip_map, 435 }, 436 { PCI_PRODUCT_OPTI_82D568, 437 0, 438 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 439 opti_chip_map, 440 }, 441 { 0, 442 0, 443 NULL, 444 NULL 445 } 446 }; 447 448 const struct pciide_product_desc pciide_triones_products[] = { 449 { PCI_PRODUCT_TRIONES_HPT366, 450 IDE_PCI_CLASS_OVERRIDE, 451 NULL, 452 hpt_chip_map, 453 }, 454 { 0, 455 0, 456 NULL, 457 NULL 458 } 459 }; 460 461 const struct pciide_product_desc pciide_acard_products[] = { 462 { PCI_PRODUCT_ACARD_ATP850U, 463 IDE_PCI_CLASS_OVERRIDE, 464 "Acard ATP850U Ultra33 IDE Controller", 465 acard_chip_map, 466 }, 467 { PCI_PRODUCT_ACARD_ATP860, 468 IDE_PCI_CLASS_OVERRIDE, 469 "Acard ATP860 Ultra66 IDE Controller", 470 acard_chip_map, 471 }, 472 { PCI_PRODUCT_ACARD_ATP860A, 473 IDE_PCI_CLASS_OVERRIDE, 474 "Acard ATP860-A Ultra66 IDE Controller", 475 acard_chip_map, 476 }, 477 { 0, 478 0, 479 NULL, 480 NULL 481 } 482 }; 483 484 #ifdef PCIIDE_SERVERWORKS_ENABLE 485 const struct pciide_product_desc pciide_serverworks_products[] = { 486 { PCI_PRODUCT_SERVERWORKS_IDE, 487 0, 488 "ServerWorks ROSB4 IDE Controller", 489 piix_chip_map, 490 }, 491 { 0, 492 0, 493 NULL, 494 } 495 }; 496 #endif 497 498 #ifdef PCIIDE_WINBOND_ENABLE 499 const struct pciide_product_desc pciide_winbond_products[] = { 500 { PCI_PRODUCT_WINBOND_W83C553F_1, 501 0, 502 "Winbond W83C553F IDE controller", 503 winbond_chip_map, 504 }, 505 { 0, 506 0, 507 NULL, 508 } 509 }; 510 #endif 511 512 struct pciide_vendor_desc { 513 u_int32_t ide_vendor; 514 const struct pciide_product_desc *ide_products; 515 }; 516 517 const struct pciide_vendor_desc pciide_vendors[] = { 518 { PCI_VENDOR_INTEL, pciide_intel_products }, 519 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 520 { PCI_VENDOR_VIATECH, pciide_via_products }, 521 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 522 { PCI_VENDOR_SIS, pciide_sis_products }, 523 { PCI_VENDOR_ALI, pciide_acer_products }, 524 { PCI_VENDOR_PROMISE, pciide_promise_products }, 525 { PCI_VENDOR_AMD, pciide_amd_products }, 526 { PCI_VENDOR_OPTI, pciide_opti_products }, 527 { PCI_VENDOR_TRIONES, pciide_triones_products }, 528 #ifdef PCIIDE_ACARD_ENABLE 529 { PCI_VENDOR_ACARD, pciide_acard_products }, 530 #endif 531 #ifdef PCIIDE_SERVERWORKS_ENABLE 532 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 533 #endif 534 #ifdef PCIIDE_WINBOND_ENABLE 535 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 536 #endif 537 { 0, NULL } 538 }; 539 540 /* options passed via the 'flags' config keyword */ 541 #define PCIIDE_OPTIONS_DMA 0x01 542 543 int pciide_match __P((struct device *, struct cfdata *, void *)); 544 void pciide_attach __P((struct device *, struct device *, void *)); 545 546 struct cfattach pciide_ca = { 547 sizeof(struct pciide_softc), pciide_match, pciide_attach 548 }; 549 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 550 int pciide_mapregs_compat __P(( struct pci_attach_args *, 551 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 552 int pciide_mapregs_native __P((struct pci_attach_args *, 553 struct pciide_channel *, bus_size_t *, bus_size_t *, 554 int (*pci_intr) __P((void *)))); 555 void pciide_mapreg_dma __P((struct pciide_softc *, 556 struct pci_attach_args *)); 557 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 558 void pciide_mapchan __P((struct pci_attach_args *, 559 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 560 int (*pci_intr) __P((void *)))); 561 int pciide_chan_candisable __P((struct pciide_channel *)); 562 void pciide_map_compat_intr __P(( struct pci_attach_args *, 563 struct pciide_channel *, int, int)); 564 int pciide_print __P((void *, const char *pnp)); 565 int pciide_compat_intr __P((void *)); 566 int pciide_pci_intr __P((void *)); 567 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 568 569 const struct pciide_product_desc * 570 pciide_lookup_product(id) 571 u_int32_t id; 572 { 573 const struct pciide_product_desc *pp; 574 const struct pciide_vendor_desc *vp; 575 576 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 577 if (PCI_VENDOR(id) == vp->ide_vendor) 578 break; 579 580 if ((pp = vp->ide_products) == NULL) 581 return NULL; 582 583 for (; pp->chip_map != NULL; pp++) 584 if (PCI_PRODUCT(id) == pp->ide_product) 585 break; 586 587 if (pp->chip_map == NULL) 588 return NULL; 589 return pp; 590 } 591 592 int 593 pciide_match(parent, match, aux) 594 struct device *parent; 595 struct cfdata *match; 596 void *aux; 597 { 598 struct pci_attach_args *pa = aux; 599 const struct pciide_product_desc *pp; 600 601 /* 602 * Check the ID register to see that it's a PCI IDE controller. 603 * If it is, we assume that we can deal with it; it _should_ 604 * work in a standardized way... 605 */ 606 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 607 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 608 return (1); 609 } 610 611 /* 612 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 613 * controllers. Let see if we can deal with it anyway. 614 */ 615 pp = pciide_lookup_product(pa->pa_id); 616 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 617 return (1); 618 } 619 620 return (0); 621 } 622 623 void 624 pciide_attach(parent, self, aux) 625 struct device *parent, *self; 626 void *aux; 627 { 628 struct pci_attach_args *pa = aux; 629 pci_chipset_tag_t pc = pa->pa_pc; 630 pcitag_t tag = pa->pa_tag; 631 struct pciide_softc *sc = (struct pciide_softc *)self; 632 pcireg_t csr; 633 char devinfo[256]; 634 const char *displaydev; 635 636 sc->sc_pp = pciide_lookup_product(pa->pa_id); 637 if (sc->sc_pp == NULL) { 638 sc->sc_pp = &default_product_desc; 639 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 640 displaydev = devinfo; 641 } else 642 displaydev = sc->sc_pp->ide_name; 643 644 /* if displaydev == NULL, printf is done in chip-specific map */ 645 if (displaydev) 646 printf(": %s (rev. 0x%02x)\n", displaydev, 647 PCI_REVISION(pa->pa_class)); 648 649 sc->sc_pc = pa->pa_pc; 650 sc->sc_tag = pa->pa_tag; 651 #ifdef WDCDEBUG 652 if (wdcdebug_pciide_mask & DEBUG_PROBE) 653 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 654 #endif 655 sc->sc_pp->chip_map(sc, pa); 656 657 if (sc->sc_dma_ok) { 658 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 659 csr |= PCI_COMMAND_MASTER_ENABLE; 660 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 661 } 662 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 663 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 664 } 665 666 /* tell wether the chip is enabled or not */ 667 int 668 pciide_chipen(sc, pa) 669 struct pciide_softc *sc; 670 struct pci_attach_args *pa; 671 { 672 pcireg_t csr; 673 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 674 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 675 PCI_COMMAND_STATUS_REG); 676 printf("%s: device disabled (at %s)\n", 677 sc->sc_wdcdev.sc_dev.dv_xname, 678 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 679 "device" : "bridge"); 680 return 0; 681 } 682 return 1; 683 } 684 685 int 686 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 687 struct pci_attach_args *pa; 688 struct pciide_channel *cp; 689 int compatchan; 690 bus_size_t *cmdsizep, *ctlsizep; 691 { 692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 693 struct channel_softc *wdc_cp = &cp->wdc_channel; 694 695 cp->compat = 1; 696 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 697 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 698 699 wdc_cp->cmd_iot = pa->pa_iot; 700 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 701 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 702 printf("%s: couldn't map %s channel cmd regs\n", 703 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 704 return (0); 705 } 706 707 wdc_cp->ctl_iot = pa->pa_iot; 708 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 709 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 710 printf("%s: couldn't map %s channel ctl regs\n", 711 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 712 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 713 PCIIDE_COMPAT_CMD_SIZE); 714 return (0); 715 } 716 717 return (1); 718 } 719 720 int 721 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 722 struct pci_attach_args * pa; 723 struct pciide_channel *cp; 724 bus_size_t *cmdsizep, *ctlsizep; 725 int (*pci_intr) __P((void *)); 726 { 727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 728 struct channel_softc *wdc_cp = &cp->wdc_channel; 729 const char *intrstr; 730 pci_intr_handle_t intrhandle; 731 732 cp->compat = 0; 733 734 if (sc->sc_pci_ih == NULL) { 735 if (pci_intr_map(pa, &intrhandle) != 0) { 736 printf("%s: couldn't map native-PCI interrupt\n", 737 sc->sc_wdcdev.sc_dev.dv_xname); 738 return 0; 739 } 740 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 741 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 742 intrhandle, IPL_BIO, pci_intr, sc); 743 if (sc->sc_pci_ih != NULL) { 744 printf("%s: using %s for native-PCI interrupt\n", 745 sc->sc_wdcdev.sc_dev.dv_xname, 746 intrstr ? intrstr : "unknown interrupt"); 747 } else { 748 printf("%s: couldn't establish native-PCI interrupt", 749 sc->sc_wdcdev.sc_dev.dv_xname); 750 if (intrstr != NULL) 751 printf(" at %s", intrstr); 752 printf("\n"); 753 return 0; 754 } 755 } 756 cp->ih = sc->sc_pci_ih; 757 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 758 PCI_MAPREG_TYPE_IO, 0, 759 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 760 printf("%s: couldn't map %s channel cmd regs\n", 761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 762 return 0; 763 } 764 765 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 766 PCI_MAPREG_TYPE_IO, 0, 767 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 768 printf("%s: couldn't map %s channel ctl regs\n", 769 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 770 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 771 return 0; 772 } 773 /* 774 * In native mode, 4 bytes of I/O space are mapped for the control 775 * register, the control register is at offset 2. Pass the generic 776 * code a handle for only one byte at the rigth offset. 777 */ 778 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 779 &wdc_cp->ctl_ioh) != 0) { 780 printf("%s: unable to subregion %s channel ctl regs\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 782 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 783 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 784 return 0; 785 } 786 return (1); 787 } 788 789 void 790 pciide_mapreg_dma(sc, pa) 791 struct pciide_softc *sc; 792 struct pci_attach_args *pa; 793 { 794 pcireg_t maptype; 795 bus_addr_t addr; 796 797 /* 798 * Map DMA registers 799 * 800 * Note that sc_dma_ok is the right variable to test to see if 801 * DMA can be done. If the interface doesn't support DMA, 802 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 803 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 804 * non-zero if the interface supports DMA and the registers 805 * could be mapped. 806 * 807 * XXX Note that despite the fact that the Bus Master IDE specs 808 * XXX say that "The bus master IDE function uses 16 bytes of IO 809 * XXX space," some controllers (at least the United 810 * XXX Microelectronics UM8886BF) place it in memory space. 811 */ 812 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 813 PCIIDE_REG_BUS_MASTER_DMA); 814 815 switch (maptype) { 816 case PCI_MAPREG_TYPE_IO: 817 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 818 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 819 &addr, NULL, NULL) == 0); 820 if (sc->sc_dma_ok == 0) { 821 printf(", but unused (couldn't query registers)"); 822 break; 823 } 824 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 825 && addr >= 0x10000) { 826 sc->sc_dma_ok = 0; 827 printf(", but unused (registers at unsafe address %#lx)", (unsigned long)addr); 828 break; 829 } 830 /* FALLTHROUGH */ 831 832 case PCI_MAPREG_MEM_TYPE_32BIT: 833 sc->sc_dma_ok = (pci_mapreg_map(pa, 834 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 835 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 836 sc->sc_dmat = pa->pa_dmat; 837 if (sc->sc_dma_ok == 0) { 838 printf(", but unused (couldn't map registers)"); 839 } else { 840 sc->sc_wdcdev.dma_arg = sc; 841 sc->sc_wdcdev.dma_init = pciide_dma_init; 842 sc->sc_wdcdev.dma_start = pciide_dma_start; 843 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 844 } 845 break; 846 847 default: 848 sc->sc_dma_ok = 0; 849 printf(", but unsupported register maptype (0x%x)", maptype); 850 } 851 } 852 853 int 854 pciide_compat_intr(arg) 855 void *arg; 856 { 857 struct pciide_channel *cp = arg; 858 859 #ifdef DIAGNOSTIC 860 /* should only be called for a compat channel */ 861 if (cp->compat == 0) 862 panic("pciide compat intr called for non-compat chan %p\n", cp); 863 #endif 864 return (wdcintr(&cp->wdc_channel)); 865 } 866 867 int 868 pciide_pci_intr(arg) 869 void *arg; 870 { 871 struct pciide_softc *sc = arg; 872 struct pciide_channel *cp; 873 struct channel_softc *wdc_cp; 874 int i, rv, crv; 875 876 rv = 0; 877 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 878 cp = &sc->pciide_channels[i]; 879 wdc_cp = &cp->wdc_channel; 880 881 /* If a compat channel skip. */ 882 if (cp->compat) 883 continue; 884 /* if this channel not waiting for intr, skip */ 885 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 886 continue; 887 888 crv = wdcintr(wdc_cp); 889 if (crv == 0) 890 ; /* leave rv alone */ 891 else if (crv == 1) 892 rv = 1; /* claim the intr */ 893 else if (rv == 0) /* crv should be -1 in this case */ 894 rv = crv; /* if we've done no better, take it */ 895 } 896 return (rv); 897 } 898 899 void 900 pciide_channel_dma_setup(cp) 901 struct pciide_channel *cp; 902 { 903 int drive; 904 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 905 struct ata_drive_datas *drvp; 906 907 for (drive = 0; drive < 2; drive++) { 908 drvp = &cp->wdc_channel.ch_drive[drive]; 909 /* If no drive, skip */ 910 if ((drvp->drive_flags & DRIVE) == 0) 911 continue; 912 /* setup DMA if needed */ 913 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 914 (drvp->drive_flags & DRIVE_UDMA) == 0) || 915 sc->sc_dma_ok == 0) { 916 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 917 continue; 918 } 919 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 920 != 0) { 921 /* Abort DMA setup */ 922 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 923 continue; 924 } 925 } 926 } 927 928 int 929 pciide_dma_table_setup(sc, channel, drive) 930 struct pciide_softc *sc; 931 int channel, drive; 932 { 933 bus_dma_segment_t seg; 934 int error, rseg; 935 const bus_size_t dma_table_size = 936 sizeof(struct idedma_table) * NIDEDMA_TABLES; 937 struct pciide_dma_maps *dma_maps = 938 &sc->pciide_channels[channel].dma_maps[drive]; 939 940 /* If table was already allocated, just return */ 941 if (dma_maps->dma_table) 942 return 0; 943 944 /* Allocate memory for the DMA tables and map it */ 945 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 946 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 947 BUS_DMA_NOWAIT)) != 0) { 948 printf("%s:%d: unable to allocate table DMA for " 949 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 950 channel, drive, error); 951 return error; 952 } 953 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 954 dma_table_size, 955 (caddr_t *)&dma_maps->dma_table, 956 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 957 printf("%s:%d: unable to map table DMA for" 958 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 959 channel, drive, error); 960 return error; 961 } 962 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 963 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 964 (unsigned long)seg.ds_addr), DEBUG_PROBE); 965 966 /* Create and load table DMA map for this disk */ 967 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 968 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 969 &dma_maps->dmamap_table)) != 0) { 970 printf("%s:%d: unable to create table DMA map for " 971 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 972 channel, drive, error); 973 return error; 974 } 975 if ((error = bus_dmamap_load(sc->sc_dmat, 976 dma_maps->dmamap_table, 977 dma_maps->dma_table, 978 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 979 printf("%s:%d: unable to load table DMA map for " 980 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 981 channel, drive, error); 982 return error; 983 } 984 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 985 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 986 DEBUG_PROBE); 987 /* Create a xfer DMA map for this drive */ 988 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 989 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 990 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 991 &dma_maps->dmamap_xfer)) != 0) { 992 printf("%s:%d: unable to create xfer DMA map for " 993 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 994 channel, drive, error); 995 return error; 996 } 997 return 0; 998 } 999 1000 int 1001 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1002 void *v; 1003 int channel, drive; 1004 void *databuf; 1005 size_t datalen; 1006 int flags; 1007 { 1008 struct pciide_softc *sc = v; 1009 int error, seg; 1010 struct pciide_dma_maps *dma_maps = 1011 &sc->pciide_channels[channel].dma_maps[drive]; 1012 1013 error = bus_dmamap_load(sc->sc_dmat, 1014 dma_maps->dmamap_xfer, 1015 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING); 1016 if (error) { 1017 printf("%s:%d: unable to load xfer DMA map for" 1018 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1019 channel, drive, error); 1020 return error; 1021 } 1022 1023 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1024 dma_maps->dmamap_xfer->dm_mapsize, 1025 (flags & WDC_DMA_READ) ? 1026 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1027 1028 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1029 #ifdef DIAGNOSTIC 1030 /* A segment must not cross a 64k boundary */ 1031 { 1032 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1033 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1034 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1035 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1036 printf("pciide_dma: segment %d physical addr 0x%lx" 1037 " len 0x%lx not properly aligned\n", 1038 seg, phys, len); 1039 panic("pciide_dma: buf align"); 1040 } 1041 } 1042 #endif 1043 dma_maps->dma_table[seg].base_addr = 1044 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1045 dma_maps->dma_table[seg].byte_count = 1046 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1047 IDEDMA_BYTE_COUNT_MASK); 1048 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1049 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1050 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1051 1052 } 1053 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1054 htole32(IDEDMA_BYTE_COUNT_EOT); 1055 1056 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1057 dma_maps->dmamap_table->dm_mapsize, 1058 BUS_DMASYNC_PREWRITE); 1059 1060 /* Maps are ready. Start DMA function */ 1061 #ifdef DIAGNOSTIC 1062 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1063 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1064 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1065 panic("pciide_dma_init: table align"); 1066 } 1067 #endif 1068 1069 /* Clear status bits */ 1070 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1071 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1072 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1073 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1074 /* Write table addr */ 1075 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1076 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1077 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1078 /* set read/write */ 1079 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1080 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1081 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1082 /* remember flags */ 1083 dma_maps->dma_flags = flags; 1084 return 0; 1085 } 1086 1087 void 1088 pciide_dma_start(v, channel, drive) 1089 void *v; 1090 int channel, drive; 1091 { 1092 struct pciide_softc *sc = v; 1093 1094 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1095 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1096 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1097 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1098 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1099 } 1100 1101 int 1102 pciide_dma_finish(v, channel, drive, force) 1103 void *v; 1104 int channel, drive; 1105 int force; 1106 { 1107 struct pciide_softc *sc = v; 1108 u_int8_t status; 1109 int error = 0; 1110 struct pciide_dma_maps *dma_maps = 1111 &sc->pciide_channels[channel].dma_maps[drive]; 1112 1113 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1114 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1115 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1116 DEBUG_XFERS); 1117 1118 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1119 return WDC_DMAST_NOIRQ; 1120 1121 /* stop DMA channel */ 1122 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1123 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1124 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1125 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1126 1127 /* Unload the map of the data buffer */ 1128 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1129 dma_maps->dmamap_xfer->dm_mapsize, 1130 (dma_maps->dma_flags & WDC_DMA_READ) ? 1131 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1132 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1133 1134 if ((status & IDEDMA_CTL_ERR) != 0) { 1135 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1136 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1137 error |= WDC_DMAST_ERR; 1138 } 1139 1140 if ((status & IDEDMA_CTL_INTR) == 0) { 1141 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1142 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1143 drive, status); 1144 error |= WDC_DMAST_NOIRQ; 1145 } 1146 1147 if ((status & IDEDMA_CTL_ACT) != 0) { 1148 /* data underrun, may be a valid condition for ATAPI */ 1149 error |= WDC_DMAST_UNDER; 1150 } 1151 return error; 1152 } 1153 1154 void 1155 pciide_irqack(chp) 1156 struct channel_softc *chp; 1157 { 1158 struct pciide_channel *cp = (struct pciide_channel*)chp; 1159 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1160 1161 /* clear status bits in IDE DMA registers */ 1162 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1163 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1164 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1165 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1166 } 1167 1168 /* some common code used by several chip_map */ 1169 int 1170 pciide_chansetup(sc, channel, interface) 1171 struct pciide_softc *sc; 1172 int channel; 1173 pcireg_t interface; 1174 { 1175 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1176 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1177 cp->name = PCIIDE_CHANNEL_NAME(channel); 1178 cp->wdc_channel.channel = channel; 1179 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1180 cp->wdc_channel.ch_queue = 1181 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1182 if (cp->wdc_channel.ch_queue == NULL) { 1183 printf("%s %s channel: " 1184 "can't allocate memory for command queue", 1185 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1186 return 0; 1187 } 1188 printf("%s: %s channel %s to %s mode\n", 1189 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1190 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1191 "configured" : "wired", 1192 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1193 "native-PCI" : "compatibility"); 1194 return 1; 1195 } 1196 1197 /* some common code used by several chip channel_map */ 1198 void 1199 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1200 struct pci_attach_args *pa; 1201 struct pciide_channel *cp; 1202 pcireg_t interface; 1203 bus_size_t *cmdsizep, *ctlsizep; 1204 int (*pci_intr) __P((void *)); 1205 { 1206 struct channel_softc *wdc_cp = &cp->wdc_channel; 1207 1208 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1209 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1210 pci_intr); 1211 else 1212 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1213 wdc_cp->channel, cmdsizep, ctlsizep); 1214 1215 if (cp->hw_ok == 0) 1216 return; 1217 wdc_cp->data32iot = wdc_cp->cmd_iot; 1218 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1219 wdcattach(wdc_cp); 1220 } 1221 1222 /* 1223 * Generic code to call to know if a channel can be disabled. Return 1 1224 * if channel can be disabled, 0 if not 1225 */ 1226 int 1227 pciide_chan_candisable(cp) 1228 struct pciide_channel *cp; 1229 { 1230 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1231 struct channel_softc *wdc_cp = &cp->wdc_channel; 1232 1233 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1234 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1235 printf("%s: disabling %s channel (no drives)\n", 1236 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1237 cp->hw_ok = 0; 1238 return 1; 1239 } 1240 return 0; 1241 } 1242 1243 /* 1244 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1245 * Set hw_ok=0 on failure 1246 */ 1247 void 1248 pciide_map_compat_intr(pa, cp, compatchan, interface) 1249 struct pci_attach_args *pa; 1250 struct pciide_channel *cp; 1251 int compatchan, interface; 1252 { 1253 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1254 struct channel_softc *wdc_cp = &cp->wdc_channel; 1255 1256 if (cp->hw_ok == 0) 1257 return; 1258 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1259 return; 1260 1261 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1262 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1263 pa, compatchan, pciide_compat_intr, cp); 1264 if (cp->ih == NULL) { 1265 #endif 1266 printf("%s: no compatibility interrupt for use by %s " 1267 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1268 cp->hw_ok = 0; 1269 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1270 } 1271 #endif 1272 } 1273 1274 void 1275 pciide_print_modes(cp) 1276 struct pciide_channel *cp; 1277 { 1278 wdc_print_modes(&cp->wdc_channel); 1279 } 1280 1281 void 1282 default_chip_map(sc, pa) 1283 struct pciide_softc *sc; 1284 struct pci_attach_args *pa; 1285 { 1286 struct pciide_channel *cp; 1287 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1288 pcireg_t csr; 1289 int channel, drive; 1290 struct ata_drive_datas *drvp; 1291 u_int8_t idedma_ctl; 1292 bus_size_t cmdsize, ctlsize; 1293 char *failreason; 1294 1295 if (pciide_chipen(sc, pa) == 0) 1296 return; 1297 1298 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1299 printf("%s: bus-master DMA support present", 1300 sc->sc_wdcdev.sc_dev.dv_xname); 1301 if (sc->sc_pp == &default_product_desc && 1302 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1303 PCIIDE_OPTIONS_DMA) == 0) { 1304 printf(", but unused (no driver support)"); 1305 sc->sc_dma_ok = 0; 1306 } else { 1307 pciide_mapreg_dma(sc, pa); 1308 if (sc->sc_dma_ok != 0) 1309 printf(", used without full driver " 1310 "support"); 1311 } 1312 } else { 1313 printf("%s: hardware does not support DMA", 1314 sc->sc_wdcdev.sc_dev.dv_xname); 1315 sc->sc_dma_ok = 0; 1316 } 1317 printf("\n"); 1318 if (sc->sc_dma_ok) { 1319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1320 sc->sc_wdcdev.irqack = pciide_irqack; 1321 } 1322 sc->sc_wdcdev.PIO_cap = 0; 1323 sc->sc_wdcdev.DMA_cap = 0; 1324 1325 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1326 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1327 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1328 1329 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1330 cp = &sc->pciide_channels[channel]; 1331 if (pciide_chansetup(sc, channel, interface) == 0) 1332 continue; 1333 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1334 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1335 &ctlsize, pciide_pci_intr); 1336 } else { 1337 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1338 channel, &cmdsize, &ctlsize); 1339 } 1340 if (cp->hw_ok == 0) 1341 continue; 1342 /* 1343 * Check to see if something appears to be there. 1344 */ 1345 failreason = NULL; 1346 if (!wdcprobe(&cp->wdc_channel)) { 1347 failreason = "not responding; disabled or no drives?"; 1348 goto next; 1349 } 1350 /* 1351 * Now, make sure it's actually attributable to this PCI IDE 1352 * channel by trying to access the channel again while the 1353 * PCI IDE controller's I/O space is disabled. (If the 1354 * channel no longer appears to be there, it belongs to 1355 * this controller.) YUCK! 1356 */ 1357 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1358 PCI_COMMAND_STATUS_REG); 1359 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1360 csr & ~PCI_COMMAND_IO_ENABLE); 1361 if (wdcprobe(&cp->wdc_channel)) 1362 failreason = "other hardware responding at addresses"; 1363 pci_conf_write(sc->sc_pc, sc->sc_tag, 1364 PCI_COMMAND_STATUS_REG, csr); 1365 next: 1366 if (failreason) { 1367 printf("%s: %s channel ignored (%s)\n", 1368 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1369 failreason); 1370 cp->hw_ok = 0; 1371 bus_space_unmap(cp->wdc_channel.cmd_iot, 1372 cp->wdc_channel.cmd_ioh, cmdsize); 1373 bus_space_unmap(cp->wdc_channel.ctl_iot, 1374 cp->wdc_channel.ctl_ioh, ctlsize); 1375 } else { 1376 pciide_map_compat_intr(pa, cp, channel, interface); 1377 } 1378 if (cp->hw_ok) { 1379 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1380 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1381 wdcattach(&cp->wdc_channel); 1382 } 1383 } 1384 1385 if (sc->sc_dma_ok == 0) 1386 return; 1387 1388 /* Allocate DMA maps */ 1389 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1390 idedma_ctl = 0; 1391 cp = &sc->pciide_channels[channel]; 1392 for (drive = 0; drive < 2; drive++) { 1393 drvp = &cp->wdc_channel.ch_drive[drive]; 1394 /* If no drive, skip */ 1395 if ((drvp->drive_flags & DRIVE) == 0) 1396 continue; 1397 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1398 continue; 1399 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1400 /* Abort DMA setup */ 1401 printf("%s:%d:%d: can't allocate DMA maps, " 1402 "using PIO transfers\n", 1403 sc->sc_wdcdev.sc_dev.dv_xname, 1404 channel, drive); 1405 drvp->drive_flags &= ~DRIVE_DMA; 1406 } 1407 printf("%s:%d:%d: using DMA data transfers\n", 1408 sc->sc_wdcdev.sc_dev.dv_xname, 1409 channel, drive); 1410 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1411 } 1412 if (idedma_ctl != 0) { 1413 /* Add software bits in status register */ 1414 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1415 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1416 idedma_ctl); 1417 } 1418 } 1419 } 1420 1421 void 1422 piix_chip_map(sc, pa) 1423 struct pciide_softc *sc; 1424 struct pci_attach_args *pa; 1425 { 1426 struct pciide_channel *cp; 1427 int channel; 1428 u_int32_t idetim; 1429 bus_size_t cmdsize, ctlsize; 1430 1431 if (pciide_chipen(sc, pa) == 0) 1432 return; 1433 1434 printf("%s: bus-master DMA support present", 1435 sc->sc_wdcdev.sc_dev.dv_xname); 1436 pciide_mapreg_dma(sc, pa); 1437 printf("\n"); 1438 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1439 WDC_CAPABILITY_MODE; 1440 if (sc->sc_dma_ok) { 1441 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1442 sc->sc_wdcdev.irqack = pciide_irqack; 1443 switch(sc->sc_pp->ide_product) { 1444 case PCI_PRODUCT_INTEL_82371AB_IDE: 1445 case PCI_PRODUCT_INTEL_82440MX_IDE: 1446 case PCI_PRODUCT_INTEL_82801AA_IDE: 1447 case PCI_PRODUCT_INTEL_82801AB_IDE: 1448 case PCI_PRODUCT_INTEL_82801BA_IDE: 1449 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1450 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1451 } 1452 } 1453 sc->sc_wdcdev.PIO_cap = 4; 1454 sc->sc_wdcdev.DMA_cap = 2; 1455 switch(sc->sc_pp->ide_product) { 1456 case PCI_PRODUCT_INTEL_82801AA_IDE: 1457 sc->sc_wdcdev.UDMA_cap = 4; 1458 break; 1459 case PCI_PRODUCT_INTEL_82801BA_IDE: 1460 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1461 sc->sc_wdcdev.UDMA_cap = 5; 1462 break; 1463 default: 1464 sc->sc_wdcdev.UDMA_cap = 2; 1465 } 1466 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1467 sc->sc_wdcdev.set_modes = piix_setup_channel; 1468 else 1469 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1470 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1471 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1472 1473 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1474 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1475 DEBUG_PROBE); 1476 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1477 WDCDEBUG_PRINT((", sidetim=0x%x", 1478 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1479 DEBUG_PROBE); 1480 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1481 WDCDEBUG_PRINT((", udamreg 0x%x", 1482 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1483 DEBUG_PROBE); 1484 } 1485 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1489 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1490 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1491 DEBUG_PROBE); 1492 } 1493 1494 } 1495 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1496 1497 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1498 cp = &sc->pciide_channels[channel]; 1499 /* PIIX is compat-only */ 1500 if (pciide_chansetup(sc, channel, 0) == 0) 1501 continue; 1502 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1503 if ((PIIX_IDETIM_READ(idetim, channel) & 1504 PIIX_IDETIM_IDE) == 0) { 1505 printf("%s: %s channel ignored (disabled)\n", 1506 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1507 continue; 1508 } 1509 /* PIIX are compat-only pciide devices */ 1510 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1511 if (cp->hw_ok == 0) 1512 continue; 1513 if (pciide_chan_candisable(cp)) { 1514 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1515 channel); 1516 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1517 idetim); 1518 } 1519 pciide_map_compat_intr(pa, cp, channel, 0); 1520 if (cp->hw_ok == 0) 1521 continue; 1522 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1523 } 1524 1525 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1526 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1527 DEBUG_PROBE); 1528 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1529 WDCDEBUG_PRINT((", sidetim=0x%x", 1530 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1531 DEBUG_PROBE); 1532 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1533 WDCDEBUG_PRINT((", udamreg 0x%x", 1534 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1535 DEBUG_PROBE); 1536 } 1537 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1538 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1539 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1540 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1541 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1542 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1543 DEBUG_PROBE); 1544 } 1545 } 1546 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1547 } 1548 1549 void 1550 piix_setup_channel(chp) 1551 struct channel_softc *chp; 1552 { 1553 u_int8_t mode[2], drive; 1554 u_int32_t oidetim, idetim, idedma_ctl; 1555 struct pciide_channel *cp = (struct pciide_channel*)chp; 1556 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1557 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1558 1559 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1560 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1561 idedma_ctl = 0; 1562 1563 /* set up new idetim: Enable IDE registers decode */ 1564 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1565 chp->channel); 1566 1567 /* setup DMA */ 1568 pciide_channel_dma_setup(cp); 1569 1570 /* 1571 * Here we have to mess up with drives mode: PIIX can't have 1572 * different timings for master and slave drives. 1573 * We need to find the best combination. 1574 */ 1575 1576 /* If both drives supports DMA, take the lower mode */ 1577 if ((drvp[0].drive_flags & DRIVE_DMA) && 1578 (drvp[1].drive_flags & DRIVE_DMA)) { 1579 mode[0] = mode[1] = 1580 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1581 drvp[0].DMA_mode = mode[0]; 1582 drvp[1].DMA_mode = mode[1]; 1583 goto ok; 1584 } 1585 /* 1586 * If only one drive supports DMA, use its mode, and 1587 * put the other one in PIO mode 0 if mode not compatible 1588 */ 1589 if (drvp[0].drive_flags & DRIVE_DMA) { 1590 mode[0] = drvp[0].DMA_mode; 1591 mode[1] = drvp[1].PIO_mode; 1592 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1593 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1594 mode[1] = drvp[1].PIO_mode = 0; 1595 goto ok; 1596 } 1597 if (drvp[1].drive_flags & DRIVE_DMA) { 1598 mode[1] = drvp[1].DMA_mode; 1599 mode[0] = drvp[0].PIO_mode; 1600 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1601 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1602 mode[0] = drvp[0].PIO_mode = 0; 1603 goto ok; 1604 } 1605 /* 1606 * If both drives are not DMA, takes the lower mode, unless 1607 * one of them is PIO mode < 2 1608 */ 1609 if (drvp[0].PIO_mode < 2) { 1610 mode[0] = drvp[0].PIO_mode = 0; 1611 mode[1] = drvp[1].PIO_mode; 1612 } else if (drvp[1].PIO_mode < 2) { 1613 mode[1] = drvp[1].PIO_mode = 0; 1614 mode[0] = drvp[0].PIO_mode; 1615 } else { 1616 mode[0] = mode[1] = 1617 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1618 drvp[0].PIO_mode = mode[0]; 1619 drvp[1].PIO_mode = mode[1]; 1620 } 1621 ok: /* The modes are setup */ 1622 for (drive = 0; drive < 2; drive++) { 1623 if (drvp[drive].drive_flags & DRIVE_DMA) { 1624 idetim |= piix_setup_idetim_timings( 1625 mode[drive], 1, chp->channel); 1626 goto end; 1627 } 1628 } 1629 /* If we are there, none of the drives are DMA */ 1630 if (mode[0] >= 2) 1631 idetim |= piix_setup_idetim_timings( 1632 mode[0], 0, chp->channel); 1633 else 1634 idetim |= piix_setup_idetim_timings( 1635 mode[1], 0, chp->channel); 1636 end: /* 1637 * timing mode is now set up in the controller. Enable 1638 * it per-drive 1639 */ 1640 for (drive = 0; drive < 2; drive++) { 1641 /* If no drive, skip */ 1642 if ((drvp[drive].drive_flags & DRIVE) == 0) 1643 continue; 1644 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1645 if (drvp[drive].drive_flags & DRIVE_DMA) 1646 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1647 } 1648 if (idedma_ctl != 0) { 1649 /* Add software bits in status register */ 1650 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1651 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1652 idedma_ctl); 1653 } 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1655 pciide_print_modes(cp); 1656 } 1657 1658 void 1659 piix3_4_setup_channel(chp) 1660 struct channel_softc *chp; 1661 { 1662 struct ata_drive_datas *drvp; 1663 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1664 struct pciide_channel *cp = (struct pciide_channel*)chp; 1665 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1666 int drive; 1667 int channel = chp->channel; 1668 1669 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1670 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1671 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1672 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1673 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1674 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1675 PIIX_SIDETIM_RTC_MASK(channel)); 1676 1677 idedma_ctl = 0; 1678 /* If channel disabled, no need to go further */ 1679 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1680 return; 1681 /* set up new idetim: Enable IDE registers decode */ 1682 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1683 1684 /* setup DMA if needed */ 1685 pciide_channel_dma_setup(cp); 1686 1687 for (drive = 0; drive < 2; drive++) { 1688 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1689 PIIX_UDMATIM_SET(0x3, channel, drive)); 1690 drvp = &chp->ch_drive[drive]; 1691 /* If no drive, skip */ 1692 if ((drvp->drive_flags & DRIVE) == 0) 1693 continue; 1694 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1695 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1696 goto pio; 1697 1698 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1699 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1700 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1701 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1702 ideconf |= PIIX_CONFIG_PINGPONG; 1703 } 1704 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1705 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1706 /* setup Ultra/100 */ 1707 if (drvp->UDMA_mode > 2 && 1708 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1709 drvp->UDMA_mode = 2; 1710 if (drvp->UDMA_mode > 4) { 1711 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1712 } else { 1713 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1714 if (drvp->UDMA_mode > 2) { 1715 ideconf |= PIIX_CONFIG_UDMA66(channel, 1716 drive); 1717 } else { 1718 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1719 drive); 1720 } 1721 } 1722 } 1723 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1724 /* setup Ultra/66 */ 1725 if (drvp->UDMA_mode > 2 && 1726 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1727 drvp->UDMA_mode = 2; 1728 if (drvp->UDMA_mode > 2) 1729 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1730 else 1731 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1732 } 1733 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1734 (drvp->drive_flags & DRIVE_UDMA)) { 1735 /* use Ultra/DMA */ 1736 drvp->drive_flags &= ~DRIVE_DMA; 1737 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1738 udmareg |= PIIX_UDMATIM_SET( 1739 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1740 } else { 1741 /* use Multiword DMA */ 1742 drvp->drive_flags &= ~DRIVE_UDMA; 1743 if (drive == 0) { 1744 idetim |= piix_setup_idetim_timings( 1745 drvp->DMA_mode, 1, channel); 1746 } else { 1747 sidetim |= piix_setup_sidetim_timings( 1748 drvp->DMA_mode, 1, channel); 1749 idetim =PIIX_IDETIM_SET(idetim, 1750 PIIX_IDETIM_SITRE, channel); 1751 } 1752 } 1753 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1754 1755 pio: /* use PIO mode */ 1756 idetim |= piix_setup_idetim_drvs(drvp); 1757 if (drive == 0) { 1758 idetim |= piix_setup_idetim_timings( 1759 drvp->PIO_mode, 0, channel); 1760 } else { 1761 sidetim |= piix_setup_sidetim_timings( 1762 drvp->PIO_mode, 0, channel); 1763 idetim =PIIX_IDETIM_SET(idetim, 1764 PIIX_IDETIM_SITRE, channel); 1765 } 1766 } 1767 if (idedma_ctl != 0) { 1768 /* Add software bits in status register */ 1769 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1770 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1771 idedma_ctl); 1772 } 1773 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1774 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1775 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1776 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1777 pciide_print_modes(cp); 1778 } 1779 1780 1781 /* setup ISP and RTC fields, based on mode */ 1782 static u_int32_t 1783 piix_setup_idetim_timings(mode, dma, channel) 1784 u_int8_t mode; 1785 u_int8_t dma; 1786 u_int8_t channel; 1787 { 1788 1789 if (dma) 1790 return PIIX_IDETIM_SET(0, 1791 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1792 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1793 channel); 1794 else 1795 return PIIX_IDETIM_SET(0, 1796 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1797 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1798 channel); 1799 } 1800 1801 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1802 static u_int32_t 1803 piix_setup_idetim_drvs(drvp) 1804 struct ata_drive_datas *drvp; 1805 { 1806 u_int32_t ret = 0; 1807 struct channel_softc *chp = drvp->chnl_softc; 1808 u_int8_t channel = chp->channel; 1809 u_int8_t drive = drvp->drive; 1810 1811 /* 1812 * If drive is using UDMA, timings setups are independant 1813 * So just check DMA and PIO here. 1814 */ 1815 if (drvp->drive_flags & DRIVE_DMA) { 1816 /* if mode = DMA mode 0, use compatible timings */ 1817 if ((drvp->drive_flags & DRIVE_DMA) && 1818 drvp->DMA_mode == 0) { 1819 drvp->PIO_mode = 0; 1820 return ret; 1821 } 1822 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1823 /* 1824 * PIO and DMA timings are the same, use fast timings for PIO 1825 * too, else use compat timings. 1826 */ 1827 if ((piix_isp_pio[drvp->PIO_mode] != 1828 piix_isp_dma[drvp->DMA_mode]) || 1829 (piix_rtc_pio[drvp->PIO_mode] != 1830 piix_rtc_dma[drvp->DMA_mode])) 1831 drvp->PIO_mode = 0; 1832 /* if PIO mode <= 2, use compat timings for PIO */ 1833 if (drvp->PIO_mode <= 2) { 1834 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1835 channel); 1836 return ret; 1837 } 1838 } 1839 1840 /* 1841 * Now setup PIO modes. If mode < 2, use compat timings. 1842 * Else enable fast timings. Enable IORDY and prefetch/post 1843 * if PIO mode >= 3. 1844 */ 1845 1846 if (drvp->PIO_mode < 2) 1847 return ret; 1848 1849 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1850 if (drvp->PIO_mode >= 3) { 1851 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1852 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1853 } 1854 return ret; 1855 } 1856 1857 /* setup values in SIDETIM registers, based on mode */ 1858 static u_int32_t 1859 piix_setup_sidetim_timings(mode, dma, channel) 1860 u_int8_t mode; 1861 u_int8_t dma; 1862 u_int8_t channel; 1863 { 1864 if (dma) 1865 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1866 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1867 else 1868 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1869 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1870 } 1871 1872 void 1873 amd7x6_chip_map(sc, pa) 1874 struct pciide_softc *sc; 1875 struct pci_attach_args *pa; 1876 { 1877 struct pciide_channel *cp; 1878 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1879 int channel; 1880 pcireg_t chanenable; 1881 bus_size_t cmdsize, ctlsize; 1882 1883 if (pciide_chipen(sc, pa) == 0) 1884 return; 1885 printf("%s: bus-master DMA support present", 1886 sc->sc_wdcdev.sc_dev.dv_xname); 1887 pciide_mapreg_dma(sc, pa); 1888 printf("\n"); 1889 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1890 WDC_CAPABILITY_MODE; 1891 if (sc->sc_dma_ok) { 1892 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1894 sc->sc_wdcdev.irqack = pciide_irqack; 1895 } 1896 sc->sc_wdcdev.PIO_cap = 4; 1897 sc->sc_wdcdev.DMA_cap = 2; 1898 1899 if (sc->sc_pp->ide_product == PCI_PRODUCT_AMD_PBC766_IDE) 1900 sc->sc_wdcdev.UDMA_cap = 5; 1901 else 1902 sc->sc_wdcdev.UDMA_cap = 4; 1903 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1904 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1905 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1906 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1907 1908 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1909 DEBUG_PROBE); 1910 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1911 cp = &sc->pciide_channels[channel]; 1912 if (pciide_chansetup(sc, channel, interface) == 0) 1913 continue; 1914 1915 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1916 printf("%s: %s channel ignored (disabled)\n", 1917 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1918 continue; 1919 } 1920 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1921 pciide_pci_intr); 1922 1923 if (pciide_chan_candisable(cp)) 1924 chanenable &= ~AMD7X6_CHAN_EN(channel); 1925 pciide_map_compat_intr(pa, cp, channel, interface); 1926 if (cp->hw_ok == 0) 1927 continue; 1928 1929 amd7x6_setup_channel(&cp->wdc_channel); 1930 } 1931 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1932 chanenable); 1933 return; 1934 } 1935 1936 void 1937 amd7x6_setup_channel(chp) 1938 struct channel_softc *chp; 1939 { 1940 u_int32_t udmatim_reg, datatim_reg; 1941 u_int8_t idedma_ctl; 1942 int mode, drive; 1943 struct ata_drive_datas *drvp; 1944 struct pciide_channel *cp = (struct pciide_channel*)chp; 1945 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1946 #ifndef PCIIDE_AMD756_ENABLEDMA 1947 int rev = PCI_REVISION( 1948 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1949 #endif 1950 1951 idedma_ctl = 0; 1952 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1953 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1954 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1955 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1956 1957 /* setup DMA if needed */ 1958 pciide_channel_dma_setup(cp); 1959 1960 for (drive = 0; drive < 2; drive++) { 1961 drvp = &chp->ch_drive[drive]; 1962 /* If no drive, skip */ 1963 if ((drvp->drive_flags & DRIVE) == 0) 1964 continue; 1965 /* add timing values, setup DMA if needed */ 1966 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1967 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1968 mode = drvp->PIO_mode; 1969 goto pio; 1970 } 1971 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1972 (drvp->drive_flags & DRIVE_UDMA)) { 1973 /* use Ultra/DMA */ 1974 drvp->drive_flags &= ~DRIVE_DMA; 1975 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 1976 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 1977 AMD7X6_UDMA_TIME(chp->channel, drive, 1978 amd7x6_udma_tim[drvp->UDMA_mode]); 1979 /* can use PIO timings, MW DMA unused */ 1980 mode = drvp->PIO_mode; 1981 } else { 1982 /* use Multiword DMA, but only if revision is OK */ 1983 drvp->drive_flags &= ~DRIVE_UDMA; 1984 #ifndef PCIIDE_AMD756_ENABLEDMA 1985 /* 1986 * The workaround doesn't seem to be necessary 1987 * with all drives, so it can be disabled by 1988 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1989 * triggered. 1990 */ 1991 if (sc->sc_pp->ide_product == 1992 PCI_PRODUCT_AMD_PBC756_IDE && 1993 AMD756_CHIPREV_DISABLEDMA(rev)) { 1994 printf("%s:%d:%d: multi-word DMA disabled due " 1995 "to chip revision\n", 1996 sc->sc_wdcdev.sc_dev.dv_xname, 1997 chp->channel, drive); 1998 mode = drvp->PIO_mode; 1999 drvp->drive_flags &= ~DRIVE_DMA; 2000 goto pio; 2001 } 2002 #endif 2003 /* mode = min(pio, dma+2) */ 2004 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2005 mode = drvp->PIO_mode; 2006 else 2007 mode = drvp->DMA_mode + 2; 2008 } 2009 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2010 2011 pio: /* setup PIO mode */ 2012 if (mode <= 2) { 2013 drvp->DMA_mode = 0; 2014 drvp->PIO_mode = 0; 2015 mode = 0; 2016 } else { 2017 drvp->PIO_mode = mode; 2018 drvp->DMA_mode = mode - 2; 2019 } 2020 datatim_reg |= 2021 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2022 amd7x6_pio_set[mode]) | 2023 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2024 amd7x6_pio_rec[mode]); 2025 } 2026 if (idedma_ctl != 0) { 2027 /* Add software bits in status register */ 2028 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2029 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2030 idedma_ctl); 2031 } 2032 pciide_print_modes(cp); 2033 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2034 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2035 } 2036 2037 void 2038 apollo_chip_map(sc, pa) 2039 struct pciide_softc *sc; 2040 struct pci_attach_args *pa; 2041 { 2042 struct pciide_channel *cp; 2043 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2044 int channel; 2045 u_int32_t ideconf; 2046 bus_size_t cmdsize, ctlsize; 2047 pcitag_t pcib_tag; 2048 pcireg_t pcib_id, pcib_class; 2049 2050 if (pciide_chipen(sc, pa) == 0) 2051 return; 2052 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2053 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2054 /* and read ID and rev of the ISA bridge */ 2055 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2056 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2057 printf(": VIA Technologies "); 2058 switch (PCI_PRODUCT(pcib_id)) { 2059 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2060 printf("VT82C586 (Apollo VP) "); 2061 if(PCI_REVISION(pcib_class) >= 0x02) { 2062 printf("ATA33 controller\n"); 2063 sc->sc_wdcdev.UDMA_cap = 2; 2064 } else { 2065 printf("controller\n"); 2066 sc->sc_wdcdev.UDMA_cap = 0; 2067 } 2068 break; 2069 case PCI_PRODUCT_VIATECH_VT82C596A: 2070 printf("VT82C596A (Apollo Pro) "); 2071 if (PCI_REVISION(pcib_class) >= 0x12) { 2072 printf("ATA66 controller\n"); 2073 sc->sc_wdcdev.UDMA_cap = 4; 2074 } else { 2075 printf("ATA33 controller\n"); 2076 sc->sc_wdcdev.UDMA_cap = 2; 2077 } 2078 break; 2079 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2080 printf("VT82C686A (Apollo KX133) "); 2081 if (PCI_REVISION(pcib_class) >= 0x40) { 2082 printf("ATA100 controller\n"); 2083 sc->sc_wdcdev.UDMA_cap = 5; 2084 } else { 2085 printf("ATA66 controller\n"); 2086 sc->sc_wdcdev.UDMA_cap = 4; 2087 } 2088 break; 2089 default: 2090 printf("unknown ATA controller\n"); 2091 sc->sc_wdcdev.UDMA_cap = 0; 2092 } 2093 2094 printf("%s: bus-master DMA support present", 2095 sc->sc_wdcdev.sc_dev.dv_xname); 2096 pciide_mapreg_dma(sc, pa); 2097 printf("\n"); 2098 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2099 WDC_CAPABILITY_MODE; 2100 if (sc->sc_dma_ok) { 2101 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2102 sc->sc_wdcdev.irqack = pciide_irqack; 2103 if (sc->sc_wdcdev.UDMA_cap > 0) 2104 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2105 } 2106 sc->sc_wdcdev.PIO_cap = 4; 2107 sc->sc_wdcdev.DMA_cap = 2; 2108 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2109 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2110 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2111 2112 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2113 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2114 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2115 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2116 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2117 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2118 DEBUG_PROBE); 2119 2120 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2121 cp = &sc->pciide_channels[channel]; 2122 if (pciide_chansetup(sc, channel, interface) == 0) 2123 continue; 2124 2125 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2126 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2127 printf("%s: %s channel ignored (disabled)\n", 2128 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2129 continue; 2130 } 2131 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2132 pciide_pci_intr); 2133 if (cp->hw_ok == 0) 2134 continue; 2135 if (pciide_chan_candisable(cp)) { 2136 ideconf &= ~APO_IDECONF_EN(channel); 2137 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2138 ideconf); 2139 } 2140 pciide_map_compat_intr(pa, cp, channel, interface); 2141 2142 if (cp->hw_ok == 0) 2143 continue; 2144 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2145 } 2146 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2147 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2148 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2149 } 2150 2151 void 2152 apollo_setup_channel(chp) 2153 struct channel_softc *chp; 2154 { 2155 u_int32_t udmatim_reg, datatim_reg; 2156 u_int8_t idedma_ctl; 2157 int mode, drive; 2158 struct ata_drive_datas *drvp; 2159 struct pciide_channel *cp = (struct pciide_channel*)chp; 2160 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2161 2162 idedma_ctl = 0; 2163 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2164 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2165 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2166 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2167 2168 /* setup DMA if needed */ 2169 pciide_channel_dma_setup(cp); 2170 2171 for (drive = 0; drive < 2; drive++) { 2172 drvp = &chp->ch_drive[drive]; 2173 /* If no drive, skip */ 2174 if ((drvp->drive_flags & DRIVE) == 0) 2175 continue; 2176 /* add timing values, setup DMA if needed */ 2177 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2178 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2179 mode = drvp->PIO_mode; 2180 goto pio; 2181 } 2182 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2183 (drvp->drive_flags & DRIVE_UDMA)) { 2184 /* use Ultra/DMA */ 2185 drvp->drive_flags &= ~DRIVE_DMA; 2186 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2187 APO_UDMA_EN_MTH(chp->channel, drive); 2188 if (sc->sc_wdcdev.UDMA_cap == 5) { 2189 /* 686b */ 2190 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2191 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2192 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2193 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2194 /* 596b or 686a */ 2195 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2196 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2197 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2198 } else { 2199 /* 596a or 586b */ 2200 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2201 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2202 } 2203 /* can use PIO timings, MW DMA unused */ 2204 mode = drvp->PIO_mode; 2205 } else { 2206 /* use Multiword DMA */ 2207 drvp->drive_flags &= ~DRIVE_UDMA; 2208 /* mode = min(pio, dma+2) */ 2209 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2210 mode = drvp->PIO_mode; 2211 else 2212 mode = drvp->DMA_mode + 2; 2213 } 2214 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2215 2216 pio: /* setup PIO mode */ 2217 if (mode <= 2) { 2218 drvp->DMA_mode = 0; 2219 drvp->PIO_mode = 0; 2220 mode = 0; 2221 } else { 2222 drvp->PIO_mode = mode; 2223 drvp->DMA_mode = mode - 2; 2224 } 2225 datatim_reg |= 2226 APO_DATATIM_PULSE(chp->channel, drive, 2227 apollo_pio_set[mode]) | 2228 APO_DATATIM_RECOV(chp->channel, drive, 2229 apollo_pio_rec[mode]); 2230 } 2231 if (idedma_ctl != 0) { 2232 /* Add software bits in status register */ 2233 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2234 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2235 idedma_ctl); 2236 } 2237 pciide_print_modes(cp); 2238 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2239 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2240 } 2241 2242 void 2243 cmd_channel_map(pa, sc, channel) 2244 struct pci_attach_args *pa; 2245 struct pciide_softc *sc; 2246 int channel; 2247 { 2248 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2249 bus_size_t cmdsize, ctlsize; 2250 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2251 int interface; 2252 2253 /* 2254 * The 0648/0649 can be told to identify as a RAID controller. 2255 * In this case, we have to fake interface 2256 */ 2257 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2258 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2259 PCIIDE_INTERFACE_SETTABLE(1); 2260 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2261 CMD_CONF_DSA1) 2262 interface |= PCIIDE_INTERFACE_PCI(0) | 2263 PCIIDE_INTERFACE_PCI(1); 2264 } else { 2265 interface = PCI_INTERFACE(pa->pa_class); 2266 } 2267 2268 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2269 cp->name = PCIIDE_CHANNEL_NAME(channel); 2270 cp->wdc_channel.channel = channel; 2271 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2272 2273 if (channel > 0) { 2274 cp->wdc_channel.ch_queue = 2275 sc->pciide_channels[0].wdc_channel.ch_queue; 2276 } else { 2277 cp->wdc_channel.ch_queue = 2278 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2279 } 2280 if (cp->wdc_channel.ch_queue == NULL) { 2281 printf("%s %s channel: " 2282 "can't allocate memory for command queue", 2283 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2284 return; 2285 } 2286 2287 printf("%s: %s channel %s to %s mode\n", 2288 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2289 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2290 "configured" : "wired", 2291 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2292 "native-PCI" : "compatibility"); 2293 2294 /* 2295 * with a CMD PCI64x, if we get here, the first channel is enabled: 2296 * there's no way to disable the first channel without disabling 2297 * the whole device 2298 */ 2299 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2300 printf("%s: %s channel ignored (disabled)\n", 2301 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2302 return; 2303 } 2304 2305 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2306 if (cp->hw_ok == 0) 2307 return; 2308 if (channel == 1) { 2309 if (pciide_chan_candisable(cp)) { 2310 ctrl &= ~CMD_CTRL_2PORT; 2311 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2312 CMD_CTRL, ctrl); 2313 } 2314 } 2315 pciide_map_compat_intr(pa, cp, channel, interface); 2316 } 2317 2318 int 2319 cmd_pci_intr(arg) 2320 void *arg; 2321 { 2322 struct pciide_softc *sc = arg; 2323 struct pciide_channel *cp; 2324 struct channel_softc *wdc_cp; 2325 int i, rv, crv; 2326 u_int32_t priirq, secirq; 2327 2328 rv = 0; 2329 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2330 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2331 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2332 cp = &sc->pciide_channels[i]; 2333 wdc_cp = &cp->wdc_channel; 2334 /* If a compat channel skip. */ 2335 if (cp->compat) 2336 continue; 2337 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2338 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2339 crv = wdcintr(wdc_cp); 2340 if (crv == 0) 2341 printf("%s:%d: bogus intr\n", 2342 sc->sc_wdcdev.sc_dev.dv_xname, i); 2343 else 2344 rv = 1; 2345 } 2346 } 2347 return rv; 2348 } 2349 2350 void 2351 cmd_chip_map(sc, pa) 2352 struct pciide_softc *sc; 2353 struct pci_attach_args *pa; 2354 { 2355 int channel; 2356 2357 /* 2358 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2359 * and base adresses registers can be disabled at 2360 * hardware level. In this case, the device is wired 2361 * in compat mode and its first channel is always enabled, 2362 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2363 * In fact, it seems that the first channel of the CMD PCI0640 2364 * can't be disabled. 2365 */ 2366 2367 #ifdef PCIIDE_CMD064x_DISABLE 2368 if (pciide_chipen(sc, pa) == 0) 2369 return; 2370 #endif 2371 2372 printf("%s: hardware does not support DMA\n", 2373 sc->sc_wdcdev.sc_dev.dv_xname); 2374 sc->sc_dma_ok = 0; 2375 2376 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2377 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2378 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2379 2380 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2381 cmd_channel_map(pa, sc, channel); 2382 } 2383 } 2384 2385 void 2386 cmd0643_9_chip_map(sc, pa) 2387 struct pciide_softc *sc; 2388 struct pci_attach_args *pa; 2389 { 2390 struct pciide_channel *cp; 2391 int channel; 2392 int rev = PCI_REVISION( 2393 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2394 2395 /* 2396 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2397 * and base adresses registers can be disabled at 2398 * hardware level. In this case, the device is wired 2399 * in compat mode and its first channel is always enabled, 2400 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2401 * In fact, it seems that the first channel of the CMD PCI0640 2402 * can't be disabled. 2403 */ 2404 2405 #ifdef PCIIDE_CMD064x_DISABLE 2406 if (pciide_chipen(sc, pa) == 0) 2407 return; 2408 #endif 2409 printf("%s: bus-master DMA support present", 2410 sc->sc_wdcdev.sc_dev.dv_xname); 2411 pciide_mapreg_dma(sc, pa); 2412 printf("\n"); 2413 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2414 WDC_CAPABILITY_MODE; 2415 if (sc->sc_dma_ok) { 2416 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2417 switch (sc->sc_pp->ide_product) { 2418 case PCI_PRODUCT_CMDTECH_649: 2419 case PCI_PRODUCT_CMDTECH_648: 2420 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2421 sc->sc_wdcdev.UDMA_cap = 4; 2422 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2423 break; 2424 case PCI_PRODUCT_CMDTECH_646: 2425 if (rev >= CMD0646U2_REV) { 2426 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2427 sc->sc_wdcdev.UDMA_cap = 2; 2428 } else if (rev >= CMD0646U_REV) { 2429 /* 2430 * Linux's driver claims that the 646U is broken 2431 * with UDMA. Only enable it if we know what we're 2432 * doing 2433 */ 2434 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2435 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2436 sc->sc_wdcdev.UDMA_cap = 2; 2437 #endif 2438 /* explicitely disable UDMA */ 2439 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2440 CMD_UDMATIM(0), 0); 2441 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2442 CMD_UDMATIM(1), 0); 2443 } 2444 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2445 break; 2446 default: 2447 sc->sc_wdcdev.irqack = pciide_irqack; 2448 } 2449 } 2450 2451 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2452 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2453 sc->sc_wdcdev.PIO_cap = 4; 2454 sc->sc_wdcdev.DMA_cap = 2; 2455 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2456 2457 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2458 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2459 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2460 DEBUG_PROBE); 2461 2462 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2463 cp = &sc->pciide_channels[channel]; 2464 cmd_channel_map(pa, sc, channel); 2465 if (cp->hw_ok == 0) 2466 continue; 2467 cmd0643_9_setup_channel(&cp->wdc_channel); 2468 } 2469 /* 2470 * note - this also makes sure we clear the irq disable and reset 2471 * bits 2472 */ 2473 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2474 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2475 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2476 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2477 DEBUG_PROBE); 2478 } 2479 2480 void 2481 cmd0643_9_setup_channel(chp) 2482 struct channel_softc *chp; 2483 { 2484 struct ata_drive_datas *drvp; 2485 u_int8_t tim; 2486 u_int32_t idedma_ctl, udma_reg; 2487 int drive; 2488 struct pciide_channel *cp = (struct pciide_channel*)chp; 2489 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2490 2491 idedma_ctl = 0; 2492 /* setup DMA if needed */ 2493 pciide_channel_dma_setup(cp); 2494 2495 for (drive = 0; drive < 2; drive++) { 2496 drvp = &chp->ch_drive[drive]; 2497 /* If no drive, skip */ 2498 if ((drvp->drive_flags & DRIVE) == 0) 2499 continue; 2500 /* add timing values, setup DMA if needed */ 2501 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2502 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2503 if (drvp->drive_flags & DRIVE_UDMA) { 2504 /* UltraDMA on a 646U2, 0648 or 0649 */ 2505 drvp->drive_flags &= ~DRIVE_DMA; 2506 udma_reg = pciide_pci_read(sc->sc_pc, 2507 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2508 if (drvp->UDMA_mode > 2 && 2509 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2510 CMD_BICSR) & 2511 CMD_BICSR_80(chp->channel)) == 0) 2512 drvp->UDMA_mode = 2; 2513 if (drvp->UDMA_mode > 2) 2514 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2515 else if (sc->sc_wdcdev.UDMA_cap > 2) 2516 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2517 udma_reg |= CMD_UDMATIM_UDMA(drive); 2518 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2519 CMD_UDMATIM_TIM_OFF(drive)); 2520 udma_reg |= 2521 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2522 CMD_UDMATIM_TIM_OFF(drive)); 2523 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2524 CMD_UDMATIM(chp->channel), udma_reg); 2525 } else { 2526 /* 2527 * use Multiword DMA. 2528 * Timings will be used for both PIO and DMA, 2529 * so adjust DMA mode if needed 2530 * if we have a 0646U2/8/9, turn off UDMA 2531 */ 2532 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2533 udma_reg = pciide_pci_read(sc->sc_pc, 2534 sc->sc_tag, 2535 CMD_UDMATIM(chp->channel)); 2536 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2537 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2538 CMD_UDMATIM(chp->channel), 2539 udma_reg); 2540 } 2541 if (drvp->PIO_mode >= 3 && 2542 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2543 drvp->DMA_mode = drvp->PIO_mode - 2; 2544 } 2545 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2546 } 2547 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2548 } 2549 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2550 CMD_DATA_TIM(chp->channel, drive), tim); 2551 } 2552 if (idedma_ctl != 0) { 2553 /* Add software bits in status register */ 2554 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2555 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2556 idedma_ctl); 2557 } 2558 pciide_print_modes(cp); 2559 } 2560 2561 void 2562 cmd646_9_irqack(chp) 2563 struct channel_softc *chp; 2564 { 2565 u_int32_t priirq, secirq; 2566 struct pciide_channel *cp = (struct pciide_channel*)chp; 2567 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2568 2569 if (chp->channel == 0) { 2570 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2571 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2572 } else { 2573 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2574 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2575 } 2576 pciide_irqack(chp); 2577 } 2578 2579 void 2580 cy693_chip_map(sc, pa) 2581 struct pciide_softc *sc; 2582 struct pci_attach_args *pa; 2583 { 2584 struct pciide_channel *cp; 2585 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2586 bus_size_t cmdsize, ctlsize; 2587 2588 if (pciide_chipen(sc, pa) == 0) 2589 return; 2590 /* 2591 * this chip has 2 PCI IDE functions, one for primary and one for 2592 * secondary. So we need to call pciide_mapregs_compat() with 2593 * the real channel 2594 */ 2595 if (pa->pa_function == 1) { 2596 sc->sc_cy_compatchan = 0; 2597 } else if (pa->pa_function == 2) { 2598 sc->sc_cy_compatchan = 1; 2599 } else { 2600 printf("%s: unexpected PCI function %d\n", 2601 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2602 return; 2603 } 2604 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2605 printf("%s: bus-master DMA support present", 2606 sc->sc_wdcdev.sc_dev.dv_xname); 2607 pciide_mapreg_dma(sc, pa); 2608 } else { 2609 printf("%s: hardware does not support DMA", 2610 sc->sc_wdcdev.sc_dev.dv_xname); 2611 sc->sc_dma_ok = 0; 2612 } 2613 printf("\n"); 2614 2615 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2616 if (sc->sc_cy_handle == NULL) { 2617 printf("%s: unable to map hyperCache control registers\n", 2618 sc->sc_wdcdev.sc_dev.dv_xname); 2619 sc->sc_dma_ok = 0; 2620 } 2621 2622 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2623 WDC_CAPABILITY_MODE; 2624 if (sc->sc_dma_ok) { 2625 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2626 sc->sc_wdcdev.irqack = pciide_irqack; 2627 } 2628 sc->sc_wdcdev.PIO_cap = 4; 2629 sc->sc_wdcdev.DMA_cap = 2; 2630 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2631 2632 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2633 sc->sc_wdcdev.nchannels = 1; 2634 2635 /* Only one channel for this chip; if we are here it's enabled */ 2636 cp = &sc->pciide_channels[0]; 2637 sc->wdc_chanarray[0] = &cp->wdc_channel; 2638 cp->name = PCIIDE_CHANNEL_NAME(0); 2639 cp->wdc_channel.channel = 0; 2640 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2641 cp->wdc_channel.ch_queue = 2642 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2643 if (cp->wdc_channel.ch_queue == NULL) { 2644 printf("%s primary channel: " 2645 "can't allocate memory for command queue", 2646 sc->sc_wdcdev.sc_dev.dv_xname); 2647 return; 2648 } 2649 printf("%s: primary channel %s to ", 2650 sc->sc_wdcdev.sc_dev.dv_xname, 2651 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2652 "configured" : "wired"); 2653 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2654 printf("native-PCI"); 2655 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2656 pciide_pci_intr); 2657 } else { 2658 printf("compatibility"); 2659 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2660 &cmdsize, &ctlsize); 2661 } 2662 printf(" mode\n"); 2663 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2664 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2665 wdcattach(&cp->wdc_channel); 2666 if (pciide_chan_candisable(cp)) { 2667 pci_conf_write(sc->sc_pc, sc->sc_tag, 2668 PCI_COMMAND_STATUS_REG, 0); 2669 } 2670 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2671 if (cp->hw_ok == 0) 2672 return; 2673 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2674 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2675 cy693_setup_channel(&cp->wdc_channel); 2676 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2677 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2678 } 2679 2680 void 2681 cy693_setup_channel(chp) 2682 struct channel_softc *chp; 2683 { 2684 struct ata_drive_datas *drvp; 2685 int drive; 2686 u_int32_t cy_cmd_ctrl; 2687 u_int32_t idedma_ctl; 2688 struct pciide_channel *cp = (struct pciide_channel*)chp; 2689 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2690 int dma_mode = -1; 2691 2692 cy_cmd_ctrl = idedma_ctl = 0; 2693 2694 /* setup DMA if needed */ 2695 pciide_channel_dma_setup(cp); 2696 2697 for (drive = 0; drive < 2; drive++) { 2698 drvp = &chp->ch_drive[drive]; 2699 /* If no drive, skip */ 2700 if ((drvp->drive_flags & DRIVE) == 0) 2701 continue; 2702 /* add timing values, setup DMA if needed */ 2703 if (drvp->drive_flags & DRIVE_DMA) { 2704 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2705 /* use Multiword DMA */ 2706 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2707 dma_mode = drvp->DMA_mode; 2708 } 2709 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2710 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2711 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2712 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2713 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2714 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2715 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2716 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2717 } 2718 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2719 chp->ch_drive[0].DMA_mode = dma_mode; 2720 chp->ch_drive[1].DMA_mode = dma_mode; 2721 2722 if (dma_mode == -1) 2723 dma_mode = 0; 2724 2725 if (sc->sc_cy_handle != NULL) { 2726 /* Note: `multiple' is implied. */ 2727 cy82c693_write(sc->sc_cy_handle, 2728 (sc->sc_cy_compatchan == 0) ? 2729 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2730 } 2731 2732 pciide_print_modes(cp); 2733 2734 if (idedma_ctl != 0) { 2735 /* Add software bits in status register */ 2736 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2737 IDEDMA_CTL, idedma_ctl); 2738 } 2739 } 2740 2741 void 2742 sis_chip_map(sc, pa) 2743 struct pciide_softc *sc; 2744 struct pci_attach_args *pa; 2745 { 2746 struct pciide_channel *cp; 2747 int channel; 2748 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2749 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2750 pcireg_t rev = PCI_REVISION(pa->pa_class); 2751 bus_size_t cmdsize, ctlsize; 2752 2753 if (pciide_chipen(sc, pa) == 0) 2754 return; 2755 printf("%s: bus-master DMA support present", 2756 sc->sc_wdcdev.sc_dev.dv_xname); 2757 pciide_mapreg_dma(sc, pa); 2758 printf("\n"); 2759 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2760 WDC_CAPABILITY_MODE; 2761 if (sc->sc_dma_ok) { 2762 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2763 sc->sc_wdcdev.irqack = pciide_irqack; 2764 if (rev > 0xd0) 2765 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2766 } 2767 2768 sc->sc_wdcdev.PIO_cap = 4; 2769 sc->sc_wdcdev.DMA_cap = 2; 2770 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2771 sc->sc_wdcdev.UDMA_cap = 2; 2772 sc->sc_wdcdev.set_modes = sis_setup_channel; 2773 2774 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2775 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2776 2777 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2778 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2779 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2780 2781 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2782 cp = &sc->pciide_channels[channel]; 2783 if (pciide_chansetup(sc, channel, interface) == 0) 2784 continue; 2785 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2786 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2787 printf("%s: %s channel ignored (disabled)\n", 2788 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2789 continue; 2790 } 2791 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2792 pciide_pci_intr); 2793 if (cp->hw_ok == 0) 2794 continue; 2795 if (pciide_chan_candisable(cp)) { 2796 if (channel == 0) 2797 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2798 else 2799 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2800 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2801 sis_ctr0); 2802 } 2803 pciide_map_compat_intr(pa, cp, channel, interface); 2804 if (cp->hw_ok == 0) 2805 continue; 2806 sis_setup_channel(&cp->wdc_channel); 2807 } 2808 } 2809 2810 void 2811 sis_setup_channel(chp) 2812 struct channel_softc *chp; 2813 { 2814 struct ata_drive_datas *drvp; 2815 int drive; 2816 u_int32_t sis_tim; 2817 u_int32_t idedma_ctl; 2818 struct pciide_channel *cp = (struct pciide_channel*)chp; 2819 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2820 2821 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2822 "channel %d 0x%x\n", chp->channel, 2823 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2824 DEBUG_PROBE); 2825 sis_tim = 0; 2826 idedma_ctl = 0; 2827 /* setup DMA if needed */ 2828 pciide_channel_dma_setup(cp); 2829 2830 for (drive = 0; drive < 2; drive++) { 2831 drvp = &chp->ch_drive[drive]; 2832 /* If no drive, skip */ 2833 if ((drvp->drive_flags & DRIVE) == 0) 2834 continue; 2835 /* add timing values, setup DMA if needed */ 2836 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2837 (drvp->drive_flags & DRIVE_UDMA) == 0) 2838 goto pio; 2839 2840 if (drvp->drive_flags & DRIVE_UDMA) { 2841 /* use Ultra/DMA */ 2842 drvp->drive_flags &= ~DRIVE_DMA; 2843 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2844 SIS_TIM_UDMA_TIME_OFF(drive); 2845 sis_tim |= SIS_TIM_UDMA_EN(drive); 2846 } else { 2847 /* 2848 * use Multiword DMA 2849 * Timings will be used for both PIO and DMA, 2850 * so adjust DMA mode if needed 2851 */ 2852 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2853 drvp->PIO_mode = drvp->DMA_mode + 2; 2854 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2855 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2856 drvp->PIO_mode - 2 : 0; 2857 if (drvp->DMA_mode == 0) 2858 drvp->PIO_mode = 0; 2859 } 2860 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2861 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2862 SIS_TIM_ACT_OFF(drive); 2863 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2864 SIS_TIM_REC_OFF(drive); 2865 } 2866 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2867 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2868 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2869 if (idedma_ctl != 0) { 2870 /* Add software bits in status register */ 2871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2872 IDEDMA_CTL, idedma_ctl); 2873 } 2874 pciide_print_modes(cp); 2875 } 2876 2877 void 2878 acer_chip_map(sc, pa) 2879 struct pciide_softc *sc; 2880 struct pci_attach_args *pa; 2881 { 2882 struct pciide_channel *cp; 2883 int channel; 2884 pcireg_t cr, interface; 2885 bus_size_t cmdsize, ctlsize; 2886 pcireg_t rev = PCI_REVISION(pa->pa_class); 2887 2888 if (pciide_chipen(sc, pa) == 0) 2889 return; 2890 printf("%s: bus-master DMA support present", 2891 sc->sc_wdcdev.sc_dev.dv_xname); 2892 pciide_mapreg_dma(sc, pa); 2893 printf("\n"); 2894 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2895 WDC_CAPABILITY_MODE; 2896 if (sc->sc_dma_ok) { 2897 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2898 if (rev >= 0x20) 2899 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2900 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2901 sc->sc_wdcdev.irqack = pciide_irqack; 2902 } 2903 2904 sc->sc_wdcdev.PIO_cap = 4; 2905 sc->sc_wdcdev.DMA_cap = 2; 2906 sc->sc_wdcdev.UDMA_cap = 2; 2907 sc->sc_wdcdev.set_modes = acer_setup_channel; 2908 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2909 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2910 2911 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2912 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2913 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2914 2915 /* Enable "microsoft register bits" R/W. */ 2916 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2917 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2918 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2919 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2920 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2921 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2922 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2923 ~ACER_CHANSTATUSREGS_RO); 2924 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2925 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2926 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2927 /* Don't use cr, re-read the real register content instead */ 2928 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2929 PCI_CLASS_REG)); 2930 2931 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2932 cp = &sc->pciide_channels[channel]; 2933 if (pciide_chansetup(sc, channel, interface) == 0) 2934 continue; 2935 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2936 printf("%s: %s channel ignored (disabled)\n", 2937 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2938 continue; 2939 } 2940 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2941 acer_pci_intr); 2942 if (cp->hw_ok == 0) 2943 continue; 2944 if (pciide_chan_candisable(cp)) { 2945 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2946 pci_conf_write(sc->sc_pc, sc->sc_tag, 2947 PCI_CLASS_REG, cr); 2948 } 2949 pciide_map_compat_intr(pa, cp, channel, interface); 2950 acer_setup_channel(&cp->wdc_channel); 2951 } 2952 } 2953 2954 void 2955 acer_setup_channel(chp) 2956 struct channel_softc *chp; 2957 { 2958 struct ata_drive_datas *drvp; 2959 int drive; 2960 u_int32_t acer_fifo_udma; 2961 u_int32_t idedma_ctl; 2962 struct pciide_channel *cp = (struct pciide_channel*)chp; 2963 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2964 2965 idedma_ctl = 0; 2966 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2967 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2968 acer_fifo_udma), DEBUG_PROBE); 2969 /* setup DMA if needed */ 2970 pciide_channel_dma_setup(cp); 2971 2972 for (drive = 0; drive < 2; drive++) { 2973 drvp = &chp->ch_drive[drive]; 2974 /* If no drive, skip */ 2975 if ((drvp->drive_flags & DRIVE) == 0) 2976 continue; 2977 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2978 "channel %d drive %d 0x%x\n", chp->channel, drive, 2979 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2980 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2981 /* clear FIFO/DMA mode */ 2982 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2983 ACER_UDMA_EN(chp->channel, drive) | 2984 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2985 2986 /* add timing values, setup DMA if needed */ 2987 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2988 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2989 acer_fifo_udma |= 2990 ACER_FTH_OPL(chp->channel, drive, 0x1); 2991 goto pio; 2992 } 2993 2994 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2995 if (drvp->drive_flags & DRIVE_UDMA) { 2996 /* use Ultra/DMA */ 2997 drvp->drive_flags &= ~DRIVE_DMA; 2998 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2999 acer_fifo_udma |= 3000 ACER_UDMA_TIM(chp->channel, drive, 3001 acer_udma[drvp->UDMA_mode]); 3002 } else { 3003 /* 3004 * use Multiword DMA 3005 * Timings will be used for both PIO and DMA, 3006 * so adjust DMA mode if needed 3007 */ 3008 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3009 drvp->PIO_mode = drvp->DMA_mode + 2; 3010 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3011 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3012 drvp->PIO_mode - 2 : 0; 3013 if (drvp->DMA_mode == 0) 3014 drvp->PIO_mode = 0; 3015 } 3016 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3017 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3018 ACER_IDETIM(chp->channel, drive), 3019 acer_pio[drvp->PIO_mode]); 3020 } 3021 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3022 acer_fifo_udma), DEBUG_PROBE); 3023 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3024 if (idedma_ctl != 0) { 3025 /* Add software bits in status register */ 3026 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3027 IDEDMA_CTL, idedma_ctl); 3028 } 3029 pciide_print_modes(cp); 3030 } 3031 3032 int 3033 acer_pci_intr(arg) 3034 void *arg; 3035 { 3036 struct pciide_softc *sc = arg; 3037 struct pciide_channel *cp; 3038 struct channel_softc *wdc_cp; 3039 int i, rv, crv; 3040 u_int32_t chids; 3041 3042 rv = 0; 3043 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3044 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3045 cp = &sc->pciide_channels[i]; 3046 wdc_cp = &cp->wdc_channel; 3047 /* If a compat channel skip. */ 3048 if (cp->compat) 3049 continue; 3050 if (chids & ACER_CHIDS_INT(i)) { 3051 crv = wdcintr(wdc_cp); 3052 if (crv == 0) 3053 printf("%s:%d: bogus intr\n", 3054 sc->sc_wdcdev.sc_dev.dv_xname, i); 3055 else 3056 rv = 1; 3057 } 3058 } 3059 return rv; 3060 } 3061 3062 void 3063 hpt_chip_map(sc, pa) 3064 struct pciide_softc *sc; 3065 struct pci_attach_args *pa; 3066 { 3067 struct pciide_channel *cp; 3068 int i, compatchan, revision; 3069 pcireg_t interface; 3070 bus_size_t cmdsize, ctlsize; 3071 3072 if (pciide_chipen(sc, pa) == 0) 3073 return; 3074 revision = PCI_REVISION(pa->pa_class); 3075 printf(": Triones/Highpoint "); 3076 if (revision == HPT370_REV) 3077 printf("HPT370 IDE Controller\n"); 3078 else 3079 printf("HPT366 IDE Controller\n"); 3080 3081 /* 3082 * when the chip is in native mode it identifies itself as a 3083 * 'misc mass storage'. Fake interface in this case. 3084 */ 3085 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3086 interface = PCI_INTERFACE(pa->pa_class); 3087 } else { 3088 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3089 PCIIDE_INTERFACE_PCI(0); 3090 if (revision == HPT370_REV) 3091 interface |= PCIIDE_INTERFACE_PCI(1); 3092 } 3093 3094 printf("%s: bus-master DMA support present", 3095 sc->sc_wdcdev.sc_dev.dv_xname); 3096 pciide_mapreg_dma(sc, pa); 3097 printf("\n"); 3098 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3099 WDC_CAPABILITY_MODE; 3100 if (sc->sc_dma_ok) { 3101 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3102 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3103 sc->sc_wdcdev.irqack = pciide_irqack; 3104 } 3105 sc->sc_wdcdev.PIO_cap = 4; 3106 sc->sc_wdcdev.DMA_cap = 2; 3107 3108 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3109 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3110 if (revision == HPT366_REV) { 3111 sc->sc_wdcdev.UDMA_cap = 4; 3112 /* 3113 * The 366 has 2 PCI IDE functions, one for primary and one 3114 * for secondary. So we need to call pciide_mapregs_compat() 3115 * with the real channel 3116 */ 3117 if (pa->pa_function == 0) { 3118 compatchan = 0; 3119 } else if (pa->pa_function == 1) { 3120 compatchan = 1; 3121 } else { 3122 printf("%s: unexpected PCI function %d\n", 3123 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3124 return; 3125 } 3126 sc->sc_wdcdev.nchannels = 1; 3127 } else { 3128 sc->sc_wdcdev.nchannels = 2; 3129 sc->sc_wdcdev.UDMA_cap = 5; 3130 } 3131 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3132 cp = &sc->pciide_channels[i]; 3133 if (sc->sc_wdcdev.nchannels > 1) { 3134 compatchan = i; 3135 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3136 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3137 printf("%s: %s channel ignored (disabled)\n", 3138 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3139 continue; 3140 } 3141 } 3142 if (pciide_chansetup(sc, i, interface) == 0) 3143 continue; 3144 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3145 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3146 &ctlsize, hpt_pci_intr); 3147 } else { 3148 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3149 &cmdsize, &ctlsize); 3150 } 3151 if (cp->hw_ok == 0) 3152 return; 3153 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3154 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3155 wdcattach(&cp->wdc_channel); 3156 hpt_setup_channel(&cp->wdc_channel); 3157 } 3158 if (revision == HPT370_REV) { 3159 /* 3160 * HPT370_REV has a bit to disable interrupts, make sure 3161 * to clear it 3162 */ 3163 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3164 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3165 ~HPT_CSEL_IRQDIS); 3166 } 3167 return; 3168 } 3169 3170 void 3171 hpt_setup_channel(chp) 3172 struct channel_softc *chp; 3173 { 3174 struct ata_drive_datas *drvp; 3175 int drive; 3176 int cable; 3177 u_int32_t before, after; 3178 u_int32_t idedma_ctl; 3179 struct pciide_channel *cp = (struct pciide_channel*)chp; 3180 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3181 3182 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3183 3184 /* setup DMA if needed */ 3185 pciide_channel_dma_setup(cp); 3186 3187 idedma_ctl = 0; 3188 3189 /* Per drive settings */ 3190 for (drive = 0; drive < 2; drive++) { 3191 drvp = &chp->ch_drive[drive]; 3192 /* If no drive, skip */ 3193 if ((drvp->drive_flags & DRIVE) == 0) 3194 continue; 3195 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3196 HPT_IDETIM(chp->channel, drive)); 3197 3198 /* add timing values, setup DMA if needed */ 3199 if (drvp->drive_flags & DRIVE_UDMA) { 3200 /* use Ultra/DMA */ 3201 drvp->drive_flags &= ~DRIVE_DMA; 3202 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3203 drvp->UDMA_mode > 2) 3204 drvp->UDMA_mode = 2; 3205 after = (sc->sc_wdcdev.nchannels == 2) ? 3206 hpt370_udma[drvp->UDMA_mode] : 3207 hpt366_udma[drvp->UDMA_mode]; 3208 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3209 } else if (drvp->drive_flags & DRIVE_DMA) { 3210 /* 3211 * use Multiword DMA. 3212 * Timings will be used for both PIO and DMA, so adjust 3213 * DMA mode if needed 3214 */ 3215 if (drvp->PIO_mode >= 3 && 3216 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3217 drvp->DMA_mode = drvp->PIO_mode - 2; 3218 } 3219 after = (sc->sc_wdcdev.nchannels == 2) ? 3220 hpt370_dma[drvp->DMA_mode] : 3221 hpt366_dma[drvp->DMA_mode]; 3222 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3223 } else { 3224 /* PIO only */ 3225 after = (sc->sc_wdcdev.nchannels == 2) ? 3226 hpt370_pio[drvp->PIO_mode] : 3227 hpt366_pio[drvp->PIO_mode]; 3228 } 3229 pci_conf_write(sc->sc_pc, sc->sc_tag, 3230 HPT_IDETIM(chp->channel, drive), after); 3231 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3232 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3233 after, before), DEBUG_PROBE); 3234 } 3235 if (idedma_ctl != 0) { 3236 /* Add software bits in status register */ 3237 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3238 IDEDMA_CTL, idedma_ctl); 3239 } 3240 pciide_print_modes(cp); 3241 } 3242 3243 int 3244 hpt_pci_intr(arg) 3245 void *arg; 3246 { 3247 struct pciide_softc *sc = arg; 3248 struct pciide_channel *cp; 3249 struct channel_softc *wdc_cp; 3250 int rv = 0; 3251 int dmastat, i, crv; 3252 3253 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3254 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3255 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3256 if((dmastat & IDEDMA_CTL_INTR) == 0) 3257 continue; 3258 cp = &sc->pciide_channels[i]; 3259 wdc_cp = &cp->wdc_channel; 3260 crv = wdcintr(wdc_cp); 3261 if (crv == 0) { 3262 printf("%s:%d: bogus intr\n", 3263 sc->sc_wdcdev.sc_dev.dv_xname, i); 3264 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3265 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3266 } else 3267 rv = 1; 3268 } 3269 return rv; 3270 } 3271 3272 3273 /* Macros to test product */ 3274 #define PDC_IS_262(sc) \ 3275 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3276 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3277 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3278 #define PDC_IS_265(sc) \ 3279 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3280 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3281 3282 void 3283 pdc202xx_chip_map(sc, pa) 3284 struct pciide_softc *sc; 3285 struct pci_attach_args *pa; 3286 { 3287 struct pciide_channel *cp; 3288 int channel; 3289 pcireg_t interface, st, mode; 3290 bus_size_t cmdsize, ctlsize; 3291 3292 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3293 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3294 DEBUG_PROBE); 3295 if (pciide_chipen(sc, pa) == 0) 3296 return; 3297 3298 /* turn off RAID mode */ 3299 st &= ~PDC2xx_STATE_IDERAID; 3300 3301 /* 3302 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3303 * mode. We have to fake interface 3304 */ 3305 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3306 if (st & PDC2xx_STATE_NATIVE) 3307 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3308 3309 printf("%s: bus-master DMA support present", 3310 sc->sc_wdcdev.sc_dev.dv_xname); 3311 pciide_mapreg_dma(sc, pa); 3312 printf("\n"); 3313 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3314 WDC_CAPABILITY_MODE; 3315 if (sc->sc_dma_ok) { 3316 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3318 sc->sc_wdcdev.irqack = pciide_irqack; 3319 } 3320 sc->sc_wdcdev.PIO_cap = 4; 3321 sc->sc_wdcdev.DMA_cap = 2; 3322 if (PDC_IS_265(sc)) 3323 sc->sc_wdcdev.UDMA_cap = 5; 3324 else if (PDC_IS_262(sc)) 3325 sc->sc_wdcdev.UDMA_cap = 4; 3326 else 3327 sc->sc_wdcdev.UDMA_cap = 2; 3328 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3329 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3330 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3331 3332 /* setup failsafe defaults */ 3333 mode = 0; 3334 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3335 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3336 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3337 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3338 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3339 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3340 "initial timings 0x%x, now 0x%x\n", channel, 3341 pci_conf_read(sc->sc_pc, sc->sc_tag, 3342 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3343 DEBUG_PROBE); 3344 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3345 mode | PDC2xx_TIM_IORDYp); 3346 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3347 "initial timings 0x%x, now 0x%x\n", channel, 3348 pci_conf_read(sc->sc_pc, sc->sc_tag, 3349 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3350 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3351 mode); 3352 } 3353 3354 mode = PDC2xx_SCR_DMA; 3355 if (PDC_IS_262(sc)) { 3356 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3357 } else { 3358 /* the BIOS set it up this way */ 3359 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3360 } 3361 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3362 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3363 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3364 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3365 DEBUG_PROBE); 3366 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3367 3368 /* controller initial state register is OK even without BIOS */ 3369 /* Set DMA mode to IDE DMA compatibility */ 3370 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3371 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3372 DEBUG_PROBE); 3373 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3374 mode | 0x1); 3375 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3376 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3377 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3378 mode | 0x1); 3379 3380 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3381 cp = &sc->pciide_channels[channel]; 3382 if (pciide_chansetup(sc, channel, interface) == 0) 3383 continue; 3384 if ((st & (PDC_IS_262(sc) ? 3385 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3386 printf("%s: %s channel ignored (disabled)\n", 3387 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3388 continue; 3389 } 3390 if (PDC_IS_265(sc)) 3391 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3392 pdc20265_pci_intr); 3393 else 3394 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3395 pdc202xx_pci_intr); 3396 if (cp->hw_ok == 0) 3397 continue; 3398 if (pciide_chan_candisable(cp)) 3399 st &= ~(PDC_IS_262(sc) ? 3400 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3401 pciide_map_compat_intr(pa, cp, channel, interface); 3402 pdc202xx_setup_channel(&cp->wdc_channel); 3403 } 3404 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3405 DEBUG_PROBE); 3406 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3407 return; 3408 } 3409 3410 void 3411 pdc202xx_setup_channel(chp) 3412 struct channel_softc *chp; 3413 { 3414 struct ata_drive_datas *drvp; 3415 int drive; 3416 pcireg_t mode, st; 3417 u_int32_t idedma_ctl, scr, atapi; 3418 struct pciide_channel *cp = (struct pciide_channel*)chp; 3419 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3420 int channel = chp->channel; 3421 3422 /* setup DMA if needed */ 3423 pciide_channel_dma_setup(cp); 3424 3425 idedma_ctl = 0; 3426 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3427 sc->sc_wdcdev.sc_dev.dv_xname, 3428 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3429 DEBUG_PROBE); 3430 3431 /* Per channel settings */ 3432 if (PDC_IS_262(sc)) { 3433 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3434 PDC262_U66); 3435 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3436 /* Trimm UDMA mode */ 3437 if ((st & PDC262_STATE_80P(channel)) != 0 || 3438 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3439 chp->ch_drive[0].UDMA_mode <= 2) || 3440 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3441 chp->ch_drive[1].UDMA_mode <= 2)) { 3442 if (chp->ch_drive[0].UDMA_mode > 2) 3443 chp->ch_drive[0].UDMA_mode = 2; 3444 if (chp->ch_drive[1].UDMA_mode > 2) 3445 chp->ch_drive[1].UDMA_mode = 2; 3446 } 3447 /* Set U66 if needed */ 3448 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3449 chp->ch_drive[0].UDMA_mode > 2) || 3450 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3451 chp->ch_drive[1].UDMA_mode > 2)) 3452 scr |= PDC262_U66_EN(channel); 3453 else 3454 scr &= ~PDC262_U66_EN(channel); 3455 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3456 PDC262_U66, scr); 3457 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3458 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3459 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3460 PDC262_ATAPI(channel))), DEBUG_PROBE); 3461 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3462 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3463 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3464 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3465 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3466 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3467 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3468 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3469 atapi = 0; 3470 else 3471 atapi = PDC262_ATAPI_UDMA; 3472 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3473 PDC262_ATAPI(channel), atapi); 3474 } 3475 } 3476 for (drive = 0; drive < 2; drive++) { 3477 drvp = &chp->ch_drive[drive]; 3478 /* If no drive, skip */ 3479 if ((drvp->drive_flags & DRIVE) == 0) 3480 continue; 3481 mode = 0; 3482 if (drvp->drive_flags & DRIVE_UDMA) { 3483 /* use Ultra/DMA */ 3484 drvp->drive_flags &= ~DRIVE_DMA; 3485 mode = PDC2xx_TIM_SET_MB(mode, 3486 pdc2xx_udma_mb[drvp->UDMA_mode]); 3487 mode = PDC2xx_TIM_SET_MC(mode, 3488 pdc2xx_udma_mc[drvp->UDMA_mode]); 3489 drvp->drive_flags &= ~DRIVE_DMA; 3490 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3491 } else if (drvp->drive_flags & DRIVE_DMA) { 3492 mode = PDC2xx_TIM_SET_MB(mode, 3493 pdc2xx_dma_mb[drvp->DMA_mode]); 3494 mode = PDC2xx_TIM_SET_MC(mode, 3495 pdc2xx_dma_mc[drvp->DMA_mode]); 3496 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3497 } else { 3498 mode = PDC2xx_TIM_SET_MB(mode, 3499 pdc2xx_dma_mb[0]); 3500 mode = PDC2xx_TIM_SET_MC(mode, 3501 pdc2xx_dma_mc[0]); 3502 } 3503 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3504 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3505 if (drvp->drive_flags & DRIVE_ATA) 3506 mode |= PDC2xx_TIM_PRE; 3507 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3508 if (drvp->PIO_mode >= 3) { 3509 mode |= PDC2xx_TIM_IORDY; 3510 if (drive == 0) 3511 mode |= PDC2xx_TIM_IORDYp; 3512 } 3513 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3514 "timings 0x%x\n", 3515 sc->sc_wdcdev.sc_dev.dv_xname, 3516 chp->channel, drive, mode), DEBUG_PROBE); 3517 pci_conf_write(sc->sc_pc, sc->sc_tag, 3518 PDC2xx_TIM(chp->channel, drive), mode); 3519 } 3520 if (idedma_ctl != 0) { 3521 /* Add software bits in status register */ 3522 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3523 IDEDMA_CTL, idedma_ctl); 3524 } 3525 pciide_print_modes(cp); 3526 } 3527 3528 int 3529 pdc202xx_pci_intr(arg) 3530 void *arg; 3531 { 3532 struct pciide_softc *sc = arg; 3533 struct pciide_channel *cp; 3534 struct channel_softc *wdc_cp; 3535 int i, rv, crv; 3536 u_int32_t scr; 3537 3538 rv = 0; 3539 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3540 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3541 cp = &sc->pciide_channels[i]; 3542 wdc_cp = &cp->wdc_channel; 3543 /* If a compat channel skip. */ 3544 if (cp->compat) 3545 continue; 3546 if (scr & PDC2xx_SCR_INT(i)) { 3547 crv = wdcintr(wdc_cp); 3548 if (crv == 0) 3549 printf("%s:%d: bogus intr (reg 0x%x)\n", 3550 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3551 else 3552 rv = 1; 3553 } 3554 } 3555 return rv; 3556 } 3557 3558 int 3559 pdc20265_pci_intr(arg) 3560 void *arg; 3561 { 3562 struct pciide_softc *sc = arg; 3563 struct pciide_channel *cp; 3564 struct channel_softc *wdc_cp; 3565 int i, rv, crv; 3566 u_int32_t dmastat; 3567 3568 rv = 0; 3569 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3570 cp = &sc->pciide_channels[i]; 3571 wdc_cp = &cp->wdc_channel; 3572 /* If a compat channel skip. */ 3573 if (cp->compat) 3574 continue; 3575 /* 3576 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3577 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3578 * So use it instead (requires 2 reg reads instead of 1, 3579 * but we can't do it another way). 3580 */ 3581 dmastat = bus_space_read_1(sc->sc_dma_iot, 3582 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3583 if((dmastat & IDEDMA_CTL_INTR) == 0) 3584 continue; 3585 crv = wdcintr(wdc_cp); 3586 if (crv == 0) 3587 printf("%s:%d: bogus intr\n", 3588 sc->sc_wdcdev.sc_dev.dv_xname, i); 3589 else 3590 rv = 1; 3591 } 3592 return rv; 3593 } 3594 3595 void 3596 opti_chip_map(sc, pa) 3597 struct pciide_softc *sc; 3598 struct pci_attach_args *pa; 3599 { 3600 struct pciide_channel *cp; 3601 bus_size_t cmdsize, ctlsize; 3602 pcireg_t interface; 3603 u_int8_t init_ctrl; 3604 int channel; 3605 3606 if (pciide_chipen(sc, pa) == 0) 3607 return; 3608 printf("%s: bus-master DMA support present", 3609 sc->sc_wdcdev.sc_dev.dv_xname); 3610 3611 /* 3612 * XXXSCW: 3613 * There seem to be a couple of buggy revisions/implementations 3614 * of the OPTi pciide chipset. This kludge seems to fix one of 3615 * the reported problems (PR/11644) but still fails for the 3616 * other (PR/13151), although the latter may be due to other 3617 * issues too... 3618 */ 3619 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3620 printf(" but disabled due to chip rev. <= 0x12"); 3621 sc->sc_dma_ok = 0; 3622 sc->sc_wdcdev.cap = 0; 3623 } else { 3624 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3625 pciide_mapreg_dma(sc, pa); 3626 } 3627 printf("\n"); 3628 3629 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3630 sc->sc_wdcdev.PIO_cap = 4; 3631 if (sc->sc_dma_ok) { 3632 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3633 sc->sc_wdcdev.irqack = pciide_irqack; 3634 sc->sc_wdcdev.DMA_cap = 2; 3635 } 3636 sc->sc_wdcdev.set_modes = opti_setup_channel; 3637 3638 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3639 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3640 3641 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3642 OPTI_REG_INIT_CONTROL); 3643 3644 interface = PCI_INTERFACE(pa->pa_class); 3645 3646 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3647 cp = &sc->pciide_channels[channel]; 3648 if (pciide_chansetup(sc, channel, interface) == 0) 3649 continue; 3650 if (channel == 1 && 3651 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3652 printf("%s: %s channel ignored (disabled)\n", 3653 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3654 continue; 3655 } 3656 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3657 pciide_pci_intr); 3658 if (cp->hw_ok == 0) 3659 continue; 3660 pciide_map_compat_intr(pa, cp, channel, interface); 3661 if (cp->hw_ok == 0) 3662 continue; 3663 opti_setup_channel(&cp->wdc_channel); 3664 } 3665 } 3666 3667 void 3668 opti_setup_channel(chp) 3669 struct channel_softc *chp; 3670 { 3671 struct ata_drive_datas *drvp; 3672 struct pciide_channel *cp = (struct pciide_channel*)chp; 3673 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3674 int drive, spd; 3675 int mode[2]; 3676 u_int8_t rv, mr; 3677 3678 /* 3679 * The `Delay' and `Address Setup Time' fields of the 3680 * Miscellaneous Register are always zero initially. 3681 */ 3682 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3683 mr &= ~(OPTI_MISC_DELAY_MASK | 3684 OPTI_MISC_ADDR_SETUP_MASK | 3685 OPTI_MISC_INDEX_MASK); 3686 3687 /* Prime the control register before setting timing values */ 3688 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3689 3690 /* Determine the clockrate of the PCIbus the chip is attached to */ 3691 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3692 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3693 3694 /* setup DMA if needed */ 3695 pciide_channel_dma_setup(cp); 3696 3697 for (drive = 0; drive < 2; drive++) { 3698 drvp = &chp->ch_drive[drive]; 3699 /* If no drive, skip */ 3700 if ((drvp->drive_flags & DRIVE) == 0) { 3701 mode[drive] = -1; 3702 continue; 3703 } 3704 3705 if ((drvp->drive_flags & DRIVE_DMA)) { 3706 /* 3707 * Timings will be used for both PIO and DMA, 3708 * so adjust DMA mode if needed 3709 */ 3710 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3711 drvp->PIO_mode = drvp->DMA_mode + 2; 3712 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3713 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3714 drvp->PIO_mode - 2 : 0; 3715 if (drvp->DMA_mode == 0) 3716 drvp->PIO_mode = 0; 3717 3718 mode[drive] = drvp->DMA_mode + 5; 3719 } else 3720 mode[drive] = drvp->PIO_mode; 3721 3722 if (drive && mode[0] >= 0 && 3723 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3724 /* 3725 * Can't have two drives using different values 3726 * for `Address Setup Time'. 3727 * Slow down the faster drive to compensate. 3728 */ 3729 int d = (opti_tim_as[spd][mode[0]] > 3730 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3731 3732 mode[d] = mode[1-d]; 3733 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3734 chp->ch_drive[d].DMA_mode = 0; 3735 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3736 } 3737 } 3738 3739 for (drive = 0; drive < 2; drive++) { 3740 int m; 3741 if ((m = mode[drive]) < 0) 3742 continue; 3743 3744 /* Set the Address Setup Time and select appropriate index */ 3745 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3746 rv |= OPTI_MISC_INDEX(drive); 3747 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3748 3749 /* Set the pulse width and recovery timing parameters */ 3750 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3751 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3752 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3753 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3754 3755 /* Set the Enhanced Mode register appropriately */ 3756 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3757 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3758 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3759 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3760 } 3761 3762 /* Finally, enable the timings */ 3763 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3764 3765 pciide_print_modes(cp); 3766 } 3767 3768 #define ACARD_IS_850(sc) \ 3769 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3770 3771 void 3772 acard_chip_map(sc, pa) 3773 struct pciide_softc *sc; 3774 struct pci_attach_args *pa; 3775 { 3776 struct pciide_channel *cp; 3777 int i; 3778 pcireg_t interface; 3779 bus_size_t cmdsize, ctlsize; 3780 3781 if (pciide_chipen(sc, pa) == 0) 3782 return; 3783 3784 /* 3785 * when the chip is in native mode it identifies itself as a 3786 * 'misc mass storage'. Fake interface in this case. 3787 */ 3788 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3789 interface = PCI_INTERFACE(pa->pa_class); 3790 } else { 3791 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3792 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3793 } 3794 3795 printf("%s: bus-master DMA support present", 3796 sc->sc_wdcdev.sc_dev.dv_xname); 3797 pciide_mapreg_dma(sc, pa); 3798 printf("\n"); 3799 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3800 WDC_CAPABILITY_MODE; 3801 3802 if (sc->sc_dma_ok) { 3803 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3804 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3805 sc->sc_wdcdev.irqack = pciide_irqack; 3806 } 3807 sc->sc_wdcdev.PIO_cap = 4; 3808 sc->sc_wdcdev.DMA_cap = 2; 3809 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3810 3811 sc->sc_wdcdev.set_modes = acard_setup_channel; 3812 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3813 sc->sc_wdcdev.nchannels = 2; 3814 3815 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3816 cp = &sc->pciide_channels[i]; 3817 if (pciide_chansetup(sc, i, interface) == 0) 3818 continue; 3819 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3820 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3821 &ctlsize, pciide_pci_intr); 3822 } else { 3823 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 3824 &cmdsize, &ctlsize); 3825 } 3826 if (cp->hw_ok == 0) 3827 return; 3828 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3829 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3830 wdcattach(&cp->wdc_channel); 3831 acard_setup_channel(&cp->wdc_channel); 3832 } 3833 if (!ACARD_IS_850(sc)) { 3834 u_int32_t reg; 3835 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3836 reg &= ~ATP860_CTRL_INT; 3837 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3838 } 3839 } 3840 3841 void 3842 acard_setup_channel(chp) 3843 struct channel_softc *chp; 3844 { 3845 struct ata_drive_datas *drvp; 3846 struct pciide_channel *cp = (struct pciide_channel*)chp; 3847 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3848 int channel = chp->channel; 3849 int drive; 3850 u_int32_t idetime, udma_mode; 3851 u_int32_t idedma_ctl; 3852 3853 /* setup DMA if needed */ 3854 pciide_channel_dma_setup(cp); 3855 3856 if (ACARD_IS_850(sc)) { 3857 idetime = 0; 3858 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3859 udma_mode &= ~ATP850_UDMA_MASK(channel); 3860 } else { 3861 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3862 idetime &= ~ATP860_SETTIME_MASK(channel); 3863 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3864 udma_mode &= ~ATP860_UDMA_MASK(channel); 3865 } 3866 3867 idedma_ctl = 0; 3868 3869 /* Per drive settings */ 3870 for (drive = 0; drive < 2; drive++) { 3871 drvp = &chp->ch_drive[drive]; 3872 /* If no drive, skip */ 3873 if ((drvp->drive_flags & DRIVE) == 0) 3874 continue; 3875 /* add timing values, setup DMA if needed */ 3876 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3877 (drvp->drive_flags & DRIVE_UDMA)) { 3878 /* use Ultra/DMA */ 3879 if (ACARD_IS_850(sc)) { 3880 idetime |= ATP850_SETTIME(drive, 3881 acard_act_udma[drvp->UDMA_mode], 3882 acard_rec_udma[drvp->UDMA_mode]); 3883 udma_mode |= ATP850_UDMA_MODE(channel, drive, 3884 acard_udma_conf[drvp->UDMA_mode]); 3885 } else { 3886 idetime |= ATP860_SETTIME(channel, drive, 3887 acard_act_udma[drvp->UDMA_mode], 3888 acard_rec_udma[drvp->UDMA_mode]); 3889 udma_mode |= ATP860_UDMA_MODE(channel, drive, 3890 acard_udma_conf[drvp->UDMA_mode]); 3891 } 3892 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3893 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 3894 (drvp->drive_flags & DRIVE_DMA)) { 3895 /* use Multiword DMA */ 3896 drvp->drive_flags &= ~DRIVE_UDMA; 3897 if (ACARD_IS_850(sc)) { 3898 idetime |= ATP850_SETTIME(drive, 3899 acard_act_dma[drvp->DMA_mode], 3900 acard_rec_dma[drvp->DMA_mode]); 3901 } else { 3902 idetime |= ATP860_SETTIME(channel, drive, 3903 acard_act_dma[drvp->DMA_mode], 3904 acard_rec_dma[drvp->DMA_mode]); 3905 } 3906 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3907 } else { 3908 /* PIO only */ 3909 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 3910 if (ACARD_IS_850(sc)) { 3911 idetime |= ATP850_SETTIME(drive, 3912 acard_act_pio[drvp->PIO_mode], 3913 acard_rec_pio[drvp->PIO_mode]); 3914 } else { 3915 idetime |= ATP860_SETTIME(channel, drive, 3916 acard_act_pio[drvp->PIO_mode], 3917 acard_rec_pio[drvp->PIO_mode]); 3918 } 3919 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 3920 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3921 | ATP8x0_CTRL_EN(channel)); 3922 } 3923 } 3924 3925 if (idedma_ctl != 0) { 3926 /* Add software bits in status register */ 3927 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3928 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 3929 } 3930 pciide_print_modes(cp); 3931 3932 if (ACARD_IS_850(sc)) { 3933 pci_conf_write(sc->sc_pc, sc->sc_tag, 3934 ATP850_IDETIME(channel), idetime); 3935 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 3936 } else { 3937 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 3938 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 3939 } 3940 } 3941 3942 int 3943 acard_pci_intr(arg) 3944 void *arg; 3945 { 3946 struct pciide_softc *sc = arg; 3947 struct pciide_channel *cp; 3948 struct channel_softc *wdc_cp; 3949 int rv = 0; 3950 int dmastat, i, crv; 3951 3952 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3953 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3954 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3955 if ((dmastat & IDEDMA_CTL_INTR) == 0) 3956 continue; 3957 cp = &sc->pciide_channels[i]; 3958 wdc_cp = &cp->wdc_channel; 3959 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 3960 (void)wdcintr(wdc_cp); 3961 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3962 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3963 continue; 3964 } 3965 crv = wdcintr(wdc_cp); 3966 if (crv == 0) 3967 printf("%s:%d: bogus intr\n", 3968 sc->sc_wdcdev.sc_dev.dv_xname, i); 3969 else if (crv == 1) 3970 rv = 1; 3971 else if (rv == 0) 3972 rv = crv; 3973 } 3974 return rv; 3975 } 3976
Indexes created Mon Sep 22 05:09:51 GMT 2025