pciide.c revision 1.122
1 /* $NetBSD: pciide.c,v 1.122 2001/07/19 16:36:16 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/pciide_acard_reg.h> 119 #include <dev/pci/cy82c693var.h> 120 121 #include "opt_pciide.h" 122 123 /* inlines for reading/writing 8-bit PCI registers */ 124 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 125 int)); 126 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 127 int, u_int8_t)); 128 129 static __inline u_int8_t 130 pciide_pci_read(pc, pa, reg) 131 pci_chipset_tag_t pc; 132 pcitag_t pa; 133 int reg; 134 { 135 136 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 137 ((reg & 0x03) * 8) & 0xff); 138 } 139 140 static __inline void 141 pciide_pci_write(pc, pa, reg, val) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 u_int8_t val; 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 156 157 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 void piix_setup_channel __P((struct channel_softc*)); 159 void piix3_4_setup_channel __P((struct channel_softc*)); 160 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 161 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 162 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 164 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void amd7x6_setup_channel __P((struct channel_softc*)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 void cmd646_9_irqack __P((struct channel_softc *)); 177 178 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cy693_setup_channel __P((struct channel_softc*)); 180 181 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void sis_setup_channel __P((struct channel_softc*)); 183 184 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void acer_setup_channel __P((struct channel_softc*)); 186 int acer_pci_intr __P((void *)); 187 188 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void pdc202xx_setup_channel __P((struct channel_softc*)); 190 int pdc202xx_pci_intr __P((void *)); 191 int pdc20265_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void acard_setup_channel __P((struct channel_softc*)); 202 int acard_pci_intr __P((void *)); 203 204 #ifdef PCIIDE_WINBOND_ENABLE 205 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 #endif 207 208 void pciide_channel_dma_setup __P((struct pciide_channel *)); 209 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 210 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 211 void pciide_dma_start __P((void*, int, int)); 212 int pciide_dma_finish __P((void*, int, int, int)); 213 void pciide_irqack __P((struct channel_softc *)); 214 void pciide_print_modes __P((struct pciide_channel *)); 215 216 struct pciide_product_desc { 217 u_int32_t ide_product; 218 int ide_flags; 219 const char *ide_name; 220 /* map and setup chip, probe drives */ 221 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 222 }; 223 224 /* Flags for ide_flags */ 225 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 226 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 227 228 /* Default product description for devices not known from this controller */ 229 const struct pciide_product_desc default_product_desc = { 230 0, 231 0, 232 "Generic PCI IDE controller", 233 default_chip_map, 234 }; 235 236 const struct pciide_product_desc pciide_intel_products[] = { 237 { PCI_PRODUCT_INTEL_82092AA, 238 0, 239 "Intel 82092AA IDE controller", 240 default_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82371FB_IDE, 243 0, 244 "Intel 82371FB IDE controller (PIIX)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82371SB_IDE, 248 0, 249 "Intel 82371SB IDE Interface (PIIX3)", 250 piix_chip_map, 251 }, 252 { PCI_PRODUCT_INTEL_82371AB_IDE, 253 0, 254 "Intel 82371AB IDE controller (PIIX4)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82440MX_IDE, 258 0, 259 "Intel 82440MX IDE controller", 260 piix_chip_map 261 }, 262 { PCI_PRODUCT_INTEL_82801AA_IDE, 263 0, 264 "Intel 82801AA IDE Controller (ICH)", 265 piix_chip_map, 266 }, 267 { PCI_PRODUCT_INTEL_82801AB_IDE, 268 0, 269 "Intel 82801AB IDE Controller (ICH0)", 270 piix_chip_map, 271 }, 272 { PCI_PRODUCT_INTEL_82801BA_IDE, 273 0, 274 "Intel 82801BA IDE Controller (ICH2)", 275 piix_chip_map, 276 }, 277 { PCI_PRODUCT_INTEL_82801BAM_IDE, 278 0, 279 "Intel 82801BAM IDE Controller (ICH2)", 280 piix_chip_map, 281 }, 282 { 0, 283 0, 284 NULL, 285 NULL 286 } 287 }; 288 289 const struct pciide_product_desc pciide_amd_products[] = { 290 { PCI_PRODUCT_AMD_PBC756_IDE, 291 0, 292 "Advanced Micro Devices AMD756 IDE Controller", 293 amd7x6_chip_map 294 }, 295 { PCI_PRODUCT_AMD_PBC766_IDE, 296 0, 297 "Advanced Micro Devices AMD766 IDE Controller", 298 amd7x6_chip_map 299 }, 300 { 0, 301 0, 302 NULL, 303 NULL 304 } 305 }; 306 307 const struct pciide_product_desc pciide_cmd_products[] = { 308 { PCI_PRODUCT_CMDTECH_640, 309 0, 310 "CMD Technology PCI0640", 311 cmd_chip_map 312 }, 313 { PCI_PRODUCT_CMDTECH_643, 314 0, 315 "CMD Technology PCI0643", 316 cmd0643_9_chip_map, 317 }, 318 { PCI_PRODUCT_CMDTECH_646, 319 0, 320 "CMD Technology PCI0646", 321 cmd0643_9_chip_map, 322 }, 323 { PCI_PRODUCT_CMDTECH_648, 324 IDE_PCI_CLASS_OVERRIDE, 325 "CMD Technology PCI0648", 326 cmd0643_9_chip_map, 327 }, 328 { PCI_PRODUCT_CMDTECH_649, 329 IDE_PCI_CLASS_OVERRIDE, 330 "CMD Technology PCI0649", 331 cmd0643_9_chip_map, 332 }, 333 { 0, 334 0, 335 NULL, 336 NULL 337 } 338 }; 339 340 const struct pciide_product_desc pciide_via_products[] = { 341 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 342 0, 343 NULL, 344 apollo_chip_map, 345 }, 346 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 347 0, 348 NULL, 349 apollo_chip_map, 350 }, 351 { 0, 352 0, 353 NULL, 354 NULL 355 } 356 }; 357 358 const struct pciide_product_desc pciide_cypress_products[] = { 359 { PCI_PRODUCT_CONTAQ_82C693, 360 IDE_16BIT_IOSPACE, 361 "Cypress 82C693 IDE Controller", 362 cy693_chip_map, 363 }, 364 { 0, 365 0, 366 NULL, 367 NULL 368 } 369 }; 370 371 const struct pciide_product_desc pciide_sis_products[] = { 372 { PCI_PRODUCT_SIS_5597_IDE, 373 0, 374 "Silicon Integrated System 5597/5598 IDE controller", 375 sis_chip_map, 376 }, 377 { 0, 378 0, 379 NULL, 380 NULL 381 } 382 }; 383 384 const struct pciide_product_desc pciide_acer_products[] = { 385 { PCI_PRODUCT_ALI_M5229, 386 0, 387 "Acer Labs M5229 UDMA IDE Controller", 388 acer_chip_map, 389 }, 390 { 0, 391 0, 392 NULL, 393 NULL 394 } 395 }; 396 397 const struct pciide_product_desc pciide_promise_products[] = { 398 { PCI_PRODUCT_PROMISE_ULTRA33, 399 IDE_PCI_CLASS_OVERRIDE, 400 "Promise Ultra33/ATA Bus Master IDE Accelerator", 401 pdc202xx_chip_map, 402 }, 403 { PCI_PRODUCT_PROMISE_ULTRA66, 404 IDE_PCI_CLASS_OVERRIDE, 405 "Promise Ultra66/ATA Bus Master IDE Accelerator", 406 pdc202xx_chip_map, 407 }, 408 { PCI_PRODUCT_PROMISE_ULTRA100, 409 IDE_PCI_CLASS_OVERRIDE, 410 "Promise Ultra100/ATA Bus Master IDE Accelerator", 411 pdc202xx_chip_map, 412 }, 413 { PCI_PRODUCT_PROMISE_ULTRA100X, 414 IDE_PCI_CLASS_OVERRIDE, 415 "Promise Ultra100/ATA Bus Master IDE Accelerator", 416 pdc202xx_chip_map, 417 }, 418 { 0, 419 0, 420 NULL, 421 NULL 422 } 423 }; 424 425 const struct pciide_product_desc pciide_opti_products[] = { 426 { PCI_PRODUCT_OPTI_82C621, 427 0, 428 "OPTi 82c621 PCI IDE controller", 429 opti_chip_map, 430 }, 431 { PCI_PRODUCT_OPTI_82C568, 432 0, 433 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 434 opti_chip_map, 435 }, 436 { PCI_PRODUCT_OPTI_82D568, 437 0, 438 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 439 opti_chip_map, 440 }, 441 { 0, 442 0, 443 NULL, 444 NULL 445 } 446 }; 447 448 const struct pciide_product_desc pciide_triones_products[] = { 449 { PCI_PRODUCT_TRIONES_HPT366, 450 IDE_PCI_CLASS_OVERRIDE, 451 NULL, 452 hpt_chip_map, 453 }, 454 { 0, 455 0, 456 NULL, 457 NULL 458 } 459 }; 460 461 const struct pciide_product_desc pciide_acard_products[] = { 462 { PCI_PRODUCT_ACARD_ATP850U, 463 IDE_PCI_CLASS_OVERRIDE, 464 "Acard ATP850U Ultra33 IDE Controller", 465 acard_chip_map, 466 }, 467 { PCI_PRODUCT_ACARD_ATP860, 468 IDE_PCI_CLASS_OVERRIDE, 469 "Acard ATP860 Ultra66 IDE Controller", 470 acard_chip_map, 471 }, 472 { PCI_PRODUCT_ACARD_ATP860A, 473 IDE_PCI_CLASS_OVERRIDE, 474 "Acard ATP860-A Ultra66 IDE Controller", 475 acard_chip_map, 476 }, 477 { 0, 478 0, 479 NULL, 480 NULL 481 } 482 }; 483 484 #ifdef PCIIDE_SERVERWORKS_ENABLE 485 const struct pciide_product_desc pciide_serverworks_products[] = { 486 { PCI_PRODUCT_SERVERWORKS_IDE, 487 0, 488 "ServerWorks ROSB4 IDE Controller", 489 piix_chip_map, 490 }, 491 { 0, 492 0, 493 NULL, 494 } 495 }; 496 #endif 497 498 #ifdef PCIIDE_WINBOND_ENABLE 499 const struct pciide_product_desc pciide_winbond_products[] = { 500 { PCI_PRODUCT_WINBOND_W83C553F_1, 501 0, 502 "Winbond W83C553F IDE controller", 503 winbond_chip_map, 504 }, 505 { 0, 506 0, 507 NULL, 508 } 509 }; 510 #endif 511 512 struct pciide_vendor_desc { 513 u_int32_t ide_vendor; 514 const struct pciide_product_desc *ide_products; 515 }; 516 517 const struct pciide_vendor_desc pciide_vendors[] = { 518 { PCI_VENDOR_INTEL, pciide_intel_products }, 519 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 520 { PCI_VENDOR_VIATECH, pciide_via_products }, 521 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 522 { PCI_VENDOR_SIS, pciide_sis_products }, 523 { PCI_VENDOR_ALI, pciide_acer_products }, 524 { PCI_VENDOR_PROMISE, pciide_promise_products }, 525 { PCI_VENDOR_AMD, pciide_amd_products }, 526 { PCI_VENDOR_OPTI, pciide_opti_products }, 527 { PCI_VENDOR_TRIONES, pciide_triones_products }, 528 #ifdef PCIIDE_ACARD_ENABLE 529 { PCI_VENDOR_ACARD, pciide_acard_products }, 530 #endif 531 #ifdef PCIIDE_SERVERWORKS_ENABLE 532 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 533 #endif 534 #ifdef PCIIDE_WINBOND_ENABLE 535 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 536 #endif 537 { 0, NULL } 538 }; 539 540 /* options passed via the 'flags' config keyword */ 541 #define PCIIDE_OPTIONS_DMA 0x01 542 543 int pciide_match __P((struct device *, struct cfdata *, void *)); 544 void pciide_attach __P((struct device *, struct device *, void *)); 545 546 struct cfattach pciide_ca = { 547 sizeof(struct pciide_softc), pciide_match, pciide_attach 548 }; 549 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 550 int pciide_mapregs_compat __P(( struct pci_attach_args *, 551 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 552 int pciide_mapregs_native __P((struct pci_attach_args *, 553 struct pciide_channel *, bus_size_t *, bus_size_t *, 554 int (*pci_intr) __P((void *)))); 555 void pciide_mapreg_dma __P((struct pciide_softc *, 556 struct pci_attach_args *)); 557 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 558 void pciide_mapchan __P((struct pci_attach_args *, 559 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 560 int (*pci_intr) __P((void *)))); 561 int pciide_chan_candisable __P((struct pciide_channel *)); 562 void pciide_map_compat_intr __P(( struct pci_attach_args *, 563 struct pciide_channel *, int, int)); 564 int pciide_print __P((void *, const char *pnp)); 565 int pciide_compat_intr __P((void *)); 566 int pciide_pci_intr __P((void *)); 567 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 568 569 const struct pciide_product_desc * 570 pciide_lookup_product(id) 571 u_int32_t id; 572 { 573 const struct pciide_product_desc *pp; 574 const struct pciide_vendor_desc *vp; 575 576 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 577 if (PCI_VENDOR(id) == vp->ide_vendor) 578 break; 579 580 if ((pp = vp->ide_products) == NULL) 581 return NULL; 582 583 for (; pp->chip_map != NULL; pp++) 584 if (PCI_PRODUCT(id) == pp->ide_product) 585 break; 586 587 if (pp->chip_map == NULL) 588 return NULL; 589 return pp; 590 } 591 592 int 593 pciide_match(parent, match, aux) 594 struct device *parent; 595 struct cfdata *match; 596 void *aux; 597 { 598 struct pci_attach_args *pa = aux; 599 const struct pciide_product_desc *pp; 600 601 /* 602 * Check the ID register to see that it's a PCI IDE controller. 603 * If it is, we assume that we can deal with it; it _should_ 604 * work in a standardized way... 605 */ 606 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 607 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 608 return (1); 609 } 610 611 /* 612 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 613 * controllers. Let see if we can deal with it anyway. 614 */ 615 pp = pciide_lookup_product(pa->pa_id); 616 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 617 return (1); 618 } 619 620 return (0); 621 } 622 623 void 624 pciide_attach(parent, self, aux) 625 struct device *parent, *self; 626 void *aux; 627 { 628 struct pci_attach_args *pa = aux; 629 pci_chipset_tag_t pc = pa->pa_pc; 630 pcitag_t tag = pa->pa_tag; 631 struct pciide_softc *sc = (struct pciide_softc *)self; 632 pcireg_t csr; 633 char devinfo[256]; 634 const char *displaydev; 635 636 sc->sc_pp = pciide_lookup_product(pa->pa_id); 637 if (sc->sc_pp == NULL) { 638 sc->sc_pp = &default_product_desc; 639 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 640 displaydev = devinfo; 641 } else 642 displaydev = sc->sc_pp->ide_name; 643 644 /* if displaydev == NULL, printf is done in chip-specific map */ 645 if (displaydev) 646 printf(": %s (rev. 0x%02x)\n", displaydev, 647 PCI_REVISION(pa->pa_class)); 648 649 sc->sc_pc = pa->pa_pc; 650 sc->sc_tag = pa->pa_tag; 651 #ifdef WDCDEBUG 652 if (wdcdebug_pciide_mask & DEBUG_PROBE) 653 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 654 #endif 655 sc->sc_pp->chip_map(sc, pa); 656 657 if (sc->sc_dma_ok) { 658 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 659 csr |= PCI_COMMAND_MASTER_ENABLE; 660 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 661 } 662 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 663 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 664 } 665 666 /* tell wether the chip is enabled or not */ 667 int 668 pciide_chipen(sc, pa) 669 struct pciide_softc *sc; 670 struct pci_attach_args *pa; 671 { 672 pcireg_t csr; 673 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 674 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 675 PCI_COMMAND_STATUS_REG); 676 printf("%s: device disabled (at %s)\n", 677 sc->sc_wdcdev.sc_dev.dv_xname, 678 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 679 "device" : "bridge"); 680 return 0; 681 } 682 return 1; 683 } 684 685 int 686 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 687 struct pci_attach_args *pa; 688 struct pciide_channel *cp; 689 int compatchan; 690 bus_size_t *cmdsizep, *ctlsizep; 691 { 692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 693 struct channel_softc *wdc_cp = &cp->wdc_channel; 694 695 cp->compat = 1; 696 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 697 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 698 699 wdc_cp->cmd_iot = pa->pa_iot; 700 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 701 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 702 printf("%s: couldn't map %s channel cmd regs\n", 703 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 704 return (0); 705 } 706 707 wdc_cp->ctl_iot = pa->pa_iot; 708 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 709 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 710 printf("%s: couldn't map %s channel ctl regs\n", 711 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 712 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 713 PCIIDE_COMPAT_CMD_SIZE); 714 return (0); 715 } 716 717 return (1); 718 } 719 720 int 721 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 722 struct pci_attach_args * pa; 723 struct pciide_channel *cp; 724 bus_size_t *cmdsizep, *ctlsizep; 725 int (*pci_intr) __P((void *)); 726 { 727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 728 struct channel_softc *wdc_cp = &cp->wdc_channel; 729 const char *intrstr; 730 pci_intr_handle_t intrhandle; 731 732 cp->compat = 0; 733 734 if (sc->sc_pci_ih == NULL) { 735 if (pci_intr_map(pa, &intrhandle) != 0) { 736 printf("%s: couldn't map native-PCI interrupt\n", 737 sc->sc_wdcdev.sc_dev.dv_xname); 738 return 0; 739 } 740 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 741 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 742 intrhandle, IPL_BIO, pci_intr, sc); 743 if (sc->sc_pci_ih != NULL) { 744 printf("%s: using %s for native-PCI interrupt\n", 745 sc->sc_wdcdev.sc_dev.dv_xname, 746 intrstr ? intrstr : "unknown interrupt"); 747 } else { 748 printf("%s: couldn't establish native-PCI interrupt", 749 sc->sc_wdcdev.sc_dev.dv_xname); 750 if (intrstr != NULL) 751 printf(" at %s", intrstr); 752 printf("\n"); 753 return 0; 754 } 755 } 756 cp->ih = sc->sc_pci_ih; 757 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 758 PCI_MAPREG_TYPE_IO, 0, 759 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 760 printf("%s: couldn't map %s channel cmd regs\n", 761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 762 return 0; 763 } 764 765 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 766 PCI_MAPREG_TYPE_IO, 0, 767 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 768 printf("%s: couldn't map %s channel ctl regs\n", 769 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 770 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 771 return 0; 772 } 773 /* 774 * In native mode, 4 bytes of I/O space are mapped for the control 775 * register, the control register is at offset 2. Pass the generic 776 * code a handle for only one byte at the rigth offset. 777 */ 778 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 779 &wdc_cp->ctl_ioh) != 0) { 780 printf("%s: unable to subregion %s channel ctl regs\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 782 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 783 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 784 return 0; 785 } 786 return (1); 787 } 788 789 void 790 pciide_mapreg_dma(sc, pa) 791 struct pciide_softc *sc; 792 struct pci_attach_args *pa; 793 { 794 pcireg_t maptype; 795 bus_addr_t addr; 796 797 /* 798 * Map DMA registers 799 * 800 * Note that sc_dma_ok is the right variable to test to see if 801 * DMA can be done. If the interface doesn't support DMA, 802 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 803 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 804 * non-zero if the interface supports DMA and the registers 805 * could be mapped. 806 * 807 * XXX Note that despite the fact that the Bus Master IDE specs 808 * XXX say that "The bus master IDE function uses 16 bytes of IO 809 * XXX space," some controllers (at least the United 810 * XXX Microelectronics UM8886BF) place it in memory space. 811 */ 812 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 813 PCIIDE_REG_BUS_MASTER_DMA); 814 815 switch (maptype) { 816 case PCI_MAPREG_TYPE_IO: 817 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 818 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 819 &addr, NULL, NULL) == 0); 820 if (sc->sc_dma_ok == 0) { 821 printf(", but unused (couldn't query registers)"); 822 break; 823 } 824 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 825 && addr >= 0x10000) { 826 sc->sc_dma_ok = 0; 827 printf(", but unused (registers at unsafe address %#lx)", (unsigned long)addr); 828 break; 829 } 830 /* FALLTHROUGH */ 831 832 case PCI_MAPREG_MEM_TYPE_32BIT: 833 sc->sc_dma_ok = (pci_mapreg_map(pa, 834 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 835 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 836 sc->sc_dmat = pa->pa_dmat; 837 if (sc->sc_dma_ok == 0) { 838 printf(", but unused (couldn't map registers)"); 839 } else { 840 sc->sc_wdcdev.dma_arg = sc; 841 sc->sc_wdcdev.dma_init = pciide_dma_init; 842 sc->sc_wdcdev.dma_start = pciide_dma_start; 843 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 844 } 845 break; 846 847 default: 848 sc->sc_dma_ok = 0; 849 printf(", but unsupported register maptype (0x%x)", maptype); 850 } 851 } 852 853 int 854 pciide_compat_intr(arg) 855 void *arg; 856 { 857 struct pciide_channel *cp = arg; 858 859 #ifdef DIAGNOSTIC 860 /* should only be called for a compat channel */ 861 if (cp->compat == 0) 862 panic("pciide compat intr called for non-compat chan %p\n", cp); 863 #endif 864 return (wdcintr(&cp->wdc_channel)); 865 } 866 867 int 868 pciide_pci_intr(arg) 869 void *arg; 870 { 871 struct pciide_softc *sc = arg; 872 struct pciide_channel *cp; 873 struct channel_softc *wdc_cp; 874 int i, rv, crv; 875 876 rv = 0; 877 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 878 cp = &sc->pciide_channels[i]; 879 wdc_cp = &cp->wdc_channel; 880 881 /* If a compat channel skip. */ 882 if (cp->compat) 883 continue; 884 /* if this channel not waiting for intr, skip */ 885 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 886 continue; 887 888 crv = wdcintr(wdc_cp); 889 if (crv == 0) 890 ; /* leave rv alone */ 891 else if (crv == 1) 892 rv = 1; /* claim the intr */ 893 else if (rv == 0) /* crv should be -1 in this case */ 894 rv = crv; /* if we've done no better, take it */ 895 } 896 return (rv); 897 } 898 899 void 900 pciide_channel_dma_setup(cp) 901 struct pciide_channel *cp; 902 { 903 int drive; 904 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 905 struct ata_drive_datas *drvp; 906 907 for (drive = 0; drive < 2; drive++) { 908 drvp = &cp->wdc_channel.ch_drive[drive]; 909 /* If no drive, skip */ 910 if ((drvp->drive_flags & DRIVE) == 0) 911 continue; 912 /* setup DMA if needed */ 913 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 914 (drvp->drive_flags & DRIVE_UDMA) == 0) || 915 sc->sc_dma_ok == 0) { 916 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 917 continue; 918 } 919 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 920 != 0) { 921 /* Abort DMA setup */ 922 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 923 continue; 924 } 925 } 926 } 927 928 int 929 pciide_dma_table_setup(sc, channel, drive) 930 struct pciide_softc *sc; 931 int channel, drive; 932 { 933 bus_dma_segment_t seg; 934 int error, rseg; 935 const bus_size_t dma_table_size = 936 sizeof(struct idedma_table) * NIDEDMA_TABLES; 937 struct pciide_dma_maps *dma_maps = 938 &sc->pciide_channels[channel].dma_maps[drive]; 939 940 /* If table was already allocated, just return */ 941 if (dma_maps->dma_table) 942 return 0; 943 944 /* Allocate memory for the DMA tables and map it */ 945 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 946 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 947 BUS_DMA_NOWAIT)) != 0) { 948 printf("%s:%d: unable to allocate table DMA for " 949 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 950 channel, drive, error); 951 return error; 952 } 953 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 954 dma_table_size, 955 (caddr_t *)&dma_maps->dma_table, 956 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 957 printf("%s:%d: unable to map table DMA for" 958 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 959 channel, drive, error); 960 return error; 961 } 962 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 963 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 964 (unsigned long)seg.ds_addr), DEBUG_PROBE); 965 966 /* Create and load table DMA map for this disk */ 967 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 968 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 969 &dma_maps->dmamap_table)) != 0) { 970 printf("%s:%d: unable to create table DMA map for " 971 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 972 channel, drive, error); 973 return error; 974 } 975 if ((error = bus_dmamap_load(sc->sc_dmat, 976 dma_maps->dmamap_table, 977 dma_maps->dma_table, 978 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 979 printf("%s:%d: unable to load table DMA map for " 980 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 981 channel, drive, error); 982 return error; 983 } 984 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 985 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 986 DEBUG_PROBE); 987 /* Create a xfer DMA map for this drive */ 988 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 989 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 990 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 991 &dma_maps->dmamap_xfer)) != 0) { 992 printf("%s:%d: unable to create xfer DMA map for " 993 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 994 channel, drive, error); 995 return error; 996 } 997 return 0; 998 } 999 1000 int 1001 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1002 void *v; 1003 int channel, drive; 1004 void *databuf; 1005 size_t datalen; 1006 int flags; 1007 { 1008 struct pciide_softc *sc = v; 1009 int error, seg; 1010 struct pciide_dma_maps *dma_maps = 1011 &sc->pciide_channels[channel].dma_maps[drive]; 1012 1013 error = bus_dmamap_load(sc->sc_dmat, 1014 dma_maps->dmamap_xfer, 1015 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1016 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1017 if (error) { 1018 printf("%s:%d: unable to load xfer DMA map for" 1019 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1020 channel, drive, error); 1021 return error; 1022 } 1023 1024 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1025 dma_maps->dmamap_xfer->dm_mapsize, 1026 (flags & WDC_DMA_READ) ? 1027 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1028 1029 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1030 #ifdef DIAGNOSTIC 1031 /* A segment must not cross a 64k boundary */ 1032 { 1033 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1034 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1035 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1036 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1037 printf("pciide_dma: segment %d physical addr 0x%lx" 1038 " len 0x%lx not properly aligned\n", 1039 seg, phys, len); 1040 panic("pciide_dma: buf align"); 1041 } 1042 } 1043 #endif 1044 dma_maps->dma_table[seg].base_addr = 1045 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1046 dma_maps->dma_table[seg].byte_count = 1047 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1048 IDEDMA_BYTE_COUNT_MASK); 1049 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1050 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1051 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1052 1053 } 1054 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1055 htole32(IDEDMA_BYTE_COUNT_EOT); 1056 1057 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1058 dma_maps->dmamap_table->dm_mapsize, 1059 BUS_DMASYNC_PREWRITE); 1060 1061 /* Maps are ready. Start DMA function */ 1062 #ifdef DIAGNOSTIC 1063 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1064 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1065 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1066 panic("pciide_dma_init: table align"); 1067 } 1068 #endif 1069 1070 /* Clear status bits */ 1071 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1072 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1073 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1074 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1075 /* Write table addr */ 1076 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1077 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1078 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1079 /* set read/write */ 1080 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1081 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1082 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1083 /* remember flags */ 1084 dma_maps->dma_flags = flags; 1085 return 0; 1086 } 1087 1088 void 1089 pciide_dma_start(v, channel, drive) 1090 void *v; 1091 int channel, drive; 1092 { 1093 struct pciide_softc *sc = v; 1094 1095 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1096 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1097 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1098 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1099 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1100 } 1101 1102 int 1103 pciide_dma_finish(v, channel, drive, force) 1104 void *v; 1105 int channel, drive; 1106 int force; 1107 { 1108 struct pciide_softc *sc = v; 1109 u_int8_t status; 1110 int error = 0; 1111 struct pciide_dma_maps *dma_maps = 1112 &sc->pciide_channels[channel].dma_maps[drive]; 1113 1114 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1115 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1116 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1117 DEBUG_XFERS); 1118 1119 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1120 return WDC_DMAST_NOIRQ; 1121 1122 /* stop DMA channel */ 1123 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1124 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1125 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1126 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1127 1128 /* Unload the map of the data buffer */ 1129 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1130 dma_maps->dmamap_xfer->dm_mapsize, 1131 (dma_maps->dma_flags & WDC_DMA_READ) ? 1132 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1133 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1134 1135 if ((status & IDEDMA_CTL_ERR) != 0) { 1136 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1137 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1138 error |= WDC_DMAST_ERR; 1139 } 1140 1141 if ((status & IDEDMA_CTL_INTR) == 0) { 1142 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1143 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1144 drive, status); 1145 error |= WDC_DMAST_NOIRQ; 1146 } 1147 1148 if ((status & IDEDMA_CTL_ACT) != 0) { 1149 /* data underrun, may be a valid condition for ATAPI */ 1150 error |= WDC_DMAST_UNDER; 1151 } 1152 return error; 1153 } 1154 1155 void 1156 pciide_irqack(chp) 1157 struct channel_softc *chp; 1158 { 1159 struct pciide_channel *cp = (struct pciide_channel*)chp; 1160 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1161 1162 /* clear status bits in IDE DMA registers */ 1163 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1164 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1165 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1166 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1167 } 1168 1169 /* some common code used by several chip_map */ 1170 int 1171 pciide_chansetup(sc, channel, interface) 1172 struct pciide_softc *sc; 1173 int channel; 1174 pcireg_t interface; 1175 { 1176 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1177 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1178 cp->name = PCIIDE_CHANNEL_NAME(channel); 1179 cp->wdc_channel.channel = channel; 1180 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1181 cp->wdc_channel.ch_queue = 1182 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1183 if (cp->wdc_channel.ch_queue == NULL) { 1184 printf("%s %s channel: " 1185 "can't allocate memory for command queue", 1186 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1187 return 0; 1188 } 1189 printf("%s: %s channel %s to %s mode\n", 1190 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1191 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1192 "configured" : "wired", 1193 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1194 "native-PCI" : "compatibility"); 1195 return 1; 1196 } 1197 1198 /* some common code used by several chip channel_map */ 1199 void 1200 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1201 struct pci_attach_args *pa; 1202 struct pciide_channel *cp; 1203 pcireg_t interface; 1204 bus_size_t *cmdsizep, *ctlsizep; 1205 int (*pci_intr) __P((void *)); 1206 { 1207 struct channel_softc *wdc_cp = &cp->wdc_channel; 1208 1209 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1210 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1211 pci_intr); 1212 else 1213 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1214 wdc_cp->channel, cmdsizep, ctlsizep); 1215 1216 if (cp->hw_ok == 0) 1217 return; 1218 wdc_cp->data32iot = wdc_cp->cmd_iot; 1219 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1220 wdcattach(wdc_cp); 1221 } 1222 1223 /* 1224 * Generic code to call to know if a channel can be disabled. Return 1 1225 * if channel can be disabled, 0 if not 1226 */ 1227 int 1228 pciide_chan_candisable(cp) 1229 struct pciide_channel *cp; 1230 { 1231 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1232 struct channel_softc *wdc_cp = &cp->wdc_channel; 1233 1234 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1235 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1236 printf("%s: disabling %s channel (no drives)\n", 1237 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1238 cp->hw_ok = 0; 1239 return 1; 1240 } 1241 return 0; 1242 } 1243 1244 /* 1245 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1246 * Set hw_ok=0 on failure 1247 */ 1248 void 1249 pciide_map_compat_intr(pa, cp, compatchan, interface) 1250 struct pci_attach_args *pa; 1251 struct pciide_channel *cp; 1252 int compatchan, interface; 1253 { 1254 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1255 struct channel_softc *wdc_cp = &cp->wdc_channel; 1256 1257 if (cp->hw_ok == 0) 1258 return; 1259 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1260 return; 1261 1262 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1263 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1264 pa, compatchan, pciide_compat_intr, cp); 1265 if (cp->ih == NULL) { 1266 #endif 1267 printf("%s: no compatibility interrupt for use by %s " 1268 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1269 cp->hw_ok = 0; 1270 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1271 } 1272 #endif 1273 } 1274 1275 void 1276 pciide_print_modes(cp) 1277 struct pciide_channel *cp; 1278 { 1279 wdc_print_modes(&cp->wdc_channel); 1280 } 1281 1282 void 1283 default_chip_map(sc, pa) 1284 struct pciide_softc *sc; 1285 struct pci_attach_args *pa; 1286 { 1287 struct pciide_channel *cp; 1288 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1289 pcireg_t csr; 1290 int channel, drive; 1291 struct ata_drive_datas *drvp; 1292 u_int8_t idedma_ctl; 1293 bus_size_t cmdsize, ctlsize; 1294 char *failreason; 1295 1296 if (pciide_chipen(sc, pa) == 0) 1297 return; 1298 1299 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1300 printf("%s: bus-master DMA support present", 1301 sc->sc_wdcdev.sc_dev.dv_xname); 1302 if (sc->sc_pp == &default_product_desc && 1303 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1304 PCIIDE_OPTIONS_DMA) == 0) { 1305 printf(", but unused (no driver support)"); 1306 sc->sc_dma_ok = 0; 1307 } else { 1308 pciide_mapreg_dma(sc, pa); 1309 if (sc->sc_dma_ok != 0) 1310 printf(", used without full driver " 1311 "support"); 1312 } 1313 } else { 1314 printf("%s: hardware does not support DMA", 1315 sc->sc_wdcdev.sc_dev.dv_xname); 1316 sc->sc_dma_ok = 0; 1317 } 1318 printf("\n"); 1319 if (sc->sc_dma_ok) { 1320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1321 sc->sc_wdcdev.irqack = pciide_irqack; 1322 } 1323 sc->sc_wdcdev.PIO_cap = 0; 1324 sc->sc_wdcdev.DMA_cap = 0; 1325 1326 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1327 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1328 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1329 1330 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1331 cp = &sc->pciide_channels[channel]; 1332 if (pciide_chansetup(sc, channel, interface) == 0) 1333 continue; 1334 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1335 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1336 &ctlsize, pciide_pci_intr); 1337 } else { 1338 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1339 channel, &cmdsize, &ctlsize); 1340 } 1341 if (cp->hw_ok == 0) 1342 continue; 1343 /* 1344 * Check to see if something appears to be there. 1345 */ 1346 failreason = NULL; 1347 if (!wdcprobe(&cp->wdc_channel)) { 1348 failreason = "not responding; disabled or no drives?"; 1349 goto next; 1350 } 1351 /* 1352 * Now, make sure it's actually attributable to this PCI IDE 1353 * channel by trying to access the channel again while the 1354 * PCI IDE controller's I/O space is disabled. (If the 1355 * channel no longer appears to be there, it belongs to 1356 * this controller.) YUCK! 1357 */ 1358 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1359 PCI_COMMAND_STATUS_REG); 1360 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1361 csr & ~PCI_COMMAND_IO_ENABLE); 1362 if (wdcprobe(&cp->wdc_channel)) 1363 failreason = "other hardware responding at addresses"; 1364 pci_conf_write(sc->sc_pc, sc->sc_tag, 1365 PCI_COMMAND_STATUS_REG, csr); 1366 next: 1367 if (failreason) { 1368 printf("%s: %s channel ignored (%s)\n", 1369 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1370 failreason); 1371 cp->hw_ok = 0; 1372 bus_space_unmap(cp->wdc_channel.cmd_iot, 1373 cp->wdc_channel.cmd_ioh, cmdsize); 1374 bus_space_unmap(cp->wdc_channel.ctl_iot, 1375 cp->wdc_channel.ctl_ioh, ctlsize); 1376 } else { 1377 pciide_map_compat_intr(pa, cp, channel, interface); 1378 } 1379 if (cp->hw_ok) { 1380 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1381 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1382 wdcattach(&cp->wdc_channel); 1383 } 1384 } 1385 1386 if (sc->sc_dma_ok == 0) 1387 return; 1388 1389 /* Allocate DMA maps */ 1390 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1391 idedma_ctl = 0; 1392 cp = &sc->pciide_channels[channel]; 1393 for (drive = 0; drive < 2; drive++) { 1394 drvp = &cp->wdc_channel.ch_drive[drive]; 1395 /* If no drive, skip */ 1396 if ((drvp->drive_flags & DRIVE) == 0) 1397 continue; 1398 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1399 continue; 1400 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1401 /* Abort DMA setup */ 1402 printf("%s:%d:%d: can't allocate DMA maps, " 1403 "using PIO transfers\n", 1404 sc->sc_wdcdev.sc_dev.dv_xname, 1405 channel, drive); 1406 drvp->drive_flags &= ~DRIVE_DMA; 1407 } 1408 printf("%s:%d:%d: using DMA data transfers\n", 1409 sc->sc_wdcdev.sc_dev.dv_xname, 1410 channel, drive); 1411 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1412 } 1413 if (idedma_ctl != 0) { 1414 /* Add software bits in status register */ 1415 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1416 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1417 idedma_ctl); 1418 } 1419 } 1420 } 1421 1422 void 1423 piix_chip_map(sc, pa) 1424 struct pciide_softc *sc; 1425 struct pci_attach_args *pa; 1426 { 1427 struct pciide_channel *cp; 1428 int channel; 1429 u_int32_t idetim; 1430 bus_size_t cmdsize, ctlsize; 1431 1432 if (pciide_chipen(sc, pa) == 0) 1433 return; 1434 1435 printf("%s: bus-master DMA support present", 1436 sc->sc_wdcdev.sc_dev.dv_xname); 1437 pciide_mapreg_dma(sc, pa); 1438 printf("\n"); 1439 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1440 WDC_CAPABILITY_MODE; 1441 if (sc->sc_dma_ok) { 1442 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1443 sc->sc_wdcdev.irqack = pciide_irqack; 1444 switch(sc->sc_pp->ide_product) { 1445 case PCI_PRODUCT_INTEL_82371AB_IDE: 1446 case PCI_PRODUCT_INTEL_82440MX_IDE: 1447 case PCI_PRODUCT_INTEL_82801AA_IDE: 1448 case PCI_PRODUCT_INTEL_82801AB_IDE: 1449 case PCI_PRODUCT_INTEL_82801BA_IDE: 1450 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1451 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1452 } 1453 } 1454 sc->sc_wdcdev.PIO_cap = 4; 1455 sc->sc_wdcdev.DMA_cap = 2; 1456 switch(sc->sc_pp->ide_product) { 1457 case PCI_PRODUCT_INTEL_82801AA_IDE: 1458 sc->sc_wdcdev.UDMA_cap = 4; 1459 break; 1460 case PCI_PRODUCT_INTEL_82801BA_IDE: 1461 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1462 sc->sc_wdcdev.UDMA_cap = 5; 1463 break; 1464 default: 1465 sc->sc_wdcdev.UDMA_cap = 2; 1466 } 1467 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1468 sc->sc_wdcdev.set_modes = piix_setup_channel; 1469 else 1470 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1471 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1472 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1473 1474 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1475 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1476 DEBUG_PROBE); 1477 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1478 WDCDEBUG_PRINT((", sidetim=0x%x", 1479 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1480 DEBUG_PROBE); 1481 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1482 WDCDEBUG_PRINT((", udamreg 0x%x", 1483 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1484 DEBUG_PROBE); 1485 } 1486 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1490 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1491 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1492 DEBUG_PROBE); 1493 } 1494 1495 } 1496 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1497 1498 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1499 cp = &sc->pciide_channels[channel]; 1500 /* PIIX is compat-only */ 1501 if (pciide_chansetup(sc, channel, 0) == 0) 1502 continue; 1503 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1504 if ((PIIX_IDETIM_READ(idetim, channel) & 1505 PIIX_IDETIM_IDE) == 0) { 1506 printf("%s: %s channel ignored (disabled)\n", 1507 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1508 continue; 1509 } 1510 /* PIIX are compat-only pciide devices */ 1511 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1512 if (cp->hw_ok == 0) 1513 continue; 1514 if (pciide_chan_candisable(cp)) { 1515 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1516 channel); 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1518 idetim); 1519 } 1520 pciide_map_compat_intr(pa, cp, channel, 0); 1521 if (cp->hw_ok == 0) 1522 continue; 1523 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1524 } 1525 1526 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1527 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1528 DEBUG_PROBE); 1529 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1530 WDCDEBUG_PRINT((", sidetim=0x%x", 1531 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1532 DEBUG_PROBE); 1533 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1534 WDCDEBUG_PRINT((", udamreg 0x%x", 1535 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1536 DEBUG_PROBE); 1537 } 1538 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1539 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1540 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1541 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1542 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1543 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1544 DEBUG_PROBE); 1545 } 1546 } 1547 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1548 } 1549 1550 void 1551 piix_setup_channel(chp) 1552 struct channel_softc *chp; 1553 { 1554 u_int8_t mode[2], drive; 1555 u_int32_t oidetim, idetim, idedma_ctl; 1556 struct pciide_channel *cp = (struct pciide_channel*)chp; 1557 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1558 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1559 1560 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1561 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1562 idedma_ctl = 0; 1563 1564 /* set up new idetim: Enable IDE registers decode */ 1565 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1566 chp->channel); 1567 1568 /* setup DMA */ 1569 pciide_channel_dma_setup(cp); 1570 1571 /* 1572 * Here we have to mess up with drives mode: PIIX can't have 1573 * different timings for master and slave drives. 1574 * We need to find the best combination. 1575 */ 1576 1577 /* If both drives supports DMA, take the lower mode */ 1578 if ((drvp[0].drive_flags & DRIVE_DMA) && 1579 (drvp[1].drive_flags & DRIVE_DMA)) { 1580 mode[0] = mode[1] = 1581 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1582 drvp[0].DMA_mode = mode[0]; 1583 drvp[1].DMA_mode = mode[1]; 1584 goto ok; 1585 } 1586 /* 1587 * If only one drive supports DMA, use its mode, and 1588 * put the other one in PIO mode 0 if mode not compatible 1589 */ 1590 if (drvp[0].drive_flags & DRIVE_DMA) { 1591 mode[0] = drvp[0].DMA_mode; 1592 mode[1] = drvp[1].PIO_mode; 1593 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1594 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1595 mode[1] = drvp[1].PIO_mode = 0; 1596 goto ok; 1597 } 1598 if (drvp[1].drive_flags & DRIVE_DMA) { 1599 mode[1] = drvp[1].DMA_mode; 1600 mode[0] = drvp[0].PIO_mode; 1601 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1602 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1603 mode[0] = drvp[0].PIO_mode = 0; 1604 goto ok; 1605 } 1606 /* 1607 * If both drives are not DMA, takes the lower mode, unless 1608 * one of them is PIO mode < 2 1609 */ 1610 if (drvp[0].PIO_mode < 2) { 1611 mode[0] = drvp[0].PIO_mode = 0; 1612 mode[1] = drvp[1].PIO_mode; 1613 } else if (drvp[1].PIO_mode < 2) { 1614 mode[1] = drvp[1].PIO_mode = 0; 1615 mode[0] = drvp[0].PIO_mode; 1616 } else { 1617 mode[0] = mode[1] = 1618 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1619 drvp[0].PIO_mode = mode[0]; 1620 drvp[1].PIO_mode = mode[1]; 1621 } 1622 ok: /* The modes are setup */ 1623 for (drive = 0; drive < 2; drive++) { 1624 if (drvp[drive].drive_flags & DRIVE_DMA) { 1625 idetim |= piix_setup_idetim_timings( 1626 mode[drive], 1, chp->channel); 1627 goto end; 1628 } 1629 } 1630 /* If we are there, none of the drives are DMA */ 1631 if (mode[0] >= 2) 1632 idetim |= piix_setup_idetim_timings( 1633 mode[0], 0, chp->channel); 1634 else 1635 idetim |= piix_setup_idetim_timings( 1636 mode[1], 0, chp->channel); 1637 end: /* 1638 * timing mode is now set up in the controller. Enable 1639 * it per-drive 1640 */ 1641 for (drive = 0; drive < 2; drive++) { 1642 /* If no drive, skip */ 1643 if ((drvp[drive].drive_flags & DRIVE) == 0) 1644 continue; 1645 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1646 if (drvp[drive].drive_flags & DRIVE_DMA) 1647 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1648 } 1649 if (idedma_ctl != 0) { 1650 /* Add software bits in status register */ 1651 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1652 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1653 idedma_ctl); 1654 } 1655 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1656 pciide_print_modes(cp); 1657 } 1658 1659 void 1660 piix3_4_setup_channel(chp) 1661 struct channel_softc *chp; 1662 { 1663 struct ata_drive_datas *drvp; 1664 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1665 struct pciide_channel *cp = (struct pciide_channel*)chp; 1666 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1667 int drive; 1668 int channel = chp->channel; 1669 1670 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1671 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1672 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1673 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1674 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1675 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1676 PIIX_SIDETIM_RTC_MASK(channel)); 1677 1678 idedma_ctl = 0; 1679 /* If channel disabled, no need to go further */ 1680 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1681 return; 1682 /* set up new idetim: Enable IDE registers decode */ 1683 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1684 1685 /* setup DMA if needed */ 1686 pciide_channel_dma_setup(cp); 1687 1688 for (drive = 0; drive < 2; drive++) { 1689 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1690 PIIX_UDMATIM_SET(0x3, channel, drive)); 1691 drvp = &chp->ch_drive[drive]; 1692 /* If no drive, skip */ 1693 if ((drvp->drive_flags & DRIVE) == 0) 1694 continue; 1695 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1696 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1697 goto pio; 1698 1699 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1700 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1701 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1702 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1703 ideconf |= PIIX_CONFIG_PINGPONG; 1704 } 1705 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1706 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1707 /* setup Ultra/100 */ 1708 if (drvp->UDMA_mode > 2 && 1709 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1710 drvp->UDMA_mode = 2; 1711 if (drvp->UDMA_mode > 4) { 1712 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1713 } else { 1714 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1715 if (drvp->UDMA_mode > 2) { 1716 ideconf |= PIIX_CONFIG_UDMA66(channel, 1717 drive); 1718 } else { 1719 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1720 drive); 1721 } 1722 } 1723 } 1724 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1725 /* setup Ultra/66 */ 1726 if (drvp->UDMA_mode > 2 && 1727 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1728 drvp->UDMA_mode = 2; 1729 if (drvp->UDMA_mode > 2) 1730 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1731 else 1732 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1733 } 1734 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1735 (drvp->drive_flags & DRIVE_UDMA)) { 1736 /* use Ultra/DMA */ 1737 drvp->drive_flags &= ~DRIVE_DMA; 1738 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1739 udmareg |= PIIX_UDMATIM_SET( 1740 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1741 } else { 1742 /* use Multiword DMA */ 1743 drvp->drive_flags &= ~DRIVE_UDMA; 1744 if (drive == 0) { 1745 idetim |= piix_setup_idetim_timings( 1746 drvp->DMA_mode, 1, channel); 1747 } else { 1748 sidetim |= piix_setup_sidetim_timings( 1749 drvp->DMA_mode, 1, channel); 1750 idetim =PIIX_IDETIM_SET(idetim, 1751 PIIX_IDETIM_SITRE, channel); 1752 } 1753 } 1754 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1755 1756 pio: /* use PIO mode */ 1757 idetim |= piix_setup_idetim_drvs(drvp); 1758 if (drive == 0) { 1759 idetim |= piix_setup_idetim_timings( 1760 drvp->PIO_mode, 0, channel); 1761 } else { 1762 sidetim |= piix_setup_sidetim_timings( 1763 drvp->PIO_mode, 0, channel); 1764 idetim =PIIX_IDETIM_SET(idetim, 1765 PIIX_IDETIM_SITRE, channel); 1766 } 1767 } 1768 if (idedma_ctl != 0) { 1769 /* Add software bits in status register */ 1770 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1771 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1772 idedma_ctl); 1773 } 1774 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1775 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1776 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1777 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1778 pciide_print_modes(cp); 1779 } 1780 1781 1782 /* setup ISP and RTC fields, based on mode */ 1783 static u_int32_t 1784 piix_setup_idetim_timings(mode, dma, channel) 1785 u_int8_t mode; 1786 u_int8_t dma; 1787 u_int8_t channel; 1788 { 1789 1790 if (dma) 1791 return PIIX_IDETIM_SET(0, 1792 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1793 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1794 channel); 1795 else 1796 return PIIX_IDETIM_SET(0, 1797 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1798 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1799 channel); 1800 } 1801 1802 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1803 static u_int32_t 1804 piix_setup_idetim_drvs(drvp) 1805 struct ata_drive_datas *drvp; 1806 { 1807 u_int32_t ret = 0; 1808 struct channel_softc *chp = drvp->chnl_softc; 1809 u_int8_t channel = chp->channel; 1810 u_int8_t drive = drvp->drive; 1811 1812 /* 1813 * If drive is using UDMA, timings setups are independant 1814 * So just check DMA and PIO here. 1815 */ 1816 if (drvp->drive_flags & DRIVE_DMA) { 1817 /* if mode = DMA mode 0, use compatible timings */ 1818 if ((drvp->drive_flags & DRIVE_DMA) && 1819 drvp->DMA_mode == 0) { 1820 drvp->PIO_mode = 0; 1821 return ret; 1822 } 1823 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1824 /* 1825 * PIO and DMA timings are the same, use fast timings for PIO 1826 * too, else use compat timings. 1827 */ 1828 if ((piix_isp_pio[drvp->PIO_mode] != 1829 piix_isp_dma[drvp->DMA_mode]) || 1830 (piix_rtc_pio[drvp->PIO_mode] != 1831 piix_rtc_dma[drvp->DMA_mode])) 1832 drvp->PIO_mode = 0; 1833 /* if PIO mode <= 2, use compat timings for PIO */ 1834 if (drvp->PIO_mode <= 2) { 1835 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1836 channel); 1837 return ret; 1838 } 1839 } 1840 1841 /* 1842 * Now setup PIO modes. If mode < 2, use compat timings. 1843 * Else enable fast timings. Enable IORDY and prefetch/post 1844 * if PIO mode >= 3. 1845 */ 1846 1847 if (drvp->PIO_mode < 2) 1848 return ret; 1849 1850 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1851 if (drvp->PIO_mode >= 3) { 1852 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1853 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1854 } 1855 return ret; 1856 } 1857 1858 /* setup values in SIDETIM registers, based on mode */ 1859 static u_int32_t 1860 piix_setup_sidetim_timings(mode, dma, channel) 1861 u_int8_t mode; 1862 u_int8_t dma; 1863 u_int8_t channel; 1864 { 1865 if (dma) 1866 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1867 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1868 else 1869 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1870 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1871 } 1872 1873 void 1874 amd7x6_chip_map(sc, pa) 1875 struct pciide_softc *sc; 1876 struct pci_attach_args *pa; 1877 { 1878 struct pciide_channel *cp; 1879 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1880 int channel; 1881 pcireg_t chanenable; 1882 bus_size_t cmdsize, ctlsize; 1883 1884 if (pciide_chipen(sc, pa) == 0) 1885 return; 1886 printf("%s: bus-master DMA support present", 1887 sc->sc_wdcdev.sc_dev.dv_xname); 1888 pciide_mapreg_dma(sc, pa); 1889 printf("\n"); 1890 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1891 WDC_CAPABILITY_MODE; 1892 if (sc->sc_dma_ok) { 1893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1894 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1895 sc->sc_wdcdev.irqack = pciide_irqack; 1896 } 1897 sc->sc_wdcdev.PIO_cap = 4; 1898 sc->sc_wdcdev.DMA_cap = 2; 1899 1900 if (sc->sc_pp->ide_product == PCI_PRODUCT_AMD_PBC766_IDE) 1901 sc->sc_wdcdev.UDMA_cap = 5; 1902 else 1903 sc->sc_wdcdev.UDMA_cap = 4; 1904 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1905 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1906 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1907 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1908 1909 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1910 DEBUG_PROBE); 1911 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1912 cp = &sc->pciide_channels[channel]; 1913 if (pciide_chansetup(sc, channel, interface) == 0) 1914 continue; 1915 1916 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1917 printf("%s: %s channel ignored (disabled)\n", 1918 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1919 continue; 1920 } 1921 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1922 pciide_pci_intr); 1923 1924 if (pciide_chan_candisable(cp)) 1925 chanenable &= ~AMD7X6_CHAN_EN(channel); 1926 pciide_map_compat_intr(pa, cp, channel, interface); 1927 if (cp->hw_ok == 0) 1928 continue; 1929 1930 amd7x6_setup_channel(&cp->wdc_channel); 1931 } 1932 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1933 chanenable); 1934 return; 1935 } 1936 1937 void 1938 amd7x6_setup_channel(chp) 1939 struct channel_softc *chp; 1940 { 1941 u_int32_t udmatim_reg, datatim_reg; 1942 u_int8_t idedma_ctl; 1943 int mode, drive; 1944 struct ata_drive_datas *drvp; 1945 struct pciide_channel *cp = (struct pciide_channel*)chp; 1946 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1947 #ifndef PCIIDE_AMD756_ENABLEDMA 1948 int rev = PCI_REVISION( 1949 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1950 #endif 1951 1952 idedma_ctl = 0; 1953 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1954 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1955 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1956 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1957 1958 /* setup DMA if needed */ 1959 pciide_channel_dma_setup(cp); 1960 1961 for (drive = 0; drive < 2; drive++) { 1962 drvp = &chp->ch_drive[drive]; 1963 /* If no drive, skip */ 1964 if ((drvp->drive_flags & DRIVE) == 0) 1965 continue; 1966 /* add timing values, setup DMA if needed */ 1967 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1968 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1969 mode = drvp->PIO_mode; 1970 goto pio; 1971 } 1972 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1973 (drvp->drive_flags & DRIVE_UDMA)) { 1974 /* use Ultra/DMA */ 1975 drvp->drive_flags &= ~DRIVE_DMA; 1976 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 1977 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 1978 AMD7X6_UDMA_TIME(chp->channel, drive, 1979 amd7x6_udma_tim[drvp->UDMA_mode]); 1980 /* can use PIO timings, MW DMA unused */ 1981 mode = drvp->PIO_mode; 1982 } else { 1983 /* use Multiword DMA, but only if revision is OK */ 1984 drvp->drive_flags &= ~DRIVE_UDMA; 1985 #ifndef PCIIDE_AMD756_ENABLEDMA 1986 /* 1987 * The workaround doesn't seem to be necessary 1988 * with all drives, so it can be disabled by 1989 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1990 * triggered. 1991 */ 1992 if (sc->sc_pp->ide_product == 1993 PCI_PRODUCT_AMD_PBC756_IDE && 1994 AMD756_CHIPREV_DISABLEDMA(rev)) { 1995 printf("%s:%d:%d: multi-word DMA disabled due " 1996 "to chip revision\n", 1997 sc->sc_wdcdev.sc_dev.dv_xname, 1998 chp->channel, drive); 1999 mode = drvp->PIO_mode; 2000 drvp->drive_flags &= ~DRIVE_DMA; 2001 goto pio; 2002 } 2003 #endif 2004 /* mode = min(pio, dma+2) */ 2005 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2006 mode = drvp->PIO_mode; 2007 else 2008 mode = drvp->DMA_mode + 2; 2009 } 2010 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2011 2012 pio: /* setup PIO mode */ 2013 if (mode <= 2) { 2014 drvp->DMA_mode = 0; 2015 drvp->PIO_mode = 0; 2016 mode = 0; 2017 } else { 2018 drvp->PIO_mode = mode; 2019 drvp->DMA_mode = mode - 2; 2020 } 2021 datatim_reg |= 2022 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2023 amd7x6_pio_set[mode]) | 2024 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2025 amd7x6_pio_rec[mode]); 2026 } 2027 if (idedma_ctl != 0) { 2028 /* Add software bits in status register */ 2029 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2030 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2031 idedma_ctl); 2032 } 2033 pciide_print_modes(cp); 2034 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2035 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2036 } 2037 2038 void 2039 apollo_chip_map(sc, pa) 2040 struct pciide_softc *sc; 2041 struct pci_attach_args *pa; 2042 { 2043 struct pciide_channel *cp; 2044 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2045 int channel; 2046 u_int32_t ideconf; 2047 bus_size_t cmdsize, ctlsize; 2048 pcitag_t pcib_tag; 2049 pcireg_t pcib_id, pcib_class; 2050 2051 if (pciide_chipen(sc, pa) == 0) 2052 return; 2053 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2054 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2055 /* and read ID and rev of the ISA bridge */ 2056 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2057 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2058 printf(": VIA Technologies "); 2059 switch (PCI_PRODUCT(pcib_id)) { 2060 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2061 printf("VT82C586 (Apollo VP) "); 2062 if(PCI_REVISION(pcib_class) >= 0x02) { 2063 printf("ATA33 controller\n"); 2064 sc->sc_wdcdev.UDMA_cap = 2; 2065 } else { 2066 printf("controller\n"); 2067 sc->sc_wdcdev.UDMA_cap = 0; 2068 } 2069 break; 2070 case PCI_PRODUCT_VIATECH_VT82C596A: 2071 printf("VT82C596A (Apollo Pro) "); 2072 if (PCI_REVISION(pcib_class) >= 0x12) { 2073 printf("ATA66 controller\n"); 2074 sc->sc_wdcdev.UDMA_cap = 4; 2075 } else { 2076 printf("ATA33 controller\n"); 2077 sc->sc_wdcdev.UDMA_cap = 2; 2078 } 2079 break; 2080 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2081 printf("VT82C686A (Apollo KX133) "); 2082 if (PCI_REVISION(pcib_class) >= 0x40) { 2083 printf("ATA100 controller\n"); 2084 sc->sc_wdcdev.UDMA_cap = 5; 2085 } else { 2086 printf("ATA66 controller\n"); 2087 sc->sc_wdcdev.UDMA_cap = 4; 2088 } 2089 break; 2090 default: 2091 printf("unknown ATA controller\n"); 2092 sc->sc_wdcdev.UDMA_cap = 0; 2093 } 2094 2095 printf("%s: bus-master DMA support present", 2096 sc->sc_wdcdev.sc_dev.dv_xname); 2097 pciide_mapreg_dma(sc, pa); 2098 printf("\n"); 2099 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2100 WDC_CAPABILITY_MODE; 2101 if (sc->sc_dma_ok) { 2102 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2103 sc->sc_wdcdev.irqack = pciide_irqack; 2104 if (sc->sc_wdcdev.UDMA_cap > 0) 2105 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2106 } 2107 sc->sc_wdcdev.PIO_cap = 4; 2108 sc->sc_wdcdev.DMA_cap = 2; 2109 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2110 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2111 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2112 2113 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2114 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2115 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2116 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2117 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2118 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2119 DEBUG_PROBE); 2120 2121 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2122 cp = &sc->pciide_channels[channel]; 2123 if (pciide_chansetup(sc, channel, interface) == 0) 2124 continue; 2125 2126 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2127 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2128 printf("%s: %s channel ignored (disabled)\n", 2129 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2130 continue; 2131 } 2132 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2133 pciide_pci_intr); 2134 if (cp->hw_ok == 0) 2135 continue; 2136 if (pciide_chan_candisable(cp)) { 2137 ideconf &= ~APO_IDECONF_EN(channel); 2138 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2139 ideconf); 2140 } 2141 pciide_map_compat_intr(pa, cp, channel, interface); 2142 2143 if (cp->hw_ok == 0) 2144 continue; 2145 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2146 } 2147 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2148 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2149 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2150 } 2151 2152 void 2153 apollo_setup_channel(chp) 2154 struct channel_softc *chp; 2155 { 2156 u_int32_t udmatim_reg, datatim_reg; 2157 u_int8_t idedma_ctl; 2158 int mode, drive; 2159 struct ata_drive_datas *drvp; 2160 struct pciide_channel *cp = (struct pciide_channel*)chp; 2161 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2162 2163 idedma_ctl = 0; 2164 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2165 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2166 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2167 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2168 2169 /* setup DMA if needed */ 2170 pciide_channel_dma_setup(cp); 2171 2172 for (drive = 0; drive < 2; drive++) { 2173 drvp = &chp->ch_drive[drive]; 2174 /* If no drive, skip */ 2175 if ((drvp->drive_flags & DRIVE) == 0) 2176 continue; 2177 /* add timing values, setup DMA if needed */ 2178 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2179 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2180 mode = drvp->PIO_mode; 2181 goto pio; 2182 } 2183 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2184 (drvp->drive_flags & DRIVE_UDMA)) { 2185 /* use Ultra/DMA */ 2186 drvp->drive_flags &= ~DRIVE_DMA; 2187 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2188 APO_UDMA_EN_MTH(chp->channel, drive); 2189 if (sc->sc_wdcdev.UDMA_cap == 5) { 2190 /* 686b */ 2191 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2192 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2193 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2194 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2195 /* 596b or 686a */ 2196 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2197 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2198 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2199 } else { 2200 /* 596a or 586b */ 2201 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2202 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2203 } 2204 /* can use PIO timings, MW DMA unused */ 2205 mode = drvp->PIO_mode; 2206 } else { 2207 /* use Multiword DMA */ 2208 drvp->drive_flags &= ~DRIVE_UDMA; 2209 /* mode = min(pio, dma+2) */ 2210 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2211 mode = drvp->PIO_mode; 2212 else 2213 mode = drvp->DMA_mode + 2; 2214 } 2215 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2216 2217 pio: /* setup PIO mode */ 2218 if (mode <= 2) { 2219 drvp->DMA_mode = 0; 2220 drvp->PIO_mode = 0; 2221 mode = 0; 2222 } else { 2223 drvp->PIO_mode = mode; 2224 drvp->DMA_mode = mode - 2; 2225 } 2226 datatim_reg |= 2227 APO_DATATIM_PULSE(chp->channel, drive, 2228 apollo_pio_set[mode]) | 2229 APO_DATATIM_RECOV(chp->channel, drive, 2230 apollo_pio_rec[mode]); 2231 } 2232 if (idedma_ctl != 0) { 2233 /* Add software bits in status register */ 2234 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2235 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2236 idedma_ctl); 2237 } 2238 pciide_print_modes(cp); 2239 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2240 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2241 } 2242 2243 void 2244 cmd_channel_map(pa, sc, channel) 2245 struct pci_attach_args *pa; 2246 struct pciide_softc *sc; 2247 int channel; 2248 { 2249 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2250 bus_size_t cmdsize, ctlsize; 2251 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2252 int interface; 2253 2254 /* 2255 * The 0648/0649 can be told to identify as a RAID controller. 2256 * In this case, we have to fake interface 2257 */ 2258 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2259 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2260 PCIIDE_INTERFACE_SETTABLE(1); 2261 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2262 CMD_CONF_DSA1) 2263 interface |= PCIIDE_INTERFACE_PCI(0) | 2264 PCIIDE_INTERFACE_PCI(1); 2265 } else { 2266 interface = PCI_INTERFACE(pa->pa_class); 2267 } 2268 2269 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2270 cp->name = PCIIDE_CHANNEL_NAME(channel); 2271 cp->wdc_channel.channel = channel; 2272 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2273 2274 if (channel > 0) { 2275 cp->wdc_channel.ch_queue = 2276 sc->pciide_channels[0].wdc_channel.ch_queue; 2277 } else { 2278 cp->wdc_channel.ch_queue = 2279 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2280 } 2281 if (cp->wdc_channel.ch_queue == NULL) { 2282 printf("%s %s channel: " 2283 "can't allocate memory for command queue", 2284 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2285 return; 2286 } 2287 2288 printf("%s: %s channel %s to %s mode\n", 2289 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2290 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2291 "configured" : "wired", 2292 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2293 "native-PCI" : "compatibility"); 2294 2295 /* 2296 * with a CMD PCI64x, if we get here, the first channel is enabled: 2297 * there's no way to disable the first channel without disabling 2298 * the whole device 2299 */ 2300 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2301 printf("%s: %s channel ignored (disabled)\n", 2302 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2303 return; 2304 } 2305 2306 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2307 if (cp->hw_ok == 0) 2308 return; 2309 if (channel == 1) { 2310 if (pciide_chan_candisable(cp)) { 2311 ctrl &= ~CMD_CTRL_2PORT; 2312 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2313 CMD_CTRL, ctrl); 2314 } 2315 } 2316 pciide_map_compat_intr(pa, cp, channel, interface); 2317 } 2318 2319 int 2320 cmd_pci_intr(arg) 2321 void *arg; 2322 { 2323 struct pciide_softc *sc = arg; 2324 struct pciide_channel *cp; 2325 struct channel_softc *wdc_cp; 2326 int i, rv, crv; 2327 u_int32_t priirq, secirq; 2328 2329 rv = 0; 2330 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2331 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2332 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2333 cp = &sc->pciide_channels[i]; 2334 wdc_cp = &cp->wdc_channel; 2335 /* If a compat channel skip. */ 2336 if (cp->compat) 2337 continue; 2338 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2339 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2340 crv = wdcintr(wdc_cp); 2341 if (crv == 0) 2342 printf("%s:%d: bogus intr\n", 2343 sc->sc_wdcdev.sc_dev.dv_xname, i); 2344 else 2345 rv = 1; 2346 } 2347 } 2348 return rv; 2349 } 2350 2351 void 2352 cmd_chip_map(sc, pa) 2353 struct pciide_softc *sc; 2354 struct pci_attach_args *pa; 2355 { 2356 int channel; 2357 2358 /* 2359 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2360 * and base adresses registers can be disabled at 2361 * hardware level. In this case, the device is wired 2362 * in compat mode and its first channel is always enabled, 2363 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2364 * In fact, it seems that the first channel of the CMD PCI0640 2365 * can't be disabled. 2366 */ 2367 2368 #ifdef PCIIDE_CMD064x_DISABLE 2369 if (pciide_chipen(sc, pa) == 0) 2370 return; 2371 #endif 2372 2373 printf("%s: hardware does not support DMA\n", 2374 sc->sc_wdcdev.sc_dev.dv_xname); 2375 sc->sc_dma_ok = 0; 2376 2377 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2378 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2379 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2380 2381 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2382 cmd_channel_map(pa, sc, channel); 2383 } 2384 } 2385 2386 void 2387 cmd0643_9_chip_map(sc, pa) 2388 struct pciide_softc *sc; 2389 struct pci_attach_args *pa; 2390 { 2391 struct pciide_channel *cp; 2392 int channel; 2393 int rev = PCI_REVISION( 2394 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2395 2396 /* 2397 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2398 * and base adresses registers can be disabled at 2399 * hardware level. In this case, the device is wired 2400 * in compat mode and its first channel is always enabled, 2401 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2402 * In fact, it seems that the first channel of the CMD PCI0640 2403 * can't be disabled. 2404 */ 2405 2406 #ifdef PCIIDE_CMD064x_DISABLE 2407 if (pciide_chipen(sc, pa) == 0) 2408 return; 2409 #endif 2410 printf("%s: bus-master DMA support present", 2411 sc->sc_wdcdev.sc_dev.dv_xname); 2412 pciide_mapreg_dma(sc, pa); 2413 printf("\n"); 2414 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2415 WDC_CAPABILITY_MODE; 2416 if (sc->sc_dma_ok) { 2417 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2418 switch (sc->sc_pp->ide_product) { 2419 case PCI_PRODUCT_CMDTECH_649: 2420 case PCI_PRODUCT_CMDTECH_648: 2421 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2422 sc->sc_wdcdev.UDMA_cap = 4; 2423 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2424 break; 2425 case PCI_PRODUCT_CMDTECH_646: 2426 if (rev >= CMD0646U2_REV) { 2427 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2428 sc->sc_wdcdev.UDMA_cap = 2; 2429 } else if (rev >= CMD0646U_REV) { 2430 /* 2431 * Linux's driver claims that the 646U is broken 2432 * with UDMA. Only enable it if we know what we're 2433 * doing 2434 */ 2435 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2436 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2437 sc->sc_wdcdev.UDMA_cap = 2; 2438 #endif 2439 /* explicitely disable UDMA */ 2440 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2441 CMD_UDMATIM(0), 0); 2442 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2443 CMD_UDMATIM(1), 0); 2444 } 2445 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2446 break; 2447 default: 2448 sc->sc_wdcdev.irqack = pciide_irqack; 2449 } 2450 } 2451 2452 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2453 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2454 sc->sc_wdcdev.PIO_cap = 4; 2455 sc->sc_wdcdev.DMA_cap = 2; 2456 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2457 2458 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2459 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2460 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2461 DEBUG_PROBE); 2462 2463 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2464 cp = &sc->pciide_channels[channel]; 2465 cmd_channel_map(pa, sc, channel); 2466 if (cp->hw_ok == 0) 2467 continue; 2468 cmd0643_9_setup_channel(&cp->wdc_channel); 2469 } 2470 /* 2471 * note - this also makes sure we clear the irq disable and reset 2472 * bits 2473 */ 2474 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2475 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2476 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2477 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2478 DEBUG_PROBE); 2479 } 2480 2481 void 2482 cmd0643_9_setup_channel(chp) 2483 struct channel_softc *chp; 2484 { 2485 struct ata_drive_datas *drvp; 2486 u_int8_t tim; 2487 u_int32_t idedma_ctl, udma_reg; 2488 int drive; 2489 struct pciide_channel *cp = (struct pciide_channel*)chp; 2490 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2491 2492 idedma_ctl = 0; 2493 /* setup DMA if needed */ 2494 pciide_channel_dma_setup(cp); 2495 2496 for (drive = 0; drive < 2; drive++) { 2497 drvp = &chp->ch_drive[drive]; 2498 /* If no drive, skip */ 2499 if ((drvp->drive_flags & DRIVE) == 0) 2500 continue; 2501 /* add timing values, setup DMA if needed */ 2502 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2503 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2504 if (drvp->drive_flags & DRIVE_UDMA) { 2505 /* UltraDMA on a 646U2, 0648 or 0649 */ 2506 drvp->drive_flags &= ~DRIVE_DMA; 2507 udma_reg = pciide_pci_read(sc->sc_pc, 2508 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2509 if (drvp->UDMA_mode > 2 && 2510 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2511 CMD_BICSR) & 2512 CMD_BICSR_80(chp->channel)) == 0) 2513 drvp->UDMA_mode = 2; 2514 if (drvp->UDMA_mode > 2) 2515 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2516 else if (sc->sc_wdcdev.UDMA_cap > 2) 2517 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2518 udma_reg |= CMD_UDMATIM_UDMA(drive); 2519 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2520 CMD_UDMATIM_TIM_OFF(drive)); 2521 udma_reg |= 2522 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2523 CMD_UDMATIM_TIM_OFF(drive)); 2524 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2525 CMD_UDMATIM(chp->channel), udma_reg); 2526 } else { 2527 /* 2528 * use Multiword DMA. 2529 * Timings will be used for both PIO and DMA, 2530 * so adjust DMA mode if needed 2531 * if we have a 0646U2/8/9, turn off UDMA 2532 */ 2533 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2534 udma_reg = pciide_pci_read(sc->sc_pc, 2535 sc->sc_tag, 2536 CMD_UDMATIM(chp->channel)); 2537 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2538 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2539 CMD_UDMATIM(chp->channel), 2540 udma_reg); 2541 } 2542 if (drvp->PIO_mode >= 3 && 2543 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2544 drvp->DMA_mode = drvp->PIO_mode - 2; 2545 } 2546 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2547 } 2548 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2549 } 2550 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2551 CMD_DATA_TIM(chp->channel, drive), tim); 2552 } 2553 if (idedma_ctl != 0) { 2554 /* Add software bits in status register */ 2555 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2556 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2557 idedma_ctl); 2558 } 2559 pciide_print_modes(cp); 2560 } 2561 2562 void 2563 cmd646_9_irqack(chp) 2564 struct channel_softc *chp; 2565 { 2566 u_int32_t priirq, secirq; 2567 struct pciide_channel *cp = (struct pciide_channel*)chp; 2568 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2569 2570 if (chp->channel == 0) { 2571 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2572 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2573 } else { 2574 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2575 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2576 } 2577 pciide_irqack(chp); 2578 } 2579 2580 void 2581 cy693_chip_map(sc, pa) 2582 struct pciide_softc *sc; 2583 struct pci_attach_args *pa; 2584 { 2585 struct pciide_channel *cp; 2586 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2587 bus_size_t cmdsize, ctlsize; 2588 2589 if (pciide_chipen(sc, pa) == 0) 2590 return; 2591 /* 2592 * this chip has 2 PCI IDE functions, one for primary and one for 2593 * secondary. So we need to call pciide_mapregs_compat() with 2594 * the real channel 2595 */ 2596 if (pa->pa_function == 1) { 2597 sc->sc_cy_compatchan = 0; 2598 } else if (pa->pa_function == 2) { 2599 sc->sc_cy_compatchan = 1; 2600 } else { 2601 printf("%s: unexpected PCI function %d\n", 2602 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2603 return; 2604 } 2605 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2606 printf("%s: bus-master DMA support present", 2607 sc->sc_wdcdev.sc_dev.dv_xname); 2608 pciide_mapreg_dma(sc, pa); 2609 } else { 2610 printf("%s: hardware does not support DMA", 2611 sc->sc_wdcdev.sc_dev.dv_xname); 2612 sc->sc_dma_ok = 0; 2613 } 2614 printf("\n"); 2615 2616 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2617 if (sc->sc_cy_handle == NULL) { 2618 printf("%s: unable to map hyperCache control registers\n", 2619 sc->sc_wdcdev.sc_dev.dv_xname); 2620 sc->sc_dma_ok = 0; 2621 } 2622 2623 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2624 WDC_CAPABILITY_MODE; 2625 if (sc->sc_dma_ok) { 2626 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2627 sc->sc_wdcdev.irqack = pciide_irqack; 2628 } 2629 sc->sc_wdcdev.PIO_cap = 4; 2630 sc->sc_wdcdev.DMA_cap = 2; 2631 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2632 2633 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2634 sc->sc_wdcdev.nchannels = 1; 2635 2636 /* Only one channel for this chip; if we are here it's enabled */ 2637 cp = &sc->pciide_channels[0]; 2638 sc->wdc_chanarray[0] = &cp->wdc_channel; 2639 cp->name = PCIIDE_CHANNEL_NAME(0); 2640 cp->wdc_channel.channel = 0; 2641 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2642 cp->wdc_channel.ch_queue = 2643 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2644 if (cp->wdc_channel.ch_queue == NULL) { 2645 printf("%s primary channel: " 2646 "can't allocate memory for command queue", 2647 sc->sc_wdcdev.sc_dev.dv_xname); 2648 return; 2649 } 2650 printf("%s: primary channel %s to ", 2651 sc->sc_wdcdev.sc_dev.dv_xname, 2652 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2653 "configured" : "wired"); 2654 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2655 printf("native-PCI"); 2656 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2657 pciide_pci_intr); 2658 } else { 2659 printf("compatibility"); 2660 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2661 &cmdsize, &ctlsize); 2662 } 2663 printf(" mode\n"); 2664 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2665 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2666 wdcattach(&cp->wdc_channel); 2667 if (pciide_chan_candisable(cp)) { 2668 pci_conf_write(sc->sc_pc, sc->sc_tag, 2669 PCI_COMMAND_STATUS_REG, 0); 2670 } 2671 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2672 if (cp->hw_ok == 0) 2673 return; 2674 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2675 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2676 cy693_setup_channel(&cp->wdc_channel); 2677 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2678 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2679 } 2680 2681 void 2682 cy693_setup_channel(chp) 2683 struct channel_softc *chp; 2684 { 2685 struct ata_drive_datas *drvp; 2686 int drive; 2687 u_int32_t cy_cmd_ctrl; 2688 u_int32_t idedma_ctl; 2689 struct pciide_channel *cp = (struct pciide_channel*)chp; 2690 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2691 int dma_mode = -1; 2692 2693 cy_cmd_ctrl = idedma_ctl = 0; 2694 2695 /* setup DMA if needed */ 2696 pciide_channel_dma_setup(cp); 2697 2698 for (drive = 0; drive < 2; drive++) { 2699 drvp = &chp->ch_drive[drive]; 2700 /* If no drive, skip */ 2701 if ((drvp->drive_flags & DRIVE) == 0) 2702 continue; 2703 /* add timing values, setup DMA if needed */ 2704 if (drvp->drive_flags & DRIVE_DMA) { 2705 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2706 /* use Multiword DMA */ 2707 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2708 dma_mode = drvp->DMA_mode; 2709 } 2710 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2711 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2712 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2713 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2714 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2715 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2716 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2717 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2718 } 2719 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2720 chp->ch_drive[0].DMA_mode = dma_mode; 2721 chp->ch_drive[1].DMA_mode = dma_mode; 2722 2723 if (dma_mode == -1) 2724 dma_mode = 0; 2725 2726 if (sc->sc_cy_handle != NULL) { 2727 /* Note: `multiple' is implied. */ 2728 cy82c693_write(sc->sc_cy_handle, 2729 (sc->sc_cy_compatchan == 0) ? 2730 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2731 } 2732 2733 pciide_print_modes(cp); 2734 2735 if (idedma_ctl != 0) { 2736 /* Add software bits in status register */ 2737 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2738 IDEDMA_CTL, idedma_ctl); 2739 } 2740 } 2741 2742 void 2743 sis_chip_map(sc, pa) 2744 struct pciide_softc *sc; 2745 struct pci_attach_args *pa; 2746 { 2747 struct pciide_channel *cp; 2748 int channel; 2749 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2750 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2751 pcireg_t rev = PCI_REVISION(pa->pa_class); 2752 bus_size_t cmdsize, ctlsize; 2753 pcitag_t pchb_tag; 2754 pcireg_t pchb_id, pchb_class; 2755 2756 if (pciide_chipen(sc, pa) == 0) 2757 return; 2758 printf("%s: bus-master DMA support present", 2759 sc->sc_wdcdev.sc_dev.dv_xname); 2760 pciide_mapreg_dma(sc, pa); 2761 printf("\n"); 2762 2763 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2764 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2765 /* and read ID and rev of the ISA bridge */ 2766 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2767 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2768 2769 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2770 WDC_CAPABILITY_MODE; 2771 if (sc->sc_dma_ok) { 2772 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2773 sc->sc_wdcdev.irqack = pciide_irqack; 2774 /* 2775 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2776 * have problems with UDMA (info provided by Christos) 2777 */ 2778 if (rev >= 0xd0 && 2779 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2780 PCI_REVISION(pchb_class) >= 0x03)) 2781 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2782 } 2783 2784 sc->sc_wdcdev.PIO_cap = 4; 2785 sc->sc_wdcdev.DMA_cap = 2; 2786 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2787 sc->sc_wdcdev.UDMA_cap = 2; 2788 sc->sc_wdcdev.set_modes = sis_setup_channel; 2789 2790 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2791 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2792 2793 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2794 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2795 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2796 2797 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2798 cp = &sc->pciide_channels[channel]; 2799 if (pciide_chansetup(sc, channel, interface) == 0) 2800 continue; 2801 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2802 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2803 printf("%s: %s channel ignored (disabled)\n", 2804 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2805 continue; 2806 } 2807 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2808 pciide_pci_intr); 2809 if (cp->hw_ok == 0) 2810 continue; 2811 if (pciide_chan_candisable(cp)) { 2812 if (channel == 0) 2813 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2814 else 2815 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2816 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2817 sis_ctr0); 2818 } 2819 pciide_map_compat_intr(pa, cp, channel, interface); 2820 if (cp->hw_ok == 0) 2821 continue; 2822 sis_setup_channel(&cp->wdc_channel); 2823 } 2824 } 2825 2826 void 2827 sis_setup_channel(chp) 2828 struct channel_softc *chp; 2829 { 2830 struct ata_drive_datas *drvp; 2831 int drive; 2832 u_int32_t sis_tim; 2833 u_int32_t idedma_ctl; 2834 struct pciide_channel *cp = (struct pciide_channel*)chp; 2835 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2836 2837 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2838 "channel %d 0x%x\n", chp->channel, 2839 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2840 DEBUG_PROBE); 2841 sis_tim = 0; 2842 idedma_ctl = 0; 2843 /* setup DMA if needed */ 2844 pciide_channel_dma_setup(cp); 2845 2846 for (drive = 0; drive < 2; drive++) { 2847 drvp = &chp->ch_drive[drive]; 2848 /* If no drive, skip */ 2849 if ((drvp->drive_flags & DRIVE) == 0) 2850 continue; 2851 /* add timing values, setup DMA if needed */ 2852 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2853 (drvp->drive_flags & DRIVE_UDMA) == 0) 2854 goto pio; 2855 2856 if (drvp->drive_flags & DRIVE_UDMA) { 2857 /* use Ultra/DMA */ 2858 drvp->drive_flags &= ~DRIVE_DMA; 2859 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2860 SIS_TIM_UDMA_TIME_OFF(drive); 2861 sis_tim |= SIS_TIM_UDMA_EN(drive); 2862 } else { 2863 /* 2864 * use Multiword DMA 2865 * Timings will be used for both PIO and DMA, 2866 * so adjust DMA mode if needed 2867 */ 2868 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2869 drvp->PIO_mode = drvp->DMA_mode + 2; 2870 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2871 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2872 drvp->PIO_mode - 2 : 0; 2873 if (drvp->DMA_mode == 0) 2874 drvp->PIO_mode = 0; 2875 } 2876 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2877 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2878 SIS_TIM_ACT_OFF(drive); 2879 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2880 SIS_TIM_REC_OFF(drive); 2881 } 2882 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2883 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2884 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2885 if (idedma_ctl != 0) { 2886 /* Add software bits in status register */ 2887 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2888 IDEDMA_CTL, idedma_ctl); 2889 } 2890 pciide_print_modes(cp); 2891 } 2892 2893 void 2894 acer_chip_map(sc, pa) 2895 struct pciide_softc *sc; 2896 struct pci_attach_args *pa; 2897 { 2898 struct pciide_channel *cp; 2899 int channel; 2900 pcireg_t cr, interface; 2901 bus_size_t cmdsize, ctlsize; 2902 pcireg_t rev = PCI_REVISION(pa->pa_class); 2903 2904 if (pciide_chipen(sc, pa) == 0) 2905 return; 2906 printf("%s: bus-master DMA support present", 2907 sc->sc_wdcdev.sc_dev.dv_xname); 2908 pciide_mapreg_dma(sc, pa); 2909 printf("\n"); 2910 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2911 WDC_CAPABILITY_MODE; 2912 if (sc->sc_dma_ok) { 2913 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2914 if (rev >= 0x20) 2915 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2916 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2917 sc->sc_wdcdev.irqack = pciide_irqack; 2918 } 2919 2920 sc->sc_wdcdev.PIO_cap = 4; 2921 sc->sc_wdcdev.DMA_cap = 2; 2922 sc->sc_wdcdev.UDMA_cap = 2; 2923 sc->sc_wdcdev.set_modes = acer_setup_channel; 2924 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2925 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2926 2927 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2928 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2929 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2930 2931 /* Enable "microsoft register bits" R/W. */ 2932 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2933 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2934 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2935 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2936 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2937 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2938 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2939 ~ACER_CHANSTATUSREGS_RO); 2940 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2941 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2942 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2943 /* Don't use cr, re-read the real register content instead */ 2944 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2945 PCI_CLASS_REG)); 2946 2947 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2948 cp = &sc->pciide_channels[channel]; 2949 if (pciide_chansetup(sc, channel, interface) == 0) 2950 continue; 2951 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2952 printf("%s: %s channel ignored (disabled)\n", 2953 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2954 continue; 2955 } 2956 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2957 acer_pci_intr); 2958 if (cp->hw_ok == 0) 2959 continue; 2960 if (pciide_chan_candisable(cp)) { 2961 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2962 pci_conf_write(sc->sc_pc, sc->sc_tag, 2963 PCI_CLASS_REG, cr); 2964 } 2965 pciide_map_compat_intr(pa, cp, channel, interface); 2966 acer_setup_channel(&cp->wdc_channel); 2967 } 2968 } 2969 2970 void 2971 acer_setup_channel(chp) 2972 struct channel_softc *chp; 2973 { 2974 struct ata_drive_datas *drvp; 2975 int drive; 2976 u_int32_t acer_fifo_udma; 2977 u_int32_t idedma_ctl; 2978 struct pciide_channel *cp = (struct pciide_channel*)chp; 2979 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2980 2981 idedma_ctl = 0; 2982 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2983 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2984 acer_fifo_udma), DEBUG_PROBE); 2985 /* setup DMA if needed */ 2986 pciide_channel_dma_setup(cp); 2987 2988 for (drive = 0; drive < 2; drive++) { 2989 drvp = &chp->ch_drive[drive]; 2990 /* If no drive, skip */ 2991 if ((drvp->drive_flags & DRIVE) == 0) 2992 continue; 2993 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2994 "channel %d drive %d 0x%x\n", chp->channel, drive, 2995 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2996 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2997 /* clear FIFO/DMA mode */ 2998 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2999 ACER_UDMA_EN(chp->channel, drive) | 3000 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3001 3002 /* add timing values, setup DMA if needed */ 3003 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3004 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3005 acer_fifo_udma |= 3006 ACER_FTH_OPL(chp->channel, drive, 0x1); 3007 goto pio; 3008 } 3009 3010 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3011 if (drvp->drive_flags & DRIVE_UDMA) { 3012 /* use Ultra/DMA */ 3013 drvp->drive_flags &= ~DRIVE_DMA; 3014 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3015 acer_fifo_udma |= 3016 ACER_UDMA_TIM(chp->channel, drive, 3017 acer_udma[drvp->UDMA_mode]); 3018 } else { 3019 /* 3020 * use Multiword DMA 3021 * Timings will be used for both PIO and DMA, 3022 * so adjust DMA mode if needed 3023 */ 3024 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3025 drvp->PIO_mode = drvp->DMA_mode + 2; 3026 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3027 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3028 drvp->PIO_mode - 2 : 0; 3029 if (drvp->DMA_mode == 0) 3030 drvp->PIO_mode = 0; 3031 } 3032 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3033 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3034 ACER_IDETIM(chp->channel, drive), 3035 acer_pio[drvp->PIO_mode]); 3036 } 3037 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3038 acer_fifo_udma), DEBUG_PROBE); 3039 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3040 if (idedma_ctl != 0) { 3041 /* Add software bits in status register */ 3042 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3043 IDEDMA_CTL, idedma_ctl); 3044 } 3045 pciide_print_modes(cp); 3046 } 3047 3048 int 3049 acer_pci_intr(arg) 3050 void *arg; 3051 { 3052 struct pciide_softc *sc = arg; 3053 struct pciide_channel *cp; 3054 struct channel_softc *wdc_cp; 3055 int i, rv, crv; 3056 u_int32_t chids; 3057 3058 rv = 0; 3059 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3060 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3061 cp = &sc->pciide_channels[i]; 3062 wdc_cp = &cp->wdc_channel; 3063 /* If a compat channel skip. */ 3064 if (cp->compat) 3065 continue; 3066 if (chids & ACER_CHIDS_INT(i)) { 3067 crv = wdcintr(wdc_cp); 3068 if (crv == 0) 3069 printf("%s:%d: bogus intr\n", 3070 sc->sc_wdcdev.sc_dev.dv_xname, i); 3071 else 3072 rv = 1; 3073 } 3074 } 3075 return rv; 3076 } 3077 3078 void 3079 hpt_chip_map(sc, pa) 3080 struct pciide_softc *sc; 3081 struct pci_attach_args *pa; 3082 { 3083 struct pciide_channel *cp; 3084 int i, compatchan, revision; 3085 pcireg_t interface; 3086 bus_size_t cmdsize, ctlsize; 3087 3088 if (pciide_chipen(sc, pa) == 0) 3089 return; 3090 revision = PCI_REVISION(pa->pa_class); 3091 printf(": Triones/Highpoint "); 3092 if (revision == HPT370_REV) 3093 printf("HPT370 IDE Controller\n"); 3094 else 3095 printf("HPT366 IDE Controller\n"); 3096 3097 /* 3098 * when the chip is in native mode it identifies itself as a 3099 * 'misc mass storage'. Fake interface in this case. 3100 */ 3101 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3102 interface = PCI_INTERFACE(pa->pa_class); 3103 } else { 3104 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3105 PCIIDE_INTERFACE_PCI(0); 3106 if (revision == HPT370_REV) 3107 interface |= PCIIDE_INTERFACE_PCI(1); 3108 } 3109 3110 printf("%s: bus-master DMA support present", 3111 sc->sc_wdcdev.sc_dev.dv_xname); 3112 pciide_mapreg_dma(sc, pa); 3113 printf("\n"); 3114 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3115 WDC_CAPABILITY_MODE; 3116 if (sc->sc_dma_ok) { 3117 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3118 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3119 sc->sc_wdcdev.irqack = pciide_irqack; 3120 } 3121 sc->sc_wdcdev.PIO_cap = 4; 3122 sc->sc_wdcdev.DMA_cap = 2; 3123 3124 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3125 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3126 if (revision == HPT366_REV) { 3127 sc->sc_wdcdev.UDMA_cap = 4; 3128 /* 3129 * The 366 has 2 PCI IDE functions, one for primary and one 3130 * for secondary. So we need to call pciide_mapregs_compat() 3131 * with the real channel 3132 */ 3133 if (pa->pa_function == 0) { 3134 compatchan = 0; 3135 } else if (pa->pa_function == 1) { 3136 compatchan = 1; 3137 } else { 3138 printf("%s: unexpected PCI function %d\n", 3139 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3140 return; 3141 } 3142 sc->sc_wdcdev.nchannels = 1; 3143 } else { 3144 sc->sc_wdcdev.nchannels = 2; 3145 sc->sc_wdcdev.UDMA_cap = 5; 3146 } 3147 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3148 cp = &sc->pciide_channels[i]; 3149 if (sc->sc_wdcdev.nchannels > 1) { 3150 compatchan = i; 3151 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3152 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3153 printf("%s: %s channel ignored (disabled)\n", 3154 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3155 continue; 3156 } 3157 } 3158 if (pciide_chansetup(sc, i, interface) == 0) 3159 continue; 3160 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3161 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3162 &ctlsize, hpt_pci_intr); 3163 } else { 3164 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3165 &cmdsize, &ctlsize); 3166 } 3167 if (cp->hw_ok == 0) 3168 return; 3169 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3170 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3171 wdcattach(&cp->wdc_channel); 3172 hpt_setup_channel(&cp->wdc_channel); 3173 } 3174 if (revision == HPT370_REV) { 3175 /* 3176 * HPT370_REV has a bit to disable interrupts, make sure 3177 * to clear it 3178 */ 3179 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3180 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3181 ~HPT_CSEL_IRQDIS); 3182 } 3183 return; 3184 } 3185 3186 void 3187 hpt_setup_channel(chp) 3188 struct channel_softc *chp; 3189 { 3190 struct ata_drive_datas *drvp; 3191 int drive; 3192 int cable; 3193 u_int32_t before, after; 3194 u_int32_t idedma_ctl; 3195 struct pciide_channel *cp = (struct pciide_channel*)chp; 3196 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3197 3198 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3199 3200 /* setup DMA if needed */ 3201 pciide_channel_dma_setup(cp); 3202 3203 idedma_ctl = 0; 3204 3205 /* Per drive settings */ 3206 for (drive = 0; drive < 2; drive++) { 3207 drvp = &chp->ch_drive[drive]; 3208 /* If no drive, skip */ 3209 if ((drvp->drive_flags & DRIVE) == 0) 3210 continue; 3211 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3212 HPT_IDETIM(chp->channel, drive)); 3213 3214 /* add timing values, setup DMA if needed */ 3215 if (drvp->drive_flags & DRIVE_UDMA) { 3216 /* use Ultra/DMA */ 3217 drvp->drive_flags &= ~DRIVE_DMA; 3218 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3219 drvp->UDMA_mode > 2) 3220 drvp->UDMA_mode = 2; 3221 after = (sc->sc_wdcdev.nchannels == 2) ? 3222 hpt370_udma[drvp->UDMA_mode] : 3223 hpt366_udma[drvp->UDMA_mode]; 3224 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3225 } else if (drvp->drive_flags & DRIVE_DMA) { 3226 /* 3227 * use Multiword DMA. 3228 * Timings will be used for both PIO and DMA, so adjust 3229 * DMA mode if needed 3230 */ 3231 if (drvp->PIO_mode >= 3 && 3232 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3233 drvp->DMA_mode = drvp->PIO_mode - 2; 3234 } 3235 after = (sc->sc_wdcdev.nchannels == 2) ? 3236 hpt370_dma[drvp->DMA_mode] : 3237 hpt366_dma[drvp->DMA_mode]; 3238 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3239 } else { 3240 /* PIO only */ 3241 after = (sc->sc_wdcdev.nchannels == 2) ? 3242 hpt370_pio[drvp->PIO_mode] : 3243 hpt366_pio[drvp->PIO_mode]; 3244 } 3245 pci_conf_write(sc->sc_pc, sc->sc_tag, 3246 HPT_IDETIM(chp->channel, drive), after); 3247 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3248 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3249 after, before), DEBUG_PROBE); 3250 } 3251 if (idedma_ctl != 0) { 3252 /* Add software bits in status register */ 3253 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3254 IDEDMA_CTL, idedma_ctl); 3255 } 3256 pciide_print_modes(cp); 3257 } 3258 3259 int 3260 hpt_pci_intr(arg) 3261 void *arg; 3262 { 3263 struct pciide_softc *sc = arg; 3264 struct pciide_channel *cp; 3265 struct channel_softc *wdc_cp; 3266 int rv = 0; 3267 int dmastat, i, crv; 3268 3269 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3270 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3271 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3272 if((dmastat & IDEDMA_CTL_INTR) == 0) 3273 continue; 3274 cp = &sc->pciide_channels[i]; 3275 wdc_cp = &cp->wdc_channel; 3276 crv = wdcintr(wdc_cp); 3277 if (crv == 0) { 3278 printf("%s:%d: bogus intr\n", 3279 sc->sc_wdcdev.sc_dev.dv_xname, i); 3280 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3281 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3282 } else 3283 rv = 1; 3284 } 3285 return rv; 3286 } 3287 3288 3289 /* Macros to test product */ 3290 #define PDC_IS_262(sc) \ 3291 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3292 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3293 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3294 #define PDC_IS_265(sc) \ 3295 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3296 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3297 3298 void 3299 pdc202xx_chip_map(sc, pa) 3300 struct pciide_softc *sc; 3301 struct pci_attach_args *pa; 3302 { 3303 struct pciide_channel *cp; 3304 int channel; 3305 pcireg_t interface, st, mode; 3306 bus_size_t cmdsize, ctlsize; 3307 3308 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3309 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3310 DEBUG_PROBE); 3311 if (pciide_chipen(sc, pa) == 0) 3312 return; 3313 3314 /* turn off RAID mode */ 3315 st &= ~PDC2xx_STATE_IDERAID; 3316 3317 /* 3318 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3319 * mode. We have to fake interface 3320 */ 3321 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3322 if (st & PDC2xx_STATE_NATIVE) 3323 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3324 3325 printf("%s: bus-master DMA support present", 3326 sc->sc_wdcdev.sc_dev.dv_xname); 3327 pciide_mapreg_dma(sc, pa); 3328 printf("\n"); 3329 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3330 WDC_CAPABILITY_MODE; 3331 if (sc->sc_dma_ok) { 3332 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3333 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3334 sc->sc_wdcdev.irqack = pciide_irqack; 3335 } 3336 sc->sc_wdcdev.PIO_cap = 4; 3337 sc->sc_wdcdev.DMA_cap = 2; 3338 if (PDC_IS_265(sc)) 3339 sc->sc_wdcdev.UDMA_cap = 5; 3340 else if (PDC_IS_262(sc)) 3341 sc->sc_wdcdev.UDMA_cap = 4; 3342 else 3343 sc->sc_wdcdev.UDMA_cap = 2; 3344 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3345 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3346 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3347 3348 /* setup failsafe defaults */ 3349 mode = 0; 3350 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3351 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3352 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3353 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3354 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3355 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3356 "initial timings 0x%x, now 0x%x\n", channel, 3357 pci_conf_read(sc->sc_pc, sc->sc_tag, 3358 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3359 DEBUG_PROBE); 3360 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3361 mode | PDC2xx_TIM_IORDYp); 3362 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3363 "initial timings 0x%x, now 0x%x\n", channel, 3364 pci_conf_read(sc->sc_pc, sc->sc_tag, 3365 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3366 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3367 mode); 3368 } 3369 3370 mode = PDC2xx_SCR_DMA; 3371 if (PDC_IS_262(sc)) { 3372 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3373 } else { 3374 /* the BIOS set it up this way */ 3375 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3376 } 3377 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3378 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3379 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3380 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3381 DEBUG_PROBE); 3382 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3383 3384 /* controller initial state register is OK even without BIOS */ 3385 /* Set DMA mode to IDE DMA compatibility */ 3386 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3387 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3388 DEBUG_PROBE); 3389 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3390 mode | 0x1); 3391 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3392 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3393 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3394 mode | 0x1); 3395 3396 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3397 cp = &sc->pciide_channels[channel]; 3398 if (pciide_chansetup(sc, channel, interface) == 0) 3399 continue; 3400 if ((st & (PDC_IS_262(sc) ? 3401 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3402 printf("%s: %s channel ignored (disabled)\n", 3403 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3404 continue; 3405 } 3406 if (PDC_IS_265(sc)) 3407 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3408 pdc20265_pci_intr); 3409 else 3410 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3411 pdc202xx_pci_intr); 3412 if (cp->hw_ok == 0) 3413 continue; 3414 if (pciide_chan_candisable(cp)) 3415 st &= ~(PDC_IS_262(sc) ? 3416 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3417 pciide_map_compat_intr(pa, cp, channel, interface); 3418 pdc202xx_setup_channel(&cp->wdc_channel); 3419 } 3420 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3421 DEBUG_PROBE); 3422 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3423 return; 3424 } 3425 3426 void 3427 pdc202xx_setup_channel(chp) 3428 struct channel_softc *chp; 3429 { 3430 struct ata_drive_datas *drvp; 3431 int drive; 3432 pcireg_t mode, st; 3433 u_int32_t idedma_ctl, scr, atapi; 3434 struct pciide_channel *cp = (struct pciide_channel*)chp; 3435 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3436 int channel = chp->channel; 3437 3438 /* setup DMA if needed */ 3439 pciide_channel_dma_setup(cp); 3440 3441 idedma_ctl = 0; 3442 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3443 sc->sc_wdcdev.sc_dev.dv_xname, 3444 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3445 DEBUG_PROBE); 3446 3447 /* Per channel settings */ 3448 if (PDC_IS_262(sc)) { 3449 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3450 PDC262_U66); 3451 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3452 /* Trimm UDMA mode */ 3453 if ((st & PDC262_STATE_80P(channel)) != 0 || 3454 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3455 chp->ch_drive[0].UDMA_mode <= 2) || 3456 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3457 chp->ch_drive[1].UDMA_mode <= 2)) { 3458 if (chp->ch_drive[0].UDMA_mode > 2) 3459 chp->ch_drive[0].UDMA_mode = 2; 3460 if (chp->ch_drive[1].UDMA_mode > 2) 3461 chp->ch_drive[1].UDMA_mode = 2; 3462 } 3463 /* Set U66 if needed */ 3464 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3465 chp->ch_drive[0].UDMA_mode > 2) || 3466 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3467 chp->ch_drive[1].UDMA_mode > 2)) 3468 scr |= PDC262_U66_EN(channel); 3469 else 3470 scr &= ~PDC262_U66_EN(channel); 3471 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3472 PDC262_U66, scr); 3473 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3474 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3475 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3476 PDC262_ATAPI(channel))), DEBUG_PROBE); 3477 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3478 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3479 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3480 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3481 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3482 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3483 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3484 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3485 atapi = 0; 3486 else 3487 atapi = PDC262_ATAPI_UDMA; 3488 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3489 PDC262_ATAPI(channel), atapi); 3490 } 3491 } 3492 for (drive = 0; drive < 2; drive++) { 3493 drvp = &chp->ch_drive[drive]; 3494 /* If no drive, skip */ 3495 if ((drvp->drive_flags & DRIVE) == 0) 3496 continue; 3497 mode = 0; 3498 if (drvp->drive_flags & DRIVE_UDMA) { 3499 /* use Ultra/DMA */ 3500 drvp->drive_flags &= ~DRIVE_DMA; 3501 mode = PDC2xx_TIM_SET_MB(mode, 3502 pdc2xx_udma_mb[drvp->UDMA_mode]); 3503 mode = PDC2xx_TIM_SET_MC(mode, 3504 pdc2xx_udma_mc[drvp->UDMA_mode]); 3505 drvp->drive_flags &= ~DRIVE_DMA; 3506 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3507 } else if (drvp->drive_flags & DRIVE_DMA) { 3508 mode = PDC2xx_TIM_SET_MB(mode, 3509 pdc2xx_dma_mb[drvp->DMA_mode]); 3510 mode = PDC2xx_TIM_SET_MC(mode, 3511 pdc2xx_dma_mc[drvp->DMA_mode]); 3512 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3513 } else { 3514 mode = PDC2xx_TIM_SET_MB(mode, 3515 pdc2xx_dma_mb[0]); 3516 mode = PDC2xx_TIM_SET_MC(mode, 3517 pdc2xx_dma_mc[0]); 3518 } 3519 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3520 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3521 if (drvp->drive_flags & DRIVE_ATA) 3522 mode |= PDC2xx_TIM_PRE; 3523 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3524 if (drvp->PIO_mode >= 3) { 3525 mode |= PDC2xx_TIM_IORDY; 3526 if (drive == 0) 3527 mode |= PDC2xx_TIM_IORDYp; 3528 } 3529 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3530 "timings 0x%x\n", 3531 sc->sc_wdcdev.sc_dev.dv_xname, 3532 chp->channel, drive, mode), DEBUG_PROBE); 3533 pci_conf_write(sc->sc_pc, sc->sc_tag, 3534 PDC2xx_TIM(chp->channel, drive), mode); 3535 } 3536 if (idedma_ctl != 0) { 3537 /* Add software bits in status register */ 3538 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3539 IDEDMA_CTL, idedma_ctl); 3540 } 3541 pciide_print_modes(cp); 3542 } 3543 3544 int 3545 pdc202xx_pci_intr(arg) 3546 void *arg; 3547 { 3548 struct pciide_softc *sc = arg; 3549 struct pciide_channel *cp; 3550 struct channel_softc *wdc_cp; 3551 int i, rv, crv; 3552 u_int32_t scr; 3553 3554 rv = 0; 3555 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3556 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3557 cp = &sc->pciide_channels[i]; 3558 wdc_cp = &cp->wdc_channel; 3559 /* If a compat channel skip. */ 3560 if (cp->compat) 3561 continue; 3562 if (scr & PDC2xx_SCR_INT(i)) { 3563 crv = wdcintr(wdc_cp); 3564 if (crv == 0) 3565 printf("%s:%d: bogus intr (reg 0x%x)\n", 3566 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3567 else 3568 rv = 1; 3569 } 3570 } 3571 return rv; 3572 } 3573 3574 int 3575 pdc20265_pci_intr(arg) 3576 void *arg; 3577 { 3578 struct pciide_softc *sc = arg; 3579 struct pciide_channel *cp; 3580 struct channel_softc *wdc_cp; 3581 int i, rv, crv; 3582 u_int32_t dmastat; 3583 3584 rv = 0; 3585 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3586 cp = &sc->pciide_channels[i]; 3587 wdc_cp = &cp->wdc_channel; 3588 /* If a compat channel skip. */ 3589 if (cp->compat) 3590 continue; 3591 /* 3592 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3593 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3594 * So use it instead (requires 2 reg reads instead of 1, 3595 * but we can't do it another way). 3596 */ 3597 dmastat = bus_space_read_1(sc->sc_dma_iot, 3598 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3599 if((dmastat & IDEDMA_CTL_INTR) == 0) 3600 continue; 3601 crv = wdcintr(wdc_cp); 3602 if (crv == 0) 3603 printf("%s:%d: bogus intr\n", 3604 sc->sc_wdcdev.sc_dev.dv_xname, i); 3605 else 3606 rv = 1; 3607 } 3608 return rv; 3609 } 3610 3611 void 3612 opti_chip_map(sc, pa) 3613 struct pciide_softc *sc; 3614 struct pci_attach_args *pa; 3615 { 3616 struct pciide_channel *cp; 3617 bus_size_t cmdsize, ctlsize; 3618 pcireg_t interface; 3619 u_int8_t init_ctrl; 3620 int channel; 3621 3622 if (pciide_chipen(sc, pa) == 0) 3623 return; 3624 printf("%s: bus-master DMA support present", 3625 sc->sc_wdcdev.sc_dev.dv_xname); 3626 3627 /* 3628 * XXXSCW: 3629 * There seem to be a couple of buggy revisions/implementations 3630 * of the OPTi pciide chipset. This kludge seems to fix one of 3631 * the reported problems (PR/11644) but still fails for the 3632 * other (PR/13151), although the latter may be due to other 3633 * issues too... 3634 */ 3635 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3636 printf(" but disabled due to chip rev. <= 0x12"); 3637 sc->sc_dma_ok = 0; 3638 sc->sc_wdcdev.cap = 0; 3639 } else { 3640 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3641 pciide_mapreg_dma(sc, pa); 3642 } 3643 printf("\n"); 3644 3645 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3646 sc->sc_wdcdev.PIO_cap = 4; 3647 if (sc->sc_dma_ok) { 3648 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3649 sc->sc_wdcdev.irqack = pciide_irqack; 3650 sc->sc_wdcdev.DMA_cap = 2; 3651 } 3652 sc->sc_wdcdev.set_modes = opti_setup_channel; 3653 3654 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3655 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3656 3657 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3658 OPTI_REG_INIT_CONTROL); 3659 3660 interface = PCI_INTERFACE(pa->pa_class); 3661 3662 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3663 cp = &sc->pciide_channels[channel]; 3664 if (pciide_chansetup(sc, channel, interface) == 0) 3665 continue; 3666 if (channel == 1 && 3667 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3668 printf("%s: %s channel ignored (disabled)\n", 3669 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3670 continue; 3671 } 3672 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3673 pciide_pci_intr); 3674 if (cp->hw_ok == 0) 3675 continue; 3676 pciide_map_compat_intr(pa, cp, channel, interface); 3677 if (cp->hw_ok == 0) 3678 continue; 3679 opti_setup_channel(&cp->wdc_channel); 3680 } 3681 } 3682 3683 void 3684 opti_setup_channel(chp) 3685 struct channel_softc *chp; 3686 { 3687 struct ata_drive_datas *drvp; 3688 struct pciide_channel *cp = (struct pciide_channel*)chp; 3689 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3690 int drive, spd; 3691 int mode[2]; 3692 u_int8_t rv, mr; 3693 3694 /* 3695 * The `Delay' and `Address Setup Time' fields of the 3696 * Miscellaneous Register are always zero initially. 3697 */ 3698 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3699 mr &= ~(OPTI_MISC_DELAY_MASK | 3700 OPTI_MISC_ADDR_SETUP_MASK | 3701 OPTI_MISC_INDEX_MASK); 3702 3703 /* Prime the control register before setting timing values */ 3704 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3705 3706 /* Determine the clockrate of the PCIbus the chip is attached to */ 3707 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3708 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3709 3710 /* setup DMA if needed */ 3711 pciide_channel_dma_setup(cp); 3712 3713 for (drive = 0; drive < 2; drive++) { 3714 drvp = &chp->ch_drive[drive]; 3715 /* If no drive, skip */ 3716 if ((drvp->drive_flags & DRIVE) == 0) { 3717 mode[drive] = -1; 3718 continue; 3719 } 3720 3721 if ((drvp->drive_flags & DRIVE_DMA)) { 3722 /* 3723 * Timings will be used for both PIO and DMA, 3724 * so adjust DMA mode if needed 3725 */ 3726 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3727 drvp->PIO_mode = drvp->DMA_mode + 2; 3728 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3729 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3730 drvp->PIO_mode - 2 : 0; 3731 if (drvp->DMA_mode == 0) 3732 drvp->PIO_mode = 0; 3733 3734 mode[drive] = drvp->DMA_mode + 5; 3735 } else 3736 mode[drive] = drvp->PIO_mode; 3737 3738 if (drive && mode[0] >= 0 && 3739 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3740 /* 3741 * Can't have two drives using different values 3742 * for `Address Setup Time'. 3743 * Slow down the faster drive to compensate. 3744 */ 3745 int d = (opti_tim_as[spd][mode[0]] > 3746 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3747 3748 mode[d] = mode[1-d]; 3749 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3750 chp->ch_drive[d].DMA_mode = 0; 3751 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3752 } 3753 } 3754 3755 for (drive = 0; drive < 2; drive++) { 3756 int m; 3757 if ((m = mode[drive]) < 0) 3758 continue; 3759 3760 /* Set the Address Setup Time and select appropriate index */ 3761 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3762 rv |= OPTI_MISC_INDEX(drive); 3763 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3764 3765 /* Set the pulse width and recovery timing parameters */ 3766 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3767 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3768 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3769 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3770 3771 /* Set the Enhanced Mode register appropriately */ 3772 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3773 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3774 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3775 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3776 } 3777 3778 /* Finally, enable the timings */ 3779 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3780 3781 pciide_print_modes(cp); 3782 } 3783 3784 #define ACARD_IS_850(sc) \ 3785 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3786 3787 void 3788 acard_chip_map(sc, pa) 3789 struct pciide_softc *sc; 3790 struct pci_attach_args *pa; 3791 { 3792 struct pciide_channel *cp; 3793 int i; 3794 pcireg_t interface; 3795 bus_size_t cmdsize, ctlsize; 3796 3797 if (pciide_chipen(sc, pa) == 0) 3798 return; 3799 3800 /* 3801 * when the chip is in native mode it identifies itself as a 3802 * 'misc mass storage'. Fake interface in this case. 3803 */ 3804 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3805 interface = PCI_INTERFACE(pa->pa_class); 3806 } else { 3807 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3808 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3809 } 3810 3811 printf("%s: bus-master DMA support present", 3812 sc->sc_wdcdev.sc_dev.dv_xname); 3813 pciide_mapreg_dma(sc, pa); 3814 printf("\n"); 3815 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3816 WDC_CAPABILITY_MODE; 3817 3818 if (sc->sc_dma_ok) { 3819 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3820 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3821 sc->sc_wdcdev.irqack = pciide_irqack; 3822 } 3823 sc->sc_wdcdev.PIO_cap = 4; 3824 sc->sc_wdcdev.DMA_cap = 2; 3825 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3826 3827 sc->sc_wdcdev.set_modes = acard_setup_channel; 3828 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3829 sc->sc_wdcdev.nchannels = 2; 3830 3831 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3832 cp = &sc->pciide_channels[i]; 3833 if (pciide_chansetup(sc, i, interface) == 0) 3834 continue; 3835 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3836 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3837 &ctlsize, pciide_pci_intr); 3838 } else { 3839 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 3840 &cmdsize, &ctlsize); 3841 } 3842 if (cp->hw_ok == 0) 3843 return; 3844 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3845 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3846 wdcattach(&cp->wdc_channel); 3847 acard_setup_channel(&cp->wdc_channel); 3848 } 3849 if (!ACARD_IS_850(sc)) { 3850 u_int32_t reg; 3851 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3852 reg &= ~ATP860_CTRL_INT; 3853 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3854 } 3855 } 3856 3857 void 3858 acard_setup_channel(chp) 3859 struct channel_softc *chp; 3860 { 3861 struct ata_drive_datas *drvp; 3862 struct pciide_channel *cp = (struct pciide_channel*)chp; 3863 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3864 int channel = chp->channel; 3865 int drive; 3866 u_int32_t idetime, udma_mode; 3867 u_int32_t idedma_ctl; 3868 3869 /* setup DMA if needed */ 3870 pciide_channel_dma_setup(cp); 3871 3872 if (ACARD_IS_850(sc)) { 3873 idetime = 0; 3874 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3875 udma_mode &= ~ATP850_UDMA_MASK(channel); 3876 } else { 3877 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3878 idetime &= ~ATP860_SETTIME_MASK(channel); 3879 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3880 udma_mode &= ~ATP860_UDMA_MASK(channel); 3881 } 3882 3883 idedma_ctl = 0; 3884 3885 /* Per drive settings */ 3886 for (drive = 0; drive < 2; drive++) { 3887 drvp = &chp->ch_drive[drive]; 3888 /* If no drive, skip */ 3889 if ((drvp->drive_flags & DRIVE) == 0) 3890 continue; 3891 /* add timing values, setup DMA if needed */ 3892 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3893 (drvp->drive_flags & DRIVE_UDMA)) { 3894 /* use Ultra/DMA */ 3895 if (ACARD_IS_850(sc)) { 3896 idetime |= ATP850_SETTIME(drive, 3897 acard_act_udma[drvp->UDMA_mode], 3898 acard_rec_udma[drvp->UDMA_mode]); 3899 udma_mode |= ATP850_UDMA_MODE(channel, drive, 3900 acard_udma_conf[drvp->UDMA_mode]); 3901 } else { 3902 idetime |= ATP860_SETTIME(channel, drive, 3903 acard_act_udma[drvp->UDMA_mode], 3904 acard_rec_udma[drvp->UDMA_mode]); 3905 udma_mode |= ATP860_UDMA_MODE(channel, drive, 3906 acard_udma_conf[drvp->UDMA_mode]); 3907 } 3908 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3909 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 3910 (drvp->drive_flags & DRIVE_DMA)) { 3911 /* use Multiword DMA */ 3912 drvp->drive_flags &= ~DRIVE_UDMA; 3913 if (ACARD_IS_850(sc)) { 3914 idetime |= ATP850_SETTIME(drive, 3915 acard_act_dma[drvp->DMA_mode], 3916 acard_rec_dma[drvp->DMA_mode]); 3917 } else { 3918 idetime |= ATP860_SETTIME(channel, drive, 3919 acard_act_dma[drvp->DMA_mode], 3920 acard_rec_dma[drvp->DMA_mode]); 3921 } 3922 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3923 } else { 3924 /* PIO only */ 3925 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 3926 if (ACARD_IS_850(sc)) { 3927 idetime |= ATP850_SETTIME(drive, 3928 acard_act_pio[drvp->PIO_mode], 3929 acard_rec_pio[drvp->PIO_mode]); 3930 } else { 3931 idetime |= ATP860_SETTIME(channel, drive, 3932 acard_act_pio[drvp->PIO_mode], 3933 acard_rec_pio[drvp->PIO_mode]); 3934 } 3935 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 3936 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3937 | ATP8x0_CTRL_EN(channel)); 3938 } 3939 } 3940 3941 if (idedma_ctl != 0) { 3942 /* Add software bits in status register */ 3943 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3944 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 3945 } 3946 pciide_print_modes(cp); 3947 3948 if (ACARD_IS_850(sc)) { 3949 pci_conf_write(sc->sc_pc, sc->sc_tag, 3950 ATP850_IDETIME(channel), idetime); 3951 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 3952 } else { 3953 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 3954 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 3955 } 3956 } 3957 3958 int 3959 acard_pci_intr(arg) 3960 void *arg; 3961 { 3962 struct pciide_softc *sc = arg; 3963 struct pciide_channel *cp; 3964 struct channel_softc *wdc_cp; 3965 int rv = 0; 3966 int dmastat, i, crv; 3967 3968 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3969 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3970 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3971 if ((dmastat & IDEDMA_CTL_INTR) == 0) 3972 continue; 3973 cp = &sc->pciide_channels[i]; 3974 wdc_cp = &cp->wdc_channel; 3975 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 3976 (void)wdcintr(wdc_cp); 3977 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3978 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3979 continue; 3980 } 3981 crv = wdcintr(wdc_cp); 3982 if (crv == 0) 3983 printf("%s:%d: bogus intr\n", 3984 sc->sc_wdcdev.sc_dev.dv_xname, i); 3985 else if (crv == 1) 3986 rv = 1; 3987 else if (rv == 0) 3988 rv = crv; 3989 } 3990 return rv; 3991 } 3992
Indexes created Thu Oct 02 10:09:58 GMT 2025