pciide.c revision 1.132.2.1
1 /* $NetBSD: pciide.c,v 1.132.2.1 2001/11/12 21:18:19 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/pciide_acard_reg.h> 119 #include <dev/pci/cy82c693var.h> 120 121 #include "opt_pciide.h" 122 123 /* inlines for reading/writing 8-bit PCI registers */ 124 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 125 int)); 126 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 127 int, u_int8_t)); 128 129 static __inline u_int8_t 130 pciide_pci_read(pc, pa, reg) 131 pci_chipset_tag_t pc; 132 pcitag_t pa; 133 int reg; 134 { 135 136 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 137 ((reg & 0x03) * 8) & 0xff); 138 } 139 140 static __inline void 141 pciide_pci_write(pc, pa, reg, val) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 u_int8_t val; 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 156 157 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 void piix_setup_channel __P((struct channel_softc*)); 159 void piix3_4_setup_channel __P((struct channel_softc*)); 160 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 161 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 162 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 164 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void amd7x6_setup_channel __P((struct channel_softc*)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 void cmd646_9_irqack __P((struct channel_softc *)); 177 178 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cy693_setup_channel __P((struct channel_softc*)); 180 181 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void sis_setup_channel __P((struct channel_softc*)); 183 static int sis_hostbr_match __P(( struct pci_attach_args *)); 184 185 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void acer_setup_channel __P((struct channel_softc*)); 187 int acer_pci_intr __P((void *)); 188 static int acer_isabr_match __P(( struct pci_attach_args *)); 189 190 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void pdc202xx_setup_channel __P((struct channel_softc*)); 192 int pdc202xx_pci_intr __P((void *)); 193 int pdc20265_pci_intr __P((void *)); 194 195 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void opti_setup_channel __P((struct channel_softc*)); 197 198 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void hpt_setup_channel __P((struct channel_softc*)); 200 int hpt_pci_intr __P((void *)); 201 202 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void acard_setup_channel __P((struct channel_softc*)); 204 int acard_pci_intr __P((void *)); 205 206 #ifdef PCIIDE_WINBOND_ENABLE 207 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 #endif 209 210 void pciide_channel_dma_setup __P((struct pciide_channel *)); 211 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 212 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 213 void pciide_dma_start __P((void*, int, int)); 214 int pciide_dma_finish __P((void*, int, int, int)); 215 void pciide_irqack __P((struct channel_softc *)); 216 void pciide_print_modes __P((struct pciide_channel *)); 217 218 struct pciide_product_desc { 219 u_int32_t ide_product; 220 int ide_flags; 221 const char *ide_name; 222 /* map and setup chip, probe drives */ 223 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 224 }; 225 226 /* Flags for ide_flags */ 227 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 228 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 229 230 /* Default product description for devices not known from this controller */ 231 const struct pciide_product_desc default_product_desc = { 232 0, 233 0, 234 "Generic PCI IDE controller", 235 default_chip_map, 236 }; 237 238 const struct pciide_product_desc pciide_intel_products[] = { 239 { PCI_PRODUCT_INTEL_82092AA, 240 0, 241 "Intel 82092AA IDE controller", 242 default_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82371FB_IDE, 245 0, 246 "Intel 82371FB IDE controller (PIIX)", 247 piix_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_82371SB_IDE, 250 0, 251 "Intel 82371SB IDE Interface (PIIX3)", 252 piix_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82371AB_IDE, 255 0, 256 "Intel 82371AB IDE controller (PIIX4)", 257 piix_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82440MX_IDE, 260 0, 261 "Intel 82440MX IDE controller", 262 piix_chip_map 263 }, 264 { PCI_PRODUCT_INTEL_82801AA_IDE, 265 0, 266 "Intel 82801AA IDE Controller (ICH)", 267 piix_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82801AB_IDE, 270 0, 271 "Intel 82801AB IDE Controller (ICH0)", 272 piix_chip_map, 273 }, 274 { PCI_PRODUCT_INTEL_82801BA_IDE, 275 0, 276 "Intel 82801BA IDE Controller (ICH2)", 277 piix_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_82801BAM_IDE, 280 0, 281 "Intel 82801BAM IDE Controller (ICH2)", 282 piix_chip_map, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 const struct pciide_product_desc pciide_amd_products[] = { 292 { PCI_PRODUCT_AMD_PBC756_IDE, 293 0, 294 "Advanced Micro Devices AMD756 IDE Controller", 295 amd7x6_chip_map 296 }, 297 { PCI_PRODUCT_AMD_PBC766_IDE, 298 0, 299 "Advanced Micro Devices AMD766 IDE Controller", 300 amd7x6_chip_map 301 }, 302 { 0, 303 0, 304 NULL, 305 NULL 306 } 307 }; 308 309 const struct pciide_product_desc pciide_cmd_products[] = { 310 { PCI_PRODUCT_CMDTECH_640, 311 0, 312 "CMD Technology PCI0640", 313 cmd_chip_map 314 }, 315 { PCI_PRODUCT_CMDTECH_643, 316 0, 317 "CMD Technology PCI0643", 318 cmd0643_9_chip_map, 319 }, 320 { PCI_PRODUCT_CMDTECH_646, 321 0, 322 "CMD Technology PCI0646", 323 cmd0643_9_chip_map, 324 }, 325 { PCI_PRODUCT_CMDTECH_648, 326 IDE_PCI_CLASS_OVERRIDE, 327 "CMD Technology PCI0648", 328 cmd0643_9_chip_map, 329 }, 330 { PCI_PRODUCT_CMDTECH_649, 331 IDE_PCI_CLASS_OVERRIDE, 332 "CMD Technology PCI0649", 333 cmd0643_9_chip_map, 334 }, 335 { 0, 336 0, 337 NULL, 338 NULL 339 } 340 }; 341 342 const struct pciide_product_desc pciide_via_products[] = { 343 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 344 0, 345 NULL, 346 apollo_chip_map, 347 }, 348 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 349 0, 350 NULL, 351 apollo_chip_map, 352 }, 353 { 0, 354 0, 355 NULL, 356 NULL 357 } 358 }; 359 360 const struct pciide_product_desc pciide_cypress_products[] = { 361 { PCI_PRODUCT_CONTAQ_82C693, 362 IDE_16BIT_IOSPACE, 363 "Cypress 82C693 IDE Controller", 364 cy693_chip_map, 365 }, 366 { 0, 367 0, 368 NULL, 369 NULL 370 } 371 }; 372 373 const struct pciide_product_desc pciide_sis_products[] = { 374 { PCI_PRODUCT_SIS_5597_IDE, 375 0, 376 "Silicon Integrated System 5597/5598 IDE controller", 377 sis_chip_map, 378 }, 379 { 0, 380 0, 381 NULL, 382 NULL 383 } 384 }; 385 386 const struct pciide_product_desc pciide_acer_products[] = { 387 { PCI_PRODUCT_ALI_M5229, 388 0, 389 "Acer Labs M5229 UDMA IDE Controller", 390 acer_chip_map, 391 }, 392 { 0, 393 0, 394 NULL, 395 NULL 396 } 397 }; 398 399 const struct pciide_product_desc pciide_promise_products[] = { 400 { PCI_PRODUCT_PROMISE_ULTRA33, 401 IDE_PCI_CLASS_OVERRIDE, 402 "Promise Ultra33/ATA Bus Master IDE Accelerator", 403 pdc202xx_chip_map, 404 }, 405 { PCI_PRODUCT_PROMISE_ULTRA66, 406 IDE_PCI_CLASS_OVERRIDE, 407 "Promise Ultra66/ATA Bus Master IDE Accelerator", 408 pdc202xx_chip_map, 409 }, 410 { PCI_PRODUCT_PROMISE_ULTRA100, 411 IDE_PCI_CLASS_OVERRIDE, 412 "Promise Ultra100/ATA Bus Master IDE Accelerator", 413 pdc202xx_chip_map, 414 }, 415 { PCI_PRODUCT_PROMISE_ULTRA100X, 416 IDE_PCI_CLASS_OVERRIDE, 417 "Promise Ultra100/ATA Bus Master IDE Accelerator", 418 pdc202xx_chip_map, 419 }, 420 { 0, 421 0, 422 NULL, 423 NULL 424 } 425 }; 426 427 const struct pciide_product_desc pciide_opti_products[] = { 428 { PCI_PRODUCT_OPTI_82C621, 429 0, 430 "OPTi 82c621 PCI IDE controller", 431 opti_chip_map, 432 }, 433 { PCI_PRODUCT_OPTI_82C568, 434 0, 435 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 436 opti_chip_map, 437 }, 438 { PCI_PRODUCT_OPTI_82D568, 439 0, 440 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 441 opti_chip_map, 442 }, 443 { 0, 444 0, 445 NULL, 446 NULL 447 } 448 }; 449 450 const struct pciide_product_desc pciide_triones_products[] = { 451 { PCI_PRODUCT_TRIONES_HPT366, 452 IDE_PCI_CLASS_OVERRIDE, 453 NULL, 454 hpt_chip_map, 455 }, 456 { 0, 457 0, 458 NULL, 459 NULL 460 } 461 }; 462 463 const struct pciide_product_desc pciide_acard_products[] = { 464 { PCI_PRODUCT_ACARD_ATP850U, 465 IDE_PCI_CLASS_OVERRIDE, 466 "Acard ATP850U Ultra33 IDE Controller", 467 acard_chip_map, 468 }, 469 { PCI_PRODUCT_ACARD_ATP860, 470 IDE_PCI_CLASS_OVERRIDE, 471 "Acard ATP860 Ultra66 IDE Controller", 472 acard_chip_map, 473 }, 474 { PCI_PRODUCT_ACARD_ATP860A, 475 IDE_PCI_CLASS_OVERRIDE, 476 "Acard ATP860-A Ultra66 IDE Controller", 477 acard_chip_map, 478 }, 479 { 0, 480 0, 481 NULL, 482 NULL 483 } 484 }; 485 486 #ifdef PCIIDE_SERVERWORKS_ENABLE 487 const struct pciide_product_desc pciide_serverworks_products[] = { 488 { PCI_PRODUCT_SERVERWORKS_IDE, 489 0, 490 "ServerWorks ROSB4 IDE Controller", 491 piix_chip_map, 492 }, 493 { 0, 494 0, 495 NULL, 496 } 497 }; 498 #endif 499 500 #ifdef PCIIDE_WINBOND_ENABLE 501 const struct pciide_product_desc pciide_winbond_products[] = { 502 { PCI_PRODUCT_WINBOND_W83C553F_1, 503 0, 504 "Winbond W83C553F IDE controller", 505 winbond_chip_map, 506 }, 507 { 0, 508 0, 509 NULL, 510 } 511 }; 512 #endif 513 514 struct pciide_vendor_desc { 515 u_int32_t ide_vendor; 516 const struct pciide_product_desc *ide_products; 517 }; 518 519 const struct pciide_vendor_desc pciide_vendors[] = { 520 { PCI_VENDOR_INTEL, pciide_intel_products }, 521 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 522 { PCI_VENDOR_VIATECH, pciide_via_products }, 523 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 524 { PCI_VENDOR_SIS, pciide_sis_products }, 525 { PCI_VENDOR_ALI, pciide_acer_products }, 526 { PCI_VENDOR_PROMISE, pciide_promise_products }, 527 { PCI_VENDOR_AMD, pciide_amd_products }, 528 { PCI_VENDOR_OPTI, pciide_opti_products }, 529 { PCI_VENDOR_TRIONES, pciide_triones_products }, 530 { PCI_VENDOR_ACARD, pciide_acard_products }, 531 #ifdef PCIIDE_SERVERWORKS_ENABLE 532 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 533 #endif 534 #ifdef PCIIDE_WINBOND_ENABLE 535 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 536 #endif 537 { 0, NULL } 538 }; 539 540 /* options passed via the 'flags' config keyword */ 541 #define PCIIDE_OPTIONS_DMA 0x01 542 #define PCIIDE_OPTIONS_NODMA 0x02 543 544 int pciide_match __P((struct device *, struct cfdata *, void *)); 545 void pciide_attach __P((struct device *, struct device *, void *)); 546 547 struct cfattach pciide_ca = { 548 sizeof(struct pciide_softc), pciide_match, pciide_attach 549 }; 550 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 551 int pciide_mapregs_compat __P(( struct pci_attach_args *, 552 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 553 int pciide_mapregs_native __P((struct pci_attach_args *, 554 struct pciide_channel *, bus_size_t *, bus_size_t *, 555 int (*pci_intr) __P((void *)))); 556 void pciide_mapreg_dma __P((struct pciide_softc *, 557 struct pci_attach_args *)); 558 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 559 void pciide_mapchan __P((struct pci_attach_args *, 560 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 561 int (*pci_intr) __P((void *)))); 562 int pciide_chan_candisable __P((struct pciide_channel *)); 563 void pciide_map_compat_intr __P(( struct pci_attach_args *, 564 struct pciide_channel *, int, int)); 565 int pciide_compat_intr __P((void *)); 566 int pciide_pci_intr __P((void *)); 567 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 568 569 const struct pciide_product_desc * 570 pciide_lookup_product(id) 571 u_int32_t id; 572 { 573 const struct pciide_product_desc *pp; 574 const struct pciide_vendor_desc *vp; 575 576 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 577 if (PCI_VENDOR(id) == vp->ide_vendor) 578 break; 579 580 if ((pp = vp->ide_products) == NULL) 581 return NULL; 582 583 for (; pp->chip_map != NULL; pp++) 584 if (PCI_PRODUCT(id) == pp->ide_product) 585 break; 586 587 if (pp->chip_map == NULL) 588 return NULL; 589 return pp; 590 } 591 592 int 593 pciide_match(parent, match, aux) 594 struct device *parent; 595 struct cfdata *match; 596 void *aux; 597 { 598 struct pci_attach_args *pa = aux; 599 const struct pciide_product_desc *pp; 600 601 /* 602 * Check the ID register to see that it's a PCI IDE controller. 603 * If it is, we assume that we can deal with it; it _should_ 604 * work in a standardized way... 605 */ 606 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 607 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 608 return (1); 609 } 610 611 /* 612 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 613 * controllers. Let see if we can deal with it anyway. 614 */ 615 pp = pciide_lookup_product(pa->pa_id); 616 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 617 return (1); 618 } 619 620 return (0); 621 } 622 623 void 624 pciide_attach(parent, self, aux) 625 struct device *parent, *self; 626 void *aux; 627 { 628 struct pci_attach_args *pa = aux; 629 pci_chipset_tag_t pc = pa->pa_pc; 630 pcitag_t tag = pa->pa_tag; 631 struct pciide_softc *sc = (struct pciide_softc *)self; 632 pcireg_t csr; 633 char devinfo[256]; 634 const char *displaydev; 635 636 sc->sc_pp = pciide_lookup_product(pa->pa_id); 637 if (sc->sc_pp == NULL) { 638 sc->sc_pp = &default_product_desc; 639 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 640 displaydev = devinfo; 641 } else 642 displaydev = sc->sc_pp->ide_name; 643 644 /* if displaydev == NULL, printf is done in chip-specific map */ 645 if (displaydev) 646 printf(": %s (rev. 0x%02x)\n", displaydev, 647 PCI_REVISION(pa->pa_class)); 648 649 sc->sc_pc = pa->pa_pc; 650 sc->sc_tag = pa->pa_tag; 651 #ifdef WDCDEBUG 652 if (wdcdebug_pciide_mask & DEBUG_PROBE) 653 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 654 #endif 655 sc->sc_pp->chip_map(sc, pa); 656 657 if (sc->sc_dma_ok) { 658 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 659 csr |= PCI_COMMAND_MASTER_ENABLE; 660 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 661 } 662 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 663 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 664 } 665 666 /* tell wether the chip is enabled or not */ 667 int 668 pciide_chipen(sc, pa) 669 struct pciide_softc *sc; 670 struct pci_attach_args *pa; 671 { 672 pcireg_t csr; 673 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 674 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 675 PCI_COMMAND_STATUS_REG); 676 printf("%s: device disabled (at %s)\n", 677 sc->sc_wdcdev.sc_dev.dv_xname, 678 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 679 "device" : "bridge"); 680 return 0; 681 } 682 return 1; 683 } 684 685 int 686 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 687 struct pci_attach_args *pa; 688 struct pciide_channel *cp; 689 int compatchan; 690 bus_size_t *cmdsizep, *ctlsizep; 691 { 692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 693 struct channel_softc *wdc_cp = &cp->wdc_channel; 694 695 cp->compat = 1; 696 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 697 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 698 699 wdc_cp->cmd_iot = pa->pa_iot; 700 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 701 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 702 printf("%s: couldn't map %s channel cmd regs\n", 703 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 704 return (0); 705 } 706 707 wdc_cp->ctl_iot = pa->pa_iot; 708 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 709 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 710 printf("%s: couldn't map %s channel ctl regs\n", 711 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 712 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 713 PCIIDE_COMPAT_CMD_SIZE); 714 return (0); 715 } 716 717 return (1); 718 } 719 720 int 721 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 722 struct pci_attach_args * pa; 723 struct pciide_channel *cp; 724 bus_size_t *cmdsizep, *ctlsizep; 725 int (*pci_intr) __P((void *)); 726 { 727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 728 struct channel_softc *wdc_cp = &cp->wdc_channel; 729 const char *intrstr; 730 pci_intr_handle_t intrhandle; 731 732 cp->compat = 0; 733 734 if (sc->sc_pci_ih == NULL) { 735 if (pci_intr_map(pa, &intrhandle) != 0) { 736 printf("%s: couldn't map native-PCI interrupt\n", 737 sc->sc_wdcdev.sc_dev.dv_xname); 738 return 0; 739 } 740 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 741 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 742 intrhandle, IPL_BIO, pci_intr, sc); 743 if (sc->sc_pci_ih != NULL) { 744 printf("%s: using %s for native-PCI interrupt\n", 745 sc->sc_wdcdev.sc_dev.dv_xname, 746 intrstr ? intrstr : "unknown interrupt"); 747 } else { 748 printf("%s: couldn't establish native-PCI interrupt", 749 sc->sc_wdcdev.sc_dev.dv_xname); 750 if (intrstr != NULL) 751 printf(" at %s", intrstr); 752 printf("\n"); 753 return 0; 754 } 755 } 756 cp->ih = sc->sc_pci_ih; 757 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 758 PCI_MAPREG_TYPE_IO, 0, 759 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 760 printf("%s: couldn't map %s channel cmd regs\n", 761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 762 return 0; 763 } 764 765 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 766 PCI_MAPREG_TYPE_IO, 0, 767 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 768 printf("%s: couldn't map %s channel ctl regs\n", 769 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 770 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 771 return 0; 772 } 773 /* 774 * In native mode, 4 bytes of I/O space are mapped for the control 775 * register, the control register is at offset 2. Pass the generic 776 * code a handle for only one byte at the rigth offset. 777 */ 778 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 779 &wdc_cp->ctl_ioh) != 0) { 780 printf("%s: unable to subregion %s channel ctl regs\n", 781 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 782 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 783 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 784 return 0; 785 } 786 return (1); 787 } 788 789 void 790 pciide_mapreg_dma(sc, pa) 791 struct pciide_softc *sc; 792 struct pci_attach_args *pa; 793 { 794 pcireg_t maptype; 795 bus_addr_t addr; 796 797 /* 798 * Map DMA registers 799 * 800 * Note that sc_dma_ok is the right variable to test to see if 801 * DMA can be done. If the interface doesn't support DMA, 802 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 803 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 804 * non-zero if the interface supports DMA and the registers 805 * could be mapped. 806 * 807 * XXX Note that despite the fact that the Bus Master IDE specs 808 * XXX say that "The bus master IDE function uses 16 bytes of IO 809 * XXX space," some controllers (at least the United 810 * XXX Microelectronics UM8886BF) place it in memory space. 811 */ 812 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 813 PCIIDE_REG_BUS_MASTER_DMA); 814 815 switch (maptype) { 816 case PCI_MAPREG_TYPE_IO: 817 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 818 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 819 &addr, NULL, NULL) == 0); 820 if (sc->sc_dma_ok == 0) { 821 printf(", but unused (couldn't query registers)"); 822 break; 823 } 824 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 825 && addr >= 0x10000) { 826 sc->sc_dma_ok = 0; 827 printf(", but unused (registers at unsafe address " 828 "%#lx)", (unsigned long)addr); 829 break; 830 } 831 /* FALLTHROUGH */ 832 833 case PCI_MAPREG_MEM_TYPE_32BIT: 834 sc->sc_dma_ok = (pci_mapreg_map(pa, 835 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 836 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 837 sc->sc_dmat = pa->pa_dmat; 838 if (sc->sc_dma_ok == 0) { 839 printf(", but unused (couldn't map registers)"); 840 } else { 841 sc->sc_wdcdev.dma_arg = sc; 842 sc->sc_wdcdev.dma_init = pciide_dma_init; 843 sc->sc_wdcdev.dma_start = pciide_dma_start; 844 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 845 } 846 847 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 848 PCIIDE_OPTIONS_NODMA) { 849 printf(", but unused (forced off by config file)"); 850 sc->sc_dma_ok = 0; 851 } 852 break; 853 854 default: 855 sc->sc_dma_ok = 0; 856 printf(", but unsupported register maptype (0x%x)", maptype); 857 } 858 } 859 860 int 861 pciide_compat_intr(arg) 862 void *arg; 863 { 864 struct pciide_channel *cp = arg; 865 866 #ifdef DIAGNOSTIC 867 /* should only be called for a compat channel */ 868 if (cp->compat == 0) 869 panic("pciide compat intr called for non-compat chan %p\n", cp); 870 #endif 871 return (wdcintr(&cp->wdc_channel)); 872 } 873 874 int 875 pciide_pci_intr(arg) 876 void *arg; 877 { 878 struct pciide_softc *sc = arg; 879 struct pciide_channel *cp; 880 struct channel_softc *wdc_cp; 881 int i, rv, crv; 882 883 rv = 0; 884 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 885 cp = &sc->pciide_channels[i]; 886 wdc_cp = &cp->wdc_channel; 887 888 /* If a compat channel skip. */ 889 if (cp->compat) 890 continue; 891 /* if this channel not waiting for intr, skip */ 892 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 893 continue; 894 895 crv = wdcintr(wdc_cp); 896 if (crv == 0) 897 ; /* leave rv alone */ 898 else if (crv == 1) 899 rv = 1; /* claim the intr */ 900 else if (rv == 0) /* crv should be -1 in this case */ 901 rv = crv; /* if we've done no better, take it */ 902 } 903 return (rv); 904 } 905 906 void 907 pciide_channel_dma_setup(cp) 908 struct pciide_channel *cp; 909 { 910 int drive; 911 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 912 struct ata_drive_datas *drvp; 913 914 for (drive = 0; drive < 2; drive++) { 915 drvp = &cp->wdc_channel.ch_drive[drive]; 916 /* If no drive, skip */ 917 if ((drvp->drive_flags & DRIVE) == 0) 918 continue; 919 /* setup DMA if needed */ 920 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 921 (drvp->drive_flags & DRIVE_UDMA) == 0) || 922 sc->sc_dma_ok == 0) { 923 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 924 continue; 925 } 926 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 927 != 0) { 928 /* Abort DMA setup */ 929 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 930 continue; 931 } 932 } 933 } 934 935 int 936 pciide_dma_table_setup(sc, channel, drive) 937 struct pciide_softc *sc; 938 int channel, drive; 939 { 940 bus_dma_segment_t seg; 941 int error, rseg; 942 const bus_size_t dma_table_size = 943 sizeof(struct idedma_table) * NIDEDMA_TABLES; 944 struct pciide_dma_maps *dma_maps = 945 &sc->pciide_channels[channel].dma_maps[drive]; 946 947 /* If table was already allocated, just return */ 948 if (dma_maps->dma_table) 949 return 0; 950 951 /* Allocate memory for the DMA tables and map it */ 952 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 953 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 954 BUS_DMA_NOWAIT)) != 0) { 955 printf("%s:%d: unable to allocate table DMA for " 956 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 957 channel, drive, error); 958 return error; 959 } 960 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 961 dma_table_size, 962 (caddr_t *)&dma_maps->dma_table, 963 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 964 printf("%s:%d: unable to map table DMA for" 965 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 966 channel, drive, error); 967 return error; 968 } 969 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 970 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 971 (unsigned long)seg.ds_addr), DEBUG_PROBE); 972 973 /* Create and load table DMA map for this disk */ 974 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 975 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 976 &dma_maps->dmamap_table)) != 0) { 977 printf("%s:%d: unable to create table DMA map for " 978 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 979 channel, drive, error); 980 return error; 981 } 982 if ((error = bus_dmamap_load(sc->sc_dmat, 983 dma_maps->dmamap_table, 984 dma_maps->dma_table, 985 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 986 printf("%s:%d: unable to load table DMA map for " 987 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 988 channel, drive, error); 989 return error; 990 } 991 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 992 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 993 DEBUG_PROBE); 994 /* Create a xfer DMA map for this drive */ 995 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 996 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 997 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 998 &dma_maps->dmamap_xfer)) != 0) { 999 printf("%s:%d: unable to create xfer DMA map for " 1000 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1001 channel, drive, error); 1002 return error; 1003 } 1004 return 0; 1005 } 1006 1007 int 1008 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1009 void *v; 1010 int channel, drive; 1011 void *databuf; 1012 size_t datalen; 1013 int flags; 1014 { 1015 struct pciide_softc *sc = v; 1016 int error, seg; 1017 struct pciide_dma_maps *dma_maps = 1018 &sc->pciide_channels[channel].dma_maps[drive]; 1019 1020 error = bus_dmamap_load(sc->sc_dmat, 1021 dma_maps->dmamap_xfer, 1022 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1023 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1024 if (error) { 1025 printf("%s:%d: unable to load xfer DMA map for" 1026 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1027 channel, drive, error); 1028 return error; 1029 } 1030 1031 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1032 dma_maps->dmamap_xfer->dm_mapsize, 1033 (flags & WDC_DMA_READ) ? 1034 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1035 1036 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1037 #ifdef DIAGNOSTIC 1038 /* A segment must not cross a 64k boundary */ 1039 { 1040 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1041 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1042 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1043 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1044 printf("pciide_dma: segment %d physical addr 0x%lx" 1045 " len 0x%lx not properly aligned\n", 1046 seg, phys, len); 1047 panic("pciide_dma: buf align"); 1048 } 1049 } 1050 #endif 1051 dma_maps->dma_table[seg].base_addr = 1052 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1053 dma_maps->dma_table[seg].byte_count = 1054 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1055 IDEDMA_BYTE_COUNT_MASK); 1056 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1057 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1058 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1059 1060 } 1061 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1062 htole32(IDEDMA_BYTE_COUNT_EOT); 1063 1064 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1065 dma_maps->dmamap_table->dm_mapsize, 1066 BUS_DMASYNC_PREWRITE); 1067 1068 /* Maps are ready. Start DMA function */ 1069 #ifdef DIAGNOSTIC 1070 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1071 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1072 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1073 panic("pciide_dma_init: table align"); 1074 } 1075 #endif 1076 1077 /* Clear status bits */ 1078 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1079 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1080 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1081 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1082 /* Write table addr */ 1083 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1084 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1085 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1086 /* set read/write */ 1087 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1088 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1089 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1090 /* remember flags */ 1091 dma_maps->dma_flags = flags; 1092 return 0; 1093 } 1094 1095 void 1096 pciide_dma_start(v, channel, drive) 1097 void *v; 1098 int channel, drive; 1099 { 1100 struct pciide_softc *sc = v; 1101 1102 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1103 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1104 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1105 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1106 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1107 } 1108 1109 int 1110 pciide_dma_finish(v, channel, drive, force) 1111 void *v; 1112 int channel, drive; 1113 int force; 1114 { 1115 struct pciide_softc *sc = v; 1116 u_int8_t status; 1117 int error = 0; 1118 struct pciide_dma_maps *dma_maps = 1119 &sc->pciide_channels[channel].dma_maps[drive]; 1120 1121 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1122 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1123 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1124 DEBUG_XFERS); 1125 1126 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1127 return WDC_DMAST_NOIRQ; 1128 1129 /* stop DMA channel */ 1130 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1131 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1132 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1133 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1134 1135 /* Unload the map of the data buffer */ 1136 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1137 dma_maps->dmamap_xfer->dm_mapsize, 1138 (dma_maps->dma_flags & WDC_DMA_READ) ? 1139 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1140 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1141 1142 if ((status & IDEDMA_CTL_ERR) != 0) { 1143 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1144 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1145 error |= WDC_DMAST_ERR; 1146 } 1147 1148 if ((status & IDEDMA_CTL_INTR) == 0) { 1149 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1150 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1151 drive, status); 1152 error |= WDC_DMAST_NOIRQ; 1153 } 1154 1155 if ((status & IDEDMA_CTL_ACT) != 0) { 1156 /* data underrun, may be a valid condition for ATAPI */ 1157 error |= WDC_DMAST_UNDER; 1158 } 1159 return error; 1160 } 1161 1162 void 1163 pciide_irqack(chp) 1164 struct channel_softc *chp; 1165 { 1166 struct pciide_channel *cp = (struct pciide_channel*)chp; 1167 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1168 1169 /* clear status bits in IDE DMA registers */ 1170 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1171 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1172 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1173 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1174 } 1175 1176 /* some common code used by several chip_map */ 1177 int 1178 pciide_chansetup(sc, channel, interface) 1179 struct pciide_softc *sc; 1180 int channel; 1181 pcireg_t interface; 1182 { 1183 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1184 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1185 cp->name = PCIIDE_CHANNEL_NAME(channel); 1186 cp->wdc_channel.channel = channel; 1187 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1188 cp->wdc_channel.ch_queue = 1189 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1190 if (cp->wdc_channel.ch_queue == NULL) { 1191 printf("%s %s channel: " 1192 "can't allocate memory for command queue", 1193 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1194 return 0; 1195 } 1196 printf("%s: %s channel %s to %s mode\n", 1197 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1198 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1199 "configured" : "wired", 1200 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1201 "native-PCI" : "compatibility"); 1202 return 1; 1203 } 1204 1205 /* some common code used by several chip channel_map */ 1206 void 1207 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1208 struct pci_attach_args *pa; 1209 struct pciide_channel *cp; 1210 pcireg_t interface; 1211 bus_size_t *cmdsizep, *ctlsizep; 1212 int (*pci_intr) __P((void *)); 1213 { 1214 struct channel_softc *wdc_cp = &cp->wdc_channel; 1215 1216 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1217 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1218 pci_intr); 1219 else 1220 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1221 wdc_cp->channel, cmdsizep, ctlsizep); 1222 1223 if (cp->hw_ok == 0) 1224 return; 1225 wdc_cp->data32iot = wdc_cp->cmd_iot; 1226 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1227 wdcattach(wdc_cp); 1228 } 1229 1230 /* 1231 * Generic code to call to know if a channel can be disabled. Return 1 1232 * if channel can be disabled, 0 if not 1233 */ 1234 int 1235 pciide_chan_candisable(cp) 1236 struct pciide_channel *cp; 1237 { 1238 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1239 struct channel_softc *wdc_cp = &cp->wdc_channel; 1240 1241 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1242 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1243 printf("%s: disabling %s channel (no drives)\n", 1244 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1245 cp->hw_ok = 0; 1246 return 1; 1247 } 1248 return 0; 1249 } 1250 1251 /* 1252 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1253 * Set hw_ok=0 on failure 1254 */ 1255 void 1256 pciide_map_compat_intr(pa, cp, compatchan, interface) 1257 struct pci_attach_args *pa; 1258 struct pciide_channel *cp; 1259 int compatchan, interface; 1260 { 1261 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1262 struct channel_softc *wdc_cp = &cp->wdc_channel; 1263 1264 if (cp->hw_ok == 0) 1265 return; 1266 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1267 return; 1268 1269 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1270 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1271 pa, compatchan, pciide_compat_intr, cp); 1272 if (cp->ih == NULL) { 1273 #endif 1274 printf("%s: no compatibility interrupt for use by %s " 1275 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1276 cp->hw_ok = 0; 1277 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1278 } 1279 #endif 1280 } 1281 1282 void 1283 pciide_print_modes(cp) 1284 struct pciide_channel *cp; 1285 { 1286 wdc_print_modes(&cp->wdc_channel); 1287 } 1288 1289 void 1290 default_chip_map(sc, pa) 1291 struct pciide_softc *sc; 1292 struct pci_attach_args *pa; 1293 { 1294 struct pciide_channel *cp; 1295 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1296 pcireg_t csr; 1297 int channel, drive; 1298 struct ata_drive_datas *drvp; 1299 u_int8_t idedma_ctl; 1300 bus_size_t cmdsize, ctlsize; 1301 char *failreason; 1302 1303 if (pciide_chipen(sc, pa) == 0) 1304 return; 1305 1306 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1307 printf("%s: bus-master DMA support present", 1308 sc->sc_wdcdev.sc_dev.dv_xname); 1309 if (sc->sc_pp == &default_product_desc && 1310 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1311 PCIIDE_OPTIONS_DMA) == 0) { 1312 printf(", but unused (no driver support)"); 1313 sc->sc_dma_ok = 0; 1314 } else { 1315 pciide_mapreg_dma(sc, pa); 1316 if (sc->sc_dma_ok != 0) 1317 printf(", used without full driver " 1318 "support"); 1319 } 1320 } else { 1321 printf("%s: hardware does not support DMA", 1322 sc->sc_wdcdev.sc_dev.dv_xname); 1323 sc->sc_dma_ok = 0; 1324 } 1325 printf("\n"); 1326 if (sc->sc_dma_ok) { 1327 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1328 sc->sc_wdcdev.irqack = pciide_irqack; 1329 } 1330 sc->sc_wdcdev.PIO_cap = 0; 1331 sc->sc_wdcdev.DMA_cap = 0; 1332 1333 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1334 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1335 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1336 1337 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1338 cp = &sc->pciide_channels[channel]; 1339 if (pciide_chansetup(sc, channel, interface) == 0) 1340 continue; 1341 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1342 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1343 &ctlsize, pciide_pci_intr); 1344 } else { 1345 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1346 channel, &cmdsize, &ctlsize); 1347 } 1348 if (cp->hw_ok == 0) 1349 continue; 1350 /* 1351 * Check to see if something appears to be there. 1352 */ 1353 failreason = NULL; 1354 if (!wdcprobe(&cp->wdc_channel)) { 1355 failreason = "not responding; disabled or no drives?"; 1356 goto next; 1357 } 1358 /* 1359 * Now, make sure it's actually attributable to this PCI IDE 1360 * channel by trying to access the channel again while the 1361 * PCI IDE controller's I/O space is disabled. (If the 1362 * channel no longer appears to be there, it belongs to 1363 * this controller.) YUCK! 1364 */ 1365 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1366 PCI_COMMAND_STATUS_REG); 1367 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1368 csr & ~PCI_COMMAND_IO_ENABLE); 1369 if (wdcprobe(&cp->wdc_channel)) 1370 failreason = "other hardware responding at addresses"; 1371 pci_conf_write(sc->sc_pc, sc->sc_tag, 1372 PCI_COMMAND_STATUS_REG, csr); 1373 next: 1374 if (failreason) { 1375 printf("%s: %s channel ignored (%s)\n", 1376 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1377 failreason); 1378 cp->hw_ok = 0; 1379 bus_space_unmap(cp->wdc_channel.cmd_iot, 1380 cp->wdc_channel.cmd_ioh, cmdsize); 1381 bus_space_unmap(cp->wdc_channel.ctl_iot, 1382 cp->wdc_channel.ctl_ioh, ctlsize); 1383 } else { 1384 pciide_map_compat_intr(pa, cp, channel, interface); 1385 } 1386 if (cp->hw_ok) { 1387 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1388 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1389 wdcattach(&cp->wdc_channel); 1390 } 1391 } 1392 1393 if (sc->sc_dma_ok == 0) 1394 return; 1395 1396 /* Allocate DMA maps */ 1397 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1398 idedma_ctl = 0; 1399 cp = &sc->pciide_channels[channel]; 1400 for (drive = 0; drive < 2; drive++) { 1401 drvp = &cp->wdc_channel.ch_drive[drive]; 1402 /* If no drive, skip */ 1403 if ((drvp->drive_flags & DRIVE) == 0) 1404 continue; 1405 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1406 continue; 1407 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1408 /* Abort DMA setup */ 1409 printf("%s:%d:%d: can't allocate DMA maps, " 1410 "using PIO transfers\n", 1411 sc->sc_wdcdev.sc_dev.dv_xname, 1412 channel, drive); 1413 drvp->drive_flags &= ~DRIVE_DMA; 1414 } 1415 printf("%s:%d:%d: using DMA data transfers\n", 1416 sc->sc_wdcdev.sc_dev.dv_xname, 1417 channel, drive); 1418 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1419 } 1420 if (idedma_ctl != 0) { 1421 /* Add software bits in status register */ 1422 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1423 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1424 idedma_ctl); 1425 } 1426 } 1427 } 1428 1429 void 1430 piix_chip_map(sc, pa) 1431 struct pciide_softc *sc; 1432 struct pci_attach_args *pa; 1433 { 1434 struct pciide_channel *cp; 1435 int channel; 1436 u_int32_t idetim; 1437 bus_size_t cmdsize, ctlsize; 1438 1439 if (pciide_chipen(sc, pa) == 0) 1440 return; 1441 1442 printf("%s: bus-master DMA support present", 1443 sc->sc_wdcdev.sc_dev.dv_xname); 1444 pciide_mapreg_dma(sc, pa); 1445 printf("\n"); 1446 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1447 WDC_CAPABILITY_MODE; 1448 if (sc->sc_dma_ok) { 1449 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1450 sc->sc_wdcdev.irqack = pciide_irqack; 1451 switch(sc->sc_pp->ide_product) { 1452 case PCI_PRODUCT_INTEL_82371AB_IDE: 1453 case PCI_PRODUCT_INTEL_82440MX_IDE: 1454 case PCI_PRODUCT_INTEL_82801AA_IDE: 1455 case PCI_PRODUCT_INTEL_82801AB_IDE: 1456 case PCI_PRODUCT_INTEL_82801BA_IDE: 1457 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1458 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1459 } 1460 } 1461 sc->sc_wdcdev.PIO_cap = 4; 1462 sc->sc_wdcdev.DMA_cap = 2; 1463 switch(sc->sc_pp->ide_product) { 1464 case PCI_PRODUCT_INTEL_82801AA_IDE: 1465 sc->sc_wdcdev.UDMA_cap = 4; 1466 break; 1467 case PCI_PRODUCT_INTEL_82801BA_IDE: 1468 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1469 sc->sc_wdcdev.UDMA_cap = 5; 1470 break; 1471 default: 1472 sc->sc_wdcdev.UDMA_cap = 2; 1473 } 1474 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1475 sc->sc_wdcdev.set_modes = piix_setup_channel; 1476 else 1477 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1478 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1479 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1480 1481 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1482 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1483 DEBUG_PROBE); 1484 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1485 WDCDEBUG_PRINT((", sidetim=0x%x", 1486 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1487 DEBUG_PROBE); 1488 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1489 WDCDEBUG_PRINT((", udamreg 0x%x", 1490 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1491 DEBUG_PROBE); 1492 } 1493 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1494 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1495 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1496 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1497 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1498 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1499 DEBUG_PROBE); 1500 } 1501 1502 } 1503 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1504 1505 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1506 cp = &sc->pciide_channels[channel]; 1507 /* PIIX is compat-only */ 1508 if (pciide_chansetup(sc, channel, 0) == 0) 1509 continue; 1510 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1511 if ((PIIX_IDETIM_READ(idetim, channel) & 1512 PIIX_IDETIM_IDE) == 0) { 1513 printf("%s: %s channel ignored (disabled)\n", 1514 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1515 continue; 1516 } 1517 /* PIIX are compat-only pciide devices */ 1518 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1519 if (cp->hw_ok == 0) 1520 continue; 1521 if (pciide_chan_candisable(cp)) { 1522 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1523 channel); 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1525 idetim); 1526 } 1527 pciide_map_compat_intr(pa, cp, channel, 0); 1528 if (cp->hw_ok == 0) 1529 continue; 1530 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1531 } 1532 1533 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1534 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1535 DEBUG_PROBE); 1536 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1537 WDCDEBUG_PRINT((", sidetim=0x%x", 1538 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1539 DEBUG_PROBE); 1540 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1541 WDCDEBUG_PRINT((", udamreg 0x%x", 1542 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1543 DEBUG_PROBE); 1544 } 1545 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1549 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1550 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1551 DEBUG_PROBE); 1552 } 1553 } 1554 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1555 } 1556 1557 void 1558 piix_setup_channel(chp) 1559 struct channel_softc *chp; 1560 { 1561 u_int8_t mode[2], drive; 1562 u_int32_t oidetim, idetim, idedma_ctl; 1563 struct pciide_channel *cp = (struct pciide_channel*)chp; 1564 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1565 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1566 1567 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1568 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1569 idedma_ctl = 0; 1570 1571 /* set up new idetim: Enable IDE registers decode */ 1572 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1573 chp->channel); 1574 1575 /* setup DMA */ 1576 pciide_channel_dma_setup(cp); 1577 1578 /* 1579 * Here we have to mess up with drives mode: PIIX can't have 1580 * different timings for master and slave drives. 1581 * We need to find the best combination. 1582 */ 1583 1584 /* If both drives supports DMA, take the lower mode */ 1585 if ((drvp[0].drive_flags & DRIVE_DMA) && 1586 (drvp[1].drive_flags & DRIVE_DMA)) { 1587 mode[0] = mode[1] = 1588 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1589 drvp[0].DMA_mode = mode[0]; 1590 drvp[1].DMA_mode = mode[1]; 1591 goto ok; 1592 } 1593 /* 1594 * If only one drive supports DMA, use its mode, and 1595 * put the other one in PIO mode 0 if mode not compatible 1596 */ 1597 if (drvp[0].drive_flags & DRIVE_DMA) { 1598 mode[0] = drvp[0].DMA_mode; 1599 mode[1] = drvp[1].PIO_mode; 1600 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1601 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1602 mode[1] = drvp[1].PIO_mode = 0; 1603 goto ok; 1604 } 1605 if (drvp[1].drive_flags & DRIVE_DMA) { 1606 mode[1] = drvp[1].DMA_mode; 1607 mode[0] = drvp[0].PIO_mode; 1608 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1609 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1610 mode[0] = drvp[0].PIO_mode = 0; 1611 goto ok; 1612 } 1613 /* 1614 * If both drives are not DMA, takes the lower mode, unless 1615 * one of them is PIO mode < 2 1616 */ 1617 if (drvp[0].PIO_mode < 2) { 1618 mode[0] = drvp[0].PIO_mode = 0; 1619 mode[1] = drvp[1].PIO_mode; 1620 } else if (drvp[1].PIO_mode < 2) { 1621 mode[1] = drvp[1].PIO_mode = 0; 1622 mode[0] = drvp[0].PIO_mode; 1623 } else { 1624 mode[0] = mode[1] = 1625 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1626 drvp[0].PIO_mode = mode[0]; 1627 drvp[1].PIO_mode = mode[1]; 1628 } 1629 ok: /* The modes are setup */ 1630 for (drive = 0; drive < 2; drive++) { 1631 if (drvp[drive].drive_flags & DRIVE_DMA) { 1632 idetim |= piix_setup_idetim_timings( 1633 mode[drive], 1, chp->channel); 1634 goto end; 1635 } 1636 } 1637 /* If we are there, none of the drives are DMA */ 1638 if (mode[0] >= 2) 1639 idetim |= piix_setup_idetim_timings( 1640 mode[0], 0, chp->channel); 1641 else 1642 idetim |= piix_setup_idetim_timings( 1643 mode[1], 0, chp->channel); 1644 end: /* 1645 * timing mode is now set up in the controller. Enable 1646 * it per-drive 1647 */ 1648 for (drive = 0; drive < 2; drive++) { 1649 /* If no drive, skip */ 1650 if ((drvp[drive].drive_flags & DRIVE) == 0) 1651 continue; 1652 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1653 if (drvp[drive].drive_flags & DRIVE_DMA) 1654 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1655 } 1656 if (idedma_ctl != 0) { 1657 /* Add software bits in status register */ 1658 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1659 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1660 idedma_ctl); 1661 } 1662 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1663 pciide_print_modes(cp); 1664 } 1665 1666 void 1667 piix3_4_setup_channel(chp) 1668 struct channel_softc *chp; 1669 { 1670 struct ata_drive_datas *drvp; 1671 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1672 struct pciide_channel *cp = (struct pciide_channel*)chp; 1673 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1674 int drive; 1675 int channel = chp->channel; 1676 1677 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1678 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1679 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1680 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1681 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1682 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1683 PIIX_SIDETIM_RTC_MASK(channel)); 1684 1685 idedma_ctl = 0; 1686 /* If channel disabled, no need to go further */ 1687 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1688 return; 1689 /* set up new idetim: Enable IDE registers decode */ 1690 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1691 1692 /* setup DMA if needed */ 1693 pciide_channel_dma_setup(cp); 1694 1695 for (drive = 0; drive < 2; drive++) { 1696 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1697 PIIX_UDMATIM_SET(0x3, channel, drive)); 1698 drvp = &chp->ch_drive[drive]; 1699 /* If no drive, skip */ 1700 if ((drvp->drive_flags & DRIVE) == 0) 1701 continue; 1702 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1703 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1704 goto pio; 1705 1706 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1707 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1708 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1709 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1710 ideconf |= PIIX_CONFIG_PINGPONG; 1711 } 1712 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1713 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1714 /* setup Ultra/100 */ 1715 if (drvp->UDMA_mode > 2 && 1716 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1717 drvp->UDMA_mode = 2; 1718 if (drvp->UDMA_mode > 4) { 1719 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1720 } else { 1721 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1722 if (drvp->UDMA_mode > 2) { 1723 ideconf |= PIIX_CONFIG_UDMA66(channel, 1724 drive); 1725 } else { 1726 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1727 drive); 1728 } 1729 } 1730 } 1731 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1732 /* setup Ultra/66 */ 1733 if (drvp->UDMA_mode > 2 && 1734 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1735 drvp->UDMA_mode = 2; 1736 if (drvp->UDMA_mode > 2) 1737 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1738 else 1739 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1740 } 1741 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1742 (drvp->drive_flags & DRIVE_UDMA)) { 1743 /* use Ultra/DMA */ 1744 drvp->drive_flags &= ~DRIVE_DMA; 1745 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1746 udmareg |= PIIX_UDMATIM_SET( 1747 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1748 } else { 1749 /* use Multiword DMA */ 1750 drvp->drive_flags &= ~DRIVE_UDMA; 1751 if (drive == 0) { 1752 idetim |= piix_setup_idetim_timings( 1753 drvp->DMA_mode, 1, channel); 1754 } else { 1755 sidetim |= piix_setup_sidetim_timings( 1756 drvp->DMA_mode, 1, channel); 1757 idetim =PIIX_IDETIM_SET(idetim, 1758 PIIX_IDETIM_SITRE, channel); 1759 } 1760 } 1761 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1762 1763 pio: /* use PIO mode */ 1764 idetim |= piix_setup_idetim_drvs(drvp); 1765 if (drive == 0) { 1766 idetim |= piix_setup_idetim_timings( 1767 drvp->PIO_mode, 0, channel); 1768 } else { 1769 sidetim |= piix_setup_sidetim_timings( 1770 drvp->PIO_mode, 0, channel); 1771 idetim =PIIX_IDETIM_SET(idetim, 1772 PIIX_IDETIM_SITRE, channel); 1773 } 1774 } 1775 if (idedma_ctl != 0) { 1776 /* Add software bits in status register */ 1777 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1778 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1779 idedma_ctl); 1780 } 1781 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1782 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1783 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1784 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1785 pciide_print_modes(cp); 1786 } 1787 1788 1789 /* setup ISP and RTC fields, based on mode */ 1790 static u_int32_t 1791 piix_setup_idetim_timings(mode, dma, channel) 1792 u_int8_t mode; 1793 u_int8_t dma; 1794 u_int8_t channel; 1795 { 1796 1797 if (dma) 1798 return PIIX_IDETIM_SET(0, 1799 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1800 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1801 channel); 1802 else 1803 return PIIX_IDETIM_SET(0, 1804 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1805 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1806 channel); 1807 } 1808 1809 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1810 static u_int32_t 1811 piix_setup_idetim_drvs(drvp) 1812 struct ata_drive_datas *drvp; 1813 { 1814 u_int32_t ret = 0; 1815 struct channel_softc *chp = drvp->chnl_softc; 1816 u_int8_t channel = chp->channel; 1817 u_int8_t drive = drvp->drive; 1818 1819 /* 1820 * If drive is using UDMA, timings setups are independant 1821 * So just check DMA and PIO here. 1822 */ 1823 if (drvp->drive_flags & DRIVE_DMA) { 1824 /* if mode = DMA mode 0, use compatible timings */ 1825 if ((drvp->drive_flags & DRIVE_DMA) && 1826 drvp->DMA_mode == 0) { 1827 drvp->PIO_mode = 0; 1828 return ret; 1829 } 1830 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1831 /* 1832 * PIO and DMA timings are the same, use fast timings for PIO 1833 * too, else use compat timings. 1834 */ 1835 if ((piix_isp_pio[drvp->PIO_mode] != 1836 piix_isp_dma[drvp->DMA_mode]) || 1837 (piix_rtc_pio[drvp->PIO_mode] != 1838 piix_rtc_dma[drvp->DMA_mode])) 1839 drvp->PIO_mode = 0; 1840 /* if PIO mode <= 2, use compat timings for PIO */ 1841 if (drvp->PIO_mode <= 2) { 1842 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1843 channel); 1844 return ret; 1845 } 1846 } 1847 1848 /* 1849 * Now setup PIO modes. If mode < 2, use compat timings. 1850 * Else enable fast timings. Enable IORDY and prefetch/post 1851 * if PIO mode >= 3. 1852 */ 1853 1854 if (drvp->PIO_mode < 2) 1855 return ret; 1856 1857 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1858 if (drvp->PIO_mode >= 3) { 1859 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1860 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1861 } 1862 return ret; 1863 } 1864 1865 /* setup values in SIDETIM registers, based on mode */ 1866 static u_int32_t 1867 piix_setup_sidetim_timings(mode, dma, channel) 1868 u_int8_t mode; 1869 u_int8_t dma; 1870 u_int8_t channel; 1871 { 1872 if (dma) 1873 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1874 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1875 else 1876 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1877 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1878 } 1879 1880 void 1881 amd7x6_chip_map(sc, pa) 1882 struct pciide_softc *sc; 1883 struct pci_attach_args *pa; 1884 { 1885 struct pciide_channel *cp; 1886 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1887 int channel; 1888 pcireg_t chanenable; 1889 bus_size_t cmdsize, ctlsize; 1890 1891 if (pciide_chipen(sc, pa) == 0) 1892 return; 1893 printf("%s: bus-master DMA support present", 1894 sc->sc_wdcdev.sc_dev.dv_xname); 1895 pciide_mapreg_dma(sc, pa); 1896 printf("\n"); 1897 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1898 WDC_CAPABILITY_MODE; 1899 if (sc->sc_dma_ok) { 1900 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1901 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1902 sc->sc_wdcdev.irqack = pciide_irqack; 1903 } 1904 sc->sc_wdcdev.PIO_cap = 4; 1905 sc->sc_wdcdev.DMA_cap = 2; 1906 1907 if (sc->sc_pp->ide_product == PCI_PRODUCT_AMD_PBC766_IDE) 1908 sc->sc_wdcdev.UDMA_cap = 5; 1909 else 1910 sc->sc_wdcdev.UDMA_cap = 4; 1911 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1912 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1913 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1914 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1915 1916 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1917 DEBUG_PROBE); 1918 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1919 cp = &sc->pciide_channels[channel]; 1920 if (pciide_chansetup(sc, channel, interface) == 0) 1921 continue; 1922 1923 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1924 printf("%s: %s channel ignored (disabled)\n", 1925 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1926 continue; 1927 } 1928 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1929 pciide_pci_intr); 1930 1931 if (pciide_chan_candisable(cp)) 1932 chanenable &= ~AMD7X6_CHAN_EN(channel); 1933 pciide_map_compat_intr(pa, cp, channel, interface); 1934 if (cp->hw_ok == 0) 1935 continue; 1936 1937 amd7x6_setup_channel(&cp->wdc_channel); 1938 } 1939 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1940 chanenable); 1941 return; 1942 } 1943 1944 void 1945 amd7x6_setup_channel(chp) 1946 struct channel_softc *chp; 1947 { 1948 u_int32_t udmatim_reg, datatim_reg; 1949 u_int8_t idedma_ctl; 1950 int mode, drive; 1951 struct ata_drive_datas *drvp; 1952 struct pciide_channel *cp = (struct pciide_channel*)chp; 1953 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1954 #ifndef PCIIDE_AMD756_ENABLEDMA 1955 int rev = PCI_REVISION( 1956 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1957 #endif 1958 1959 idedma_ctl = 0; 1960 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1961 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1962 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1963 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1964 1965 /* setup DMA if needed */ 1966 pciide_channel_dma_setup(cp); 1967 1968 for (drive = 0; drive < 2; drive++) { 1969 drvp = &chp->ch_drive[drive]; 1970 /* If no drive, skip */ 1971 if ((drvp->drive_flags & DRIVE) == 0) 1972 continue; 1973 /* add timing values, setup DMA if needed */ 1974 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1975 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1976 mode = drvp->PIO_mode; 1977 goto pio; 1978 } 1979 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1980 (drvp->drive_flags & DRIVE_UDMA)) { 1981 /* use Ultra/DMA */ 1982 drvp->drive_flags &= ~DRIVE_DMA; 1983 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 1984 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 1985 AMD7X6_UDMA_TIME(chp->channel, drive, 1986 amd7x6_udma_tim[drvp->UDMA_mode]); 1987 /* can use PIO timings, MW DMA unused */ 1988 mode = drvp->PIO_mode; 1989 } else { 1990 /* use Multiword DMA, but only if revision is OK */ 1991 drvp->drive_flags &= ~DRIVE_UDMA; 1992 #ifndef PCIIDE_AMD756_ENABLEDMA 1993 /* 1994 * The workaround doesn't seem to be necessary 1995 * with all drives, so it can be disabled by 1996 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1997 * triggered. 1998 */ 1999 if (sc->sc_pp->ide_product == 2000 PCI_PRODUCT_AMD_PBC756_IDE && 2001 AMD756_CHIPREV_DISABLEDMA(rev)) { 2002 printf("%s:%d:%d: multi-word DMA disabled due " 2003 "to chip revision\n", 2004 sc->sc_wdcdev.sc_dev.dv_xname, 2005 chp->channel, drive); 2006 mode = drvp->PIO_mode; 2007 drvp->drive_flags &= ~DRIVE_DMA; 2008 goto pio; 2009 } 2010 #endif 2011 /* mode = min(pio, dma+2) */ 2012 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2013 mode = drvp->PIO_mode; 2014 else 2015 mode = drvp->DMA_mode + 2; 2016 } 2017 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2018 2019 pio: /* setup PIO mode */ 2020 if (mode <= 2) { 2021 drvp->DMA_mode = 0; 2022 drvp->PIO_mode = 0; 2023 mode = 0; 2024 } else { 2025 drvp->PIO_mode = mode; 2026 drvp->DMA_mode = mode - 2; 2027 } 2028 datatim_reg |= 2029 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2030 amd7x6_pio_set[mode]) | 2031 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2032 amd7x6_pio_rec[mode]); 2033 } 2034 if (idedma_ctl != 0) { 2035 /* Add software bits in status register */ 2036 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2037 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2038 idedma_ctl); 2039 } 2040 pciide_print_modes(cp); 2041 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2042 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2043 } 2044 2045 void 2046 apollo_chip_map(sc, pa) 2047 struct pciide_softc *sc; 2048 struct pci_attach_args *pa; 2049 { 2050 struct pciide_channel *cp; 2051 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2052 int channel; 2053 u_int32_t ideconf; 2054 bus_size_t cmdsize, ctlsize; 2055 pcitag_t pcib_tag; 2056 pcireg_t pcib_id, pcib_class; 2057 2058 if (pciide_chipen(sc, pa) == 0) 2059 return; 2060 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2061 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2062 /* and read ID and rev of the ISA bridge */ 2063 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2064 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2065 printf(": VIA Technologies "); 2066 switch (PCI_PRODUCT(pcib_id)) { 2067 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2068 printf("VT82C586 (Apollo VP) "); 2069 if(PCI_REVISION(pcib_class) >= 0x02) { 2070 printf("ATA33 controller\n"); 2071 sc->sc_wdcdev.UDMA_cap = 2; 2072 } else { 2073 printf("controller\n"); 2074 sc->sc_wdcdev.UDMA_cap = 0; 2075 } 2076 break; 2077 case PCI_PRODUCT_VIATECH_VT82C596A: 2078 printf("VT82C596A (Apollo Pro) "); 2079 if (PCI_REVISION(pcib_class) >= 0x12) { 2080 printf("ATA66 controller\n"); 2081 sc->sc_wdcdev.UDMA_cap = 4; 2082 } else { 2083 printf("ATA33 controller\n"); 2084 sc->sc_wdcdev.UDMA_cap = 2; 2085 } 2086 break; 2087 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2088 printf("VT82C686A (Apollo KX133) "); 2089 if (PCI_REVISION(pcib_class) >= 0x40) { 2090 printf("ATA100 controller\n"); 2091 sc->sc_wdcdev.UDMA_cap = 5; 2092 } else { 2093 printf("ATA66 controller\n"); 2094 sc->sc_wdcdev.UDMA_cap = 4; 2095 } 2096 break; 2097 case PCI_PRODUCT_VIATECH_VT8233: 2098 printf("VT8233 ATA100 controller\n"); 2099 sc->sc_wdcdev.UDMA_cap = 5; 2100 break; 2101 default: 2102 printf("unknown ATA controller\n"); 2103 sc->sc_wdcdev.UDMA_cap = 0; 2104 } 2105 2106 printf("%s: bus-master DMA support present", 2107 sc->sc_wdcdev.sc_dev.dv_xname); 2108 pciide_mapreg_dma(sc, pa); 2109 printf("\n"); 2110 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2111 WDC_CAPABILITY_MODE; 2112 if (sc->sc_dma_ok) { 2113 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2114 sc->sc_wdcdev.irqack = pciide_irqack; 2115 if (sc->sc_wdcdev.UDMA_cap > 0) 2116 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2117 } 2118 sc->sc_wdcdev.PIO_cap = 4; 2119 sc->sc_wdcdev.DMA_cap = 2; 2120 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2121 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2122 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2123 2124 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2125 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2126 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2127 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2128 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2129 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2130 DEBUG_PROBE); 2131 2132 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2133 cp = &sc->pciide_channels[channel]; 2134 if (pciide_chansetup(sc, channel, interface) == 0) 2135 continue; 2136 2137 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2138 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2139 printf("%s: %s channel ignored (disabled)\n", 2140 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2141 continue; 2142 } 2143 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2144 pciide_pci_intr); 2145 if (cp->hw_ok == 0) 2146 continue; 2147 if (pciide_chan_candisable(cp)) { 2148 ideconf &= ~APO_IDECONF_EN(channel); 2149 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2150 ideconf); 2151 } 2152 pciide_map_compat_intr(pa, cp, channel, interface); 2153 2154 if (cp->hw_ok == 0) 2155 continue; 2156 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2157 } 2158 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2159 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2160 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2161 } 2162 2163 void 2164 apollo_setup_channel(chp) 2165 struct channel_softc *chp; 2166 { 2167 u_int32_t udmatim_reg, datatim_reg; 2168 u_int8_t idedma_ctl; 2169 int mode, drive; 2170 struct ata_drive_datas *drvp; 2171 struct pciide_channel *cp = (struct pciide_channel*)chp; 2172 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2173 2174 idedma_ctl = 0; 2175 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2176 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2177 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2178 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2179 2180 /* setup DMA if needed */ 2181 pciide_channel_dma_setup(cp); 2182 2183 for (drive = 0; drive < 2; drive++) { 2184 drvp = &chp->ch_drive[drive]; 2185 /* If no drive, skip */ 2186 if ((drvp->drive_flags & DRIVE) == 0) 2187 continue; 2188 /* add timing values, setup DMA if needed */ 2189 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2190 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2191 mode = drvp->PIO_mode; 2192 goto pio; 2193 } 2194 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2195 (drvp->drive_flags & DRIVE_UDMA)) { 2196 /* use Ultra/DMA */ 2197 drvp->drive_flags &= ~DRIVE_DMA; 2198 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2199 APO_UDMA_EN_MTH(chp->channel, drive); 2200 if (sc->sc_wdcdev.UDMA_cap == 5) { 2201 /* 686b */ 2202 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2203 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2204 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2205 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2206 /* 596b or 686a */ 2207 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2208 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2209 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2210 } else { 2211 /* 596a or 586b */ 2212 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2213 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2214 } 2215 /* can use PIO timings, MW DMA unused */ 2216 mode = drvp->PIO_mode; 2217 } else { 2218 /* use Multiword DMA */ 2219 drvp->drive_flags &= ~DRIVE_UDMA; 2220 /* mode = min(pio, dma+2) */ 2221 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2222 mode = drvp->PIO_mode; 2223 else 2224 mode = drvp->DMA_mode + 2; 2225 } 2226 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2227 2228 pio: /* setup PIO mode */ 2229 if (mode <= 2) { 2230 drvp->DMA_mode = 0; 2231 drvp->PIO_mode = 0; 2232 mode = 0; 2233 } else { 2234 drvp->PIO_mode = mode; 2235 drvp->DMA_mode = mode - 2; 2236 } 2237 datatim_reg |= 2238 APO_DATATIM_PULSE(chp->channel, drive, 2239 apollo_pio_set[mode]) | 2240 APO_DATATIM_RECOV(chp->channel, drive, 2241 apollo_pio_rec[mode]); 2242 } 2243 if (idedma_ctl != 0) { 2244 /* Add software bits in status register */ 2245 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2246 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2247 idedma_ctl); 2248 } 2249 pciide_print_modes(cp); 2250 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2251 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2252 } 2253 2254 void 2255 cmd_channel_map(pa, sc, channel) 2256 struct pci_attach_args *pa; 2257 struct pciide_softc *sc; 2258 int channel; 2259 { 2260 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2261 bus_size_t cmdsize, ctlsize; 2262 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2263 int interface; 2264 2265 /* 2266 * The 0648/0649 can be told to identify as a RAID controller. 2267 * In this case, we have to fake interface 2268 */ 2269 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2270 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2271 PCIIDE_INTERFACE_SETTABLE(1); 2272 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2273 CMD_CONF_DSA1) 2274 interface |= PCIIDE_INTERFACE_PCI(0) | 2275 PCIIDE_INTERFACE_PCI(1); 2276 } else { 2277 interface = PCI_INTERFACE(pa->pa_class); 2278 } 2279 2280 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2281 cp->name = PCIIDE_CHANNEL_NAME(channel); 2282 cp->wdc_channel.channel = channel; 2283 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2284 2285 if (channel > 0) { 2286 cp->wdc_channel.ch_queue = 2287 sc->pciide_channels[0].wdc_channel.ch_queue; 2288 } else { 2289 cp->wdc_channel.ch_queue = 2290 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2291 } 2292 if (cp->wdc_channel.ch_queue == NULL) { 2293 printf("%s %s channel: " 2294 "can't allocate memory for command queue", 2295 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2296 return; 2297 } 2298 2299 printf("%s: %s channel %s to %s mode\n", 2300 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2301 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2302 "configured" : "wired", 2303 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2304 "native-PCI" : "compatibility"); 2305 2306 /* 2307 * with a CMD PCI64x, if we get here, the first channel is enabled: 2308 * there's no way to disable the first channel without disabling 2309 * the whole device 2310 */ 2311 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2312 printf("%s: %s channel ignored (disabled)\n", 2313 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2314 return; 2315 } 2316 2317 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2318 if (cp->hw_ok == 0) 2319 return; 2320 if (channel == 1) { 2321 if (pciide_chan_candisable(cp)) { 2322 ctrl &= ~CMD_CTRL_2PORT; 2323 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2324 CMD_CTRL, ctrl); 2325 } 2326 } 2327 pciide_map_compat_intr(pa, cp, channel, interface); 2328 } 2329 2330 int 2331 cmd_pci_intr(arg) 2332 void *arg; 2333 { 2334 struct pciide_softc *sc = arg; 2335 struct pciide_channel *cp; 2336 struct channel_softc *wdc_cp; 2337 int i, rv, crv; 2338 u_int32_t priirq, secirq; 2339 2340 rv = 0; 2341 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2342 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2343 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2344 cp = &sc->pciide_channels[i]; 2345 wdc_cp = &cp->wdc_channel; 2346 /* If a compat channel skip. */ 2347 if (cp->compat) 2348 continue; 2349 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2350 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2351 crv = wdcintr(wdc_cp); 2352 if (crv == 0) 2353 printf("%s:%d: bogus intr\n", 2354 sc->sc_wdcdev.sc_dev.dv_xname, i); 2355 else 2356 rv = 1; 2357 } 2358 } 2359 return rv; 2360 } 2361 2362 void 2363 cmd_chip_map(sc, pa) 2364 struct pciide_softc *sc; 2365 struct pci_attach_args *pa; 2366 { 2367 int channel; 2368 2369 /* 2370 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2371 * and base adresses registers can be disabled at 2372 * hardware level. In this case, the device is wired 2373 * in compat mode and its first channel is always enabled, 2374 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2375 * In fact, it seems that the first channel of the CMD PCI0640 2376 * can't be disabled. 2377 */ 2378 2379 #ifdef PCIIDE_CMD064x_DISABLE 2380 if (pciide_chipen(sc, pa) == 0) 2381 return; 2382 #endif 2383 2384 printf("%s: hardware does not support DMA\n", 2385 sc->sc_wdcdev.sc_dev.dv_xname); 2386 sc->sc_dma_ok = 0; 2387 2388 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2389 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2390 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2391 2392 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2393 cmd_channel_map(pa, sc, channel); 2394 } 2395 } 2396 2397 void 2398 cmd0643_9_chip_map(sc, pa) 2399 struct pciide_softc *sc; 2400 struct pci_attach_args *pa; 2401 { 2402 struct pciide_channel *cp; 2403 int channel; 2404 int rev = PCI_REVISION( 2405 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2406 2407 /* 2408 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2409 * and base adresses registers can be disabled at 2410 * hardware level. In this case, the device is wired 2411 * in compat mode and its first channel is always enabled, 2412 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2413 * In fact, it seems that the first channel of the CMD PCI0640 2414 * can't be disabled. 2415 */ 2416 2417 #ifdef PCIIDE_CMD064x_DISABLE 2418 if (pciide_chipen(sc, pa) == 0) 2419 return; 2420 #endif 2421 printf("%s: bus-master DMA support present", 2422 sc->sc_wdcdev.sc_dev.dv_xname); 2423 pciide_mapreg_dma(sc, pa); 2424 printf("\n"); 2425 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2426 WDC_CAPABILITY_MODE; 2427 if (sc->sc_dma_ok) { 2428 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2429 switch (sc->sc_pp->ide_product) { 2430 case PCI_PRODUCT_CMDTECH_649: 2431 case PCI_PRODUCT_CMDTECH_648: 2432 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2433 sc->sc_wdcdev.UDMA_cap = 4; 2434 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2435 break; 2436 case PCI_PRODUCT_CMDTECH_646: 2437 if (rev >= CMD0646U2_REV) { 2438 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2439 sc->sc_wdcdev.UDMA_cap = 2; 2440 } else if (rev >= CMD0646U_REV) { 2441 /* 2442 * Linux's driver claims that the 646U is broken 2443 * with UDMA. Only enable it if we know what we're 2444 * doing 2445 */ 2446 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2447 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2448 sc->sc_wdcdev.UDMA_cap = 2; 2449 #endif 2450 /* explicitely disable UDMA */ 2451 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2452 CMD_UDMATIM(0), 0); 2453 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2454 CMD_UDMATIM(1), 0); 2455 } 2456 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2457 break; 2458 default: 2459 sc->sc_wdcdev.irqack = pciide_irqack; 2460 } 2461 } 2462 2463 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2464 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2465 sc->sc_wdcdev.PIO_cap = 4; 2466 sc->sc_wdcdev.DMA_cap = 2; 2467 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2468 2469 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2470 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2471 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2472 DEBUG_PROBE); 2473 2474 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2475 cp = &sc->pciide_channels[channel]; 2476 cmd_channel_map(pa, sc, channel); 2477 if (cp->hw_ok == 0) 2478 continue; 2479 cmd0643_9_setup_channel(&cp->wdc_channel); 2480 } 2481 /* 2482 * note - this also makes sure we clear the irq disable and reset 2483 * bits 2484 */ 2485 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2486 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2487 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2488 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2489 DEBUG_PROBE); 2490 } 2491 2492 void 2493 cmd0643_9_setup_channel(chp) 2494 struct channel_softc *chp; 2495 { 2496 struct ata_drive_datas *drvp; 2497 u_int8_t tim; 2498 u_int32_t idedma_ctl, udma_reg; 2499 int drive; 2500 struct pciide_channel *cp = (struct pciide_channel*)chp; 2501 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2502 2503 idedma_ctl = 0; 2504 /* setup DMA if needed */ 2505 pciide_channel_dma_setup(cp); 2506 2507 for (drive = 0; drive < 2; drive++) { 2508 drvp = &chp->ch_drive[drive]; 2509 /* If no drive, skip */ 2510 if ((drvp->drive_flags & DRIVE) == 0) 2511 continue; 2512 /* add timing values, setup DMA if needed */ 2513 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2514 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2515 if (drvp->drive_flags & DRIVE_UDMA) { 2516 /* UltraDMA on a 646U2, 0648 or 0649 */ 2517 drvp->drive_flags &= ~DRIVE_DMA; 2518 udma_reg = pciide_pci_read(sc->sc_pc, 2519 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2520 if (drvp->UDMA_mode > 2 && 2521 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2522 CMD_BICSR) & 2523 CMD_BICSR_80(chp->channel)) == 0) 2524 drvp->UDMA_mode = 2; 2525 if (drvp->UDMA_mode > 2) 2526 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2527 else if (sc->sc_wdcdev.UDMA_cap > 2) 2528 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2529 udma_reg |= CMD_UDMATIM_UDMA(drive); 2530 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2531 CMD_UDMATIM_TIM_OFF(drive)); 2532 udma_reg |= 2533 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2534 CMD_UDMATIM_TIM_OFF(drive)); 2535 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2536 CMD_UDMATIM(chp->channel), udma_reg); 2537 } else { 2538 /* 2539 * use Multiword DMA. 2540 * Timings will be used for both PIO and DMA, 2541 * so adjust DMA mode if needed 2542 * if we have a 0646U2/8/9, turn off UDMA 2543 */ 2544 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2545 udma_reg = pciide_pci_read(sc->sc_pc, 2546 sc->sc_tag, 2547 CMD_UDMATIM(chp->channel)); 2548 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2549 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2550 CMD_UDMATIM(chp->channel), 2551 udma_reg); 2552 } 2553 if (drvp->PIO_mode >= 3 && 2554 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2555 drvp->DMA_mode = drvp->PIO_mode - 2; 2556 } 2557 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2558 } 2559 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2560 } 2561 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2562 CMD_DATA_TIM(chp->channel, drive), tim); 2563 } 2564 if (idedma_ctl != 0) { 2565 /* Add software bits in status register */ 2566 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2567 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2568 idedma_ctl); 2569 } 2570 pciide_print_modes(cp); 2571 } 2572 2573 void 2574 cmd646_9_irqack(chp) 2575 struct channel_softc *chp; 2576 { 2577 u_int32_t priirq, secirq; 2578 struct pciide_channel *cp = (struct pciide_channel*)chp; 2579 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2580 2581 if (chp->channel == 0) { 2582 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2583 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2584 } else { 2585 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2586 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2587 } 2588 pciide_irqack(chp); 2589 } 2590 2591 void 2592 cy693_chip_map(sc, pa) 2593 struct pciide_softc *sc; 2594 struct pci_attach_args *pa; 2595 { 2596 struct pciide_channel *cp; 2597 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2598 bus_size_t cmdsize, ctlsize; 2599 2600 if (pciide_chipen(sc, pa) == 0) 2601 return; 2602 /* 2603 * this chip has 2 PCI IDE functions, one for primary and one for 2604 * secondary. So we need to call pciide_mapregs_compat() with 2605 * the real channel 2606 */ 2607 if (pa->pa_function == 1) { 2608 sc->sc_cy_compatchan = 0; 2609 } else if (pa->pa_function == 2) { 2610 sc->sc_cy_compatchan = 1; 2611 } else { 2612 printf("%s: unexpected PCI function %d\n", 2613 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2614 return; 2615 } 2616 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2617 printf("%s: bus-master DMA support present", 2618 sc->sc_wdcdev.sc_dev.dv_xname); 2619 pciide_mapreg_dma(sc, pa); 2620 } else { 2621 printf("%s: hardware does not support DMA", 2622 sc->sc_wdcdev.sc_dev.dv_xname); 2623 sc->sc_dma_ok = 0; 2624 } 2625 printf("\n"); 2626 2627 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2628 if (sc->sc_cy_handle == NULL) { 2629 printf("%s: unable to map hyperCache control registers\n", 2630 sc->sc_wdcdev.sc_dev.dv_xname); 2631 sc->sc_dma_ok = 0; 2632 } 2633 2634 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2635 WDC_CAPABILITY_MODE; 2636 if (sc->sc_dma_ok) { 2637 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2638 sc->sc_wdcdev.irqack = pciide_irqack; 2639 } 2640 sc->sc_wdcdev.PIO_cap = 4; 2641 sc->sc_wdcdev.DMA_cap = 2; 2642 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2643 2644 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2645 sc->sc_wdcdev.nchannels = 1; 2646 2647 /* Only one channel for this chip; if we are here it's enabled */ 2648 cp = &sc->pciide_channels[0]; 2649 sc->wdc_chanarray[0] = &cp->wdc_channel; 2650 cp->name = PCIIDE_CHANNEL_NAME(0); 2651 cp->wdc_channel.channel = 0; 2652 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2653 cp->wdc_channel.ch_queue = 2654 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2655 if (cp->wdc_channel.ch_queue == NULL) { 2656 printf("%s primary channel: " 2657 "can't allocate memory for command queue", 2658 sc->sc_wdcdev.sc_dev.dv_xname); 2659 return; 2660 } 2661 printf("%s: primary channel %s to ", 2662 sc->sc_wdcdev.sc_dev.dv_xname, 2663 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2664 "configured" : "wired"); 2665 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2666 printf("native-PCI"); 2667 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2668 pciide_pci_intr); 2669 } else { 2670 printf("compatibility"); 2671 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2672 &cmdsize, &ctlsize); 2673 } 2674 printf(" mode\n"); 2675 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2676 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2677 wdcattach(&cp->wdc_channel); 2678 if (pciide_chan_candisable(cp)) { 2679 pci_conf_write(sc->sc_pc, sc->sc_tag, 2680 PCI_COMMAND_STATUS_REG, 0); 2681 } 2682 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2683 if (cp->hw_ok == 0) 2684 return; 2685 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2686 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2687 cy693_setup_channel(&cp->wdc_channel); 2688 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2689 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2690 } 2691 2692 void 2693 cy693_setup_channel(chp) 2694 struct channel_softc *chp; 2695 { 2696 struct ata_drive_datas *drvp; 2697 int drive; 2698 u_int32_t cy_cmd_ctrl; 2699 u_int32_t idedma_ctl; 2700 struct pciide_channel *cp = (struct pciide_channel*)chp; 2701 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2702 int dma_mode = -1; 2703 2704 cy_cmd_ctrl = idedma_ctl = 0; 2705 2706 /* setup DMA if needed */ 2707 pciide_channel_dma_setup(cp); 2708 2709 for (drive = 0; drive < 2; drive++) { 2710 drvp = &chp->ch_drive[drive]; 2711 /* If no drive, skip */ 2712 if ((drvp->drive_flags & DRIVE) == 0) 2713 continue; 2714 /* add timing values, setup DMA if needed */ 2715 if (drvp->drive_flags & DRIVE_DMA) { 2716 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2717 /* use Multiword DMA */ 2718 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2719 dma_mode = drvp->DMA_mode; 2720 } 2721 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2722 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2723 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2724 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2725 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2726 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2727 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2728 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2729 } 2730 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2731 chp->ch_drive[0].DMA_mode = dma_mode; 2732 chp->ch_drive[1].DMA_mode = dma_mode; 2733 2734 if (dma_mode == -1) 2735 dma_mode = 0; 2736 2737 if (sc->sc_cy_handle != NULL) { 2738 /* Note: `multiple' is implied. */ 2739 cy82c693_write(sc->sc_cy_handle, 2740 (sc->sc_cy_compatchan == 0) ? 2741 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2742 } 2743 2744 pciide_print_modes(cp); 2745 2746 if (idedma_ctl != 0) { 2747 /* Add software bits in status register */ 2748 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2749 IDEDMA_CTL, idedma_ctl); 2750 } 2751 } 2752 2753 static int 2754 sis_hostbr_match(pa) 2755 struct pci_attach_args *pa; 2756 { 2757 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2758 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2759 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2760 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2761 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2762 } 2763 2764 void 2765 sis_chip_map(sc, pa) 2766 struct pciide_softc *sc; 2767 struct pci_attach_args *pa; 2768 { 2769 struct pciide_channel *cp; 2770 int channel; 2771 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2772 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2773 pcireg_t rev = PCI_REVISION(pa->pa_class); 2774 bus_size_t cmdsize, ctlsize; 2775 pcitag_t pchb_tag; 2776 pcireg_t pchb_id, pchb_class; 2777 2778 if (pciide_chipen(sc, pa) == 0) 2779 return; 2780 printf("%s: bus-master DMA support present", 2781 sc->sc_wdcdev.sc_dev.dv_xname); 2782 pciide_mapreg_dma(sc, pa); 2783 printf("\n"); 2784 2785 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2786 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2787 /* and read ID and rev of the ISA bridge */ 2788 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2789 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2790 2791 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2792 WDC_CAPABILITY_MODE; 2793 if (sc->sc_dma_ok) { 2794 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2795 sc->sc_wdcdev.irqack = pciide_irqack; 2796 /* 2797 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2798 * have problems with UDMA (info provided by Christos) 2799 */ 2800 if (rev >= 0xd0 && 2801 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2802 PCI_REVISION(pchb_class) >= 0x03)) 2803 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2804 } 2805 2806 sc->sc_wdcdev.PIO_cap = 4; 2807 sc->sc_wdcdev.DMA_cap = 2; 2808 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2809 /* 2810 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2811 * chipsets. 2812 */ 2813 sc->sc_wdcdev.UDMA_cap = 2814 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2815 sc->sc_wdcdev.set_modes = sis_setup_channel; 2816 2817 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2818 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2819 2820 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2821 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2822 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2823 2824 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2825 cp = &sc->pciide_channels[channel]; 2826 if (pciide_chansetup(sc, channel, interface) == 0) 2827 continue; 2828 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2829 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2830 printf("%s: %s channel ignored (disabled)\n", 2831 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2832 continue; 2833 } 2834 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2835 pciide_pci_intr); 2836 if (cp->hw_ok == 0) 2837 continue; 2838 if (pciide_chan_candisable(cp)) { 2839 if (channel == 0) 2840 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2841 else 2842 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2843 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2844 sis_ctr0); 2845 } 2846 pciide_map_compat_intr(pa, cp, channel, interface); 2847 if (cp->hw_ok == 0) 2848 continue; 2849 sis_setup_channel(&cp->wdc_channel); 2850 } 2851 } 2852 2853 void 2854 sis_setup_channel(chp) 2855 struct channel_softc *chp; 2856 { 2857 struct ata_drive_datas *drvp; 2858 int drive; 2859 u_int32_t sis_tim; 2860 u_int32_t idedma_ctl; 2861 struct pciide_channel *cp = (struct pciide_channel*)chp; 2862 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2863 2864 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2865 "channel %d 0x%x\n", chp->channel, 2866 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2867 DEBUG_PROBE); 2868 sis_tim = 0; 2869 idedma_ctl = 0; 2870 /* setup DMA if needed */ 2871 pciide_channel_dma_setup(cp); 2872 2873 for (drive = 0; drive < 2; drive++) { 2874 drvp = &chp->ch_drive[drive]; 2875 /* If no drive, skip */ 2876 if ((drvp->drive_flags & DRIVE) == 0) 2877 continue; 2878 /* add timing values, setup DMA if needed */ 2879 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2880 (drvp->drive_flags & DRIVE_UDMA) == 0) 2881 goto pio; 2882 2883 if (drvp->drive_flags & DRIVE_UDMA) { 2884 /* use Ultra/DMA */ 2885 drvp->drive_flags &= ~DRIVE_DMA; 2886 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2887 SIS_TIM_UDMA_TIME_OFF(drive); 2888 sis_tim |= SIS_TIM_UDMA_EN(drive); 2889 } else { 2890 /* 2891 * use Multiword DMA 2892 * Timings will be used for both PIO and DMA, 2893 * so adjust DMA mode if needed 2894 */ 2895 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2896 drvp->PIO_mode = drvp->DMA_mode + 2; 2897 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2898 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2899 drvp->PIO_mode - 2 : 0; 2900 if (drvp->DMA_mode == 0) 2901 drvp->PIO_mode = 0; 2902 } 2903 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2904 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2905 SIS_TIM_ACT_OFF(drive); 2906 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2907 SIS_TIM_REC_OFF(drive); 2908 } 2909 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2910 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2911 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2912 if (idedma_ctl != 0) { 2913 /* Add software bits in status register */ 2914 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2915 IDEDMA_CTL, idedma_ctl); 2916 } 2917 pciide_print_modes(cp); 2918 } 2919 2920 static int 2921 acer_isabr_match(pa) 2922 struct pci_attach_args *pa; 2923 { 2924 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 2925 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 2926 } 2927 2928 void 2929 acer_chip_map(sc, pa) 2930 struct pciide_softc *sc; 2931 struct pci_attach_args *pa; 2932 { 2933 struct pci_attach_args isa_pa; 2934 struct pciide_channel *cp; 2935 int channel; 2936 pcireg_t cr, interface; 2937 bus_size_t cmdsize, ctlsize; 2938 pcireg_t rev = PCI_REVISION(pa->pa_class); 2939 2940 if (pciide_chipen(sc, pa) == 0) 2941 return; 2942 printf("%s: bus-master DMA support present", 2943 sc->sc_wdcdev.sc_dev.dv_xname); 2944 pciide_mapreg_dma(sc, pa); 2945 printf("\n"); 2946 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2947 WDC_CAPABILITY_MODE; 2948 if (sc->sc_dma_ok) { 2949 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2950 if (rev >= 0x20) { 2951 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2952 if (rev >= 0xC4) 2953 sc->sc_wdcdev.UDMA_cap = 5; 2954 else if (rev >= 0xC2) 2955 sc->sc_wdcdev.UDMA_cap = 4; 2956 else 2957 sc->sc_wdcdev.UDMA_cap = 2; 2958 } 2959 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2960 sc->sc_wdcdev.irqack = pciide_irqack; 2961 } 2962 2963 sc->sc_wdcdev.PIO_cap = 4; 2964 sc->sc_wdcdev.DMA_cap = 2; 2965 sc->sc_wdcdev.set_modes = acer_setup_channel; 2966 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2967 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2968 2969 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2970 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2971 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2972 2973 /* Enable "microsoft register bits" R/W. */ 2974 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2975 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2976 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2977 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2978 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2979 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2980 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2981 ~ACER_CHANSTATUSREGS_RO); 2982 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2983 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2984 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2985 /* Don't use cr, re-read the real register content instead */ 2986 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2987 PCI_CLASS_REG)); 2988 2989 /* From linux: enable "Cable Detection" */ 2990 if (rev >= 0xC2) { 2991 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 2992 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 2993 | ACER_0x4B_CDETECT); 2994 /* set south-bridge's enable bit, m1533, 0x79 */ 2995 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 2996 printf("%s: can't find PCI/ISA bridge, downgrading " 2997 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 2998 sc->sc_wdcdev.UDMA_cap = 2; 2999 } else { 3000 if (rev == 0xC2) 3001 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3002 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3003 ACER_0x79, 3004 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3005 ACER_0x79) 3006 | ACER_0x79_REVC2_EN); 3007 else 3008 /* 1553/1535 (m1533, 0x79, bit 1) */ 3009 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3010 ACER_0x79, 3011 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3012 ACER_0x79) 3013 | ACER_0x79_EN); 3014 } 3015 } 3016 3017 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3018 cp = &sc->pciide_channels[channel]; 3019 if (pciide_chansetup(sc, channel, interface) == 0) 3020 continue; 3021 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3022 printf("%s: %s channel ignored (disabled)\n", 3023 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3024 continue; 3025 } 3026 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3027 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3028 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3029 if (cp->hw_ok == 0) 3030 continue; 3031 if (pciide_chan_candisable(cp)) { 3032 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3033 pci_conf_write(sc->sc_pc, sc->sc_tag, 3034 PCI_CLASS_REG, cr); 3035 } 3036 pciide_map_compat_intr(pa, cp, channel, interface); 3037 acer_setup_channel(&cp->wdc_channel); 3038 } 3039 } 3040 3041 void 3042 acer_setup_channel(chp) 3043 struct channel_softc *chp; 3044 { 3045 struct ata_drive_datas *drvp; 3046 int drive; 3047 u_int32_t acer_fifo_udma; 3048 u_int32_t idedma_ctl; 3049 struct pciide_channel *cp = (struct pciide_channel*)chp; 3050 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3051 3052 idedma_ctl = 0; 3053 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3054 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3055 acer_fifo_udma), DEBUG_PROBE); 3056 /* setup DMA if needed */ 3057 pciide_channel_dma_setup(cp); 3058 3059 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3060 DRIVE_UDMA) { /* check 80 pins cable */ 3061 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3062 ACER_0x4A_80PIN(chp->channel)) { 3063 if (chp->ch_drive[0].UDMA_mode > 2) 3064 chp->ch_drive[0].UDMA_mode = 2; 3065 if (chp->ch_drive[1].UDMA_mode > 2) 3066 chp->ch_drive[1].UDMA_mode = 2; 3067 } 3068 } 3069 3070 for (drive = 0; drive < 2; drive++) { 3071 drvp = &chp->ch_drive[drive]; 3072 /* If no drive, skip */ 3073 if ((drvp->drive_flags & DRIVE) == 0) 3074 continue; 3075 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3076 "channel %d drive %d 0x%x\n", chp->channel, drive, 3077 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3078 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3079 /* clear FIFO/DMA mode */ 3080 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3081 ACER_UDMA_EN(chp->channel, drive) | 3082 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3083 3084 /* add timing values, setup DMA if needed */ 3085 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3086 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3087 acer_fifo_udma |= 3088 ACER_FTH_OPL(chp->channel, drive, 0x1); 3089 goto pio; 3090 } 3091 3092 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3093 if (drvp->drive_flags & DRIVE_UDMA) { 3094 /* use Ultra/DMA */ 3095 drvp->drive_flags &= ~DRIVE_DMA; 3096 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3097 acer_fifo_udma |= 3098 ACER_UDMA_TIM(chp->channel, drive, 3099 acer_udma[drvp->UDMA_mode]); 3100 /* XXX disable if one drive < UDMA3 ? */ 3101 if (drvp->UDMA_mode >= 3) { 3102 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3103 ACER_0x4B, 3104 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3105 ACER_0x4B) | ACER_0x4B_UDMA66); 3106 } 3107 } else { 3108 /* 3109 * use Multiword DMA 3110 * Timings will be used for both PIO and DMA, 3111 * so adjust DMA mode if needed 3112 */ 3113 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3114 drvp->PIO_mode = drvp->DMA_mode + 2; 3115 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3116 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3117 drvp->PIO_mode - 2 : 0; 3118 if (drvp->DMA_mode == 0) 3119 drvp->PIO_mode = 0; 3120 } 3121 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3122 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3123 ACER_IDETIM(chp->channel, drive), 3124 acer_pio[drvp->PIO_mode]); 3125 } 3126 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3127 acer_fifo_udma), DEBUG_PROBE); 3128 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3129 if (idedma_ctl != 0) { 3130 /* Add software bits in status register */ 3131 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3132 IDEDMA_CTL, idedma_ctl); 3133 } 3134 pciide_print_modes(cp); 3135 } 3136 3137 int 3138 acer_pci_intr(arg) 3139 void *arg; 3140 { 3141 struct pciide_softc *sc = arg; 3142 struct pciide_channel *cp; 3143 struct channel_softc *wdc_cp; 3144 int i, rv, crv; 3145 u_int32_t chids; 3146 3147 rv = 0; 3148 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3149 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3150 cp = &sc->pciide_channels[i]; 3151 wdc_cp = &cp->wdc_channel; 3152 /* If a compat channel skip. */ 3153 if (cp->compat) 3154 continue; 3155 if (chids & ACER_CHIDS_INT(i)) { 3156 crv = wdcintr(wdc_cp); 3157 if (crv == 0) 3158 printf("%s:%d: bogus intr\n", 3159 sc->sc_wdcdev.sc_dev.dv_xname, i); 3160 else 3161 rv = 1; 3162 } 3163 } 3164 return rv; 3165 } 3166 3167 void 3168 hpt_chip_map(sc, pa) 3169 struct pciide_softc *sc; 3170 struct pci_attach_args *pa; 3171 { 3172 struct pciide_channel *cp; 3173 int i, compatchan, revision; 3174 pcireg_t interface; 3175 bus_size_t cmdsize, ctlsize; 3176 3177 if (pciide_chipen(sc, pa) == 0) 3178 return; 3179 revision = PCI_REVISION(pa->pa_class); 3180 printf(": Triones/Highpoint "); 3181 if (revision == HPT370_REV) 3182 printf("HPT370 IDE Controller\n"); 3183 else if (revision == HPT370A_REV) 3184 printf("HPT370A IDE Controller\n"); 3185 else if (revision == HPT366_REV) 3186 printf("HPT366 IDE Controller\n"); 3187 else 3188 printf("unknown HPT IDE controller rev %d\n", revision); 3189 3190 /* 3191 * when the chip is in native mode it identifies itself as a 3192 * 'misc mass storage'. Fake interface in this case. 3193 */ 3194 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3195 interface = PCI_INTERFACE(pa->pa_class); 3196 } else { 3197 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3198 PCIIDE_INTERFACE_PCI(0); 3199 if (revision == HPT370_REV || revision == HPT370A_REV) 3200 interface |= PCIIDE_INTERFACE_PCI(1); 3201 } 3202 3203 printf("%s: bus-master DMA support present", 3204 sc->sc_wdcdev.sc_dev.dv_xname); 3205 pciide_mapreg_dma(sc, pa); 3206 printf("\n"); 3207 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3208 WDC_CAPABILITY_MODE; 3209 if (sc->sc_dma_ok) { 3210 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3212 sc->sc_wdcdev.irqack = pciide_irqack; 3213 } 3214 sc->sc_wdcdev.PIO_cap = 4; 3215 sc->sc_wdcdev.DMA_cap = 2; 3216 3217 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3218 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3219 if (revision == HPT366_REV) { 3220 sc->sc_wdcdev.UDMA_cap = 4; 3221 /* 3222 * The 366 has 2 PCI IDE functions, one for primary and one 3223 * for secondary. So we need to call pciide_mapregs_compat() 3224 * with the real channel 3225 */ 3226 if (pa->pa_function == 0) { 3227 compatchan = 0; 3228 } else if (pa->pa_function == 1) { 3229 compatchan = 1; 3230 } else { 3231 printf("%s: unexpected PCI function %d\n", 3232 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3233 return; 3234 } 3235 sc->sc_wdcdev.nchannels = 1; 3236 } else { 3237 sc->sc_wdcdev.nchannels = 2; 3238 sc->sc_wdcdev.UDMA_cap = 5; 3239 } 3240 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3241 cp = &sc->pciide_channels[i]; 3242 if (sc->sc_wdcdev.nchannels > 1) { 3243 compatchan = i; 3244 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3245 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3246 printf("%s: %s channel ignored (disabled)\n", 3247 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3248 continue; 3249 } 3250 } 3251 if (pciide_chansetup(sc, i, interface) == 0) 3252 continue; 3253 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3254 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3255 &ctlsize, hpt_pci_intr); 3256 } else { 3257 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3258 &cmdsize, &ctlsize); 3259 } 3260 if (cp->hw_ok == 0) 3261 return; 3262 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3263 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3264 wdcattach(&cp->wdc_channel); 3265 hpt_setup_channel(&cp->wdc_channel); 3266 } 3267 if (revision == HPT370_REV || revision == HPT370A_REV) { 3268 /* 3269 * HPT370_REV has a bit to disable interrupts, make sure 3270 * to clear it 3271 */ 3272 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3273 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3274 ~HPT_CSEL_IRQDIS); 3275 } 3276 return; 3277 } 3278 3279 void 3280 hpt_setup_channel(chp) 3281 struct channel_softc *chp; 3282 { 3283 struct ata_drive_datas *drvp; 3284 int drive; 3285 int cable; 3286 u_int32_t before, after; 3287 u_int32_t idedma_ctl; 3288 struct pciide_channel *cp = (struct pciide_channel*)chp; 3289 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3290 3291 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3292 3293 /* setup DMA if needed */ 3294 pciide_channel_dma_setup(cp); 3295 3296 idedma_ctl = 0; 3297 3298 /* Per drive settings */ 3299 for (drive = 0; drive < 2; drive++) { 3300 drvp = &chp->ch_drive[drive]; 3301 /* If no drive, skip */ 3302 if ((drvp->drive_flags & DRIVE) == 0) 3303 continue; 3304 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3305 HPT_IDETIM(chp->channel, drive)); 3306 3307 /* add timing values, setup DMA if needed */ 3308 if (drvp->drive_flags & DRIVE_UDMA) { 3309 /* use Ultra/DMA */ 3310 drvp->drive_flags &= ~DRIVE_DMA; 3311 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3312 drvp->UDMA_mode > 2) 3313 drvp->UDMA_mode = 2; 3314 after = (sc->sc_wdcdev.nchannels == 2) ? 3315 hpt370_udma[drvp->UDMA_mode] : 3316 hpt366_udma[drvp->UDMA_mode]; 3317 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3318 } else if (drvp->drive_flags & DRIVE_DMA) { 3319 /* 3320 * use Multiword DMA. 3321 * Timings will be used for both PIO and DMA, so adjust 3322 * DMA mode if needed 3323 */ 3324 if (drvp->PIO_mode >= 3 && 3325 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3326 drvp->DMA_mode = drvp->PIO_mode - 2; 3327 } 3328 after = (sc->sc_wdcdev.nchannels == 2) ? 3329 hpt370_dma[drvp->DMA_mode] : 3330 hpt366_dma[drvp->DMA_mode]; 3331 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3332 } else { 3333 /* PIO only */ 3334 after = (sc->sc_wdcdev.nchannels == 2) ? 3335 hpt370_pio[drvp->PIO_mode] : 3336 hpt366_pio[drvp->PIO_mode]; 3337 } 3338 pci_conf_write(sc->sc_pc, sc->sc_tag, 3339 HPT_IDETIM(chp->channel, drive), after); 3340 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3341 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3342 after, before), DEBUG_PROBE); 3343 } 3344 if (idedma_ctl != 0) { 3345 /* Add software bits in status register */ 3346 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3347 IDEDMA_CTL, idedma_ctl); 3348 } 3349 pciide_print_modes(cp); 3350 } 3351 3352 int 3353 hpt_pci_intr(arg) 3354 void *arg; 3355 { 3356 struct pciide_softc *sc = arg; 3357 struct pciide_channel *cp; 3358 struct channel_softc *wdc_cp; 3359 int rv = 0; 3360 int dmastat, i, crv; 3361 3362 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3363 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3364 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3365 if((dmastat & IDEDMA_CTL_INTR) == 0) 3366 continue; 3367 cp = &sc->pciide_channels[i]; 3368 wdc_cp = &cp->wdc_channel; 3369 crv = wdcintr(wdc_cp); 3370 if (crv == 0) { 3371 printf("%s:%d: bogus intr\n", 3372 sc->sc_wdcdev.sc_dev.dv_xname, i); 3373 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3374 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3375 } else 3376 rv = 1; 3377 } 3378 return rv; 3379 } 3380 3381 3382 /* Macros to test product */ 3383 #define PDC_IS_262(sc) \ 3384 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3385 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3386 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3387 #define PDC_IS_265(sc) \ 3388 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3389 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3390 3391 void 3392 pdc202xx_chip_map(sc, pa) 3393 struct pciide_softc *sc; 3394 struct pci_attach_args *pa; 3395 { 3396 struct pciide_channel *cp; 3397 int channel; 3398 pcireg_t interface, st, mode; 3399 bus_size_t cmdsize, ctlsize; 3400 3401 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3402 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3403 DEBUG_PROBE); 3404 if (pciide_chipen(sc, pa) == 0) 3405 return; 3406 3407 /* turn off RAID mode */ 3408 st &= ~PDC2xx_STATE_IDERAID; 3409 3410 /* 3411 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3412 * mode. We have to fake interface 3413 */ 3414 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3415 if (st & PDC2xx_STATE_NATIVE) 3416 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3417 3418 printf("%s: bus-master DMA support present", 3419 sc->sc_wdcdev.sc_dev.dv_xname); 3420 pciide_mapreg_dma(sc, pa); 3421 printf("\n"); 3422 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3423 WDC_CAPABILITY_MODE; 3424 if (sc->sc_dma_ok) { 3425 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3426 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3427 sc->sc_wdcdev.irqack = pciide_irqack; 3428 } 3429 sc->sc_wdcdev.PIO_cap = 4; 3430 sc->sc_wdcdev.DMA_cap = 2; 3431 if (PDC_IS_265(sc)) 3432 sc->sc_wdcdev.UDMA_cap = 5; 3433 else if (PDC_IS_262(sc)) 3434 sc->sc_wdcdev.UDMA_cap = 4; 3435 else 3436 sc->sc_wdcdev.UDMA_cap = 2; 3437 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3438 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3439 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3440 3441 /* setup failsafe defaults */ 3442 mode = 0; 3443 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3444 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3445 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3446 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3447 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3448 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3449 "initial timings 0x%x, now 0x%x\n", channel, 3450 pci_conf_read(sc->sc_pc, sc->sc_tag, 3451 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3452 DEBUG_PROBE); 3453 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3454 mode | PDC2xx_TIM_IORDYp); 3455 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3456 "initial timings 0x%x, now 0x%x\n", channel, 3457 pci_conf_read(sc->sc_pc, sc->sc_tag, 3458 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3459 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3460 mode); 3461 } 3462 3463 mode = PDC2xx_SCR_DMA; 3464 if (PDC_IS_262(sc)) { 3465 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3466 } else { 3467 /* the BIOS set it up this way */ 3468 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3469 } 3470 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3471 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3472 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3473 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3474 DEBUG_PROBE); 3475 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3476 3477 /* controller initial state register is OK even without BIOS */ 3478 /* Set DMA mode to IDE DMA compatibility */ 3479 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3480 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3481 DEBUG_PROBE); 3482 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3483 mode | 0x1); 3484 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3485 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3486 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3487 mode | 0x1); 3488 3489 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3490 cp = &sc->pciide_channels[channel]; 3491 if (pciide_chansetup(sc, channel, interface) == 0) 3492 continue; 3493 if ((st & (PDC_IS_262(sc) ? 3494 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3495 printf("%s: %s channel ignored (disabled)\n", 3496 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3497 continue; 3498 } 3499 if (PDC_IS_265(sc)) 3500 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3501 pdc20265_pci_intr); 3502 else 3503 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3504 pdc202xx_pci_intr); 3505 if (cp->hw_ok == 0) 3506 continue; 3507 if (pciide_chan_candisable(cp)) 3508 st &= ~(PDC_IS_262(sc) ? 3509 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3510 pciide_map_compat_intr(pa, cp, channel, interface); 3511 pdc202xx_setup_channel(&cp->wdc_channel); 3512 } 3513 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3514 DEBUG_PROBE); 3515 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3516 return; 3517 } 3518 3519 void 3520 pdc202xx_setup_channel(chp) 3521 struct channel_softc *chp; 3522 { 3523 struct ata_drive_datas *drvp; 3524 int drive; 3525 pcireg_t mode, st; 3526 u_int32_t idedma_ctl, scr, atapi; 3527 struct pciide_channel *cp = (struct pciide_channel*)chp; 3528 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3529 int channel = chp->channel; 3530 3531 /* setup DMA if needed */ 3532 pciide_channel_dma_setup(cp); 3533 3534 idedma_ctl = 0; 3535 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3536 sc->sc_wdcdev.sc_dev.dv_xname, 3537 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3538 DEBUG_PROBE); 3539 3540 /* Per channel settings */ 3541 if (PDC_IS_262(sc)) { 3542 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3543 PDC262_U66); 3544 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3545 /* Trimm UDMA mode */ 3546 if ((st & PDC262_STATE_80P(channel)) != 0 || 3547 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3548 chp->ch_drive[0].UDMA_mode <= 2) || 3549 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3550 chp->ch_drive[1].UDMA_mode <= 2)) { 3551 if (chp->ch_drive[0].UDMA_mode > 2) 3552 chp->ch_drive[0].UDMA_mode = 2; 3553 if (chp->ch_drive[1].UDMA_mode > 2) 3554 chp->ch_drive[1].UDMA_mode = 2; 3555 } 3556 /* Set U66 if needed */ 3557 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3558 chp->ch_drive[0].UDMA_mode > 2) || 3559 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3560 chp->ch_drive[1].UDMA_mode > 2)) 3561 scr |= PDC262_U66_EN(channel); 3562 else 3563 scr &= ~PDC262_U66_EN(channel); 3564 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3565 PDC262_U66, scr); 3566 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3567 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3568 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3569 PDC262_ATAPI(channel))), DEBUG_PROBE); 3570 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3571 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3572 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3573 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3574 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3575 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3576 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3577 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3578 atapi = 0; 3579 else 3580 atapi = PDC262_ATAPI_UDMA; 3581 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3582 PDC262_ATAPI(channel), atapi); 3583 } 3584 } 3585 for (drive = 0; drive < 2; drive++) { 3586 drvp = &chp->ch_drive[drive]; 3587 /* If no drive, skip */ 3588 if ((drvp->drive_flags & DRIVE) == 0) 3589 continue; 3590 mode = 0; 3591 if (drvp->drive_flags & DRIVE_UDMA) { 3592 /* use Ultra/DMA */ 3593 drvp->drive_flags &= ~DRIVE_DMA; 3594 mode = PDC2xx_TIM_SET_MB(mode, 3595 pdc2xx_udma_mb[drvp->UDMA_mode]); 3596 mode = PDC2xx_TIM_SET_MC(mode, 3597 pdc2xx_udma_mc[drvp->UDMA_mode]); 3598 drvp->drive_flags &= ~DRIVE_DMA; 3599 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3600 } else if (drvp->drive_flags & DRIVE_DMA) { 3601 mode = PDC2xx_TIM_SET_MB(mode, 3602 pdc2xx_dma_mb[drvp->DMA_mode]); 3603 mode = PDC2xx_TIM_SET_MC(mode, 3604 pdc2xx_dma_mc[drvp->DMA_mode]); 3605 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3606 } else { 3607 mode = PDC2xx_TIM_SET_MB(mode, 3608 pdc2xx_dma_mb[0]); 3609 mode = PDC2xx_TIM_SET_MC(mode, 3610 pdc2xx_dma_mc[0]); 3611 } 3612 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3613 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3614 if (drvp->drive_flags & DRIVE_ATA) 3615 mode |= PDC2xx_TIM_PRE; 3616 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3617 if (drvp->PIO_mode >= 3) { 3618 mode |= PDC2xx_TIM_IORDY; 3619 if (drive == 0) 3620 mode |= PDC2xx_TIM_IORDYp; 3621 } 3622 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3623 "timings 0x%x\n", 3624 sc->sc_wdcdev.sc_dev.dv_xname, 3625 chp->channel, drive, mode), DEBUG_PROBE); 3626 pci_conf_write(sc->sc_pc, sc->sc_tag, 3627 PDC2xx_TIM(chp->channel, drive), mode); 3628 } 3629 if (idedma_ctl != 0) { 3630 /* Add software bits in status register */ 3631 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3632 IDEDMA_CTL, idedma_ctl); 3633 } 3634 pciide_print_modes(cp); 3635 } 3636 3637 int 3638 pdc202xx_pci_intr(arg) 3639 void *arg; 3640 { 3641 struct pciide_softc *sc = arg; 3642 struct pciide_channel *cp; 3643 struct channel_softc *wdc_cp; 3644 int i, rv, crv; 3645 u_int32_t scr; 3646 3647 rv = 0; 3648 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3649 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3650 cp = &sc->pciide_channels[i]; 3651 wdc_cp = &cp->wdc_channel; 3652 /* If a compat channel skip. */ 3653 if (cp->compat) 3654 continue; 3655 if (scr & PDC2xx_SCR_INT(i)) { 3656 crv = wdcintr(wdc_cp); 3657 if (crv == 0) 3658 printf("%s:%d: bogus intr (reg 0x%x)\n", 3659 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3660 else 3661 rv = 1; 3662 } 3663 } 3664 return rv; 3665 } 3666 3667 int 3668 pdc20265_pci_intr(arg) 3669 void *arg; 3670 { 3671 struct pciide_softc *sc = arg; 3672 struct pciide_channel *cp; 3673 struct channel_softc *wdc_cp; 3674 int i, rv, crv; 3675 u_int32_t dmastat; 3676 3677 rv = 0; 3678 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3679 cp = &sc->pciide_channels[i]; 3680 wdc_cp = &cp->wdc_channel; 3681 /* If a compat channel skip. */ 3682 if (cp->compat) 3683 continue; 3684 /* 3685 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3686 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3687 * So use it instead (requires 2 reg reads instead of 1, 3688 * but we can't do it another way). 3689 */ 3690 dmastat = bus_space_read_1(sc->sc_dma_iot, 3691 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3692 if((dmastat & IDEDMA_CTL_INTR) == 0) 3693 continue; 3694 crv = wdcintr(wdc_cp); 3695 if (crv == 0) 3696 printf("%s:%d: bogus intr\n", 3697 sc->sc_wdcdev.sc_dev.dv_xname, i); 3698 else 3699 rv = 1; 3700 } 3701 return rv; 3702 } 3703 3704 void 3705 opti_chip_map(sc, pa) 3706 struct pciide_softc *sc; 3707 struct pci_attach_args *pa; 3708 { 3709 struct pciide_channel *cp; 3710 bus_size_t cmdsize, ctlsize; 3711 pcireg_t interface; 3712 u_int8_t init_ctrl; 3713 int channel; 3714 3715 if (pciide_chipen(sc, pa) == 0) 3716 return; 3717 printf("%s: bus-master DMA support present", 3718 sc->sc_wdcdev.sc_dev.dv_xname); 3719 3720 /* 3721 * XXXSCW: 3722 * There seem to be a couple of buggy revisions/implementations 3723 * of the OPTi pciide chipset. This kludge seems to fix one of 3724 * the reported problems (PR/11644) but still fails for the 3725 * other (PR/13151), although the latter may be due to other 3726 * issues too... 3727 */ 3728 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3729 printf(" but disabled due to chip rev. <= 0x12"); 3730 sc->sc_dma_ok = 0; 3731 sc->sc_wdcdev.cap = 0; 3732 } else { 3733 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3734 pciide_mapreg_dma(sc, pa); 3735 } 3736 printf("\n"); 3737 3738 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3739 sc->sc_wdcdev.PIO_cap = 4; 3740 if (sc->sc_dma_ok) { 3741 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3742 sc->sc_wdcdev.irqack = pciide_irqack; 3743 sc->sc_wdcdev.DMA_cap = 2; 3744 } 3745 sc->sc_wdcdev.set_modes = opti_setup_channel; 3746 3747 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3748 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3749 3750 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3751 OPTI_REG_INIT_CONTROL); 3752 3753 interface = PCI_INTERFACE(pa->pa_class); 3754 3755 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3756 cp = &sc->pciide_channels[channel]; 3757 if (pciide_chansetup(sc, channel, interface) == 0) 3758 continue; 3759 if (channel == 1 && 3760 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3761 printf("%s: %s channel ignored (disabled)\n", 3762 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3763 continue; 3764 } 3765 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3766 pciide_pci_intr); 3767 if (cp->hw_ok == 0) 3768 continue; 3769 pciide_map_compat_intr(pa, cp, channel, interface); 3770 if (cp->hw_ok == 0) 3771 continue; 3772 opti_setup_channel(&cp->wdc_channel); 3773 } 3774 } 3775 3776 void 3777 opti_setup_channel(chp) 3778 struct channel_softc *chp; 3779 { 3780 struct ata_drive_datas *drvp; 3781 struct pciide_channel *cp = (struct pciide_channel*)chp; 3782 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3783 int drive, spd; 3784 int mode[2]; 3785 u_int8_t rv, mr; 3786 3787 /* 3788 * The `Delay' and `Address Setup Time' fields of the 3789 * Miscellaneous Register are always zero initially. 3790 */ 3791 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3792 mr &= ~(OPTI_MISC_DELAY_MASK | 3793 OPTI_MISC_ADDR_SETUP_MASK | 3794 OPTI_MISC_INDEX_MASK); 3795 3796 /* Prime the control register before setting timing values */ 3797 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3798 3799 /* Determine the clockrate of the PCIbus the chip is attached to */ 3800 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3801 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3802 3803 /* setup DMA if needed */ 3804 pciide_channel_dma_setup(cp); 3805 3806 for (drive = 0; drive < 2; drive++) { 3807 drvp = &chp->ch_drive[drive]; 3808 /* If no drive, skip */ 3809 if ((drvp->drive_flags & DRIVE) == 0) { 3810 mode[drive] = -1; 3811 continue; 3812 } 3813 3814 if ((drvp->drive_flags & DRIVE_DMA)) { 3815 /* 3816 * Timings will be used for both PIO and DMA, 3817 * so adjust DMA mode if needed 3818 */ 3819 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3820 drvp->PIO_mode = drvp->DMA_mode + 2; 3821 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3822 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3823 drvp->PIO_mode - 2 : 0; 3824 if (drvp->DMA_mode == 0) 3825 drvp->PIO_mode = 0; 3826 3827 mode[drive] = drvp->DMA_mode + 5; 3828 } else 3829 mode[drive] = drvp->PIO_mode; 3830 3831 if (drive && mode[0] >= 0 && 3832 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3833 /* 3834 * Can't have two drives using different values 3835 * for `Address Setup Time'. 3836 * Slow down the faster drive to compensate. 3837 */ 3838 int d = (opti_tim_as[spd][mode[0]] > 3839 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3840 3841 mode[d] = mode[1-d]; 3842 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3843 chp->ch_drive[d].DMA_mode = 0; 3844 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3845 } 3846 } 3847 3848 for (drive = 0; drive < 2; drive++) { 3849 int m; 3850 if ((m = mode[drive]) < 0) 3851 continue; 3852 3853 /* Set the Address Setup Time and select appropriate index */ 3854 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3855 rv |= OPTI_MISC_INDEX(drive); 3856 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3857 3858 /* Set the pulse width and recovery timing parameters */ 3859 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3860 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3861 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3862 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3863 3864 /* Set the Enhanced Mode register appropriately */ 3865 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3866 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3867 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3868 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3869 } 3870 3871 /* Finally, enable the timings */ 3872 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3873 3874 pciide_print_modes(cp); 3875 } 3876 3877 #define ACARD_IS_850(sc) \ 3878 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3879 3880 void 3881 acard_chip_map(sc, pa) 3882 struct pciide_softc *sc; 3883 struct pci_attach_args *pa; 3884 { 3885 struct pciide_channel *cp; 3886 int i; 3887 pcireg_t interface; 3888 bus_size_t cmdsize, ctlsize; 3889 3890 if (pciide_chipen(sc, pa) == 0) 3891 return; 3892 3893 /* 3894 * when the chip is in native mode it identifies itself as a 3895 * 'misc mass storage'. Fake interface in this case. 3896 */ 3897 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3898 interface = PCI_INTERFACE(pa->pa_class); 3899 } else { 3900 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3901 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3902 } 3903 3904 printf("%s: bus-master DMA support present", 3905 sc->sc_wdcdev.sc_dev.dv_xname); 3906 pciide_mapreg_dma(sc, pa); 3907 printf("\n"); 3908 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3909 WDC_CAPABILITY_MODE; 3910 3911 if (sc->sc_dma_ok) { 3912 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3913 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3914 sc->sc_wdcdev.irqack = pciide_irqack; 3915 } 3916 sc->sc_wdcdev.PIO_cap = 4; 3917 sc->sc_wdcdev.DMA_cap = 2; 3918 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3919 3920 sc->sc_wdcdev.set_modes = acard_setup_channel; 3921 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3922 sc->sc_wdcdev.nchannels = 2; 3923 3924 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3925 cp = &sc->pciide_channels[i]; 3926 if (pciide_chansetup(sc, i, interface) == 0) 3927 continue; 3928 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3929 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3930 &ctlsize, pciide_pci_intr); 3931 } else { 3932 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 3933 &cmdsize, &ctlsize); 3934 } 3935 if (cp->hw_ok == 0) 3936 return; 3937 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3938 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3939 wdcattach(&cp->wdc_channel); 3940 acard_setup_channel(&cp->wdc_channel); 3941 } 3942 if (!ACARD_IS_850(sc)) { 3943 u_int32_t reg; 3944 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3945 reg &= ~ATP860_CTRL_INT; 3946 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3947 } 3948 } 3949 3950 void 3951 acard_setup_channel(chp) 3952 struct channel_softc *chp; 3953 { 3954 struct ata_drive_datas *drvp; 3955 struct pciide_channel *cp = (struct pciide_channel*)chp; 3956 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3957 int channel = chp->channel; 3958 int drive; 3959 u_int32_t idetime, udma_mode; 3960 u_int32_t idedma_ctl; 3961 3962 /* setup DMA if needed */ 3963 pciide_channel_dma_setup(cp); 3964 3965 if (ACARD_IS_850(sc)) { 3966 idetime = 0; 3967 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3968 udma_mode &= ~ATP850_UDMA_MASK(channel); 3969 } else { 3970 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3971 idetime &= ~ATP860_SETTIME_MASK(channel); 3972 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3973 udma_mode &= ~ATP860_UDMA_MASK(channel); 3974 3975 /* check 80 pins cable */ 3976 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 3977 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 3978 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3979 & ATP860_CTRL_80P(chp->channel)) { 3980 if (chp->ch_drive[0].UDMA_mode > 2) 3981 chp->ch_drive[0].UDMA_mode = 2; 3982 if (chp->ch_drive[1].UDMA_mode > 2) 3983 chp->ch_drive[1].UDMA_mode = 2; 3984 } 3985 } 3986 } 3987 3988 idedma_ctl = 0; 3989 3990 /* Per drive settings */ 3991 for (drive = 0; drive < 2; drive++) { 3992 drvp = &chp->ch_drive[drive]; 3993 /* If no drive, skip */ 3994 if ((drvp->drive_flags & DRIVE) == 0) 3995 continue; 3996 /* add timing values, setup DMA if needed */ 3997 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3998 (drvp->drive_flags & DRIVE_UDMA)) { 3999 /* use Ultra/DMA */ 4000 if (ACARD_IS_850(sc)) { 4001 idetime |= ATP850_SETTIME(drive, 4002 acard_act_udma[drvp->UDMA_mode], 4003 acard_rec_udma[drvp->UDMA_mode]); 4004 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4005 acard_udma_conf[drvp->UDMA_mode]); 4006 } else { 4007 idetime |= ATP860_SETTIME(channel, drive, 4008 acard_act_udma[drvp->UDMA_mode], 4009 acard_rec_udma[drvp->UDMA_mode]); 4010 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4011 acard_udma_conf[drvp->UDMA_mode]); 4012 } 4013 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4014 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4015 (drvp->drive_flags & DRIVE_DMA)) { 4016 /* use Multiword DMA */ 4017 drvp->drive_flags &= ~DRIVE_UDMA; 4018 if (ACARD_IS_850(sc)) { 4019 idetime |= ATP850_SETTIME(drive, 4020 acard_act_dma[drvp->DMA_mode], 4021 acard_rec_dma[drvp->DMA_mode]); 4022 } else { 4023 idetime |= ATP860_SETTIME(channel, drive, 4024 acard_act_dma[drvp->DMA_mode], 4025 acard_rec_dma[drvp->DMA_mode]); 4026 } 4027 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4028 } else { 4029 /* PIO only */ 4030 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4031 if (ACARD_IS_850(sc)) { 4032 idetime |= ATP850_SETTIME(drive, 4033 acard_act_pio[drvp->PIO_mode], 4034 acard_rec_pio[drvp->PIO_mode]); 4035 } else { 4036 idetime |= ATP860_SETTIME(channel, drive, 4037 acard_act_pio[drvp->PIO_mode], 4038 acard_rec_pio[drvp->PIO_mode]); 4039 } 4040 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4041 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4042 | ATP8x0_CTRL_EN(channel)); 4043 } 4044 } 4045 4046 if (idedma_ctl != 0) { 4047 /* Add software bits in status register */ 4048 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4049 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4050 } 4051 pciide_print_modes(cp); 4052 4053 if (ACARD_IS_850(sc)) { 4054 pci_conf_write(sc->sc_pc, sc->sc_tag, 4055 ATP850_IDETIME(channel), idetime); 4056 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4057 } else { 4058 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4059 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4060 } 4061 } 4062 4063 int 4064 acard_pci_intr(arg) 4065 void *arg; 4066 { 4067 struct pciide_softc *sc = arg; 4068 struct pciide_channel *cp; 4069 struct channel_softc *wdc_cp; 4070 int rv = 0; 4071 int dmastat, i, crv; 4072 4073 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4074 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4075 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4076 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4077 continue; 4078 cp = &sc->pciide_channels[i]; 4079 wdc_cp = &cp->wdc_channel; 4080 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4081 (void)wdcintr(wdc_cp); 4082 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4083 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4084 continue; 4085 } 4086 crv = wdcintr(wdc_cp); 4087 if (crv == 0) 4088 printf("%s:%d: bogus intr\n", 4089 sc->sc_wdcdev.sc_dev.dv_xname, i); 4090 else if (crv == 1) 4091 rv = 1; 4092 else if (rv == 0) 4093 rv = crv; 4094 } 4095 return rv; 4096 } 4097
Indexes created Thu Oct 02 10:09:58 GMT 2025