pciide.c revision 1.138
1 /* $NetBSD: pciide.c,v 1.138 2001/12/16 23:35:52 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.138 2001/12/16 23:35:52 bouyer Exp $"); 81 82 #ifndef WDCDEBUG 83 #define WDCDEBUG 84 #endif 85 86 #define DEBUG_DMA 0x01 87 #define DEBUG_XFERS 0x02 88 #define DEBUG_FUNCS 0x08 89 #define DEBUG_PROBE 0x10 90 #ifdef WDCDEBUG 91 int wdcdebug_pciide_mask = 0; 92 #define WDCDEBUG_PRINT(args, level) \ 93 if (wdcdebug_pciide_mask & (level)) printf args 94 #else 95 #define WDCDEBUG_PRINT(args, level) 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 102 #include <uvm/uvm_extern.h> 103 104 #include <machine/endian.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 #include <dev/pci/pciide_opti_reg.h> 120 #include <dev/pci/pciide_hpt_reg.h> 121 #include <dev/pci/pciide_acard_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 static int acer_isabr_match __P(( struct pci_attach_args *)); 192 193 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void pdc202xx_setup_channel __P((struct channel_softc*)); 195 void pdc20268_setup_channel __P((struct channel_softc*)); 196 int pdc202xx_pci_intr __P((void *)); 197 int pdc20265_pci_intr __P((void *)); 198 199 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void opti_setup_channel __P((struct channel_softc*)); 201 202 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void hpt_setup_channel __P((struct channel_softc*)); 204 int hpt_pci_intr __P((void *)); 205 206 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 207 void acard_setup_channel __P((struct channel_softc*)); 208 int acard_pci_intr __P((void *)); 209 210 #ifdef PCIIDE_WINBOND_ENABLE 211 void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 #endif 213 214 void pciide_channel_dma_setup __P((struct pciide_channel *)); 215 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 216 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 217 void pciide_dma_start __P((void*, int, int)); 218 int pciide_dma_finish __P((void*, int, int, int)); 219 void pciide_irqack __P((struct channel_softc *)); 220 void pciide_print_modes __P((struct pciide_channel *)); 221 222 struct pciide_product_desc { 223 u_int32_t ide_product; 224 int ide_flags; 225 const char *ide_name; 226 /* map and setup chip, probe drives */ 227 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 228 }; 229 230 /* Flags for ide_flags */ 231 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 232 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 233 234 /* Default product description for devices not known from this controller */ 235 const struct pciide_product_desc default_product_desc = { 236 0, 237 0, 238 "Generic PCI IDE controller", 239 default_chip_map, 240 }; 241 242 const struct pciide_product_desc pciide_intel_products[] = { 243 { PCI_PRODUCT_INTEL_82092AA, 244 0, 245 "Intel 82092AA IDE controller", 246 default_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82371FB_IDE, 249 0, 250 "Intel 82371FB IDE controller (PIIX)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82371SB_IDE, 254 0, 255 "Intel 82371SB IDE Interface (PIIX3)", 256 piix_chip_map, 257 }, 258 { PCI_PRODUCT_INTEL_82371AB_IDE, 259 0, 260 "Intel 82371AB IDE controller (PIIX4)", 261 piix_chip_map, 262 }, 263 { PCI_PRODUCT_INTEL_82440MX_IDE, 264 0, 265 "Intel 82440MX IDE controller", 266 piix_chip_map 267 }, 268 { PCI_PRODUCT_INTEL_82801AA_IDE, 269 0, 270 "Intel 82801AA IDE Controller (ICH)", 271 piix_chip_map, 272 }, 273 { PCI_PRODUCT_INTEL_82801AB_IDE, 274 0, 275 "Intel 82801AB IDE Controller (ICH0)", 276 piix_chip_map, 277 }, 278 { PCI_PRODUCT_INTEL_82801BA_IDE, 279 0, 280 "Intel 82801BA IDE Controller (ICH2)", 281 piix_chip_map, 282 }, 283 { PCI_PRODUCT_INTEL_82801BAM_IDE, 284 0, 285 "Intel 82801BAM IDE Controller (ICH2)", 286 piix_chip_map, 287 }, 288 { 0, 289 0, 290 NULL, 291 NULL 292 } 293 }; 294 295 const struct pciide_product_desc pciide_amd_products[] = { 296 { PCI_PRODUCT_AMD_PBC756_IDE, 297 0, 298 "Advanced Micro Devices AMD756 IDE Controller", 299 amd7x6_chip_map 300 }, 301 { PCI_PRODUCT_AMD_PBC766_IDE, 302 0, 303 "Advanced Micro Devices AMD766 IDE Controller", 304 amd7x6_chip_map 305 }, 306 { 0, 307 0, 308 NULL, 309 NULL 310 } 311 }; 312 313 const struct pciide_product_desc pciide_cmd_products[] = { 314 { PCI_PRODUCT_CMDTECH_640, 315 0, 316 "CMD Technology PCI0640", 317 cmd_chip_map 318 }, 319 { PCI_PRODUCT_CMDTECH_643, 320 0, 321 "CMD Technology PCI0643", 322 cmd0643_9_chip_map, 323 }, 324 { PCI_PRODUCT_CMDTECH_646, 325 0, 326 "CMD Technology PCI0646", 327 cmd0643_9_chip_map, 328 }, 329 { PCI_PRODUCT_CMDTECH_648, 330 IDE_PCI_CLASS_OVERRIDE, 331 "CMD Technology PCI0648", 332 cmd0643_9_chip_map, 333 }, 334 { PCI_PRODUCT_CMDTECH_649, 335 IDE_PCI_CLASS_OVERRIDE, 336 "CMD Technology PCI0649", 337 cmd0643_9_chip_map, 338 }, 339 { 0, 340 0, 341 NULL, 342 NULL 343 } 344 }; 345 346 const struct pciide_product_desc pciide_via_products[] = { 347 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 348 0, 349 NULL, 350 apollo_chip_map, 351 }, 352 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 353 0, 354 NULL, 355 apollo_chip_map, 356 }, 357 { 0, 358 0, 359 NULL, 360 NULL 361 } 362 }; 363 364 const struct pciide_product_desc pciide_cypress_products[] = { 365 { PCI_PRODUCT_CONTAQ_82C693, 366 IDE_16BIT_IOSPACE, 367 "Cypress 82C693 IDE Controller", 368 cy693_chip_map, 369 }, 370 { 0, 371 0, 372 NULL, 373 NULL 374 } 375 }; 376 377 const struct pciide_product_desc pciide_sis_products[] = { 378 { PCI_PRODUCT_SIS_5597_IDE, 379 0, 380 "Silicon Integrated System 5597/5598 IDE controller", 381 sis_chip_map, 382 }, 383 { 0, 384 0, 385 NULL, 386 NULL 387 } 388 }; 389 390 const struct pciide_product_desc pciide_acer_products[] = { 391 { PCI_PRODUCT_ALI_M5229, 392 0, 393 "Acer Labs M5229 UDMA IDE Controller", 394 acer_chip_map, 395 }, 396 { 0, 397 0, 398 NULL, 399 NULL 400 } 401 }; 402 403 const struct pciide_product_desc pciide_promise_products[] = { 404 { PCI_PRODUCT_PROMISE_ULTRA33, 405 IDE_PCI_CLASS_OVERRIDE, 406 "Promise Ultra33/ATA Bus Master IDE Accelerator", 407 pdc202xx_chip_map, 408 }, 409 { PCI_PRODUCT_PROMISE_ULTRA66, 410 IDE_PCI_CLASS_OVERRIDE, 411 "Promise Ultra66/ATA Bus Master IDE Accelerator", 412 pdc202xx_chip_map, 413 }, 414 { PCI_PRODUCT_PROMISE_ULTRA100, 415 IDE_PCI_CLASS_OVERRIDE, 416 "Promise Ultra100/ATA Bus Master IDE Accelerator", 417 pdc202xx_chip_map, 418 }, 419 { PCI_PRODUCT_PROMISE_ULTRA100X, 420 IDE_PCI_CLASS_OVERRIDE, 421 "Promise Ultra100/ATA Bus Master IDE Accelerator", 422 pdc202xx_chip_map, 423 }, 424 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 425 IDE_PCI_CLASS_OVERRIDE, 426 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 427 pdc202xx_chip_map, 428 }, 429 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 430 IDE_PCI_CLASS_OVERRIDE, 431 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 432 pdc202xx_chip_map, 433 }, 434 { PCI_PRODUCT_PROMISE_ULTRA133, 435 IDE_PCI_CLASS_OVERRIDE, 436 "Promise Ultra133/ATA Bus Master IDE Accelerator", 437 pdc202xx_chip_map, 438 }, 439 { 0, 440 0, 441 NULL, 442 NULL 443 } 444 }; 445 446 const struct pciide_product_desc pciide_opti_products[] = { 447 { PCI_PRODUCT_OPTI_82C621, 448 0, 449 "OPTi 82c621 PCI IDE controller", 450 opti_chip_map, 451 }, 452 { PCI_PRODUCT_OPTI_82C568, 453 0, 454 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 455 opti_chip_map, 456 }, 457 { PCI_PRODUCT_OPTI_82D568, 458 0, 459 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 460 opti_chip_map, 461 }, 462 { 0, 463 0, 464 NULL, 465 NULL 466 } 467 }; 468 469 const struct pciide_product_desc pciide_triones_products[] = { 470 { PCI_PRODUCT_TRIONES_HPT366, 471 IDE_PCI_CLASS_OVERRIDE, 472 NULL, 473 hpt_chip_map, 474 }, 475 { 0, 476 0, 477 NULL, 478 NULL 479 } 480 }; 481 482 const struct pciide_product_desc pciide_acard_products[] = { 483 { PCI_PRODUCT_ACARD_ATP850U, 484 IDE_PCI_CLASS_OVERRIDE, 485 "Acard ATP850U Ultra33 IDE Controller", 486 acard_chip_map, 487 }, 488 { PCI_PRODUCT_ACARD_ATP860, 489 IDE_PCI_CLASS_OVERRIDE, 490 "Acard ATP860 Ultra66 IDE Controller", 491 acard_chip_map, 492 }, 493 { PCI_PRODUCT_ACARD_ATP860A, 494 IDE_PCI_CLASS_OVERRIDE, 495 "Acard ATP860-A Ultra66 IDE Controller", 496 acard_chip_map, 497 }, 498 { 0, 499 0, 500 NULL, 501 NULL 502 } 503 }; 504 505 #ifdef PCIIDE_SERVERWORKS_ENABLE 506 const struct pciide_product_desc pciide_serverworks_products[] = { 507 { PCI_PRODUCT_SERVERWORKS_IDE, 508 0, 509 "ServerWorks ROSB4 IDE Controller", 510 piix_chip_map, 511 }, 512 { 0, 513 0, 514 NULL, 515 } 516 }; 517 #endif 518 519 #ifdef PCIIDE_WINBOND_ENABLE 520 const struct pciide_product_desc pciide_winbond_products[] = { 521 { PCI_PRODUCT_WINBOND_W83C553F_1, 522 0, 523 "Winbond W83C553F IDE controller", 524 winbond_chip_map, 525 }, 526 { 0, 527 0, 528 NULL, 529 } 530 }; 531 #endif 532 533 struct pciide_vendor_desc { 534 u_int32_t ide_vendor; 535 const struct pciide_product_desc *ide_products; 536 }; 537 538 const struct pciide_vendor_desc pciide_vendors[] = { 539 { PCI_VENDOR_INTEL, pciide_intel_products }, 540 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 541 { PCI_VENDOR_VIATECH, pciide_via_products }, 542 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 543 { PCI_VENDOR_SIS, pciide_sis_products }, 544 { PCI_VENDOR_ALI, pciide_acer_products }, 545 { PCI_VENDOR_PROMISE, pciide_promise_products }, 546 { PCI_VENDOR_AMD, pciide_amd_products }, 547 { PCI_VENDOR_OPTI, pciide_opti_products }, 548 { PCI_VENDOR_TRIONES, pciide_triones_products }, 549 { PCI_VENDOR_ACARD, pciide_acard_products }, 550 #ifdef PCIIDE_SERVERWORKS_ENABLE 551 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 552 #endif 553 #ifdef PCIIDE_WINBOND_ENABLE 554 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 555 #endif 556 { 0, NULL } 557 }; 558 559 /* options passed via the 'flags' config keyword */ 560 #define PCIIDE_OPTIONS_DMA 0x01 561 #define PCIIDE_OPTIONS_NODMA 0x02 562 563 int pciide_match __P((struct device *, struct cfdata *, void *)); 564 void pciide_attach __P((struct device *, struct device *, void *)); 565 566 struct cfattach pciide_ca = { 567 sizeof(struct pciide_softc), pciide_match, pciide_attach 568 }; 569 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 570 int pciide_mapregs_compat __P(( struct pci_attach_args *, 571 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 572 int pciide_mapregs_native __P((struct pci_attach_args *, 573 struct pciide_channel *, bus_size_t *, bus_size_t *, 574 int (*pci_intr) __P((void *)))); 575 void pciide_mapreg_dma __P((struct pciide_softc *, 576 struct pci_attach_args *)); 577 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 578 void pciide_mapchan __P((struct pci_attach_args *, 579 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 580 int (*pci_intr) __P((void *)))); 581 int pciide_chan_candisable __P((struct pciide_channel *)); 582 void pciide_map_compat_intr __P(( struct pci_attach_args *, 583 struct pciide_channel *, int, int)); 584 int pciide_compat_intr __P((void *)); 585 int pciide_pci_intr __P((void *)); 586 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 587 588 const struct pciide_product_desc * 589 pciide_lookup_product(id) 590 u_int32_t id; 591 { 592 const struct pciide_product_desc *pp; 593 const struct pciide_vendor_desc *vp; 594 595 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 596 if (PCI_VENDOR(id) == vp->ide_vendor) 597 break; 598 599 if ((pp = vp->ide_products) == NULL) 600 return NULL; 601 602 for (; pp->chip_map != NULL; pp++) 603 if (PCI_PRODUCT(id) == pp->ide_product) 604 break; 605 606 if (pp->chip_map == NULL) 607 return NULL; 608 return pp; 609 } 610 611 int 612 pciide_match(parent, match, aux) 613 struct device *parent; 614 struct cfdata *match; 615 void *aux; 616 { 617 struct pci_attach_args *pa = aux; 618 const struct pciide_product_desc *pp; 619 620 /* 621 * Check the ID register to see that it's a PCI IDE controller. 622 * If it is, we assume that we can deal with it; it _should_ 623 * work in a standardized way... 624 */ 625 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 626 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 627 return (1); 628 } 629 630 /* 631 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 632 * controllers. Let see if we can deal with it anyway. 633 */ 634 pp = pciide_lookup_product(pa->pa_id); 635 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 636 return (1); 637 } 638 639 return (0); 640 } 641 642 void 643 pciide_attach(parent, self, aux) 644 struct device *parent, *self; 645 void *aux; 646 { 647 struct pci_attach_args *pa = aux; 648 pci_chipset_tag_t pc = pa->pa_pc; 649 pcitag_t tag = pa->pa_tag; 650 struct pciide_softc *sc = (struct pciide_softc *)self; 651 pcireg_t csr; 652 char devinfo[256]; 653 const char *displaydev; 654 655 sc->sc_pp = pciide_lookup_product(pa->pa_id); 656 if (sc->sc_pp == NULL) { 657 sc->sc_pp = &default_product_desc; 658 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 659 displaydev = devinfo; 660 } else 661 displaydev = sc->sc_pp->ide_name; 662 663 /* if displaydev == NULL, printf is done in chip-specific map */ 664 if (displaydev) 665 printf(": %s (rev. 0x%02x)\n", displaydev, 666 PCI_REVISION(pa->pa_class)); 667 668 sc->sc_pc = pa->pa_pc; 669 sc->sc_tag = pa->pa_tag; 670 #ifdef WDCDEBUG 671 if (wdcdebug_pciide_mask & DEBUG_PROBE) 672 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 673 #endif 674 sc->sc_pp->chip_map(sc, pa); 675 676 if (sc->sc_dma_ok) { 677 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 678 csr |= PCI_COMMAND_MASTER_ENABLE; 679 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 680 } 681 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 682 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 683 } 684 685 /* tell wether the chip is enabled or not */ 686 int 687 pciide_chipen(sc, pa) 688 struct pciide_softc *sc; 689 struct pci_attach_args *pa; 690 { 691 pcireg_t csr; 692 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 693 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 694 PCI_COMMAND_STATUS_REG); 695 printf("%s: device disabled (at %s)\n", 696 sc->sc_wdcdev.sc_dev.dv_xname, 697 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 698 "device" : "bridge"); 699 return 0; 700 } 701 return 1; 702 } 703 704 int 705 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 706 struct pci_attach_args *pa; 707 struct pciide_channel *cp; 708 int compatchan; 709 bus_size_t *cmdsizep, *ctlsizep; 710 { 711 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 712 struct channel_softc *wdc_cp = &cp->wdc_channel; 713 714 cp->compat = 1; 715 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 716 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 717 718 wdc_cp->cmd_iot = pa->pa_iot; 719 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 720 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 721 printf("%s: couldn't map %s channel cmd regs\n", 722 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 723 return (0); 724 } 725 726 wdc_cp->ctl_iot = pa->pa_iot; 727 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 728 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 729 printf("%s: couldn't map %s channel ctl regs\n", 730 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 731 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 732 PCIIDE_COMPAT_CMD_SIZE); 733 return (0); 734 } 735 736 return (1); 737 } 738 739 int 740 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 741 struct pci_attach_args * pa; 742 struct pciide_channel *cp; 743 bus_size_t *cmdsizep, *ctlsizep; 744 int (*pci_intr) __P((void *)); 745 { 746 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 747 struct channel_softc *wdc_cp = &cp->wdc_channel; 748 const char *intrstr; 749 pci_intr_handle_t intrhandle; 750 751 cp->compat = 0; 752 753 if (sc->sc_pci_ih == NULL) { 754 if (pci_intr_map(pa, &intrhandle) != 0) { 755 printf("%s: couldn't map native-PCI interrupt\n", 756 sc->sc_wdcdev.sc_dev.dv_xname); 757 return 0; 758 } 759 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 760 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 761 intrhandle, IPL_BIO, pci_intr, sc); 762 if (sc->sc_pci_ih != NULL) { 763 printf("%s: using %s for native-PCI interrupt\n", 764 sc->sc_wdcdev.sc_dev.dv_xname, 765 intrstr ? intrstr : "unknown interrupt"); 766 } else { 767 printf("%s: couldn't establish native-PCI interrupt", 768 sc->sc_wdcdev.sc_dev.dv_xname); 769 if (intrstr != NULL) 770 printf(" at %s", intrstr); 771 printf("\n"); 772 return 0; 773 } 774 } 775 cp->ih = sc->sc_pci_ih; 776 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 777 PCI_MAPREG_TYPE_IO, 0, 778 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 779 printf("%s: couldn't map %s channel cmd regs\n", 780 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 781 return 0; 782 } 783 784 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 785 PCI_MAPREG_TYPE_IO, 0, 786 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 787 printf("%s: couldn't map %s channel ctl regs\n", 788 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 789 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 790 return 0; 791 } 792 /* 793 * In native mode, 4 bytes of I/O space are mapped for the control 794 * register, the control register is at offset 2. Pass the generic 795 * code a handle for only one byte at the rigth offset. 796 */ 797 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 798 &wdc_cp->ctl_ioh) != 0) { 799 printf("%s: unable to subregion %s channel ctl regs\n", 800 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 801 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 802 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 803 return 0; 804 } 805 return (1); 806 } 807 808 void 809 pciide_mapreg_dma(sc, pa) 810 struct pciide_softc *sc; 811 struct pci_attach_args *pa; 812 { 813 pcireg_t maptype; 814 bus_addr_t addr; 815 816 /* 817 * Map DMA registers 818 * 819 * Note that sc_dma_ok is the right variable to test to see if 820 * DMA can be done. If the interface doesn't support DMA, 821 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 822 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 823 * non-zero if the interface supports DMA and the registers 824 * could be mapped. 825 * 826 * XXX Note that despite the fact that the Bus Master IDE specs 827 * XXX say that "The bus master IDE function uses 16 bytes of IO 828 * XXX space," some controllers (at least the United 829 * XXX Microelectronics UM8886BF) place it in memory space. 830 */ 831 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 832 PCIIDE_REG_BUS_MASTER_DMA); 833 834 switch (maptype) { 835 case PCI_MAPREG_TYPE_IO: 836 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 837 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 838 &addr, NULL, NULL) == 0); 839 if (sc->sc_dma_ok == 0) { 840 printf(", but unused (couldn't query registers)"); 841 break; 842 } 843 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 844 && addr >= 0x10000) { 845 sc->sc_dma_ok = 0; 846 printf(", but unused (registers at unsafe address " 847 "%#lx)", (unsigned long)addr); 848 break; 849 } 850 /* FALLTHROUGH */ 851 852 case PCI_MAPREG_MEM_TYPE_32BIT: 853 sc->sc_dma_ok = (pci_mapreg_map(pa, 854 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 855 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 856 sc->sc_dmat = pa->pa_dmat; 857 if (sc->sc_dma_ok == 0) { 858 printf(", but unused (couldn't map registers)"); 859 } else { 860 sc->sc_wdcdev.dma_arg = sc; 861 sc->sc_wdcdev.dma_init = pciide_dma_init; 862 sc->sc_wdcdev.dma_start = pciide_dma_start; 863 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 864 } 865 866 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 867 PCIIDE_OPTIONS_NODMA) { 868 printf(", but unused (forced off by config file)"); 869 sc->sc_dma_ok = 0; 870 } 871 break; 872 873 default: 874 sc->sc_dma_ok = 0; 875 printf(", but unsupported register maptype (0x%x)", maptype); 876 } 877 } 878 879 int 880 pciide_compat_intr(arg) 881 void *arg; 882 { 883 struct pciide_channel *cp = arg; 884 885 #ifdef DIAGNOSTIC 886 /* should only be called for a compat channel */ 887 if (cp->compat == 0) 888 panic("pciide compat intr called for non-compat chan %p\n", cp); 889 #endif 890 return (wdcintr(&cp->wdc_channel)); 891 } 892 893 int 894 pciide_pci_intr(arg) 895 void *arg; 896 { 897 struct pciide_softc *sc = arg; 898 struct pciide_channel *cp; 899 struct channel_softc *wdc_cp; 900 int i, rv, crv; 901 902 rv = 0; 903 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 904 cp = &sc->pciide_channels[i]; 905 wdc_cp = &cp->wdc_channel; 906 907 /* If a compat channel skip. */ 908 if (cp->compat) 909 continue; 910 /* if this channel not waiting for intr, skip */ 911 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 912 continue; 913 914 crv = wdcintr(wdc_cp); 915 if (crv == 0) 916 ; /* leave rv alone */ 917 else if (crv == 1) 918 rv = 1; /* claim the intr */ 919 else if (rv == 0) /* crv should be -1 in this case */ 920 rv = crv; /* if we've done no better, take it */ 921 } 922 return (rv); 923 } 924 925 void 926 pciide_channel_dma_setup(cp) 927 struct pciide_channel *cp; 928 { 929 int drive; 930 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 931 struct ata_drive_datas *drvp; 932 933 for (drive = 0; drive < 2; drive++) { 934 drvp = &cp->wdc_channel.ch_drive[drive]; 935 /* If no drive, skip */ 936 if ((drvp->drive_flags & DRIVE) == 0) 937 continue; 938 /* setup DMA if needed */ 939 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 940 (drvp->drive_flags & DRIVE_UDMA) == 0) || 941 sc->sc_dma_ok == 0) { 942 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 943 continue; 944 } 945 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 946 != 0) { 947 /* Abort DMA setup */ 948 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 949 continue; 950 } 951 } 952 } 953 954 int 955 pciide_dma_table_setup(sc, channel, drive) 956 struct pciide_softc *sc; 957 int channel, drive; 958 { 959 bus_dma_segment_t seg; 960 int error, rseg; 961 const bus_size_t dma_table_size = 962 sizeof(struct idedma_table) * NIDEDMA_TABLES; 963 struct pciide_dma_maps *dma_maps = 964 &sc->pciide_channels[channel].dma_maps[drive]; 965 966 /* If table was already allocated, just return */ 967 if (dma_maps->dma_table) 968 return 0; 969 970 /* Allocate memory for the DMA tables and map it */ 971 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 972 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 973 BUS_DMA_NOWAIT)) != 0) { 974 printf("%s:%d: unable to allocate table DMA for " 975 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 976 channel, drive, error); 977 return error; 978 } 979 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 980 dma_table_size, 981 (caddr_t *)&dma_maps->dma_table, 982 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 983 printf("%s:%d: unable to map table DMA for" 984 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 985 channel, drive, error); 986 return error; 987 } 988 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 989 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 990 (unsigned long)seg.ds_addr), DEBUG_PROBE); 991 992 /* Create and load table DMA map for this disk */ 993 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 994 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 995 &dma_maps->dmamap_table)) != 0) { 996 printf("%s:%d: unable to create table DMA map for " 997 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 998 channel, drive, error); 999 return error; 1000 } 1001 if ((error = bus_dmamap_load(sc->sc_dmat, 1002 dma_maps->dmamap_table, 1003 dma_maps->dma_table, 1004 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1005 printf("%s:%d: unable to load table DMA map for " 1006 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1007 channel, drive, error); 1008 return error; 1009 } 1010 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1011 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1012 DEBUG_PROBE); 1013 /* Create a xfer DMA map for this drive */ 1014 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1015 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1016 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1017 &dma_maps->dmamap_xfer)) != 0) { 1018 printf("%s:%d: unable to create xfer DMA map for " 1019 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1020 channel, drive, error); 1021 return error; 1022 } 1023 return 0; 1024 } 1025 1026 int 1027 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1028 void *v; 1029 int channel, drive; 1030 void *databuf; 1031 size_t datalen; 1032 int flags; 1033 { 1034 struct pciide_softc *sc = v; 1035 int error, seg; 1036 struct pciide_dma_maps *dma_maps = 1037 &sc->pciide_channels[channel].dma_maps[drive]; 1038 1039 error = bus_dmamap_load(sc->sc_dmat, 1040 dma_maps->dmamap_xfer, 1041 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1042 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1043 if (error) { 1044 printf("%s:%d: unable to load xfer DMA map for" 1045 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1046 channel, drive, error); 1047 return error; 1048 } 1049 1050 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1051 dma_maps->dmamap_xfer->dm_mapsize, 1052 (flags & WDC_DMA_READ) ? 1053 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1054 1055 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1056 #ifdef DIAGNOSTIC 1057 /* A segment must not cross a 64k boundary */ 1058 { 1059 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1060 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1061 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1062 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1063 printf("pciide_dma: segment %d physical addr 0x%lx" 1064 " len 0x%lx not properly aligned\n", 1065 seg, phys, len); 1066 panic("pciide_dma: buf align"); 1067 } 1068 } 1069 #endif 1070 dma_maps->dma_table[seg].base_addr = 1071 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1072 dma_maps->dma_table[seg].byte_count = 1073 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1074 IDEDMA_BYTE_COUNT_MASK); 1075 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1076 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1077 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1078 1079 } 1080 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1081 htole32(IDEDMA_BYTE_COUNT_EOT); 1082 1083 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1084 dma_maps->dmamap_table->dm_mapsize, 1085 BUS_DMASYNC_PREWRITE); 1086 1087 /* Maps are ready. Start DMA function */ 1088 #ifdef DIAGNOSTIC 1089 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1090 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1091 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1092 panic("pciide_dma_init: table align"); 1093 } 1094 #endif 1095 1096 /* Clear status bits */ 1097 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1098 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1099 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1100 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1101 /* Write table addr */ 1102 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1103 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1104 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1105 /* set read/write */ 1106 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1107 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1108 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1109 /* remember flags */ 1110 dma_maps->dma_flags = flags; 1111 return 0; 1112 } 1113 1114 void 1115 pciide_dma_start(v, channel, drive) 1116 void *v; 1117 int channel, drive; 1118 { 1119 struct pciide_softc *sc = v; 1120 1121 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1122 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1123 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1124 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1125 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1126 } 1127 1128 int 1129 pciide_dma_finish(v, channel, drive, force) 1130 void *v; 1131 int channel, drive; 1132 int force; 1133 { 1134 struct pciide_softc *sc = v; 1135 u_int8_t status; 1136 int error = 0; 1137 struct pciide_dma_maps *dma_maps = 1138 &sc->pciide_channels[channel].dma_maps[drive]; 1139 1140 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1141 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1142 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1143 DEBUG_XFERS); 1144 1145 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1146 return WDC_DMAST_NOIRQ; 1147 1148 /* stop DMA channel */ 1149 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1150 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1151 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1152 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1153 1154 /* Unload the map of the data buffer */ 1155 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1156 dma_maps->dmamap_xfer->dm_mapsize, 1157 (dma_maps->dma_flags & WDC_DMA_READ) ? 1158 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1159 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1160 1161 if ((status & IDEDMA_CTL_ERR) != 0) { 1162 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1163 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1164 error |= WDC_DMAST_ERR; 1165 } 1166 1167 if ((status & IDEDMA_CTL_INTR) == 0) { 1168 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1169 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1170 drive, status); 1171 error |= WDC_DMAST_NOIRQ; 1172 } 1173 1174 if ((status & IDEDMA_CTL_ACT) != 0) { 1175 /* data underrun, may be a valid condition for ATAPI */ 1176 error |= WDC_DMAST_UNDER; 1177 } 1178 return error; 1179 } 1180 1181 void 1182 pciide_irqack(chp) 1183 struct channel_softc *chp; 1184 { 1185 struct pciide_channel *cp = (struct pciide_channel*)chp; 1186 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1187 1188 /* clear status bits in IDE DMA registers */ 1189 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1190 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1191 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1192 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1193 } 1194 1195 /* some common code used by several chip_map */ 1196 int 1197 pciide_chansetup(sc, channel, interface) 1198 struct pciide_softc *sc; 1199 int channel; 1200 pcireg_t interface; 1201 { 1202 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1203 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1204 cp->name = PCIIDE_CHANNEL_NAME(channel); 1205 cp->wdc_channel.channel = channel; 1206 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1207 cp->wdc_channel.ch_queue = 1208 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1209 if (cp->wdc_channel.ch_queue == NULL) { 1210 printf("%s %s channel: " 1211 "can't allocate memory for command queue", 1212 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1213 return 0; 1214 } 1215 printf("%s: %s channel %s to %s mode\n", 1216 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1217 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1218 "configured" : "wired", 1219 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1220 "native-PCI" : "compatibility"); 1221 return 1; 1222 } 1223 1224 /* some common code used by several chip channel_map */ 1225 void 1226 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1227 struct pci_attach_args *pa; 1228 struct pciide_channel *cp; 1229 pcireg_t interface; 1230 bus_size_t *cmdsizep, *ctlsizep; 1231 int (*pci_intr) __P((void *)); 1232 { 1233 struct channel_softc *wdc_cp = &cp->wdc_channel; 1234 1235 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1236 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1237 pci_intr); 1238 else 1239 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1240 wdc_cp->channel, cmdsizep, ctlsizep); 1241 1242 if (cp->hw_ok == 0) 1243 return; 1244 wdc_cp->data32iot = wdc_cp->cmd_iot; 1245 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1246 wdcattach(wdc_cp); 1247 } 1248 1249 /* 1250 * Generic code to call to know if a channel can be disabled. Return 1 1251 * if channel can be disabled, 0 if not 1252 */ 1253 int 1254 pciide_chan_candisable(cp) 1255 struct pciide_channel *cp; 1256 { 1257 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1258 struct channel_softc *wdc_cp = &cp->wdc_channel; 1259 1260 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1261 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1262 printf("%s: disabling %s channel (no drives)\n", 1263 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1264 cp->hw_ok = 0; 1265 return 1; 1266 } 1267 return 0; 1268 } 1269 1270 /* 1271 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1272 * Set hw_ok=0 on failure 1273 */ 1274 void 1275 pciide_map_compat_intr(pa, cp, compatchan, interface) 1276 struct pci_attach_args *pa; 1277 struct pciide_channel *cp; 1278 int compatchan, interface; 1279 { 1280 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1281 struct channel_softc *wdc_cp = &cp->wdc_channel; 1282 1283 if (cp->hw_ok == 0) 1284 return; 1285 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1286 return; 1287 1288 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1289 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1290 pa, compatchan, pciide_compat_intr, cp); 1291 if (cp->ih == NULL) { 1292 #endif 1293 printf("%s: no compatibility interrupt for use by %s " 1294 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1295 cp->hw_ok = 0; 1296 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1297 } 1298 #endif 1299 } 1300 1301 void 1302 pciide_print_modes(cp) 1303 struct pciide_channel *cp; 1304 { 1305 wdc_print_modes(&cp->wdc_channel); 1306 } 1307 1308 void 1309 default_chip_map(sc, pa) 1310 struct pciide_softc *sc; 1311 struct pci_attach_args *pa; 1312 { 1313 struct pciide_channel *cp; 1314 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1315 pcireg_t csr; 1316 int channel, drive; 1317 struct ata_drive_datas *drvp; 1318 u_int8_t idedma_ctl; 1319 bus_size_t cmdsize, ctlsize; 1320 char *failreason; 1321 1322 if (pciide_chipen(sc, pa) == 0) 1323 return; 1324 1325 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1326 printf("%s: bus-master DMA support present", 1327 sc->sc_wdcdev.sc_dev.dv_xname); 1328 if (sc->sc_pp == &default_product_desc && 1329 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1330 PCIIDE_OPTIONS_DMA) == 0) { 1331 printf(", but unused (no driver support)"); 1332 sc->sc_dma_ok = 0; 1333 } else { 1334 pciide_mapreg_dma(sc, pa); 1335 if (sc->sc_dma_ok != 0) 1336 printf(", used without full driver " 1337 "support"); 1338 } 1339 } else { 1340 printf("%s: hardware does not support DMA", 1341 sc->sc_wdcdev.sc_dev.dv_xname); 1342 sc->sc_dma_ok = 0; 1343 } 1344 printf("\n"); 1345 if (sc->sc_dma_ok) { 1346 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1347 sc->sc_wdcdev.irqack = pciide_irqack; 1348 } 1349 sc->sc_wdcdev.PIO_cap = 0; 1350 sc->sc_wdcdev.DMA_cap = 0; 1351 1352 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1353 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1354 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1355 1356 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1357 cp = &sc->pciide_channels[channel]; 1358 if (pciide_chansetup(sc, channel, interface) == 0) 1359 continue; 1360 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1361 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1362 &ctlsize, pciide_pci_intr); 1363 } else { 1364 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1365 channel, &cmdsize, &ctlsize); 1366 } 1367 if (cp->hw_ok == 0) 1368 continue; 1369 /* 1370 * Check to see if something appears to be there. 1371 */ 1372 failreason = NULL; 1373 if (!wdcprobe(&cp->wdc_channel)) { 1374 failreason = "not responding; disabled or no drives?"; 1375 goto next; 1376 } 1377 /* 1378 * Now, make sure it's actually attributable to this PCI IDE 1379 * channel by trying to access the channel again while the 1380 * PCI IDE controller's I/O space is disabled. (If the 1381 * channel no longer appears to be there, it belongs to 1382 * this controller.) YUCK! 1383 */ 1384 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1385 PCI_COMMAND_STATUS_REG); 1386 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1387 csr & ~PCI_COMMAND_IO_ENABLE); 1388 if (wdcprobe(&cp->wdc_channel)) 1389 failreason = "other hardware responding at addresses"; 1390 pci_conf_write(sc->sc_pc, sc->sc_tag, 1391 PCI_COMMAND_STATUS_REG, csr); 1392 next: 1393 if (failreason) { 1394 printf("%s: %s channel ignored (%s)\n", 1395 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1396 failreason); 1397 cp->hw_ok = 0; 1398 bus_space_unmap(cp->wdc_channel.cmd_iot, 1399 cp->wdc_channel.cmd_ioh, cmdsize); 1400 bus_space_unmap(cp->wdc_channel.ctl_iot, 1401 cp->wdc_channel.ctl_ioh, ctlsize); 1402 } else { 1403 pciide_map_compat_intr(pa, cp, channel, interface); 1404 } 1405 if (cp->hw_ok) { 1406 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1407 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1408 wdcattach(&cp->wdc_channel); 1409 } 1410 } 1411 1412 if (sc->sc_dma_ok == 0) 1413 return; 1414 1415 /* Allocate DMA maps */ 1416 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1417 idedma_ctl = 0; 1418 cp = &sc->pciide_channels[channel]; 1419 for (drive = 0; drive < 2; drive++) { 1420 drvp = &cp->wdc_channel.ch_drive[drive]; 1421 /* If no drive, skip */ 1422 if ((drvp->drive_flags & DRIVE) == 0) 1423 continue; 1424 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1425 continue; 1426 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1427 /* Abort DMA setup */ 1428 printf("%s:%d:%d: can't allocate DMA maps, " 1429 "using PIO transfers\n", 1430 sc->sc_wdcdev.sc_dev.dv_xname, 1431 channel, drive); 1432 drvp->drive_flags &= ~DRIVE_DMA; 1433 } 1434 printf("%s:%d:%d: using DMA data transfers\n", 1435 sc->sc_wdcdev.sc_dev.dv_xname, 1436 channel, drive); 1437 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1438 } 1439 if (idedma_ctl != 0) { 1440 /* Add software bits in status register */ 1441 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1442 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1443 idedma_ctl); 1444 } 1445 } 1446 } 1447 1448 void 1449 piix_chip_map(sc, pa) 1450 struct pciide_softc *sc; 1451 struct pci_attach_args *pa; 1452 { 1453 struct pciide_channel *cp; 1454 int channel; 1455 u_int32_t idetim; 1456 bus_size_t cmdsize, ctlsize; 1457 1458 if (pciide_chipen(sc, pa) == 0) 1459 return; 1460 1461 printf("%s: bus-master DMA support present", 1462 sc->sc_wdcdev.sc_dev.dv_xname); 1463 pciide_mapreg_dma(sc, pa); 1464 printf("\n"); 1465 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1466 WDC_CAPABILITY_MODE; 1467 if (sc->sc_dma_ok) { 1468 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1469 sc->sc_wdcdev.irqack = pciide_irqack; 1470 switch(sc->sc_pp->ide_product) { 1471 case PCI_PRODUCT_INTEL_82371AB_IDE: 1472 case PCI_PRODUCT_INTEL_82440MX_IDE: 1473 case PCI_PRODUCT_INTEL_82801AA_IDE: 1474 case PCI_PRODUCT_INTEL_82801AB_IDE: 1475 case PCI_PRODUCT_INTEL_82801BA_IDE: 1476 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1477 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1478 } 1479 } 1480 sc->sc_wdcdev.PIO_cap = 4; 1481 sc->sc_wdcdev.DMA_cap = 2; 1482 switch(sc->sc_pp->ide_product) { 1483 case PCI_PRODUCT_INTEL_82801AA_IDE: 1484 sc->sc_wdcdev.UDMA_cap = 4; 1485 break; 1486 case PCI_PRODUCT_INTEL_82801BA_IDE: 1487 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1488 sc->sc_wdcdev.UDMA_cap = 5; 1489 break; 1490 default: 1491 sc->sc_wdcdev.UDMA_cap = 2; 1492 } 1493 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1494 sc->sc_wdcdev.set_modes = piix_setup_channel; 1495 else 1496 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1497 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1498 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1499 1500 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1501 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1502 DEBUG_PROBE); 1503 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1504 WDCDEBUG_PRINT((", sidetim=0x%x", 1505 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1506 DEBUG_PROBE); 1507 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1508 WDCDEBUG_PRINT((", udamreg 0x%x", 1509 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1510 DEBUG_PROBE); 1511 } 1512 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1513 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1514 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1515 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1516 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1517 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1518 DEBUG_PROBE); 1519 } 1520 1521 } 1522 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1523 1524 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1525 cp = &sc->pciide_channels[channel]; 1526 /* PIIX is compat-only */ 1527 if (pciide_chansetup(sc, channel, 0) == 0) 1528 continue; 1529 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1530 if ((PIIX_IDETIM_READ(idetim, channel) & 1531 PIIX_IDETIM_IDE) == 0) { 1532 printf("%s: %s channel ignored (disabled)\n", 1533 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1534 continue; 1535 } 1536 /* PIIX are compat-only pciide devices */ 1537 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1538 if (cp->hw_ok == 0) 1539 continue; 1540 if (pciide_chan_candisable(cp)) { 1541 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1542 channel); 1543 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1544 idetim); 1545 } 1546 pciide_map_compat_intr(pa, cp, channel, 0); 1547 if (cp->hw_ok == 0) 1548 continue; 1549 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1550 } 1551 1552 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1553 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1554 DEBUG_PROBE); 1555 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1556 WDCDEBUG_PRINT((", sidetim=0x%x", 1557 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1558 DEBUG_PROBE); 1559 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1560 WDCDEBUG_PRINT((", udamreg 0x%x", 1561 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1562 DEBUG_PROBE); 1563 } 1564 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1565 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1566 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1567 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1568 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1569 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1570 DEBUG_PROBE); 1571 } 1572 } 1573 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1574 } 1575 1576 void 1577 piix_setup_channel(chp) 1578 struct channel_softc *chp; 1579 { 1580 u_int8_t mode[2], drive; 1581 u_int32_t oidetim, idetim, idedma_ctl; 1582 struct pciide_channel *cp = (struct pciide_channel*)chp; 1583 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1584 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1585 1586 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1587 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1588 idedma_ctl = 0; 1589 1590 /* set up new idetim: Enable IDE registers decode */ 1591 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1592 chp->channel); 1593 1594 /* setup DMA */ 1595 pciide_channel_dma_setup(cp); 1596 1597 /* 1598 * Here we have to mess up with drives mode: PIIX can't have 1599 * different timings for master and slave drives. 1600 * We need to find the best combination. 1601 */ 1602 1603 /* If both drives supports DMA, take the lower mode */ 1604 if ((drvp[0].drive_flags & DRIVE_DMA) && 1605 (drvp[1].drive_flags & DRIVE_DMA)) { 1606 mode[0] = mode[1] = 1607 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1608 drvp[0].DMA_mode = mode[0]; 1609 drvp[1].DMA_mode = mode[1]; 1610 goto ok; 1611 } 1612 /* 1613 * If only one drive supports DMA, use its mode, and 1614 * put the other one in PIO mode 0 if mode not compatible 1615 */ 1616 if (drvp[0].drive_flags & DRIVE_DMA) { 1617 mode[0] = drvp[0].DMA_mode; 1618 mode[1] = drvp[1].PIO_mode; 1619 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1620 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1621 mode[1] = drvp[1].PIO_mode = 0; 1622 goto ok; 1623 } 1624 if (drvp[1].drive_flags & DRIVE_DMA) { 1625 mode[1] = drvp[1].DMA_mode; 1626 mode[0] = drvp[0].PIO_mode; 1627 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1628 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1629 mode[0] = drvp[0].PIO_mode = 0; 1630 goto ok; 1631 } 1632 /* 1633 * If both drives are not DMA, takes the lower mode, unless 1634 * one of them is PIO mode < 2 1635 */ 1636 if (drvp[0].PIO_mode < 2) { 1637 mode[0] = drvp[0].PIO_mode = 0; 1638 mode[1] = drvp[1].PIO_mode; 1639 } else if (drvp[1].PIO_mode < 2) { 1640 mode[1] = drvp[1].PIO_mode = 0; 1641 mode[0] = drvp[0].PIO_mode; 1642 } else { 1643 mode[0] = mode[1] = 1644 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1645 drvp[0].PIO_mode = mode[0]; 1646 drvp[1].PIO_mode = mode[1]; 1647 } 1648 ok: /* The modes are setup */ 1649 for (drive = 0; drive < 2; drive++) { 1650 if (drvp[drive].drive_flags & DRIVE_DMA) { 1651 idetim |= piix_setup_idetim_timings( 1652 mode[drive], 1, chp->channel); 1653 goto end; 1654 } 1655 } 1656 /* If we are there, none of the drives are DMA */ 1657 if (mode[0] >= 2) 1658 idetim |= piix_setup_idetim_timings( 1659 mode[0], 0, chp->channel); 1660 else 1661 idetim |= piix_setup_idetim_timings( 1662 mode[1], 0, chp->channel); 1663 end: /* 1664 * timing mode is now set up in the controller. Enable 1665 * it per-drive 1666 */ 1667 for (drive = 0; drive < 2; drive++) { 1668 /* If no drive, skip */ 1669 if ((drvp[drive].drive_flags & DRIVE) == 0) 1670 continue; 1671 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1672 if (drvp[drive].drive_flags & DRIVE_DMA) 1673 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1674 } 1675 if (idedma_ctl != 0) { 1676 /* Add software bits in status register */ 1677 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1678 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1679 idedma_ctl); 1680 } 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1682 pciide_print_modes(cp); 1683 } 1684 1685 void 1686 piix3_4_setup_channel(chp) 1687 struct channel_softc *chp; 1688 { 1689 struct ata_drive_datas *drvp; 1690 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1691 struct pciide_channel *cp = (struct pciide_channel*)chp; 1692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1693 int drive; 1694 int channel = chp->channel; 1695 1696 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1697 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1698 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1699 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1700 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1701 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1702 PIIX_SIDETIM_RTC_MASK(channel)); 1703 1704 idedma_ctl = 0; 1705 /* If channel disabled, no need to go further */ 1706 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1707 return; 1708 /* set up new idetim: Enable IDE registers decode */ 1709 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1710 1711 /* setup DMA if needed */ 1712 pciide_channel_dma_setup(cp); 1713 1714 for (drive = 0; drive < 2; drive++) { 1715 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1716 PIIX_UDMATIM_SET(0x3, channel, drive)); 1717 drvp = &chp->ch_drive[drive]; 1718 /* If no drive, skip */ 1719 if ((drvp->drive_flags & DRIVE) == 0) 1720 continue; 1721 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1722 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1723 goto pio; 1724 1725 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1726 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1727 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1728 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1729 ideconf |= PIIX_CONFIG_PINGPONG; 1730 } 1731 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1732 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1733 /* setup Ultra/100 */ 1734 if (drvp->UDMA_mode > 2 && 1735 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1736 drvp->UDMA_mode = 2; 1737 if (drvp->UDMA_mode > 4) { 1738 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1739 } else { 1740 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1741 if (drvp->UDMA_mode > 2) { 1742 ideconf |= PIIX_CONFIG_UDMA66(channel, 1743 drive); 1744 } else { 1745 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1746 drive); 1747 } 1748 } 1749 } 1750 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1751 /* setup Ultra/66 */ 1752 if (drvp->UDMA_mode > 2 && 1753 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1754 drvp->UDMA_mode = 2; 1755 if (drvp->UDMA_mode > 2) 1756 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1757 else 1758 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1759 } 1760 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1761 (drvp->drive_flags & DRIVE_UDMA)) { 1762 /* use Ultra/DMA */ 1763 drvp->drive_flags &= ~DRIVE_DMA; 1764 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1765 udmareg |= PIIX_UDMATIM_SET( 1766 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1767 } else { 1768 /* use Multiword DMA */ 1769 drvp->drive_flags &= ~DRIVE_UDMA; 1770 if (drive == 0) { 1771 idetim |= piix_setup_idetim_timings( 1772 drvp->DMA_mode, 1, channel); 1773 } else { 1774 sidetim |= piix_setup_sidetim_timings( 1775 drvp->DMA_mode, 1, channel); 1776 idetim =PIIX_IDETIM_SET(idetim, 1777 PIIX_IDETIM_SITRE, channel); 1778 } 1779 } 1780 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1781 1782 pio: /* use PIO mode */ 1783 idetim |= piix_setup_idetim_drvs(drvp); 1784 if (drive == 0) { 1785 idetim |= piix_setup_idetim_timings( 1786 drvp->PIO_mode, 0, channel); 1787 } else { 1788 sidetim |= piix_setup_sidetim_timings( 1789 drvp->PIO_mode, 0, channel); 1790 idetim =PIIX_IDETIM_SET(idetim, 1791 PIIX_IDETIM_SITRE, channel); 1792 } 1793 } 1794 if (idedma_ctl != 0) { 1795 /* Add software bits in status register */ 1796 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1797 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1798 idedma_ctl); 1799 } 1800 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1801 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1802 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1803 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1804 pciide_print_modes(cp); 1805 } 1806 1807 1808 /* setup ISP and RTC fields, based on mode */ 1809 static u_int32_t 1810 piix_setup_idetim_timings(mode, dma, channel) 1811 u_int8_t mode; 1812 u_int8_t dma; 1813 u_int8_t channel; 1814 { 1815 1816 if (dma) 1817 return PIIX_IDETIM_SET(0, 1818 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1819 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1820 channel); 1821 else 1822 return PIIX_IDETIM_SET(0, 1823 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1824 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1825 channel); 1826 } 1827 1828 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1829 static u_int32_t 1830 piix_setup_idetim_drvs(drvp) 1831 struct ata_drive_datas *drvp; 1832 { 1833 u_int32_t ret = 0; 1834 struct channel_softc *chp = drvp->chnl_softc; 1835 u_int8_t channel = chp->channel; 1836 u_int8_t drive = drvp->drive; 1837 1838 /* 1839 * If drive is using UDMA, timings setups are independant 1840 * So just check DMA and PIO here. 1841 */ 1842 if (drvp->drive_flags & DRIVE_DMA) { 1843 /* if mode = DMA mode 0, use compatible timings */ 1844 if ((drvp->drive_flags & DRIVE_DMA) && 1845 drvp->DMA_mode == 0) { 1846 drvp->PIO_mode = 0; 1847 return ret; 1848 } 1849 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1850 /* 1851 * PIO and DMA timings are the same, use fast timings for PIO 1852 * too, else use compat timings. 1853 */ 1854 if ((piix_isp_pio[drvp->PIO_mode] != 1855 piix_isp_dma[drvp->DMA_mode]) || 1856 (piix_rtc_pio[drvp->PIO_mode] != 1857 piix_rtc_dma[drvp->DMA_mode])) 1858 drvp->PIO_mode = 0; 1859 /* if PIO mode <= 2, use compat timings for PIO */ 1860 if (drvp->PIO_mode <= 2) { 1861 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1862 channel); 1863 return ret; 1864 } 1865 } 1866 1867 /* 1868 * Now setup PIO modes. If mode < 2, use compat timings. 1869 * Else enable fast timings. Enable IORDY and prefetch/post 1870 * if PIO mode >= 3. 1871 */ 1872 1873 if (drvp->PIO_mode < 2) 1874 return ret; 1875 1876 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1877 if (drvp->PIO_mode >= 3) { 1878 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1879 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1880 } 1881 return ret; 1882 } 1883 1884 /* setup values in SIDETIM registers, based on mode */ 1885 static u_int32_t 1886 piix_setup_sidetim_timings(mode, dma, channel) 1887 u_int8_t mode; 1888 u_int8_t dma; 1889 u_int8_t channel; 1890 { 1891 if (dma) 1892 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1893 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1894 else 1895 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1896 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1897 } 1898 1899 void 1900 amd7x6_chip_map(sc, pa) 1901 struct pciide_softc *sc; 1902 struct pci_attach_args *pa; 1903 { 1904 struct pciide_channel *cp; 1905 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1906 int channel; 1907 pcireg_t chanenable; 1908 bus_size_t cmdsize, ctlsize; 1909 1910 if (pciide_chipen(sc, pa) == 0) 1911 return; 1912 printf("%s: bus-master DMA support present", 1913 sc->sc_wdcdev.sc_dev.dv_xname); 1914 pciide_mapreg_dma(sc, pa); 1915 printf("\n"); 1916 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1917 WDC_CAPABILITY_MODE; 1918 if (sc->sc_dma_ok) { 1919 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1920 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1921 sc->sc_wdcdev.irqack = pciide_irqack; 1922 } 1923 sc->sc_wdcdev.PIO_cap = 4; 1924 sc->sc_wdcdev.DMA_cap = 2; 1925 1926 if (sc->sc_pp->ide_product == PCI_PRODUCT_AMD_PBC766_IDE) 1927 sc->sc_wdcdev.UDMA_cap = 5; 1928 else 1929 sc->sc_wdcdev.UDMA_cap = 4; 1930 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1931 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1932 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1933 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1934 1935 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1936 DEBUG_PROBE); 1937 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1938 cp = &sc->pciide_channels[channel]; 1939 if (pciide_chansetup(sc, channel, interface) == 0) 1940 continue; 1941 1942 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1943 printf("%s: %s channel ignored (disabled)\n", 1944 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1945 continue; 1946 } 1947 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1948 pciide_pci_intr); 1949 1950 if (pciide_chan_candisable(cp)) 1951 chanenable &= ~AMD7X6_CHAN_EN(channel); 1952 pciide_map_compat_intr(pa, cp, channel, interface); 1953 if (cp->hw_ok == 0) 1954 continue; 1955 1956 amd7x6_setup_channel(&cp->wdc_channel); 1957 } 1958 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1959 chanenable); 1960 return; 1961 } 1962 1963 void 1964 amd7x6_setup_channel(chp) 1965 struct channel_softc *chp; 1966 { 1967 u_int32_t udmatim_reg, datatim_reg; 1968 u_int8_t idedma_ctl; 1969 int mode, drive; 1970 struct ata_drive_datas *drvp; 1971 struct pciide_channel *cp = (struct pciide_channel*)chp; 1972 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1973 #ifndef PCIIDE_AMD756_ENABLEDMA 1974 int rev = PCI_REVISION( 1975 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1976 #endif 1977 1978 idedma_ctl = 0; 1979 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1980 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1981 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1982 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1983 1984 /* setup DMA if needed */ 1985 pciide_channel_dma_setup(cp); 1986 1987 for (drive = 0; drive < 2; drive++) { 1988 drvp = &chp->ch_drive[drive]; 1989 /* If no drive, skip */ 1990 if ((drvp->drive_flags & DRIVE) == 0) 1991 continue; 1992 /* add timing values, setup DMA if needed */ 1993 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1994 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1995 mode = drvp->PIO_mode; 1996 goto pio; 1997 } 1998 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1999 (drvp->drive_flags & DRIVE_UDMA)) { 2000 /* use Ultra/DMA */ 2001 drvp->drive_flags &= ~DRIVE_DMA; 2002 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2003 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2004 AMD7X6_UDMA_TIME(chp->channel, drive, 2005 amd7x6_udma_tim[drvp->UDMA_mode]); 2006 /* can use PIO timings, MW DMA unused */ 2007 mode = drvp->PIO_mode; 2008 } else { 2009 /* use Multiword DMA, but only if revision is OK */ 2010 drvp->drive_flags &= ~DRIVE_UDMA; 2011 #ifndef PCIIDE_AMD756_ENABLEDMA 2012 /* 2013 * The workaround doesn't seem to be necessary 2014 * with all drives, so it can be disabled by 2015 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2016 * triggered. 2017 */ 2018 if (sc->sc_pp->ide_product == 2019 PCI_PRODUCT_AMD_PBC756_IDE && 2020 AMD756_CHIPREV_DISABLEDMA(rev)) { 2021 printf("%s:%d:%d: multi-word DMA disabled due " 2022 "to chip revision\n", 2023 sc->sc_wdcdev.sc_dev.dv_xname, 2024 chp->channel, drive); 2025 mode = drvp->PIO_mode; 2026 drvp->drive_flags &= ~DRIVE_DMA; 2027 goto pio; 2028 } 2029 #endif 2030 /* mode = min(pio, dma+2) */ 2031 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2032 mode = drvp->PIO_mode; 2033 else 2034 mode = drvp->DMA_mode + 2; 2035 } 2036 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2037 2038 pio: /* setup PIO mode */ 2039 if (mode <= 2) { 2040 drvp->DMA_mode = 0; 2041 drvp->PIO_mode = 0; 2042 mode = 0; 2043 } else { 2044 drvp->PIO_mode = mode; 2045 drvp->DMA_mode = mode - 2; 2046 } 2047 datatim_reg |= 2048 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2049 amd7x6_pio_set[mode]) | 2050 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2051 amd7x6_pio_rec[mode]); 2052 } 2053 if (idedma_ctl != 0) { 2054 /* Add software bits in status register */ 2055 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2056 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2057 idedma_ctl); 2058 } 2059 pciide_print_modes(cp); 2060 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2061 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2062 } 2063 2064 void 2065 apollo_chip_map(sc, pa) 2066 struct pciide_softc *sc; 2067 struct pci_attach_args *pa; 2068 { 2069 struct pciide_channel *cp; 2070 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2071 int channel; 2072 u_int32_t ideconf; 2073 bus_size_t cmdsize, ctlsize; 2074 pcitag_t pcib_tag; 2075 pcireg_t pcib_id, pcib_class; 2076 2077 if (pciide_chipen(sc, pa) == 0) 2078 return; 2079 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2080 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2081 /* and read ID and rev of the ISA bridge */ 2082 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2083 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2084 printf(": VIA Technologies "); 2085 switch (PCI_PRODUCT(pcib_id)) { 2086 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2087 printf("VT82C586 (Apollo VP) "); 2088 if(PCI_REVISION(pcib_class) >= 0x02) { 2089 printf("ATA33 controller\n"); 2090 sc->sc_wdcdev.UDMA_cap = 2; 2091 } else { 2092 printf("controller\n"); 2093 sc->sc_wdcdev.UDMA_cap = 0; 2094 } 2095 break; 2096 case PCI_PRODUCT_VIATECH_VT82C596A: 2097 printf("VT82C596A (Apollo Pro) "); 2098 if (PCI_REVISION(pcib_class) >= 0x12) { 2099 printf("ATA66 controller\n"); 2100 sc->sc_wdcdev.UDMA_cap = 4; 2101 } else { 2102 printf("ATA33 controller\n"); 2103 sc->sc_wdcdev.UDMA_cap = 2; 2104 } 2105 break; 2106 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2107 printf("VT82C686A (Apollo KX133) "); 2108 if (PCI_REVISION(pcib_class) >= 0x40) { 2109 printf("ATA100 controller\n"); 2110 sc->sc_wdcdev.UDMA_cap = 5; 2111 } else { 2112 printf("ATA66 controller\n"); 2113 sc->sc_wdcdev.UDMA_cap = 4; 2114 } 2115 break; 2116 case PCI_PRODUCT_VIATECH_VT8233: 2117 printf("VT8233 ATA100 controller\n"); 2118 sc->sc_wdcdev.UDMA_cap = 5; 2119 break; 2120 default: 2121 printf("unknown ATA controller\n"); 2122 sc->sc_wdcdev.UDMA_cap = 0; 2123 } 2124 2125 printf("%s: bus-master DMA support present", 2126 sc->sc_wdcdev.sc_dev.dv_xname); 2127 pciide_mapreg_dma(sc, pa); 2128 printf("\n"); 2129 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2130 WDC_CAPABILITY_MODE; 2131 if (sc->sc_dma_ok) { 2132 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2133 sc->sc_wdcdev.irqack = pciide_irqack; 2134 if (sc->sc_wdcdev.UDMA_cap > 0) 2135 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2136 } 2137 sc->sc_wdcdev.PIO_cap = 4; 2138 sc->sc_wdcdev.DMA_cap = 2; 2139 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2140 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2141 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2142 2143 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2144 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2145 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2146 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2147 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2148 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2149 DEBUG_PROBE); 2150 2151 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2152 cp = &sc->pciide_channels[channel]; 2153 if (pciide_chansetup(sc, channel, interface) == 0) 2154 continue; 2155 2156 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2157 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2158 printf("%s: %s channel ignored (disabled)\n", 2159 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2160 continue; 2161 } 2162 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2163 pciide_pci_intr); 2164 if (cp->hw_ok == 0) 2165 continue; 2166 if (pciide_chan_candisable(cp)) { 2167 ideconf &= ~APO_IDECONF_EN(channel); 2168 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2169 ideconf); 2170 } 2171 pciide_map_compat_intr(pa, cp, channel, interface); 2172 2173 if (cp->hw_ok == 0) 2174 continue; 2175 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2176 } 2177 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2178 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2179 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2180 } 2181 2182 void 2183 apollo_setup_channel(chp) 2184 struct channel_softc *chp; 2185 { 2186 u_int32_t udmatim_reg, datatim_reg; 2187 u_int8_t idedma_ctl; 2188 int mode, drive; 2189 struct ata_drive_datas *drvp; 2190 struct pciide_channel *cp = (struct pciide_channel*)chp; 2191 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2192 2193 idedma_ctl = 0; 2194 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2195 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2196 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2197 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2198 2199 /* setup DMA if needed */ 2200 pciide_channel_dma_setup(cp); 2201 2202 for (drive = 0; drive < 2; drive++) { 2203 drvp = &chp->ch_drive[drive]; 2204 /* If no drive, skip */ 2205 if ((drvp->drive_flags & DRIVE) == 0) 2206 continue; 2207 /* add timing values, setup DMA if needed */ 2208 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2209 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2210 mode = drvp->PIO_mode; 2211 goto pio; 2212 } 2213 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2214 (drvp->drive_flags & DRIVE_UDMA)) { 2215 /* use Ultra/DMA */ 2216 drvp->drive_flags &= ~DRIVE_DMA; 2217 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2218 APO_UDMA_EN_MTH(chp->channel, drive); 2219 if (sc->sc_wdcdev.UDMA_cap == 5) { 2220 /* 686b */ 2221 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2222 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2223 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2224 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2225 /* 596b or 686a */ 2226 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2227 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2228 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2229 } else { 2230 /* 596a or 586b */ 2231 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2232 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2233 } 2234 /* can use PIO timings, MW DMA unused */ 2235 mode = drvp->PIO_mode; 2236 } else { 2237 /* use Multiword DMA */ 2238 drvp->drive_flags &= ~DRIVE_UDMA; 2239 /* mode = min(pio, dma+2) */ 2240 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2241 mode = drvp->PIO_mode; 2242 else 2243 mode = drvp->DMA_mode + 2; 2244 } 2245 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2246 2247 pio: /* setup PIO mode */ 2248 if (mode <= 2) { 2249 drvp->DMA_mode = 0; 2250 drvp->PIO_mode = 0; 2251 mode = 0; 2252 } else { 2253 drvp->PIO_mode = mode; 2254 drvp->DMA_mode = mode - 2; 2255 } 2256 datatim_reg |= 2257 APO_DATATIM_PULSE(chp->channel, drive, 2258 apollo_pio_set[mode]) | 2259 APO_DATATIM_RECOV(chp->channel, drive, 2260 apollo_pio_rec[mode]); 2261 } 2262 if (idedma_ctl != 0) { 2263 /* Add software bits in status register */ 2264 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2265 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2266 idedma_ctl); 2267 } 2268 pciide_print_modes(cp); 2269 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2270 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2271 } 2272 2273 void 2274 cmd_channel_map(pa, sc, channel) 2275 struct pci_attach_args *pa; 2276 struct pciide_softc *sc; 2277 int channel; 2278 { 2279 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2280 bus_size_t cmdsize, ctlsize; 2281 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2282 int interface; 2283 2284 /* 2285 * The 0648/0649 can be told to identify as a RAID controller. 2286 * In this case, we have to fake interface 2287 */ 2288 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2289 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2290 PCIIDE_INTERFACE_SETTABLE(1); 2291 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2292 CMD_CONF_DSA1) 2293 interface |= PCIIDE_INTERFACE_PCI(0) | 2294 PCIIDE_INTERFACE_PCI(1); 2295 } else { 2296 interface = PCI_INTERFACE(pa->pa_class); 2297 } 2298 2299 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2300 cp->name = PCIIDE_CHANNEL_NAME(channel); 2301 cp->wdc_channel.channel = channel; 2302 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2303 2304 if (channel > 0) { 2305 cp->wdc_channel.ch_queue = 2306 sc->pciide_channels[0].wdc_channel.ch_queue; 2307 } else { 2308 cp->wdc_channel.ch_queue = 2309 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2310 } 2311 if (cp->wdc_channel.ch_queue == NULL) { 2312 printf("%s %s channel: " 2313 "can't allocate memory for command queue", 2314 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2315 return; 2316 } 2317 2318 printf("%s: %s channel %s to %s mode\n", 2319 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2320 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2321 "configured" : "wired", 2322 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2323 "native-PCI" : "compatibility"); 2324 2325 /* 2326 * with a CMD PCI64x, if we get here, the first channel is enabled: 2327 * there's no way to disable the first channel without disabling 2328 * the whole device 2329 */ 2330 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2331 printf("%s: %s channel ignored (disabled)\n", 2332 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2333 return; 2334 } 2335 2336 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2337 if (cp->hw_ok == 0) 2338 return; 2339 if (channel == 1) { 2340 if (pciide_chan_candisable(cp)) { 2341 ctrl &= ~CMD_CTRL_2PORT; 2342 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2343 CMD_CTRL, ctrl); 2344 } 2345 } 2346 pciide_map_compat_intr(pa, cp, channel, interface); 2347 } 2348 2349 int 2350 cmd_pci_intr(arg) 2351 void *arg; 2352 { 2353 struct pciide_softc *sc = arg; 2354 struct pciide_channel *cp; 2355 struct channel_softc *wdc_cp; 2356 int i, rv, crv; 2357 u_int32_t priirq, secirq; 2358 2359 rv = 0; 2360 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2361 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2362 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2363 cp = &sc->pciide_channels[i]; 2364 wdc_cp = &cp->wdc_channel; 2365 /* If a compat channel skip. */ 2366 if (cp->compat) 2367 continue; 2368 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2369 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2370 crv = wdcintr(wdc_cp); 2371 if (crv == 0) 2372 printf("%s:%d: bogus intr\n", 2373 sc->sc_wdcdev.sc_dev.dv_xname, i); 2374 else 2375 rv = 1; 2376 } 2377 } 2378 return rv; 2379 } 2380 2381 void 2382 cmd_chip_map(sc, pa) 2383 struct pciide_softc *sc; 2384 struct pci_attach_args *pa; 2385 { 2386 int channel; 2387 2388 /* 2389 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2390 * and base adresses registers can be disabled at 2391 * hardware level. In this case, the device is wired 2392 * in compat mode and its first channel is always enabled, 2393 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2394 * In fact, it seems that the first channel of the CMD PCI0640 2395 * can't be disabled. 2396 */ 2397 2398 #ifdef PCIIDE_CMD064x_DISABLE 2399 if (pciide_chipen(sc, pa) == 0) 2400 return; 2401 #endif 2402 2403 printf("%s: hardware does not support DMA\n", 2404 sc->sc_wdcdev.sc_dev.dv_xname); 2405 sc->sc_dma_ok = 0; 2406 2407 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2408 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2409 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2410 2411 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2412 cmd_channel_map(pa, sc, channel); 2413 } 2414 } 2415 2416 void 2417 cmd0643_9_chip_map(sc, pa) 2418 struct pciide_softc *sc; 2419 struct pci_attach_args *pa; 2420 { 2421 struct pciide_channel *cp; 2422 int channel; 2423 int rev = PCI_REVISION( 2424 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2425 2426 /* 2427 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2428 * and base adresses registers can be disabled at 2429 * hardware level. In this case, the device is wired 2430 * in compat mode and its first channel is always enabled, 2431 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2432 * In fact, it seems that the first channel of the CMD PCI0640 2433 * can't be disabled. 2434 */ 2435 2436 #ifdef PCIIDE_CMD064x_DISABLE 2437 if (pciide_chipen(sc, pa) == 0) 2438 return; 2439 #endif 2440 printf("%s: bus-master DMA support present", 2441 sc->sc_wdcdev.sc_dev.dv_xname); 2442 pciide_mapreg_dma(sc, pa); 2443 printf("\n"); 2444 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2445 WDC_CAPABILITY_MODE; 2446 if (sc->sc_dma_ok) { 2447 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2448 switch (sc->sc_pp->ide_product) { 2449 case PCI_PRODUCT_CMDTECH_649: 2450 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2451 sc->sc_wdcdev.UDMA_cap = 5; 2452 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2453 break; 2454 case PCI_PRODUCT_CMDTECH_648: 2455 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2456 sc->sc_wdcdev.UDMA_cap = 4; 2457 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2458 break; 2459 case PCI_PRODUCT_CMDTECH_646: 2460 if (rev >= CMD0646U2_REV) { 2461 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2462 sc->sc_wdcdev.UDMA_cap = 2; 2463 } else if (rev >= CMD0646U_REV) { 2464 /* 2465 * Linux's driver claims that the 646U is broken 2466 * with UDMA. Only enable it if we know what we're 2467 * doing 2468 */ 2469 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2470 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2471 sc->sc_wdcdev.UDMA_cap = 2; 2472 #endif 2473 /* explicitly disable UDMA */ 2474 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2475 CMD_UDMATIM(0), 0); 2476 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2477 CMD_UDMATIM(1), 0); 2478 } 2479 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2480 break; 2481 default: 2482 sc->sc_wdcdev.irqack = pciide_irqack; 2483 } 2484 } 2485 2486 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2487 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2488 sc->sc_wdcdev.PIO_cap = 4; 2489 sc->sc_wdcdev.DMA_cap = 2; 2490 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2491 2492 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2493 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2494 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2495 DEBUG_PROBE); 2496 2497 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2498 cp = &sc->pciide_channels[channel]; 2499 cmd_channel_map(pa, sc, channel); 2500 if (cp->hw_ok == 0) 2501 continue; 2502 cmd0643_9_setup_channel(&cp->wdc_channel); 2503 } 2504 /* 2505 * note - this also makes sure we clear the irq disable and reset 2506 * bits 2507 */ 2508 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2509 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2510 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2511 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2512 DEBUG_PROBE); 2513 } 2514 2515 void 2516 cmd0643_9_setup_channel(chp) 2517 struct channel_softc *chp; 2518 { 2519 struct ata_drive_datas *drvp; 2520 u_int8_t tim; 2521 u_int32_t idedma_ctl, udma_reg; 2522 int drive; 2523 struct pciide_channel *cp = (struct pciide_channel*)chp; 2524 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2525 2526 idedma_ctl = 0; 2527 /* setup DMA if needed */ 2528 pciide_channel_dma_setup(cp); 2529 2530 for (drive = 0; drive < 2; drive++) { 2531 drvp = &chp->ch_drive[drive]; 2532 /* If no drive, skip */ 2533 if ((drvp->drive_flags & DRIVE) == 0) 2534 continue; 2535 /* add timing values, setup DMA if needed */ 2536 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2537 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2538 if (drvp->drive_flags & DRIVE_UDMA) { 2539 /* UltraDMA on a 646U2, 0648 or 0649 */ 2540 drvp->drive_flags &= ~DRIVE_DMA; 2541 udma_reg = pciide_pci_read(sc->sc_pc, 2542 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2543 if (drvp->UDMA_mode > 2 && 2544 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2545 CMD_BICSR) & 2546 CMD_BICSR_80(chp->channel)) == 0) 2547 drvp->UDMA_mode = 2; 2548 if (drvp->UDMA_mode > 2) 2549 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2550 else if (sc->sc_wdcdev.UDMA_cap > 2) 2551 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2552 udma_reg |= CMD_UDMATIM_UDMA(drive); 2553 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2554 CMD_UDMATIM_TIM_OFF(drive)); 2555 udma_reg |= 2556 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2557 CMD_UDMATIM_TIM_OFF(drive)); 2558 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2559 CMD_UDMATIM(chp->channel), udma_reg); 2560 } else { 2561 /* 2562 * use Multiword DMA. 2563 * Timings will be used for both PIO and DMA, 2564 * so adjust DMA mode if needed 2565 * if we have a 0646U2/8/9, turn off UDMA 2566 */ 2567 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2568 udma_reg = pciide_pci_read(sc->sc_pc, 2569 sc->sc_tag, 2570 CMD_UDMATIM(chp->channel)); 2571 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2572 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2573 CMD_UDMATIM(chp->channel), 2574 udma_reg); 2575 } 2576 if (drvp->PIO_mode >= 3 && 2577 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2578 drvp->DMA_mode = drvp->PIO_mode - 2; 2579 } 2580 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2581 } 2582 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2583 } 2584 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2585 CMD_DATA_TIM(chp->channel, drive), tim); 2586 } 2587 if (idedma_ctl != 0) { 2588 /* Add software bits in status register */ 2589 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2590 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2591 idedma_ctl); 2592 } 2593 pciide_print_modes(cp); 2594 } 2595 2596 void 2597 cmd646_9_irqack(chp) 2598 struct channel_softc *chp; 2599 { 2600 u_int32_t priirq, secirq; 2601 struct pciide_channel *cp = (struct pciide_channel*)chp; 2602 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2603 2604 if (chp->channel == 0) { 2605 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2606 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2607 } else { 2608 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2609 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2610 } 2611 pciide_irqack(chp); 2612 } 2613 2614 void 2615 cy693_chip_map(sc, pa) 2616 struct pciide_softc *sc; 2617 struct pci_attach_args *pa; 2618 { 2619 struct pciide_channel *cp; 2620 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2621 bus_size_t cmdsize, ctlsize; 2622 2623 if (pciide_chipen(sc, pa) == 0) 2624 return; 2625 /* 2626 * this chip has 2 PCI IDE functions, one for primary and one for 2627 * secondary. So we need to call pciide_mapregs_compat() with 2628 * the real channel 2629 */ 2630 if (pa->pa_function == 1) { 2631 sc->sc_cy_compatchan = 0; 2632 } else if (pa->pa_function == 2) { 2633 sc->sc_cy_compatchan = 1; 2634 } else { 2635 printf("%s: unexpected PCI function %d\n", 2636 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2637 return; 2638 } 2639 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2640 printf("%s: bus-master DMA support present", 2641 sc->sc_wdcdev.sc_dev.dv_xname); 2642 pciide_mapreg_dma(sc, pa); 2643 } else { 2644 printf("%s: hardware does not support DMA", 2645 sc->sc_wdcdev.sc_dev.dv_xname); 2646 sc->sc_dma_ok = 0; 2647 } 2648 printf("\n"); 2649 2650 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2651 if (sc->sc_cy_handle == NULL) { 2652 printf("%s: unable to map hyperCache control registers\n", 2653 sc->sc_wdcdev.sc_dev.dv_xname); 2654 sc->sc_dma_ok = 0; 2655 } 2656 2657 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2658 WDC_CAPABILITY_MODE; 2659 if (sc->sc_dma_ok) { 2660 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2661 sc->sc_wdcdev.irqack = pciide_irqack; 2662 } 2663 sc->sc_wdcdev.PIO_cap = 4; 2664 sc->sc_wdcdev.DMA_cap = 2; 2665 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2666 2667 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2668 sc->sc_wdcdev.nchannels = 1; 2669 2670 /* Only one channel for this chip; if we are here it's enabled */ 2671 cp = &sc->pciide_channels[0]; 2672 sc->wdc_chanarray[0] = &cp->wdc_channel; 2673 cp->name = PCIIDE_CHANNEL_NAME(0); 2674 cp->wdc_channel.channel = 0; 2675 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2676 cp->wdc_channel.ch_queue = 2677 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2678 if (cp->wdc_channel.ch_queue == NULL) { 2679 printf("%s primary channel: " 2680 "can't allocate memory for command queue", 2681 sc->sc_wdcdev.sc_dev.dv_xname); 2682 return; 2683 } 2684 printf("%s: primary channel %s to ", 2685 sc->sc_wdcdev.sc_dev.dv_xname, 2686 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2687 "configured" : "wired"); 2688 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2689 printf("native-PCI"); 2690 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2691 pciide_pci_intr); 2692 } else { 2693 printf("compatibility"); 2694 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2695 &cmdsize, &ctlsize); 2696 } 2697 printf(" mode\n"); 2698 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2699 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2700 wdcattach(&cp->wdc_channel); 2701 if (pciide_chan_candisable(cp)) { 2702 pci_conf_write(sc->sc_pc, sc->sc_tag, 2703 PCI_COMMAND_STATUS_REG, 0); 2704 } 2705 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2706 if (cp->hw_ok == 0) 2707 return; 2708 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2709 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2710 cy693_setup_channel(&cp->wdc_channel); 2711 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2712 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2713 } 2714 2715 void 2716 cy693_setup_channel(chp) 2717 struct channel_softc *chp; 2718 { 2719 struct ata_drive_datas *drvp; 2720 int drive; 2721 u_int32_t cy_cmd_ctrl; 2722 u_int32_t idedma_ctl; 2723 struct pciide_channel *cp = (struct pciide_channel*)chp; 2724 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2725 int dma_mode = -1; 2726 2727 cy_cmd_ctrl = idedma_ctl = 0; 2728 2729 /* setup DMA if needed */ 2730 pciide_channel_dma_setup(cp); 2731 2732 for (drive = 0; drive < 2; drive++) { 2733 drvp = &chp->ch_drive[drive]; 2734 /* If no drive, skip */ 2735 if ((drvp->drive_flags & DRIVE) == 0) 2736 continue; 2737 /* add timing values, setup DMA if needed */ 2738 if (drvp->drive_flags & DRIVE_DMA) { 2739 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2740 /* use Multiword DMA */ 2741 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2742 dma_mode = drvp->DMA_mode; 2743 } 2744 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2745 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2746 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2747 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2748 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2749 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2750 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2751 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2752 } 2753 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2754 chp->ch_drive[0].DMA_mode = dma_mode; 2755 chp->ch_drive[1].DMA_mode = dma_mode; 2756 2757 if (dma_mode == -1) 2758 dma_mode = 0; 2759 2760 if (sc->sc_cy_handle != NULL) { 2761 /* Note: `multiple' is implied. */ 2762 cy82c693_write(sc->sc_cy_handle, 2763 (sc->sc_cy_compatchan == 0) ? 2764 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2765 } 2766 2767 pciide_print_modes(cp); 2768 2769 if (idedma_ctl != 0) { 2770 /* Add software bits in status register */ 2771 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2772 IDEDMA_CTL, idedma_ctl); 2773 } 2774 } 2775 2776 static int 2777 sis_hostbr_match(pa) 2778 struct pci_attach_args *pa; 2779 { 2780 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2781 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2782 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2783 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2784 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2785 } 2786 2787 void 2788 sis_chip_map(sc, pa) 2789 struct pciide_softc *sc; 2790 struct pci_attach_args *pa; 2791 { 2792 struct pciide_channel *cp; 2793 int channel; 2794 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2795 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2796 pcireg_t rev = PCI_REVISION(pa->pa_class); 2797 bus_size_t cmdsize, ctlsize; 2798 pcitag_t pchb_tag; 2799 pcireg_t pchb_id, pchb_class; 2800 2801 if (pciide_chipen(sc, pa) == 0) 2802 return; 2803 printf("%s: bus-master DMA support present", 2804 sc->sc_wdcdev.sc_dev.dv_xname); 2805 pciide_mapreg_dma(sc, pa); 2806 printf("\n"); 2807 2808 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2809 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2810 /* and read ID and rev of the ISA bridge */ 2811 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2812 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2813 2814 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2815 WDC_CAPABILITY_MODE; 2816 if (sc->sc_dma_ok) { 2817 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2818 sc->sc_wdcdev.irqack = pciide_irqack; 2819 /* 2820 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2821 * have problems with UDMA (info provided by Christos) 2822 */ 2823 if (rev >= 0xd0 && 2824 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2825 PCI_REVISION(pchb_class) >= 0x03)) 2826 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2827 } 2828 2829 sc->sc_wdcdev.PIO_cap = 4; 2830 sc->sc_wdcdev.DMA_cap = 2; 2831 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2832 /* 2833 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2834 * chipsets. 2835 */ 2836 sc->sc_wdcdev.UDMA_cap = 2837 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2838 sc->sc_wdcdev.set_modes = sis_setup_channel; 2839 2840 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2841 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2842 2843 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2844 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2845 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2846 2847 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2848 cp = &sc->pciide_channels[channel]; 2849 if (pciide_chansetup(sc, channel, interface) == 0) 2850 continue; 2851 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2852 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2853 printf("%s: %s channel ignored (disabled)\n", 2854 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2855 continue; 2856 } 2857 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2858 pciide_pci_intr); 2859 if (cp->hw_ok == 0) 2860 continue; 2861 if (pciide_chan_candisable(cp)) { 2862 if (channel == 0) 2863 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2864 else 2865 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2866 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2867 sis_ctr0); 2868 } 2869 pciide_map_compat_intr(pa, cp, channel, interface); 2870 if (cp->hw_ok == 0) 2871 continue; 2872 sis_setup_channel(&cp->wdc_channel); 2873 } 2874 } 2875 2876 void 2877 sis_setup_channel(chp) 2878 struct channel_softc *chp; 2879 { 2880 struct ata_drive_datas *drvp; 2881 int drive; 2882 u_int32_t sis_tim; 2883 u_int32_t idedma_ctl; 2884 struct pciide_channel *cp = (struct pciide_channel*)chp; 2885 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2886 2887 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2888 "channel %d 0x%x\n", chp->channel, 2889 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2890 DEBUG_PROBE); 2891 sis_tim = 0; 2892 idedma_ctl = 0; 2893 /* setup DMA if needed */ 2894 pciide_channel_dma_setup(cp); 2895 2896 for (drive = 0; drive < 2; drive++) { 2897 drvp = &chp->ch_drive[drive]; 2898 /* If no drive, skip */ 2899 if ((drvp->drive_flags & DRIVE) == 0) 2900 continue; 2901 /* add timing values, setup DMA if needed */ 2902 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2903 (drvp->drive_flags & DRIVE_UDMA) == 0) 2904 goto pio; 2905 2906 if (drvp->drive_flags & DRIVE_UDMA) { 2907 /* use Ultra/DMA */ 2908 drvp->drive_flags &= ~DRIVE_DMA; 2909 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2910 SIS_TIM_UDMA_TIME_OFF(drive); 2911 sis_tim |= SIS_TIM_UDMA_EN(drive); 2912 } else { 2913 /* 2914 * use Multiword DMA 2915 * Timings will be used for both PIO and DMA, 2916 * so adjust DMA mode if needed 2917 */ 2918 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2919 drvp->PIO_mode = drvp->DMA_mode + 2; 2920 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2921 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2922 drvp->PIO_mode - 2 : 0; 2923 if (drvp->DMA_mode == 0) 2924 drvp->PIO_mode = 0; 2925 } 2926 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2927 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2928 SIS_TIM_ACT_OFF(drive); 2929 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2930 SIS_TIM_REC_OFF(drive); 2931 } 2932 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2933 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2934 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2935 if (idedma_ctl != 0) { 2936 /* Add software bits in status register */ 2937 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2938 IDEDMA_CTL, idedma_ctl); 2939 } 2940 pciide_print_modes(cp); 2941 } 2942 2943 static int 2944 acer_isabr_match(pa) 2945 struct pci_attach_args *pa; 2946 { 2947 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 2948 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 2949 } 2950 2951 void 2952 acer_chip_map(sc, pa) 2953 struct pciide_softc *sc; 2954 struct pci_attach_args *pa; 2955 { 2956 struct pci_attach_args isa_pa; 2957 struct pciide_channel *cp; 2958 int channel; 2959 pcireg_t cr, interface; 2960 bus_size_t cmdsize, ctlsize; 2961 pcireg_t rev = PCI_REVISION(pa->pa_class); 2962 2963 if (pciide_chipen(sc, pa) == 0) 2964 return; 2965 printf("%s: bus-master DMA support present", 2966 sc->sc_wdcdev.sc_dev.dv_xname); 2967 pciide_mapreg_dma(sc, pa); 2968 printf("\n"); 2969 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2970 WDC_CAPABILITY_MODE; 2971 if (sc->sc_dma_ok) { 2972 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2973 if (rev >= 0x20) { 2974 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2975 if (rev >= 0xC4) 2976 sc->sc_wdcdev.UDMA_cap = 5; 2977 else if (rev >= 0xC2) 2978 sc->sc_wdcdev.UDMA_cap = 4; 2979 else 2980 sc->sc_wdcdev.UDMA_cap = 2; 2981 } 2982 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2983 sc->sc_wdcdev.irqack = pciide_irqack; 2984 } 2985 2986 sc->sc_wdcdev.PIO_cap = 4; 2987 sc->sc_wdcdev.DMA_cap = 2; 2988 sc->sc_wdcdev.set_modes = acer_setup_channel; 2989 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2990 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2991 2992 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2993 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2994 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2995 2996 /* Enable "microsoft register bits" R/W. */ 2997 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2998 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2999 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3000 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3001 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3002 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3003 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3004 ~ACER_CHANSTATUSREGS_RO); 3005 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3006 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3007 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3008 /* Don't use cr, re-read the real register content instead */ 3009 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3010 PCI_CLASS_REG)); 3011 3012 /* From linux: enable "Cable Detection" */ 3013 if (rev >= 0xC2) { 3014 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3015 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3016 | ACER_0x4B_CDETECT); 3017 /* set south-bridge's enable bit, m1533, 0x79 */ 3018 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 3019 printf("%s: can't find PCI/ISA bridge, downgrading " 3020 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 3021 sc->sc_wdcdev.UDMA_cap = 2; 3022 } else { 3023 if (rev == 0xC2) 3024 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3025 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3026 ACER_0x79, 3027 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3028 ACER_0x79) 3029 | ACER_0x79_REVC2_EN); 3030 else 3031 /* 1553/1535 (m1533, 0x79, bit 1) */ 3032 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3033 ACER_0x79, 3034 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3035 ACER_0x79) 3036 | ACER_0x79_EN); 3037 } 3038 } 3039 3040 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3041 cp = &sc->pciide_channels[channel]; 3042 if (pciide_chansetup(sc, channel, interface) == 0) 3043 continue; 3044 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3045 printf("%s: %s channel ignored (disabled)\n", 3046 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3047 continue; 3048 } 3049 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3050 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3051 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3052 if (cp->hw_ok == 0) 3053 continue; 3054 if (pciide_chan_candisable(cp)) { 3055 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3056 pci_conf_write(sc->sc_pc, sc->sc_tag, 3057 PCI_CLASS_REG, cr); 3058 } 3059 pciide_map_compat_intr(pa, cp, channel, interface); 3060 acer_setup_channel(&cp->wdc_channel); 3061 } 3062 } 3063 3064 void 3065 acer_setup_channel(chp) 3066 struct channel_softc *chp; 3067 { 3068 struct ata_drive_datas *drvp; 3069 int drive; 3070 u_int32_t acer_fifo_udma; 3071 u_int32_t idedma_ctl; 3072 struct pciide_channel *cp = (struct pciide_channel*)chp; 3073 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3074 3075 idedma_ctl = 0; 3076 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3077 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3078 acer_fifo_udma), DEBUG_PROBE); 3079 /* setup DMA if needed */ 3080 pciide_channel_dma_setup(cp); 3081 3082 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3083 DRIVE_UDMA) { /* check 80 pins cable */ 3084 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3085 ACER_0x4A_80PIN(chp->channel)) { 3086 if (chp->ch_drive[0].UDMA_mode > 2) 3087 chp->ch_drive[0].UDMA_mode = 2; 3088 if (chp->ch_drive[1].UDMA_mode > 2) 3089 chp->ch_drive[1].UDMA_mode = 2; 3090 } 3091 } 3092 3093 for (drive = 0; drive < 2; drive++) { 3094 drvp = &chp->ch_drive[drive]; 3095 /* If no drive, skip */ 3096 if ((drvp->drive_flags & DRIVE) == 0) 3097 continue; 3098 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3099 "channel %d drive %d 0x%x\n", chp->channel, drive, 3100 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3101 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3102 /* clear FIFO/DMA mode */ 3103 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3104 ACER_UDMA_EN(chp->channel, drive) | 3105 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3106 3107 /* add timing values, setup DMA if needed */ 3108 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3109 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3110 acer_fifo_udma |= 3111 ACER_FTH_OPL(chp->channel, drive, 0x1); 3112 goto pio; 3113 } 3114 3115 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3116 if (drvp->drive_flags & DRIVE_UDMA) { 3117 /* use Ultra/DMA */ 3118 drvp->drive_flags &= ~DRIVE_DMA; 3119 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3120 acer_fifo_udma |= 3121 ACER_UDMA_TIM(chp->channel, drive, 3122 acer_udma[drvp->UDMA_mode]); 3123 /* XXX disable if one drive < UDMA3 ? */ 3124 if (drvp->UDMA_mode >= 3) { 3125 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3126 ACER_0x4B, 3127 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3128 ACER_0x4B) | ACER_0x4B_UDMA66); 3129 } 3130 } else { 3131 /* 3132 * use Multiword DMA 3133 * Timings will be used for both PIO and DMA, 3134 * so adjust DMA mode if needed 3135 */ 3136 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3137 drvp->PIO_mode = drvp->DMA_mode + 2; 3138 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3139 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3140 drvp->PIO_mode - 2 : 0; 3141 if (drvp->DMA_mode == 0) 3142 drvp->PIO_mode = 0; 3143 } 3144 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3145 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3146 ACER_IDETIM(chp->channel, drive), 3147 acer_pio[drvp->PIO_mode]); 3148 } 3149 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3150 acer_fifo_udma), DEBUG_PROBE); 3151 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3152 if (idedma_ctl != 0) { 3153 /* Add software bits in status register */ 3154 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3155 IDEDMA_CTL, idedma_ctl); 3156 } 3157 pciide_print_modes(cp); 3158 } 3159 3160 int 3161 acer_pci_intr(arg) 3162 void *arg; 3163 { 3164 struct pciide_softc *sc = arg; 3165 struct pciide_channel *cp; 3166 struct channel_softc *wdc_cp; 3167 int i, rv, crv; 3168 u_int32_t chids; 3169 3170 rv = 0; 3171 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3172 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3173 cp = &sc->pciide_channels[i]; 3174 wdc_cp = &cp->wdc_channel; 3175 /* If a compat channel skip. */ 3176 if (cp->compat) 3177 continue; 3178 if (chids & ACER_CHIDS_INT(i)) { 3179 crv = wdcintr(wdc_cp); 3180 if (crv == 0) 3181 printf("%s:%d: bogus intr\n", 3182 sc->sc_wdcdev.sc_dev.dv_xname, i); 3183 else 3184 rv = 1; 3185 } 3186 } 3187 return rv; 3188 } 3189 3190 void 3191 hpt_chip_map(sc, pa) 3192 struct pciide_softc *sc; 3193 struct pci_attach_args *pa; 3194 { 3195 struct pciide_channel *cp; 3196 int i, compatchan, revision; 3197 pcireg_t interface; 3198 bus_size_t cmdsize, ctlsize; 3199 3200 if (pciide_chipen(sc, pa) == 0) 3201 return; 3202 revision = PCI_REVISION(pa->pa_class); 3203 printf(": Triones/Highpoint "); 3204 if (revision == HPT370_REV) 3205 printf("HPT370 IDE Controller\n"); 3206 else if (revision == HPT370A_REV) 3207 printf("HPT370A IDE Controller\n"); 3208 else if (revision == HPT366_REV) 3209 printf("HPT366 IDE Controller\n"); 3210 else 3211 printf("unknown HPT IDE controller rev %d\n", revision); 3212 3213 /* 3214 * when the chip is in native mode it identifies itself as a 3215 * 'misc mass storage'. Fake interface in this case. 3216 */ 3217 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3218 interface = PCI_INTERFACE(pa->pa_class); 3219 } else { 3220 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3221 PCIIDE_INTERFACE_PCI(0); 3222 if (revision == HPT370_REV || revision == HPT370A_REV) 3223 interface |= PCIIDE_INTERFACE_PCI(1); 3224 } 3225 3226 printf("%s: bus-master DMA support present", 3227 sc->sc_wdcdev.sc_dev.dv_xname); 3228 pciide_mapreg_dma(sc, pa); 3229 printf("\n"); 3230 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3231 WDC_CAPABILITY_MODE; 3232 if (sc->sc_dma_ok) { 3233 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3234 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3235 sc->sc_wdcdev.irqack = pciide_irqack; 3236 } 3237 sc->sc_wdcdev.PIO_cap = 4; 3238 sc->sc_wdcdev.DMA_cap = 2; 3239 3240 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3241 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3242 if (revision == HPT366_REV) { 3243 sc->sc_wdcdev.UDMA_cap = 4; 3244 /* 3245 * The 366 has 2 PCI IDE functions, one for primary and one 3246 * for secondary. So we need to call pciide_mapregs_compat() 3247 * with the real channel 3248 */ 3249 if (pa->pa_function == 0) { 3250 compatchan = 0; 3251 } else if (pa->pa_function == 1) { 3252 compatchan = 1; 3253 } else { 3254 printf("%s: unexpected PCI function %d\n", 3255 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3256 return; 3257 } 3258 sc->sc_wdcdev.nchannels = 1; 3259 } else { 3260 sc->sc_wdcdev.nchannels = 2; 3261 sc->sc_wdcdev.UDMA_cap = 5; 3262 } 3263 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3264 cp = &sc->pciide_channels[i]; 3265 if (sc->sc_wdcdev.nchannels > 1) { 3266 compatchan = i; 3267 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3268 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3269 printf("%s: %s channel ignored (disabled)\n", 3270 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3271 continue; 3272 } 3273 } 3274 if (pciide_chansetup(sc, i, interface) == 0) 3275 continue; 3276 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3277 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3278 &ctlsize, hpt_pci_intr); 3279 } else { 3280 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3281 &cmdsize, &ctlsize); 3282 } 3283 if (cp->hw_ok == 0) 3284 return; 3285 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3286 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3287 wdcattach(&cp->wdc_channel); 3288 hpt_setup_channel(&cp->wdc_channel); 3289 } 3290 if (revision == HPT370_REV || revision == HPT370A_REV) { 3291 /* 3292 * HPT370_REV has a bit to disable interrupts, make sure 3293 * to clear it 3294 */ 3295 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3296 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3297 ~HPT_CSEL_IRQDIS); 3298 } 3299 return; 3300 } 3301 3302 void 3303 hpt_setup_channel(chp) 3304 struct channel_softc *chp; 3305 { 3306 struct ata_drive_datas *drvp; 3307 int drive; 3308 int cable; 3309 u_int32_t before, after; 3310 u_int32_t idedma_ctl; 3311 struct pciide_channel *cp = (struct pciide_channel*)chp; 3312 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3313 3314 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3315 3316 /* setup DMA if needed */ 3317 pciide_channel_dma_setup(cp); 3318 3319 idedma_ctl = 0; 3320 3321 /* Per drive settings */ 3322 for (drive = 0; drive < 2; drive++) { 3323 drvp = &chp->ch_drive[drive]; 3324 /* If no drive, skip */ 3325 if ((drvp->drive_flags & DRIVE) == 0) 3326 continue; 3327 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3328 HPT_IDETIM(chp->channel, drive)); 3329 3330 /* add timing values, setup DMA if needed */ 3331 if (drvp->drive_flags & DRIVE_UDMA) { 3332 /* use Ultra/DMA */ 3333 drvp->drive_flags &= ~DRIVE_DMA; 3334 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3335 drvp->UDMA_mode > 2) 3336 drvp->UDMA_mode = 2; 3337 after = (sc->sc_wdcdev.nchannels == 2) ? 3338 hpt370_udma[drvp->UDMA_mode] : 3339 hpt366_udma[drvp->UDMA_mode]; 3340 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3341 } else if (drvp->drive_flags & DRIVE_DMA) { 3342 /* 3343 * use Multiword DMA. 3344 * Timings will be used for both PIO and DMA, so adjust 3345 * DMA mode if needed 3346 */ 3347 if (drvp->PIO_mode >= 3 && 3348 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3349 drvp->DMA_mode = drvp->PIO_mode - 2; 3350 } 3351 after = (sc->sc_wdcdev.nchannels == 2) ? 3352 hpt370_dma[drvp->DMA_mode] : 3353 hpt366_dma[drvp->DMA_mode]; 3354 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3355 } else { 3356 /* PIO only */ 3357 after = (sc->sc_wdcdev.nchannels == 2) ? 3358 hpt370_pio[drvp->PIO_mode] : 3359 hpt366_pio[drvp->PIO_mode]; 3360 } 3361 pci_conf_write(sc->sc_pc, sc->sc_tag, 3362 HPT_IDETIM(chp->channel, drive), after); 3363 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3364 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3365 after, before), DEBUG_PROBE); 3366 } 3367 if (idedma_ctl != 0) { 3368 /* Add software bits in status register */ 3369 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3370 IDEDMA_CTL, idedma_ctl); 3371 } 3372 pciide_print_modes(cp); 3373 } 3374 3375 int 3376 hpt_pci_intr(arg) 3377 void *arg; 3378 { 3379 struct pciide_softc *sc = arg; 3380 struct pciide_channel *cp; 3381 struct channel_softc *wdc_cp; 3382 int rv = 0; 3383 int dmastat, i, crv; 3384 3385 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3386 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3387 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3388 if((dmastat & IDEDMA_CTL_INTR) == 0) 3389 continue; 3390 cp = &sc->pciide_channels[i]; 3391 wdc_cp = &cp->wdc_channel; 3392 crv = wdcintr(wdc_cp); 3393 if (crv == 0) { 3394 printf("%s:%d: bogus intr\n", 3395 sc->sc_wdcdev.sc_dev.dv_xname, i); 3396 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3397 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3398 } else 3399 rv = 1; 3400 } 3401 return rv; 3402 } 3403 3404 3405 /* Macros to test product */ 3406 #define PDC_IS_262(sc) \ 3407 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3408 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3409 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3410 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3411 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3412 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3413 #define PDC_IS_265(sc) \ 3414 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3415 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3416 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3417 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3418 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3419 #define PDC_IS_268(sc) \ 3420 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3421 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3422 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3423 3424 void 3425 pdc202xx_chip_map(sc, pa) 3426 struct pciide_softc *sc; 3427 struct pci_attach_args *pa; 3428 { 3429 struct pciide_channel *cp; 3430 int channel; 3431 pcireg_t interface, st, mode; 3432 bus_size_t cmdsize, ctlsize; 3433 3434 if (!PDC_IS_268(sc)) { 3435 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3436 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3437 st), DEBUG_PROBE); 3438 } 3439 if (pciide_chipen(sc, pa) == 0) 3440 return; 3441 3442 /* turn off RAID mode */ 3443 if (!PDC_IS_268(sc)) 3444 st &= ~PDC2xx_STATE_IDERAID; 3445 3446 /* 3447 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3448 * mode. We have to fake interface 3449 */ 3450 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3451 if (st & PDC2xx_STATE_NATIVE) 3452 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3453 3454 printf("%s: bus-master DMA support present", 3455 sc->sc_wdcdev.sc_dev.dv_xname); 3456 pciide_mapreg_dma(sc, pa); 3457 printf("\n"); 3458 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3459 WDC_CAPABILITY_MODE; 3460 if (sc->sc_dma_ok) { 3461 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3462 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3463 sc->sc_wdcdev.irqack = pciide_irqack; 3464 } 3465 sc->sc_wdcdev.PIO_cap = 4; 3466 sc->sc_wdcdev.DMA_cap = 2; 3467 if (PDC_IS_265(sc)) 3468 sc->sc_wdcdev.UDMA_cap = 5; 3469 else if (PDC_IS_262(sc)) 3470 sc->sc_wdcdev.UDMA_cap = 4; 3471 else 3472 sc->sc_wdcdev.UDMA_cap = 2; 3473 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3474 pdc20268_setup_channel : pdc202xx_setup_channel; 3475 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3476 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3477 3478 if (!PDC_IS_268(sc)) { 3479 /* setup failsafe defaults */ 3480 mode = 0; 3481 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3482 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3483 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3484 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3485 for (channel = 0; 3486 channel < sc->sc_wdcdev.nchannels; 3487 channel++) { 3488 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3489 "drive 0 initial timings 0x%x, now 0x%x\n", 3490 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3491 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3492 DEBUG_PROBE); 3493 pci_conf_write(sc->sc_pc, sc->sc_tag, 3494 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3495 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3496 "drive 1 initial timings 0x%x, now 0x%x\n", 3497 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3498 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3499 pci_conf_write(sc->sc_pc, sc->sc_tag, 3500 PDC2xx_TIM(channel, 1), mode); 3501 } 3502 3503 mode = PDC2xx_SCR_DMA; 3504 if (PDC_IS_262(sc)) { 3505 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3506 } else { 3507 /* the BIOS set it up this way */ 3508 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3509 } 3510 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3511 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3512 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3513 "now 0x%x\n", 3514 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3515 PDC2xx_SCR), 3516 mode), DEBUG_PROBE); 3517 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3518 PDC2xx_SCR, mode); 3519 3520 /* controller initial state register is OK even without BIOS */ 3521 /* Set DMA mode to IDE DMA compatibility */ 3522 mode = 3523 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3524 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3525 DEBUG_PROBE); 3526 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3527 mode | 0x1); 3528 mode = 3529 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3530 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3531 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3532 mode | 0x1); 3533 } 3534 3535 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3536 cp = &sc->pciide_channels[channel]; 3537 if (pciide_chansetup(sc, channel, interface) == 0) 3538 continue; 3539 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3540 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3541 printf("%s: %s channel ignored (disabled)\n", 3542 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3543 continue; 3544 } 3545 if (PDC_IS_265(sc)) 3546 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3547 pdc20265_pci_intr); 3548 else 3549 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3550 pdc202xx_pci_intr); 3551 if (cp->hw_ok == 0) 3552 continue; 3553 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3554 st &= ~(PDC_IS_262(sc) ? 3555 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3556 pciide_map_compat_intr(pa, cp, channel, interface); 3557 pdc202xx_setup_channel(&cp->wdc_channel); 3558 } 3559 if (!PDC_IS_268(sc)) { 3560 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3561 "0x%x\n", st), DEBUG_PROBE); 3562 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3563 } 3564 return; 3565 } 3566 3567 void 3568 pdc202xx_setup_channel(chp) 3569 struct channel_softc *chp; 3570 { 3571 struct ata_drive_datas *drvp; 3572 int drive; 3573 pcireg_t mode, st; 3574 u_int32_t idedma_ctl, scr, atapi; 3575 struct pciide_channel *cp = (struct pciide_channel*)chp; 3576 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3577 int channel = chp->channel; 3578 3579 /* setup DMA if needed */ 3580 pciide_channel_dma_setup(cp); 3581 3582 idedma_ctl = 0; 3583 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3584 sc->sc_wdcdev.sc_dev.dv_xname, 3585 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3586 DEBUG_PROBE); 3587 3588 /* Per channel settings */ 3589 if (PDC_IS_262(sc)) { 3590 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3591 PDC262_U66); 3592 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3593 /* Trimm UDMA mode */ 3594 if ((st & PDC262_STATE_80P(channel)) != 0 || 3595 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3596 chp->ch_drive[0].UDMA_mode <= 2) || 3597 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3598 chp->ch_drive[1].UDMA_mode <= 2)) { 3599 if (chp->ch_drive[0].UDMA_mode > 2) 3600 chp->ch_drive[0].UDMA_mode = 2; 3601 if (chp->ch_drive[1].UDMA_mode > 2) 3602 chp->ch_drive[1].UDMA_mode = 2; 3603 } 3604 /* Set U66 if needed */ 3605 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3606 chp->ch_drive[0].UDMA_mode > 2) || 3607 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3608 chp->ch_drive[1].UDMA_mode > 2)) 3609 scr |= PDC262_U66_EN(channel); 3610 else 3611 scr &= ~PDC262_U66_EN(channel); 3612 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3613 PDC262_U66, scr); 3614 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3615 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3616 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3617 PDC262_ATAPI(channel))), DEBUG_PROBE); 3618 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3619 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3620 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3621 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3622 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3623 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3624 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3625 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3626 atapi = 0; 3627 else 3628 atapi = PDC262_ATAPI_UDMA; 3629 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3630 PDC262_ATAPI(channel), atapi); 3631 } 3632 } 3633 for (drive = 0; drive < 2; drive++) { 3634 drvp = &chp->ch_drive[drive]; 3635 /* If no drive, skip */ 3636 if ((drvp->drive_flags & DRIVE) == 0) 3637 continue; 3638 mode = 0; 3639 if (drvp->drive_flags & DRIVE_UDMA) { 3640 /* use Ultra/DMA */ 3641 drvp->drive_flags &= ~DRIVE_DMA; 3642 mode = PDC2xx_TIM_SET_MB(mode, 3643 pdc2xx_udma_mb[drvp->UDMA_mode]); 3644 mode = PDC2xx_TIM_SET_MC(mode, 3645 pdc2xx_udma_mc[drvp->UDMA_mode]); 3646 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3647 } else if (drvp->drive_flags & DRIVE_DMA) { 3648 mode = PDC2xx_TIM_SET_MB(mode, 3649 pdc2xx_dma_mb[drvp->DMA_mode]); 3650 mode = PDC2xx_TIM_SET_MC(mode, 3651 pdc2xx_dma_mc[drvp->DMA_mode]); 3652 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3653 } else { 3654 mode = PDC2xx_TIM_SET_MB(mode, 3655 pdc2xx_dma_mb[0]); 3656 mode = PDC2xx_TIM_SET_MC(mode, 3657 pdc2xx_dma_mc[0]); 3658 } 3659 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3660 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3661 if (drvp->drive_flags & DRIVE_ATA) 3662 mode |= PDC2xx_TIM_PRE; 3663 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3664 if (drvp->PIO_mode >= 3) { 3665 mode |= PDC2xx_TIM_IORDY; 3666 if (drive == 0) 3667 mode |= PDC2xx_TIM_IORDYp; 3668 } 3669 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3670 "timings 0x%x\n", 3671 sc->sc_wdcdev.sc_dev.dv_xname, 3672 chp->channel, drive, mode), DEBUG_PROBE); 3673 pci_conf_write(sc->sc_pc, sc->sc_tag, 3674 PDC2xx_TIM(chp->channel, drive), mode); 3675 } 3676 if (idedma_ctl != 0) { 3677 /* Add software bits in status register */ 3678 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3679 IDEDMA_CTL, idedma_ctl); 3680 } 3681 pciide_print_modes(cp); 3682 } 3683 3684 void 3685 pdc20268_setup_channel(chp) 3686 struct channel_softc *chp; 3687 { 3688 struct ata_drive_datas *drvp; 3689 int drive; 3690 u_int32_t idedma_ctl; 3691 struct pciide_channel *cp = (struct pciide_channel*)chp; 3692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3693 int u100; 3694 3695 /* setup DMA if needed */ 3696 pciide_channel_dma_setup(cp); 3697 3698 idedma_ctl = 0; 3699 3700 /* I don't know what this is for, FreeBSD does it ... */ 3701 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3702 IDEDMA_CMD + 0x1, 0x0b); 3703 3704 /* 3705 * I don't know what this is for; FreeBSD checks this ... this is not 3706 * cable type detect. 3707 */ 3708 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3709 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3710 3711 for (drive = 0; drive < 2; drive++) { 3712 drvp = &chp->ch_drive[drive]; 3713 /* If no drive, skip */ 3714 if ((drvp->drive_flags & DRIVE) == 0) 3715 continue; 3716 if (drvp->drive_flags & DRIVE_UDMA) { 3717 /* use Ultra/DMA */ 3718 drvp->drive_flags &= ~DRIVE_DMA; 3719 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3720 if (drvp->UDMA_mode > 2 && u100 == 0) 3721 drvp->UDMA_mode = 2; 3722 } else if (drvp->drive_flags & DRIVE_DMA) { 3723 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3724 } 3725 } 3726 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3727 if (idedma_ctl != 0) { 3728 /* Add software bits in status register */ 3729 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3730 IDEDMA_CTL, idedma_ctl); 3731 } 3732 pciide_print_modes(cp); 3733 } 3734 3735 int 3736 pdc202xx_pci_intr(arg) 3737 void *arg; 3738 { 3739 struct pciide_softc *sc = arg; 3740 struct pciide_channel *cp; 3741 struct channel_softc *wdc_cp; 3742 int i, rv, crv; 3743 u_int32_t scr; 3744 3745 rv = 0; 3746 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3747 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3748 cp = &sc->pciide_channels[i]; 3749 wdc_cp = &cp->wdc_channel; 3750 /* If a compat channel skip. */ 3751 if (cp->compat) 3752 continue; 3753 if (scr & PDC2xx_SCR_INT(i)) { 3754 crv = wdcintr(wdc_cp); 3755 if (crv == 0) 3756 printf("%s:%d: bogus intr (reg 0x%x)\n", 3757 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3758 else 3759 rv = 1; 3760 } 3761 } 3762 return rv; 3763 } 3764 3765 int 3766 pdc20265_pci_intr(arg) 3767 void *arg; 3768 { 3769 struct pciide_softc *sc = arg; 3770 struct pciide_channel *cp; 3771 struct channel_softc *wdc_cp; 3772 int i, rv, crv; 3773 u_int32_t dmastat; 3774 3775 rv = 0; 3776 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3777 cp = &sc->pciide_channels[i]; 3778 wdc_cp = &cp->wdc_channel; 3779 /* If a compat channel skip. */ 3780 if (cp->compat) 3781 continue; 3782 /* 3783 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3784 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3785 * So use it instead (requires 2 reg reads instead of 1, 3786 * but we can't do it another way). 3787 */ 3788 dmastat = bus_space_read_1(sc->sc_dma_iot, 3789 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3790 if((dmastat & IDEDMA_CTL_INTR) == 0) 3791 continue; 3792 crv = wdcintr(wdc_cp); 3793 if (crv == 0) 3794 printf("%s:%d: bogus intr\n", 3795 sc->sc_wdcdev.sc_dev.dv_xname, i); 3796 else 3797 rv = 1; 3798 } 3799 return rv; 3800 } 3801 3802 void 3803 opti_chip_map(sc, pa) 3804 struct pciide_softc *sc; 3805 struct pci_attach_args *pa; 3806 { 3807 struct pciide_channel *cp; 3808 bus_size_t cmdsize, ctlsize; 3809 pcireg_t interface; 3810 u_int8_t init_ctrl; 3811 int channel; 3812 3813 if (pciide_chipen(sc, pa) == 0) 3814 return; 3815 printf("%s: bus-master DMA support present", 3816 sc->sc_wdcdev.sc_dev.dv_xname); 3817 3818 /* 3819 * XXXSCW: 3820 * There seem to be a couple of buggy revisions/implementations 3821 * of the OPTi pciide chipset. This kludge seems to fix one of 3822 * the reported problems (PR/11644) but still fails for the 3823 * other (PR/13151), although the latter may be due to other 3824 * issues too... 3825 */ 3826 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3827 printf(" but disabled due to chip rev. <= 0x12"); 3828 sc->sc_dma_ok = 0; 3829 sc->sc_wdcdev.cap = 0; 3830 } else { 3831 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3832 pciide_mapreg_dma(sc, pa); 3833 } 3834 printf("\n"); 3835 3836 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3837 sc->sc_wdcdev.PIO_cap = 4; 3838 if (sc->sc_dma_ok) { 3839 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3840 sc->sc_wdcdev.irqack = pciide_irqack; 3841 sc->sc_wdcdev.DMA_cap = 2; 3842 } 3843 sc->sc_wdcdev.set_modes = opti_setup_channel; 3844 3845 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3846 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3847 3848 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3849 OPTI_REG_INIT_CONTROL); 3850 3851 interface = PCI_INTERFACE(pa->pa_class); 3852 3853 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3854 cp = &sc->pciide_channels[channel]; 3855 if (pciide_chansetup(sc, channel, interface) == 0) 3856 continue; 3857 if (channel == 1 && 3858 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3859 printf("%s: %s channel ignored (disabled)\n", 3860 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3861 continue; 3862 } 3863 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3864 pciide_pci_intr); 3865 if (cp->hw_ok == 0) 3866 continue; 3867 pciide_map_compat_intr(pa, cp, channel, interface); 3868 if (cp->hw_ok == 0) 3869 continue; 3870 opti_setup_channel(&cp->wdc_channel); 3871 } 3872 } 3873 3874 void 3875 opti_setup_channel(chp) 3876 struct channel_softc *chp; 3877 { 3878 struct ata_drive_datas *drvp; 3879 struct pciide_channel *cp = (struct pciide_channel*)chp; 3880 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3881 int drive, spd; 3882 int mode[2]; 3883 u_int8_t rv, mr; 3884 3885 /* 3886 * The `Delay' and `Address Setup Time' fields of the 3887 * Miscellaneous Register are always zero initially. 3888 */ 3889 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3890 mr &= ~(OPTI_MISC_DELAY_MASK | 3891 OPTI_MISC_ADDR_SETUP_MASK | 3892 OPTI_MISC_INDEX_MASK); 3893 3894 /* Prime the control register before setting timing values */ 3895 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3896 3897 /* Determine the clockrate of the PCIbus the chip is attached to */ 3898 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3899 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3900 3901 /* setup DMA if needed */ 3902 pciide_channel_dma_setup(cp); 3903 3904 for (drive = 0; drive < 2; drive++) { 3905 drvp = &chp->ch_drive[drive]; 3906 /* If no drive, skip */ 3907 if ((drvp->drive_flags & DRIVE) == 0) { 3908 mode[drive] = -1; 3909 continue; 3910 } 3911 3912 if ((drvp->drive_flags & DRIVE_DMA)) { 3913 /* 3914 * Timings will be used for both PIO and DMA, 3915 * so adjust DMA mode if needed 3916 */ 3917 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3918 drvp->PIO_mode = drvp->DMA_mode + 2; 3919 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3920 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3921 drvp->PIO_mode - 2 : 0; 3922 if (drvp->DMA_mode == 0) 3923 drvp->PIO_mode = 0; 3924 3925 mode[drive] = drvp->DMA_mode + 5; 3926 } else 3927 mode[drive] = drvp->PIO_mode; 3928 3929 if (drive && mode[0] >= 0 && 3930 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3931 /* 3932 * Can't have two drives using different values 3933 * for `Address Setup Time'. 3934 * Slow down the faster drive to compensate. 3935 */ 3936 int d = (opti_tim_as[spd][mode[0]] > 3937 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3938 3939 mode[d] = mode[1-d]; 3940 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3941 chp->ch_drive[d].DMA_mode = 0; 3942 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3943 } 3944 } 3945 3946 for (drive = 0; drive < 2; drive++) { 3947 int m; 3948 if ((m = mode[drive]) < 0) 3949 continue; 3950 3951 /* Set the Address Setup Time and select appropriate index */ 3952 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3953 rv |= OPTI_MISC_INDEX(drive); 3954 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3955 3956 /* Set the pulse width and recovery timing parameters */ 3957 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3958 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3959 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3960 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3961 3962 /* Set the Enhanced Mode register appropriately */ 3963 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3964 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3965 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3966 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3967 } 3968 3969 /* Finally, enable the timings */ 3970 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3971 3972 pciide_print_modes(cp); 3973 } 3974 3975 #define ACARD_IS_850(sc) \ 3976 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3977 3978 void 3979 acard_chip_map(sc, pa) 3980 struct pciide_softc *sc; 3981 struct pci_attach_args *pa; 3982 { 3983 struct pciide_channel *cp; 3984 int i; 3985 pcireg_t interface; 3986 bus_size_t cmdsize, ctlsize; 3987 3988 if (pciide_chipen(sc, pa) == 0) 3989 return; 3990 3991 /* 3992 * when the chip is in native mode it identifies itself as a 3993 * 'misc mass storage'. Fake interface in this case. 3994 */ 3995 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3996 interface = PCI_INTERFACE(pa->pa_class); 3997 } else { 3998 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3999 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4000 } 4001 4002 printf("%s: bus-master DMA support present", 4003 sc->sc_wdcdev.sc_dev.dv_xname); 4004 pciide_mapreg_dma(sc, pa); 4005 printf("\n"); 4006 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4007 WDC_CAPABILITY_MODE; 4008 4009 if (sc->sc_dma_ok) { 4010 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4011 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4012 sc->sc_wdcdev.irqack = pciide_irqack; 4013 } 4014 sc->sc_wdcdev.PIO_cap = 4; 4015 sc->sc_wdcdev.DMA_cap = 2; 4016 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4017 4018 sc->sc_wdcdev.set_modes = acard_setup_channel; 4019 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4020 sc->sc_wdcdev.nchannels = 2; 4021 4022 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4023 cp = &sc->pciide_channels[i]; 4024 if (pciide_chansetup(sc, i, interface) == 0) 4025 continue; 4026 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4027 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4028 &ctlsize, pciide_pci_intr); 4029 } else { 4030 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4031 &cmdsize, &ctlsize); 4032 } 4033 if (cp->hw_ok == 0) 4034 return; 4035 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4036 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4037 wdcattach(&cp->wdc_channel); 4038 acard_setup_channel(&cp->wdc_channel); 4039 } 4040 if (!ACARD_IS_850(sc)) { 4041 u_int32_t reg; 4042 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4043 reg &= ~ATP860_CTRL_INT; 4044 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4045 } 4046 } 4047 4048 void 4049 acard_setup_channel(chp) 4050 struct channel_softc *chp; 4051 { 4052 struct ata_drive_datas *drvp; 4053 struct pciide_channel *cp = (struct pciide_channel*)chp; 4054 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4055 int channel = chp->channel; 4056 int drive; 4057 u_int32_t idetime, udma_mode; 4058 u_int32_t idedma_ctl; 4059 4060 /* setup DMA if needed */ 4061 pciide_channel_dma_setup(cp); 4062 4063 if (ACARD_IS_850(sc)) { 4064 idetime = 0; 4065 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4066 udma_mode &= ~ATP850_UDMA_MASK(channel); 4067 } else { 4068 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4069 idetime &= ~ATP860_SETTIME_MASK(channel); 4070 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4071 udma_mode &= ~ATP860_UDMA_MASK(channel); 4072 4073 /* check 80 pins cable */ 4074 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4075 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4076 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4077 & ATP860_CTRL_80P(chp->channel)) { 4078 if (chp->ch_drive[0].UDMA_mode > 2) 4079 chp->ch_drive[0].UDMA_mode = 2; 4080 if (chp->ch_drive[1].UDMA_mode > 2) 4081 chp->ch_drive[1].UDMA_mode = 2; 4082 } 4083 } 4084 } 4085 4086 idedma_ctl = 0; 4087 4088 /* Per drive settings */ 4089 for (drive = 0; drive < 2; drive++) { 4090 drvp = &chp->ch_drive[drive]; 4091 /* If no drive, skip */ 4092 if ((drvp->drive_flags & DRIVE) == 0) 4093 continue; 4094 /* add timing values, setup DMA if needed */ 4095 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4096 (drvp->drive_flags & DRIVE_UDMA)) { 4097 /* use Ultra/DMA */ 4098 if (ACARD_IS_850(sc)) { 4099 idetime |= ATP850_SETTIME(drive, 4100 acard_act_udma[drvp->UDMA_mode], 4101 acard_rec_udma[drvp->UDMA_mode]); 4102 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4103 acard_udma_conf[drvp->UDMA_mode]); 4104 } else { 4105 idetime |= ATP860_SETTIME(channel, drive, 4106 acard_act_udma[drvp->UDMA_mode], 4107 acard_rec_udma[drvp->UDMA_mode]); 4108 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4109 acard_udma_conf[drvp->UDMA_mode]); 4110 } 4111 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4112 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4113 (drvp->drive_flags & DRIVE_DMA)) { 4114 /* use Multiword DMA */ 4115 drvp->drive_flags &= ~DRIVE_UDMA; 4116 if (ACARD_IS_850(sc)) { 4117 idetime |= ATP850_SETTIME(drive, 4118 acard_act_dma[drvp->DMA_mode], 4119 acard_rec_dma[drvp->DMA_mode]); 4120 } else { 4121 idetime |= ATP860_SETTIME(channel, drive, 4122 acard_act_dma[drvp->DMA_mode], 4123 acard_rec_dma[drvp->DMA_mode]); 4124 } 4125 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4126 } else { 4127 /* PIO only */ 4128 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4129 if (ACARD_IS_850(sc)) { 4130 idetime |= ATP850_SETTIME(drive, 4131 acard_act_pio[drvp->PIO_mode], 4132 acard_rec_pio[drvp->PIO_mode]); 4133 } else { 4134 idetime |= ATP860_SETTIME(channel, drive, 4135 acard_act_pio[drvp->PIO_mode], 4136 acard_rec_pio[drvp->PIO_mode]); 4137 } 4138 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4139 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4140 | ATP8x0_CTRL_EN(channel)); 4141 } 4142 } 4143 4144 if (idedma_ctl != 0) { 4145 /* Add software bits in status register */ 4146 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4147 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4148 } 4149 pciide_print_modes(cp); 4150 4151 if (ACARD_IS_850(sc)) { 4152 pci_conf_write(sc->sc_pc, sc->sc_tag, 4153 ATP850_IDETIME(channel), idetime); 4154 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4155 } else { 4156 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4157 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4158 } 4159 } 4160 4161 int 4162 acard_pci_intr(arg) 4163 void *arg; 4164 { 4165 struct pciide_softc *sc = arg; 4166 struct pciide_channel *cp; 4167 struct channel_softc *wdc_cp; 4168 int rv = 0; 4169 int dmastat, i, crv; 4170 4171 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4172 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4173 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4174 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4175 continue; 4176 cp = &sc->pciide_channels[i]; 4177 wdc_cp = &cp->wdc_channel; 4178 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4179 (void)wdcintr(wdc_cp); 4180 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4181 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4182 continue; 4183 } 4184 crv = wdcintr(wdc_cp); 4185 if (crv == 0) 4186 printf("%s:%d: bogus intr\n", 4187 sc->sc_wdcdev.sc_dev.dv_xname, i); 4188 else if (crv == 1) 4189 rv = 1; 4190 else if (rv == 0) 4191 rv = crv; 4192 } 4193 return rv; 4194 } 4195
Indexes created Mon Sep 22 13:09:51 GMT 2025