pciide.c revision 1.147
1 /* $NetBSD: pciide.c,v 1.147 2002/04/04 23:47:39 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.147 2002/04/04 23:47:39 thorpej Exp $"); 81 82 #ifndef WDCDEBUG 83 #define WDCDEBUG 84 #endif 85 86 #define DEBUG_DMA 0x01 87 #define DEBUG_XFERS 0x02 88 #define DEBUG_FUNCS 0x08 89 #define DEBUG_PROBE 0x10 90 #ifdef WDCDEBUG 91 int wdcdebug_pciide_mask = 0; 92 #define WDCDEBUG_PRINT(args, level) \ 93 if (wdcdebug_pciide_mask & (level)) printf args 94 #else 95 #define WDCDEBUG_PRINT(args, level) 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 102 #include <uvm/uvm_extern.h> 103 104 #include <machine/endian.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 #include <dev/pci/pciide_opti_reg.h> 120 #include <dev/pci/pciide_hpt_reg.h> 121 #include <dev/pci/pciide_acard_reg.h> 122 #include <dev/pci/pciide_sl82c105_reg.h> 123 #include <dev/pci/cy82c693var.h> 124 125 #include "opt_pciide.h" 126 127 /* inlines for reading/writing 8-bit PCI registers */ 128 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 129 int)); 130 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 131 int, u_int8_t)); 132 133 static __inline u_int8_t 134 pciide_pci_read(pc, pa, reg) 135 pci_chipset_tag_t pc; 136 pcitag_t pa; 137 int reg; 138 { 139 140 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 141 ((reg & 0x03) * 8) & 0xff); 142 } 143 144 static __inline void 145 pciide_pci_write(pc, pa, reg, val) 146 pci_chipset_tag_t pc; 147 pcitag_t pa; 148 int reg; 149 u_int8_t val; 150 { 151 pcireg_t pcival; 152 153 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 154 pcival &= ~(0xff << ((reg & 0x03) * 8)); 155 pcival |= (val << ((reg & 0x03) * 8)); 156 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 157 } 158 159 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 161 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void piix_setup_channel __P((struct channel_softc*)); 163 void piix3_4_setup_channel __P((struct channel_softc*)); 164 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 165 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 166 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 167 168 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void amd7x6_setup_channel __P((struct channel_softc*)); 170 171 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void apollo_setup_channel __P((struct channel_softc*)); 173 174 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cmd0643_9_setup_channel __P((struct channel_softc*)); 177 void cmd_channel_map __P((struct pci_attach_args *, 178 struct pciide_softc *, int)); 179 int cmd_pci_intr __P((void *)); 180 void cmd646_9_irqack __P((struct channel_softc *)); 181 182 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void cy693_setup_channel __P((struct channel_softc*)); 184 185 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void sis_setup_channel __P((struct channel_softc*)); 187 static int sis_hostbr_match __P(( struct pci_attach_args *)); 188 189 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void acer_setup_channel __P((struct channel_softc*)); 191 int acer_pci_intr __P((void *)); 192 static int acer_isabr_match __P(( struct pci_attach_args *)); 193 194 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void pdc202xx_setup_channel __P((struct channel_softc*)); 196 void pdc20268_setup_channel __P((struct channel_softc*)); 197 int pdc202xx_pci_intr __P((void *)); 198 int pdc20265_pci_intr __P((void *)); 199 200 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void opti_setup_channel __P((struct channel_softc*)); 202 203 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 204 void hpt_setup_channel __P((struct channel_softc*)); 205 int hpt_pci_intr __P((void *)); 206 207 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 void acard_setup_channel __P((struct channel_softc*)); 209 int acard_pci_intr __P((void *)); 210 211 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 void sl82c105_setup_channel __P((struct channel_softc*)); 213 214 void pciide_channel_dma_setup __P((struct pciide_channel *)); 215 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 216 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 217 void pciide_dma_start __P((void*, int, int)); 218 int pciide_dma_finish __P((void*, int, int, int)); 219 void pciide_irqack __P((struct channel_softc *)); 220 void pciide_print_modes __P((struct pciide_channel *)); 221 222 struct pciide_product_desc { 223 u_int32_t ide_product; 224 int ide_flags; 225 const char *ide_name; 226 /* map and setup chip, probe drives */ 227 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 228 }; 229 230 /* Flags for ide_flags */ 231 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 232 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 233 234 /* Default product description for devices not known from this controller */ 235 const struct pciide_product_desc default_product_desc = { 236 0, 237 0, 238 "Generic PCI IDE controller", 239 default_chip_map, 240 }; 241 242 const struct pciide_product_desc pciide_intel_products[] = { 243 { PCI_PRODUCT_INTEL_82092AA, 244 0, 245 "Intel 82092AA IDE controller", 246 default_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82371FB_IDE, 249 0, 250 "Intel 82371FB IDE controller (PIIX)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82371SB_IDE, 254 0, 255 "Intel 82371SB IDE Interface (PIIX3)", 256 piix_chip_map, 257 }, 258 { PCI_PRODUCT_INTEL_82371AB_IDE, 259 0, 260 "Intel 82371AB IDE controller (PIIX4)", 261 piix_chip_map, 262 }, 263 { PCI_PRODUCT_INTEL_82440MX_IDE, 264 0, 265 "Intel 82440MX IDE controller", 266 piix_chip_map 267 }, 268 { PCI_PRODUCT_INTEL_82801AA_IDE, 269 0, 270 "Intel 82801AA IDE Controller (ICH)", 271 piix_chip_map, 272 }, 273 { PCI_PRODUCT_INTEL_82801AB_IDE, 274 0, 275 "Intel 82801AB IDE Controller (ICH0)", 276 piix_chip_map, 277 }, 278 { PCI_PRODUCT_INTEL_82801BA_IDE, 279 0, 280 "Intel 82801BA IDE Controller (ICH2)", 281 piix_chip_map, 282 }, 283 { PCI_PRODUCT_INTEL_82801BAM_IDE, 284 0, 285 "Intel 82801BAM IDE Controller (ICH2)", 286 piix_chip_map, 287 }, 288 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 289 0, 290 "Intel 82201CA IDE Controller", 291 piix_chip_map, 292 }, 293 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 294 0, 295 "Intel 82201CA IDE Controller", 296 piix_chip_map, 297 }, 298 { 0, 299 0, 300 NULL, 301 NULL 302 } 303 }; 304 305 const struct pciide_product_desc pciide_amd_products[] = { 306 { PCI_PRODUCT_AMD_PBC756_IDE, 307 0, 308 "Advanced Micro Devices AMD756 IDE Controller", 309 amd7x6_chip_map 310 }, 311 { PCI_PRODUCT_AMD_PBC766_IDE, 312 0, 313 "Advanced Micro Devices AMD766 IDE Controller", 314 amd7x6_chip_map 315 }, 316 { PCI_PRODUCT_AMD_PBC768_IDE, 317 0, 318 "Advanced Micro Devices AMD768 IDE Controller", 319 amd7x6_chip_map 320 }, 321 { 0, 322 0, 323 NULL, 324 NULL 325 } 326 }; 327 328 const struct pciide_product_desc pciide_cmd_products[] = { 329 { PCI_PRODUCT_CMDTECH_640, 330 0, 331 "CMD Technology PCI0640", 332 cmd_chip_map 333 }, 334 { PCI_PRODUCT_CMDTECH_643, 335 0, 336 "CMD Technology PCI0643", 337 cmd0643_9_chip_map, 338 }, 339 { PCI_PRODUCT_CMDTECH_646, 340 0, 341 "CMD Technology PCI0646", 342 cmd0643_9_chip_map, 343 }, 344 { PCI_PRODUCT_CMDTECH_648, 345 IDE_PCI_CLASS_OVERRIDE, 346 "CMD Technology PCI0648", 347 cmd0643_9_chip_map, 348 }, 349 { PCI_PRODUCT_CMDTECH_649, 350 IDE_PCI_CLASS_OVERRIDE, 351 "CMD Technology PCI0649", 352 cmd0643_9_chip_map, 353 }, 354 { 0, 355 0, 356 NULL, 357 NULL 358 } 359 }; 360 361 const struct pciide_product_desc pciide_via_products[] = { 362 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 363 0, 364 NULL, 365 apollo_chip_map, 366 }, 367 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 368 0, 369 NULL, 370 apollo_chip_map, 371 }, 372 { 0, 373 0, 374 NULL, 375 NULL 376 } 377 }; 378 379 const struct pciide_product_desc pciide_cypress_products[] = { 380 { PCI_PRODUCT_CONTAQ_82C693, 381 IDE_16BIT_IOSPACE, 382 "Cypress 82C693 IDE Controller", 383 cy693_chip_map, 384 }, 385 { 0, 386 0, 387 NULL, 388 NULL 389 } 390 }; 391 392 const struct pciide_product_desc pciide_sis_products[] = { 393 { PCI_PRODUCT_SIS_5597_IDE, 394 0, 395 "Silicon Integrated System 5597/5598 IDE controller", 396 sis_chip_map, 397 }, 398 { 0, 399 0, 400 NULL, 401 NULL 402 } 403 }; 404 405 const struct pciide_product_desc pciide_acer_products[] = { 406 { PCI_PRODUCT_ALI_M5229, 407 0, 408 "Acer Labs M5229 UDMA IDE Controller", 409 acer_chip_map, 410 }, 411 { 0, 412 0, 413 NULL, 414 NULL 415 } 416 }; 417 418 const struct pciide_product_desc pciide_promise_products[] = { 419 { PCI_PRODUCT_PROMISE_ULTRA33, 420 IDE_PCI_CLASS_OVERRIDE, 421 "Promise Ultra33/ATA Bus Master IDE Accelerator", 422 pdc202xx_chip_map, 423 }, 424 { PCI_PRODUCT_PROMISE_ULTRA66, 425 IDE_PCI_CLASS_OVERRIDE, 426 "Promise Ultra66/ATA Bus Master IDE Accelerator", 427 pdc202xx_chip_map, 428 }, 429 { PCI_PRODUCT_PROMISE_ULTRA100, 430 IDE_PCI_CLASS_OVERRIDE, 431 "Promise Ultra100/ATA Bus Master IDE Accelerator", 432 pdc202xx_chip_map, 433 }, 434 { PCI_PRODUCT_PROMISE_ULTRA100X, 435 IDE_PCI_CLASS_OVERRIDE, 436 "Promise Ultra100/ATA Bus Master IDE Accelerator", 437 pdc202xx_chip_map, 438 }, 439 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 440 IDE_PCI_CLASS_OVERRIDE, 441 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 442 pdc202xx_chip_map, 443 }, 444 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 445 IDE_PCI_CLASS_OVERRIDE, 446 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 447 pdc202xx_chip_map, 448 }, 449 { PCI_PRODUCT_PROMISE_ULTRA133, 450 IDE_PCI_CLASS_OVERRIDE, 451 "Promise Ultra133/ATA Bus Master IDE Accelerator", 452 pdc202xx_chip_map, 453 }, 454 { 0, 455 0, 456 NULL, 457 NULL 458 } 459 }; 460 461 const struct pciide_product_desc pciide_opti_products[] = { 462 { PCI_PRODUCT_OPTI_82C621, 463 0, 464 "OPTi 82c621 PCI IDE controller", 465 opti_chip_map, 466 }, 467 { PCI_PRODUCT_OPTI_82C568, 468 0, 469 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 470 opti_chip_map, 471 }, 472 { PCI_PRODUCT_OPTI_82D568, 473 0, 474 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 475 opti_chip_map, 476 }, 477 { 0, 478 0, 479 NULL, 480 NULL 481 } 482 }; 483 484 const struct pciide_product_desc pciide_triones_products[] = { 485 { PCI_PRODUCT_TRIONES_HPT366, 486 IDE_PCI_CLASS_OVERRIDE, 487 NULL, 488 hpt_chip_map, 489 }, 490 { 0, 491 0, 492 NULL, 493 NULL 494 } 495 }; 496 497 const struct pciide_product_desc pciide_acard_products[] = { 498 { PCI_PRODUCT_ACARD_ATP850U, 499 IDE_PCI_CLASS_OVERRIDE, 500 "Acard ATP850U Ultra33 IDE Controller", 501 acard_chip_map, 502 }, 503 { PCI_PRODUCT_ACARD_ATP860, 504 IDE_PCI_CLASS_OVERRIDE, 505 "Acard ATP860 Ultra66 IDE Controller", 506 acard_chip_map, 507 }, 508 { PCI_PRODUCT_ACARD_ATP860A, 509 IDE_PCI_CLASS_OVERRIDE, 510 "Acard ATP860-A Ultra66 IDE Controller", 511 acard_chip_map, 512 }, 513 { 0, 514 0, 515 NULL, 516 NULL 517 } 518 }; 519 520 #ifdef PCIIDE_SERVERWORKS_ENABLE 521 const struct pciide_product_desc pciide_serverworks_products[] = { 522 { PCI_PRODUCT_SERVERWORKS_IDE, 523 0, 524 "ServerWorks ROSB4 IDE Controller", 525 piix_chip_map, 526 }, 527 { 0, 528 0, 529 NULL, 530 } 531 }; 532 #endif 533 534 const struct pciide_product_desc pciide_symphony_products[] = { 535 { PCI_PRODUCT_SYMPHONY_82C105, 536 0, 537 "Symphony Labs 82C105 IDE controller", 538 sl82c105_chip_map, 539 }, 540 { 0, 541 0, 542 NULL, 543 } 544 }; 545 546 const struct pciide_product_desc pciide_winbond_products[] = { 547 { PCI_PRODUCT_WINBOND_W83C553F_1, 548 0, 549 "Winbond W83C553F IDE controller", 550 sl82c105_chip_map, 551 }, 552 { 0, 553 0, 554 NULL, 555 } 556 }; 557 558 struct pciide_vendor_desc { 559 u_int32_t ide_vendor; 560 const struct pciide_product_desc *ide_products; 561 }; 562 563 const struct pciide_vendor_desc pciide_vendors[] = { 564 { PCI_VENDOR_INTEL, pciide_intel_products }, 565 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 566 { PCI_VENDOR_VIATECH, pciide_via_products }, 567 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 568 { PCI_VENDOR_SIS, pciide_sis_products }, 569 { PCI_VENDOR_ALI, pciide_acer_products }, 570 { PCI_VENDOR_PROMISE, pciide_promise_products }, 571 { PCI_VENDOR_AMD, pciide_amd_products }, 572 { PCI_VENDOR_OPTI, pciide_opti_products }, 573 { PCI_VENDOR_TRIONES, pciide_triones_products }, 574 { PCI_VENDOR_ACARD, pciide_acard_products }, 575 #ifdef PCIIDE_SERVERWORKS_ENABLE 576 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 577 #endif 578 #ifdef PCIIDE_WINBOND_ENABLE 579 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 580 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 581 #endif 582 { 0, NULL } 583 }; 584 585 /* options passed via the 'flags' config keyword */ 586 #define PCIIDE_OPTIONS_DMA 0x01 587 #define PCIIDE_OPTIONS_NODMA 0x02 588 589 int pciide_match __P((struct device *, struct cfdata *, void *)); 590 void pciide_attach __P((struct device *, struct device *, void *)); 591 592 struct cfattach pciide_ca = { 593 sizeof(struct pciide_softc), pciide_match, pciide_attach 594 }; 595 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 596 int pciide_mapregs_compat __P(( struct pci_attach_args *, 597 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 598 int pciide_mapregs_native __P((struct pci_attach_args *, 599 struct pciide_channel *, bus_size_t *, bus_size_t *, 600 int (*pci_intr) __P((void *)))); 601 void pciide_mapreg_dma __P((struct pciide_softc *, 602 struct pci_attach_args *)); 603 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 604 void pciide_mapchan __P((struct pci_attach_args *, 605 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 606 int (*pci_intr) __P((void *)))); 607 int pciide_chan_candisable __P((struct pciide_channel *)); 608 void pciide_map_compat_intr __P(( struct pci_attach_args *, 609 struct pciide_channel *, int, int)); 610 int pciide_compat_intr __P((void *)); 611 int pciide_pci_intr __P((void *)); 612 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 613 614 const struct pciide_product_desc * 615 pciide_lookup_product(id) 616 u_int32_t id; 617 { 618 const struct pciide_product_desc *pp; 619 const struct pciide_vendor_desc *vp; 620 621 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 622 if (PCI_VENDOR(id) == vp->ide_vendor) 623 break; 624 625 if ((pp = vp->ide_products) == NULL) 626 return NULL; 627 628 for (; pp->chip_map != NULL; pp++) 629 if (PCI_PRODUCT(id) == pp->ide_product) 630 break; 631 632 if (pp->chip_map == NULL) 633 return NULL; 634 return pp; 635 } 636 637 int 638 pciide_match(parent, match, aux) 639 struct device *parent; 640 struct cfdata *match; 641 void *aux; 642 { 643 struct pci_attach_args *pa = aux; 644 const struct pciide_product_desc *pp; 645 646 /* 647 * Check the ID register to see that it's a PCI IDE controller. 648 * If it is, we assume that we can deal with it; it _should_ 649 * work in a standardized way... 650 */ 651 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 652 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 653 return (1); 654 } 655 656 /* 657 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 658 * controllers. Let see if we can deal with it anyway. 659 */ 660 pp = pciide_lookup_product(pa->pa_id); 661 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 662 return (1); 663 } 664 665 return (0); 666 } 667 668 void 669 pciide_attach(parent, self, aux) 670 struct device *parent, *self; 671 void *aux; 672 { 673 struct pci_attach_args *pa = aux; 674 pci_chipset_tag_t pc = pa->pa_pc; 675 pcitag_t tag = pa->pa_tag; 676 struct pciide_softc *sc = (struct pciide_softc *)self; 677 pcireg_t csr; 678 char devinfo[256]; 679 const char *displaydev; 680 681 sc->sc_pp = pciide_lookup_product(pa->pa_id); 682 if (sc->sc_pp == NULL) { 683 sc->sc_pp = &default_product_desc; 684 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 685 displaydev = devinfo; 686 } else 687 displaydev = sc->sc_pp->ide_name; 688 689 /* if displaydev == NULL, printf is done in chip-specific map */ 690 if (displaydev) 691 printf(": %s (rev. 0x%02x)\n", displaydev, 692 PCI_REVISION(pa->pa_class)); 693 694 sc->sc_pc = pa->pa_pc; 695 sc->sc_tag = pa->pa_tag; 696 #ifdef WDCDEBUG 697 if (wdcdebug_pciide_mask & DEBUG_PROBE) 698 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 699 #endif 700 sc->sc_pp->chip_map(sc, pa); 701 702 if (sc->sc_dma_ok) { 703 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 704 csr |= PCI_COMMAND_MASTER_ENABLE; 705 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 706 } 707 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 708 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 709 } 710 711 /* tell wether the chip is enabled or not */ 712 int 713 pciide_chipen(sc, pa) 714 struct pciide_softc *sc; 715 struct pci_attach_args *pa; 716 { 717 pcireg_t csr; 718 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 719 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 720 PCI_COMMAND_STATUS_REG); 721 printf("%s: device disabled (at %s)\n", 722 sc->sc_wdcdev.sc_dev.dv_xname, 723 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 724 "device" : "bridge"); 725 return 0; 726 } 727 return 1; 728 } 729 730 int 731 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 732 struct pci_attach_args *pa; 733 struct pciide_channel *cp; 734 int compatchan; 735 bus_size_t *cmdsizep, *ctlsizep; 736 { 737 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 738 struct channel_softc *wdc_cp = &cp->wdc_channel; 739 740 cp->compat = 1; 741 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 742 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 743 744 wdc_cp->cmd_iot = pa->pa_iot; 745 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 746 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 747 printf("%s: couldn't map %s channel cmd regs\n", 748 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 749 return (0); 750 } 751 752 wdc_cp->ctl_iot = pa->pa_iot; 753 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 754 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 755 printf("%s: couldn't map %s channel ctl regs\n", 756 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 757 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 758 PCIIDE_COMPAT_CMD_SIZE); 759 return (0); 760 } 761 762 return (1); 763 } 764 765 int 766 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 767 struct pci_attach_args * pa; 768 struct pciide_channel *cp; 769 bus_size_t *cmdsizep, *ctlsizep; 770 int (*pci_intr) __P((void *)); 771 { 772 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 773 struct channel_softc *wdc_cp = &cp->wdc_channel; 774 const char *intrstr; 775 pci_intr_handle_t intrhandle; 776 777 cp->compat = 0; 778 779 if (sc->sc_pci_ih == NULL) { 780 if (pci_intr_map(pa, &intrhandle) != 0) { 781 printf("%s: couldn't map native-PCI interrupt\n", 782 sc->sc_wdcdev.sc_dev.dv_xname); 783 return 0; 784 } 785 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 786 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 787 intrhandle, IPL_BIO, pci_intr, sc); 788 if (sc->sc_pci_ih != NULL) { 789 printf("%s: using %s for native-PCI interrupt\n", 790 sc->sc_wdcdev.sc_dev.dv_xname, 791 intrstr ? intrstr : "unknown interrupt"); 792 } else { 793 printf("%s: couldn't establish native-PCI interrupt", 794 sc->sc_wdcdev.sc_dev.dv_xname); 795 if (intrstr != NULL) 796 printf(" at %s", intrstr); 797 printf("\n"); 798 return 0; 799 } 800 } 801 cp->ih = sc->sc_pci_ih; 802 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 803 PCI_MAPREG_TYPE_IO, 0, 804 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 805 printf("%s: couldn't map %s channel cmd regs\n", 806 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 807 return 0; 808 } 809 810 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 811 PCI_MAPREG_TYPE_IO, 0, 812 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 813 printf("%s: couldn't map %s channel ctl regs\n", 814 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 815 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 816 return 0; 817 } 818 /* 819 * In native mode, 4 bytes of I/O space are mapped for the control 820 * register, the control register is at offset 2. Pass the generic 821 * code a handle for only one byte at the rigth offset. 822 */ 823 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 824 &wdc_cp->ctl_ioh) != 0) { 825 printf("%s: unable to subregion %s channel ctl regs\n", 826 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 827 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 828 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 829 return 0; 830 } 831 return (1); 832 } 833 834 void 835 pciide_mapreg_dma(sc, pa) 836 struct pciide_softc *sc; 837 struct pci_attach_args *pa; 838 { 839 pcireg_t maptype; 840 bus_addr_t addr; 841 842 /* 843 * Map DMA registers 844 * 845 * Note that sc_dma_ok is the right variable to test to see if 846 * DMA can be done. If the interface doesn't support DMA, 847 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 848 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 849 * non-zero if the interface supports DMA and the registers 850 * could be mapped. 851 * 852 * XXX Note that despite the fact that the Bus Master IDE specs 853 * XXX say that "The bus master IDE function uses 16 bytes of IO 854 * XXX space," some controllers (at least the United 855 * XXX Microelectronics UM8886BF) place it in memory space. 856 */ 857 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 858 PCIIDE_REG_BUS_MASTER_DMA); 859 860 switch (maptype) { 861 case PCI_MAPREG_TYPE_IO: 862 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 863 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 864 &addr, NULL, NULL) == 0); 865 if (sc->sc_dma_ok == 0) { 866 printf(", but unused (couldn't query registers)"); 867 break; 868 } 869 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 870 && addr >= 0x10000) { 871 sc->sc_dma_ok = 0; 872 printf(", but unused (registers at unsafe address " 873 "%#lx)", (unsigned long)addr); 874 break; 875 } 876 /* FALLTHROUGH */ 877 878 case PCI_MAPREG_MEM_TYPE_32BIT: 879 sc->sc_dma_ok = (pci_mapreg_map(pa, 880 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 881 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 882 sc->sc_dmat = pa->pa_dmat; 883 if (sc->sc_dma_ok == 0) { 884 printf(", but unused (couldn't map registers)"); 885 } else { 886 sc->sc_wdcdev.dma_arg = sc; 887 sc->sc_wdcdev.dma_init = pciide_dma_init; 888 sc->sc_wdcdev.dma_start = pciide_dma_start; 889 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 890 } 891 892 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 893 PCIIDE_OPTIONS_NODMA) { 894 printf(", but unused (forced off by config file)"); 895 sc->sc_dma_ok = 0; 896 } 897 break; 898 899 default: 900 sc->sc_dma_ok = 0; 901 printf(", but unsupported register maptype (0x%x)", maptype); 902 } 903 } 904 905 int 906 pciide_compat_intr(arg) 907 void *arg; 908 { 909 struct pciide_channel *cp = arg; 910 911 #ifdef DIAGNOSTIC 912 /* should only be called for a compat channel */ 913 if (cp->compat == 0) 914 panic("pciide compat intr called for non-compat chan %p\n", cp); 915 #endif 916 return (wdcintr(&cp->wdc_channel)); 917 } 918 919 int 920 pciide_pci_intr(arg) 921 void *arg; 922 { 923 struct pciide_softc *sc = arg; 924 struct pciide_channel *cp; 925 struct channel_softc *wdc_cp; 926 int i, rv, crv; 927 928 rv = 0; 929 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 930 cp = &sc->pciide_channels[i]; 931 wdc_cp = &cp->wdc_channel; 932 933 /* If a compat channel skip. */ 934 if (cp->compat) 935 continue; 936 /* if this channel not waiting for intr, skip */ 937 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 938 continue; 939 940 crv = wdcintr(wdc_cp); 941 if (crv == 0) 942 ; /* leave rv alone */ 943 else if (crv == 1) 944 rv = 1; /* claim the intr */ 945 else if (rv == 0) /* crv should be -1 in this case */ 946 rv = crv; /* if we've done no better, take it */ 947 } 948 return (rv); 949 } 950 951 void 952 pciide_channel_dma_setup(cp) 953 struct pciide_channel *cp; 954 { 955 int drive; 956 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 957 struct ata_drive_datas *drvp; 958 959 for (drive = 0; drive < 2; drive++) { 960 drvp = &cp->wdc_channel.ch_drive[drive]; 961 /* If no drive, skip */ 962 if ((drvp->drive_flags & DRIVE) == 0) 963 continue; 964 /* setup DMA if needed */ 965 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 966 (drvp->drive_flags & DRIVE_UDMA) == 0) || 967 sc->sc_dma_ok == 0) { 968 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 969 continue; 970 } 971 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 972 != 0) { 973 /* Abort DMA setup */ 974 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 975 continue; 976 } 977 } 978 } 979 980 int 981 pciide_dma_table_setup(sc, channel, drive) 982 struct pciide_softc *sc; 983 int channel, drive; 984 { 985 bus_dma_segment_t seg; 986 int error, rseg; 987 const bus_size_t dma_table_size = 988 sizeof(struct idedma_table) * NIDEDMA_TABLES; 989 struct pciide_dma_maps *dma_maps = 990 &sc->pciide_channels[channel].dma_maps[drive]; 991 992 /* If table was already allocated, just return */ 993 if (dma_maps->dma_table) 994 return 0; 995 996 /* Allocate memory for the DMA tables and map it */ 997 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 998 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 999 BUS_DMA_NOWAIT)) != 0) { 1000 printf("%s:%d: unable to allocate table DMA for " 1001 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1002 channel, drive, error); 1003 return error; 1004 } 1005 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1006 dma_table_size, 1007 (caddr_t *)&dma_maps->dma_table, 1008 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1009 printf("%s:%d: unable to map table DMA for" 1010 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1011 channel, drive, error); 1012 return error; 1013 } 1014 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1015 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1016 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1017 1018 /* Create and load table DMA map for this disk */ 1019 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1020 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1021 &dma_maps->dmamap_table)) != 0) { 1022 printf("%s:%d: unable to create table DMA map for " 1023 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1024 channel, drive, error); 1025 return error; 1026 } 1027 if ((error = bus_dmamap_load(sc->sc_dmat, 1028 dma_maps->dmamap_table, 1029 dma_maps->dma_table, 1030 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1031 printf("%s:%d: unable to load table DMA map for " 1032 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1033 channel, drive, error); 1034 return error; 1035 } 1036 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1037 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1038 DEBUG_PROBE); 1039 /* Create a xfer DMA map for this drive */ 1040 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1041 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1042 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1043 &dma_maps->dmamap_xfer)) != 0) { 1044 printf("%s:%d: unable to create xfer DMA map for " 1045 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1046 channel, drive, error); 1047 return error; 1048 } 1049 return 0; 1050 } 1051 1052 int 1053 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1054 void *v; 1055 int channel, drive; 1056 void *databuf; 1057 size_t datalen; 1058 int flags; 1059 { 1060 struct pciide_softc *sc = v; 1061 int error, seg; 1062 struct pciide_dma_maps *dma_maps = 1063 &sc->pciide_channels[channel].dma_maps[drive]; 1064 1065 error = bus_dmamap_load(sc->sc_dmat, 1066 dma_maps->dmamap_xfer, 1067 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1068 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1069 if (error) { 1070 printf("%s:%d: unable to load xfer DMA map for" 1071 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1072 channel, drive, error); 1073 return error; 1074 } 1075 1076 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1077 dma_maps->dmamap_xfer->dm_mapsize, 1078 (flags & WDC_DMA_READ) ? 1079 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1080 1081 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1082 #ifdef DIAGNOSTIC 1083 /* A segment must not cross a 64k boundary */ 1084 { 1085 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1086 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1087 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1088 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1089 printf("pciide_dma: segment %d physical addr 0x%lx" 1090 " len 0x%lx not properly aligned\n", 1091 seg, phys, len); 1092 panic("pciide_dma: buf align"); 1093 } 1094 } 1095 #endif 1096 dma_maps->dma_table[seg].base_addr = 1097 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1098 dma_maps->dma_table[seg].byte_count = 1099 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1100 IDEDMA_BYTE_COUNT_MASK); 1101 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1102 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1103 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1104 1105 } 1106 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1107 htole32(IDEDMA_BYTE_COUNT_EOT); 1108 1109 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1110 dma_maps->dmamap_table->dm_mapsize, 1111 BUS_DMASYNC_PREWRITE); 1112 1113 /* Maps are ready. Start DMA function */ 1114 #ifdef DIAGNOSTIC 1115 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1116 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1117 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1118 panic("pciide_dma_init: table align"); 1119 } 1120 #endif 1121 1122 /* Clear status bits */ 1123 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1124 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1125 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1126 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1127 /* Write table addr */ 1128 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1129 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1130 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1131 /* set read/write */ 1132 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1133 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1134 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1135 /* remember flags */ 1136 dma_maps->dma_flags = flags; 1137 return 0; 1138 } 1139 1140 void 1141 pciide_dma_start(v, channel, drive) 1142 void *v; 1143 int channel, drive; 1144 { 1145 struct pciide_softc *sc = v; 1146 1147 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1148 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1149 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1150 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1151 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1152 } 1153 1154 int 1155 pciide_dma_finish(v, channel, drive, force) 1156 void *v; 1157 int channel, drive; 1158 int force; 1159 { 1160 struct pciide_softc *sc = v; 1161 u_int8_t status; 1162 int error = 0; 1163 struct pciide_dma_maps *dma_maps = 1164 &sc->pciide_channels[channel].dma_maps[drive]; 1165 1166 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1167 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1168 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1169 DEBUG_XFERS); 1170 1171 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1172 return WDC_DMAST_NOIRQ; 1173 1174 /* stop DMA channel */ 1175 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1176 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1177 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1178 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1179 1180 /* Unload the map of the data buffer */ 1181 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1182 dma_maps->dmamap_xfer->dm_mapsize, 1183 (dma_maps->dma_flags & WDC_DMA_READ) ? 1184 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1185 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1186 1187 if ((status & IDEDMA_CTL_ERR) != 0) { 1188 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1189 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1190 error |= WDC_DMAST_ERR; 1191 } 1192 1193 if ((status & IDEDMA_CTL_INTR) == 0) { 1194 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1195 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1196 drive, status); 1197 error |= WDC_DMAST_NOIRQ; 1198 } 1199 1200 if ((status & IDEDMA_CTL_ACT) != 0) { 1201 /* data underrun, may be a valid condition for ATAPI */ 1202 error |= WDC_DMAST_UNDER; 1203 } 1204 return error; 1205 } 1206 1207 void 1208 pciide_irqack(chp) 1209 struct channel_softc *chp; 1210 { 1211 struct pciide_channel *cp = (struct pciide_channel*)chp; 1212 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1213 1214 /* clear status bits in IDE DMA registers */ 1215 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1216 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1217 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1218 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1219 } 1220 1221 /* some common code used by several chip_map */ 1222 int 1223 pciide_chansetup(sc, channel, interface) 1224 struct pciide_softc *sc; 1225 int channel; 1226 pcireg_t interface; 1227 { 1228 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1229 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1230 cp->name = PCIIDE_CHANNEL_NAME(channel); 1231 cp->wdc_channel.channel = channel; 1232 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1233 cp->wdc_channel.ch_queue = 1234 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1235 if (cp->wdc_channel.ch_queue == NULL) { 1236 printf("%s %s channel: " 1237 "can't allocate memory for command queue", 1238 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1239 return 0; 1240 } 1241 printf("%s: %s channel %s to %s mode\n", 1242 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1243 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1244 "configured" : "wired", 1245 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1246 "native-PCI" : "compatibility"); 1247 return 1; 1248 } 1249 1250 /* some common code used by several chip channel_map */ 1251 void 1252 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1253 struct pci_attach_args *pa; 1254 struct pciide_channel *cp; 1255 pcireg_t interface; 1256 bus_size_t *cmdsizep, *ctlsizep; 1257 int (*pci_intr) __P((void *)); 1258 { 1259 struct channel_softc *wdc_cp = &cp->wdc_channel; 1260 1261 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1262 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1263 pci_intr); 1264 else 1265 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1266 wdc_cp->channel, cmdsizep, ctlsizep); 1267 1268 if (cp->hw_ok == 0) 1269 return; 1270 wdc_cp->data32iot = wdc_cp->cmd_iot; 1271 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1272 wdcattach(wdc_cp); 1273 } 1274 1275 /* 1276 * Generic code to call to know if a channel can be disabled. Return 1 1277 * if channel can be disabled, 0 if not 1278 */ 1279 int 1280 pciide_chan_candisable(cp) 1281 struct pciide_channel *cp; 1282 { 1283 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1284 struct channel_softc *wdc_cp = &cp->wdc_channel; 1285 1286 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1287 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1288 printf("%s: disabling %s channel (no drives)\n", 1289 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1290 cp->hw_ok = 0; 1291 return 1; 1292 } 1293 return 0; 1294 } 1295 1296 /* 1297 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1298 * Set hw_ok=0 on failure 1299 */ 1300 void 1301 pciide_map_compat_intr(pa, cp, compatchan, interface) 1302 struct pci_attach_args *pa; 1303 struct pciide_channel *cp; 1304 int compatchan, interface; 1305 { 1306 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1307 struct channel_softc *wdc_cp = &cp->wdc_channel; 1308 1309 if (cp->hw_ok == 0) 1310 return; 1311 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1312 return; 1313 1314 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1315 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1316 pa, compatchan, pciide_compat_intr, cp); 1317 if (cp->ih == NULL) { 1318 #endif 1319 printf("%s: no compatibility interrupt for use by %s " 1320 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1321 cp->hw_ok = 0; 1322 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1323 } 1324 #endif 1325 } 1326 1327 void 1328 pciide_print_modes(cp) 1329 struct pciide_channel *cp; 1330 { 1331 wdc_print_modes(&cp->wdc_channel); 1332 } 1333 1334 void 1335 default_chip_map(sc, pa) 1336 struct pciide_softc *sc; 1337 struct pci_attach_args *pa; 1338 { 1339 struct pciide_channel *cp; 1340 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1341 pcireg_t csr; 1342 int channel, drive; 1343 struct ata_drive_datas *drvp; 1344 u_int8_t idedma_ctl; 1345 bus_size_t cmdsize, ctlsize; 1346 char *failreason; 1347 1348 if (pciide_chipen(sc, pa) == 0) 1349 return; 1350 1351 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1352 printf("%s: bus-master DMA support present", 1353 sc->sc_wdcdev.sc_dev.dv_xname); 1354 if (sc->sc_pp == &default_product_desc && 1355 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1356 PCIIDE_OPTIONS_DMA) == 0) { 1357 printf(", but unused (no driver support)"); 1358 sc->sc_dma_ok = 0; 1359 } else { 1360 pciide_mapreg_dma(sc, pa); 1361 if (sc->sc_dma_ok != 0) 1362 printf(", used without full driver " 1363 "support"); 1364 } 1365 } else { 1366 printf("%s: hardware does not support DMA", 1367 sc->sc_wdcdev.sc_dev.dv_xname); 1368 sc->sc_dma_ok = 0; 1369 } 1370 printf("\n"); 1371 if (sc->sc_dma_ok) { 1372 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1373 sc->sc_wdcdev.irqack = pciide_irqack; 1374 } 1375 sc->sc_wdcdev.PIO_cap = 0; 1376 sc->sc_wdcdev.DMA_cap = 0; 1377 1378 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1379 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1380 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1381 1382 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1383 cp = &sc->pciide_channels[channel]; 1384 if (pciide_chansetup(sc, channel, interface) == 0) 1385 continue; 1386 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1387 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1388 &ctlsize, pciide_pci_intr); 1389 } else { 1390 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1391 channel, &cmdsize, &ctlsize); 1392 } 1393 if (cp->hw_ok == 0) 1394 continue; 1395 /* 1396 * Check to see if something appears to be there. 1397 */ 1398 failreason = NULL; 1399 if (!wdcprobe(&cp->wdc_channel)) { 1400 failreason = "not responding; disabled or no drives?"; 1401 goto next; 1402 } 1403 /* 1404 * Now, make sure it's actually attributable to this PCI IDE 1405 * channel by trying to access the channel again while the 1406 * PCI IDE controller's I/O space is disabled. (If the 1407 * channel no longer appears to be there, it belongs to 1408 * this controller.) YUCK! 1409 */ 1410 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1411 PCI_COMMAND_STATUS_REG); 1412 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1413 csr & ~PCI_COMMAND_IO_ENABLE); 1414 if (wdcprobe(&cp->wdc_channel)) 1415 failreason = "other hardware responding at addresses"; 1416 pci_conf_write(sc->sc_pc, sc->sc_tag, 1417 PCI_COMMAND_STATUS_REG, csr); 1418 next: 1419 if (failreason) { 1420 printf("%s: %s channel ignored (%s)\n", 1421 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1422 failreason); 1423 cp->hw_ok = 0; 1424 bus_space_unmap(cp->wdc_channel.cmd_iot, 1425 cp->wdc_channel.cmd_ioh, cmdsize); 1426 bus_space_unmap(cp->wdc_channel.ctl_iot, 1427 cp->wdc_channel.ctl_ioh, ctlsize); 1428 } else { 1429 pciide_map_compat_intr(pa, cp, channel, interface); 1430 } 1431 if (cp->hw_ok) { 1432 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1433 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1434 wdcattach(&cp->wdc_channel); 1435 } 1436 } 1437 1438 if (sc->sc_dma_ok == 0) 1439 return; 1440 1441 /* Allocate DMA maps */ 1442 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1443 idedma_ctl = 0; 1444 cp = &sc->pciide_channels[channel]; 1445 for (drive = 0; drive < 2; drive++) { 1446 drvp = &cp->wdc_channel.ch_drive[drive]; 1447 /* If no drive, skip */ 1448 if ((drvp->drive_flags & DRIVE) == 0) 1449 continue; 1450 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1451 continue; 1452 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1453 /* Abort DMA setup */ 1454 printf("%s:%d:%d: can't allocate DMA maps, " 1455 "using PIO transfers\n", 1456 sc->sc_wdcdev.sc_dev.dv_xname, 1457 channel, drive); 1458 drvp->drive_flags &= ~DRIVE_DMA; 1459 } 1460 printf("%s:%d:%d: using DMA data transfers\n", 1461 sc->sc_wdcdev.sc_dev.dv_xname, 1462 channel, drive); 1463 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1464 } 1465 if (idedma_ctl != 0) { 1466 /* Add software bits in status register */ 1467 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1468 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1469 idedma_ctl); 1470 } 1471 } 1472 } 1473 1474 void 1475 piix_chip_map(sc, pa) 1476 struct pciide_softc *sc; 1477 struct pci_attach_args *pa; 1478 { 1479 struct pciide_channel *cp; 1480 int channel; 1481 u_int32_t idetim; 1482 bus_size_t cmdsize, ctlsize; 1483 1484 if (pciide_chipen(sc, pa) == 0) 1485 return; 1486 1487 printf("%s: bus-master DMA support present", 1488 sc->sc_wdcdev.sc_dev.dv_xname); 1489 pciide_mapreg_dma(sc, pa); 1490 printf("\n"); 1491 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1492 WDC_CAPABILITY_MODE; 1493 if (sc->sc_dma_ok) { 1494 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1495 sc->sc_wdcdev.irqack = pciide_irqack; 1496 switch(sc->sc_pp->ide_product) { 1497 case PCI_PRODUCT_INTEL_82371AB_IDE: 1498 case PCI_PRODUCT_INTEL_82440MX_IDE: 1499 case PCI_PRODUCT_INTEL_82801AA_IDE: 1500 case PCI_PRODUCT_INTEL_82801AB_IDE: 1501 case PCI_PRODUCT_INTEL_82801BA_IDE: 1502 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1503 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1504 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1505 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1506 } 1507 } 1508 sc->sc_wdcdev.PIO_cap = 4; 1509 sc->sc_wdcdev.DMA_cap = 2; 1510 switch(sc->sc_pp->ide_product) { 1511 case PCI_PRODUCT_INTEL_82801AA_IDE: 1512 sc->sc_wdcdev.UDMA_cap = 4; 1513 break; 1514 case PCI_PRODUCT_INTEL_82801BA_IDE: 1515 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1516 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1517 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1518 sc->sc_wdcdev.UDMA_cap = 5; 1519 break; 1520 default: 1521 sc->sc_wdcdev.UDMA_cap = 2; 1522 } 1523 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1524 sc->sc_wdcdev.set_modes = piix_setup_channel; 1525 else 1526 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1527 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1528 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1529 1530 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1531 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1532 DEBUG_PROBE); 1533 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1534 WDCDEBUG_PRINT((", sidetim=0x%x", 1535 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1536 DEBUG_PROBE); 1537 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1538 WDCDEBUG_PRINT((", udamreg 0x%x", 1539 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1540 DEBUG_PROBE); 1541 } 1542 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1543 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1544 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1545 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1548 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1549 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1550 DEBUG_PROBE); 1551 } 1552 1553 } 1554 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1555 1556 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1557 cp = &sc->pciide_channels[channel]; 1558 /* PIIX is compat-only */ 1559 if (pciide_chansetup(sc, channel, 0) == 0) 1560 continue; 1561 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1562 if ((PIIX_IDETIM_READ(idetim, channel) & 1563 PIIX_IDETIM_IDE) == 0) { 1564 printf("%s: %s channel ignored (disabled)\n", 1565 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1566 continue; 1567 } 1568 /* PIIX are compat-only pciide devices */ 1569 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1570 if (cp->hw_ok == 0) 1571 continue; 1572 if (pciide_chan_candisable(cp)) { 1573 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1574 channel); 1575 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1576 idetim); 1577 } 1578 pciide_map_compat_intr(pa, cp, channel, 0); 1579 if (cp->hw_ok == 0) 1580 continue; 1581 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1582 } 1583 1584 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1585 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1586 DEBUG_PROBE); 1587 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1588 WDCDEBUG_PRINT((", sidetim=0x%x", 1589 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1590 DEBUG_PROBE); 1591 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1592 WDCDEBUG_PRINT((", udamreg 0x%x", 1593 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1594 DEBUG_PROBE); 1595 } 1596 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1597 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1598 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1599 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1600 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1601 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1602 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1603 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1604 DEBUG_PROBE); 1605 } 1606 } 1607 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1608 } 1609 1610 void 1611 piix_setup_channel(chp) 1612 struct channel_softc *chp; 1613 { 1614 u_int8_t mode[2], drive; 1615 u_int32_t oidetim, idetim, idedma_ctl; 1616 struct pciide_channel *cp = (struct pciide_channel*)chp; 1617 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1618 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1619 1620 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1621 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1622 idedma_ctl = 0; 1623 1624 /* set up new idetim: Enable IDE registers decode */ 1625 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1626 chp->channel); 1627 1628 /* setup DMA */ 1629 pciide_channel_dma_setup(cp); 1630 1631 /* 1632 * Here we have to mess up with drives mode: PIIX can't have 1633 * different timings for master and slave drives. 1634 * We need to find the best combination. 1635 */ 1636 1637 /* If both drives supports DMA, take the lower mode */ 1638 if ((drvp[0].drive_flags & DRIVE_DMA) && 1639 (drvp[1].drive_flags & DRIVE_DMA)) { 1640 mode[0] = mode[1] = 1641 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1642 drvp[0].DMA_mode = mode[0]; 1643 drvp[1].DMA_mode = mode[1]; 1644 goto ok; 1645 } 1646 /* 1647 * If only one drive supports DMA, use its mode, and 1648 * put the other one in PIO mode 0 if mode not compatible 1649 */ 1650 if (drvp[0].drive_flags & DRIVE_DMA) { 1651 mode[0] = drvp[0].DMA_mode; 1652 mode[1] = drvp[1].PIO_mode; 1653 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1654 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1655 mode[1] = drvp[1].PIO_mode = 0; 1656 goto ok; 1657 } 1658 if (drvp[1].drive_flags & DRIVE_DMA) { 1659 mode[1] = drvp[1].DMA_mode; 1660 mode[0] = drvp[0].PIO_mode; 1661 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1662 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1663 mode[0] = drvp[0].PIO_mode = 0; 1664 goto ok; 1665 } 1666 /* 1667 * If both drives are not DMA, takes the lower mode, unless 1668 * one of them is PIO mode < 2 1669 */ 1670 if (drvp[0].PIO_mode < 2) { 1671 mode[0] = drvp[0].PIO_mode = 0; 1672 mode[1] = drvp[1].PIO_mode; 1673 } else if (drvp[1].PIO_mode < 2) { 1674 mode[1] = drvp[1].PIO_mode = 0; 1675 mode[0] = drvp[0].PIO_mode; 1676 } else { 1677 mode[0] = mode[1] = 1678 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1679 drvp[0].PIO_mode = mode[0]; 1680 drvp[1].PIO_mode = mode[1]; 1681 } 1682 ok: /* The modes are setup */ 1683 for (drive = 0; drive < 2; drive++) { 1684 if (drvp[drive].drive_flags & DRIVE_DMA) { 1685 idetim |= piix_setup_idetim_timings( 1686 mode[drive], 1, chp->channel); 1687 goto end; 1688 } 1689 } 1690 /* If we are there, none of the drives are DMA */ 1691 if (mode[0] >= 2) 1692 idetim |= piix_setup_idetim_timings( 1693 mode[0], 0, chp->channel); 1694 else 1695 idetim |= piix_setup_idetim_timings( 1696 mode[1], 0, chp->channel); 1697 end: /* 1698 * timing mode is now set up in the controller. Enable 1699 * it per-drive 1700 */ 1701 for (drive = 0; drive < 2; drive++) { 1702 /* If no drive, skip */ 1703 if ((drvp[drive].drive_flags & DRIVE) == 0) 1704 continue; 1705 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1706 if (drvp[drive].drive_flags & DRIVE_DMA) 1707 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1708 } 1709 if (idedma_ctl != 0) { 1710 /* Add software bits in status register */ 1711 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1712 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1713 idedma_ctl); 1714 } 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1716 pciide_print_modes(cp); 1717 } 1718 1719 void 1720 piix3_4_setup_channel(chp) 1721 struct channel_softc *chp; 1722 { 1723 struct ata_drive_datas *drvp; 1724 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1725 struct pciide_channel *cp = (struct pciide_channel*)chp; 1726 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1727 int drive; 1728 int channel = chp->channel; 1729 1730 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1731 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1732 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1733 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1734 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1735 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1736 PIIX_SIDETIM_RTC_MASK(channel)); 1737 1738 idedma_ctl = 0; 1739 /* If channel disabled, no need to go further */ 1740 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1741 return; 1742 /* set up new idetim: Enable IDE registers decode */ 1743 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1744 1745 /* setup DMA if needed */ 1746 pciide_channel_dma_setup(cp); 1747 1748 for (drive = 0; drive < 2; drive++) { 1749 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1750 PIIX_UDMATIM_SET(0x3, channel, drive)); 1751 drvp = &chp->ch_drive[drive]; 1752 /* If no drive, skip */ 1753 if ((drvp->drive_flags & DRIVE) == 0) 1754 continue; 1755 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1756 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1757 goto pio; 1758 1759 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1760 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1761 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1762 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1763 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1764 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1765 ideconf |= PIIX_CONFIG_PINGPONG; 1766 } 1767 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1768 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1769 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1770 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1771 /* setup Ultra/100 */ 1772 if (drvp->UDMA_mode > 2 && 1773 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1774 drvp->UDMA_mode = 2; 1775 if (drvp->UDMA_mode > 4) { 1776 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1777 } else { 1778 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1779 if (drvp->UDMA_mode > 2) { 1780 ideconf |= PIIX_CONFIG_UDMA66(channel, 1781 drive); 1782 } else { 1783 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1784 drive); 1785 } 1786 } 1787 } 1788 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1789 /* setup Ultra/66 */ 1790 if (drvp->UDMA_mode > 2 && 1791 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1792 drvp->UDMA_mode = 2; 1793 if (drvp->UDMA_mode > 2) 1794 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1795 else 1796 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1797 } 1798 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1799 (drvp->drive_flags & DRIVE_UDMA)) { 1800 /* use Ultra/DMA */ 1801 drvp->drive_flags &= ~DRIVE_DMA; 1802 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1803 udmareg |= PIIX_UDMATIM_SET( 1804 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1805 } else { 1806 /* use Multiword DMA */ 1807 drvp->drive_flags &= ~DRIVE_UDMA; 1808 if (drive == 0) { 1809 idetim |= piix_setup_idetim_timings( 1810 drvp->DMA_mode, 1, channel); 1811 } else { 1812 sidetim |= piix_setup_sidetim_timings( 1813 drvp->DMA_mode, 1, channel); 1814 idetim =PIIX_IDETIM_SET(idetim, 1815 PIIX_IDETIM_SITRE, channel); 1816 } 1817 } 1818 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1819 1820 pio: /* use PIO mode */ 1821 idetim |= piix_setup_idetim_drvs(drvp); 1822 if (drive == 0) { 1823 idetim |= piix_setup_idetim_timings( 1824 drvp->PIO_mode, 0, channel); 1825 } else { 1826 sidetim |= piix_setup_sidetim_timings( 1827 drvp->PIO_mode, 0, channel); 1828 idetim =PIIX_IDETIM_SET(idetim, 1829 PIIX_IDETIM_SITRE, channel); 1830 } 1831 } 1832 if (idedma_ctl != 0) { 1833 /* Add software bits in status register */ 1834 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1835 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1836 idedma_ctl); 1837 } 1838 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1839 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1840 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1841 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1842 pciide_print_modes(cp); 1843 } 1844 1845 1846 /* setup ISP and RTC fields, based on mode */ 1847 static u_int32_t 1848 piix_setup_idetim_timings(mode, dma, channel) 1849 u_int8_t mode; 1850 u_int8_t dma; 1851 u_int8_t channel; 1852 { 1853 1854 if (dma) 1855 return PIIX_IDETIM_SET(0, 1856 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1857 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1858 channel); 1859 else 1860 return PIIX_IDETIM_SET(0, 1861 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1862 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1863 channel); 1864 } 1865 1866 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1867 static u_int32_t 1868 piix_setup_idetim_drvs(drvp) 1869 struct ata_drive_datas *drvp; 1870 { 1871 u_int32_t ret = 0; 1872 struct channel_softc *chp = drvp->chnl_softc; 1873 u_int8_t channel = chp->channel; 1874 u_int8_t drive = drvp->drive; 1875 1876 /* 1877 * If drive is using UDMA, timings setups are independant 1878 * So just check DMA and PIO here. 1879 */ 1880 if (drvp->drive_flags & DRIVE_DMA) { 1881 /* if mode = DMA mode 0, use compatible timings */ 1882 if ((drvp->drive_flags & DRIVE_DMA) && 1883 drvp->DMA_mode == 0) { 1884 drvp->PIO_mode = 0; 1885 return ret; 1886 } 1887 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1888 /* 1889 * PIO and DMA timings are the same, use fast timings for PIO 1890 * too, else use compat timings. 1891 */ 1892 if ((piix_isp_pio[drvp->PIO_mode] != 1893 piix_isp_dma[drvp->DMA_mode]) || 1894 (piix_rtc_pio[drvp->PIO_mode] != 1895 piix_rtc_dma[drvp->DMA_mode])) 1896 drvp->PIO_mode = 0; 1897 /* if PIO mode <= 2, use compat timings for PIO */ 1898 if (drvp->PIO_mode <= 2) { 1899 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1900 channel); 1901 return ret; 1902 } 1903 } 1904 1905 /* 1906 * Now setup PIO modes. If mode < 2, use compat timings. 1907 * Else enable fast timings. Enable IORDY and prefetch/post 1908 * if PIO mode >= 3. 1909 */ 1910 1911 if (drvp->PIO_mode < 2) 1912 return ret; 1913 1914 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1915 if (drvp->PIO_mode >= 3) { 1916 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1917 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1918 } 1919 return ret; 1920 } 1921 1922 /* setup values in SIDETIM registers, based on mode */ 1923 static u_int32_t 1924 piix_setup_sidetim_timings(mode, dma, channel) 1925 u_int8_t mode; 1926 u_int8_t dma; 1927 u_int8_t channel; 1928 { 1929 if (dma) 1930 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1931 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1932 else 1933 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1934 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1935 } 1936 1937 void 1938 amd7x6_chip_map(sc, pa) 1939 struct pciide_softc *sc; 1940 struct pci_attach_args *pa; 1941 { 1942 struct pciide_channel *cp; 1943 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1944 int channel; 1945 pcireg_t chanenable; 1946 bus_size_t cmdsize, ctlsize; 1947 1948 if (pciide_chipen(sc, pa) == 0) 1949 return; 1950 printf("%s: bus-master DMA support present", 1951 sc->sc_wdcdev.sc_dev.dv_xname); 1952 pciide_mapreg_dma(sc, pa); 1953 printf("\n"); 1954 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1955 WDC_CAPABILITY_MODE; 1956 if (sc->sc_dma_ok) { 1957 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1958 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1959 sc->sc_wdcdev.irqack = pciide_irqack; 1960 } 1961 sc->sc_wdcdev.PIO_cap = 4; 1962 sc->sc_wdcdev.DMA_cap = 2; 1963 1964 switch (sc->sc_pp->ide_product) { 1965 case PCI_PRODUCT_AMD_PBC766_IDE: 1966 case PCI_PRODUCT_AMD_PBC768_IDE: 1967 sc->sc_wdcdev.UDMA_cap = 5; 1968 break; 1969 default: 1970 sc->sc_wdcdev.UDMA_cap = 4; 1971 } 1972 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1973 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1974 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1975 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1976 1977 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1978 DEBUG_PROBE); 1979 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1980 cp = &sc->pciide_channels[channel]; 1981 if (pciide_chansetup(sc, channel, interface) == 0) 1982 continue; 1983 1984 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1985 printf("%s: %s channel ignored (disabled)\n", 1986 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1987 continue; 1988 } 1989 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1990 pciide_pci_intr); 1991 1992 if (pciide_chan_candisable(cp)) 1993 chanenable &= ~AMD7X6_CHAN_EN(channel); 1994 pciide_map_compat_intr(pa, cp, channel, interface); 1995 if (cp->hw_ok == 0) 1996 continue; 1997 1998 amd7x6_setup_channel(&cp->wdc_channel); 1999 } 2000 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2001 chanenable); 2002 return; 2003 } 2004 2005 void 2006 amd7x6_setup_channel(chp) 2007 struct channel_softc *chp; 2008 { 2009 u_int32_t udmatim_reg, datatim_reg; 2010 u_int8_t idedma_ctl; 2011 int mode, drive; 2012 struct ata_drive_datas *drvp; 2013 struct pciide_channel *cp = (struct pciide_channel*)chp; 2014 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2015 #ifndef PCIIDE_AMD756_ENABLEDMA 2016 int rev = PCI_REVISION( 2017 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2018 #endif 2019 2020 idedma_ctl = 0; 2021 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2022 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2023 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2024 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2025 2026 /* setup DMA if needed */ 2027 pciide_channel_dma_setup(cp); 2028 2029 for (drive = 0; drive < 2; drive++) { 2030 drvp = &chp->ch_drive[drive]; 2031 /* If no drive, skip */ 2032 if ((drvp->drive_flags & DRIVE) == 0) 2033 continue; 2034 /* add timing values, setup DMA if needed */ 2035 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2036 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2037 mode = drvp->PIO_mode; 2038 goto pio; 2039 } 2040 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2041 (drvp->drive_flags & DRIVE_UDMA)) { 2042 /* use Ultra/DMA */ 2043 drvp->drive_flags &= ~DRIVE_DMA; 2044 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2045 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2046 AMD7X6_UDMA_TIME(chp->channel, drive, 2047 amd7x6_udma_tim[drvp->UDMA_mode]); 2048 /* can use PIO timings, MW DMA unused */ 2049 mode = drvp->PIO_mode; 2050 } else { 2051 /* use Multiword DMA, but only if revision is OK */ 2052 drvp->drive_flags &= ~DRIVE_UDMA; 2053 #ifndef PCIIDE_AMD756_ENABLEDMA 2054 /* 2055 * The workaround doesn't seem to be necessary 2056 * with all drives, so it can be disabled by 2057 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2058 * triggered. 2059 */ 2060 if (sc->sc_pp->ide_product == 2061 PCI_PRODUCT_AMD_PBC756_IDE && 2062 AMD756_CHIPREV_DISABLEDMA(rev)) { 2063 printf("%s:%d:%d: multi-word DMA disabled due " 2064 "to chip revision\n", 2065 sc->sc_wdcdev.sc_dev.dv_xname, 2066 chp->channel, drive); 2067 mode = drvp->PIO_mode; 2068 drvp->drive_flags &= ~DRIVE_DMA; 2069 goto pio; 2070 } 2071 #endif 2072 /* mode = min(pio, dma+2) */ 2073 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2074 mode = drvp->PIO_mode; 2075 else 2076 mode = drvp->DMA_mode + 2; 2077 } 2078 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2079 2080 pio: /* setup PIO mode */ 2081 if (mode <= 2) { 2082 drvp->DMA_mode = 0; 2083 drvp->PIO_mode = 0; 2084 mode = 0; 2085 } else { 2086 drvp->PIO_mode = mode; 2087 drvp->DMA_mode = mode - 2; 2088 } 2089 datatim_reg |= 2090 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2091 amd7x6_pio_set[mode]) | 2092 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2093 amd7x6_pio_rec[mode]); 2094 } 2095 if (idedma_ctl != 0) { 2096 /* Add software bits in status register */ 2097 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2098 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2099 idedma_ctl); 2100 } 2101 pciide_print_modes(cp); 2102 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2103 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2104 } 2105 2106 void 2107 apollo_chip_map(sc, pa) 2108 struct pciide_softc *sc; 2109 struct pci_attach_args *pa; 2110 { 2111 struct pciide_channel *cp; 2112 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2113 int channel; 2114 u_int32_t ideconf; 2115 bus_size_t cmdsize, ctlsize; 2116 pcitag_t pcib_tag; 2117 pcireg_t pcib_id, pcib_class; 2118 2119 if (pciide_chipen(sc, pa) == 0) 2120 return; 2121 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2122 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2123 /* and read ID and rev of the ISA bridge */ 2124 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2125 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2126 printf(": VIA Technologies "); 2127 switch (PCI_PRODUCT(pcib_id)) { 2128 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2129 printf("VT82C586 (Apollo VP) "); 2130 if(PCI_REVISION(pcib_class) >= 0x02) { 2131 printf("ATA33 controller\n"); 2132 sc->sc_wdcdev.UDMA_cap = 2; 2133 } else { 2134 printf("controller\n"); 2135 sc->sc_wdcdev.UDMA_cap = 0; 2136 } 2137 break; 2138 case PCI_PRODUCT_VIATECH_VT82C596A: 2139 printf("VT82C596A (Apollo Pro) "); 2140 if (PCI_REVISION(pcib_class) >= 0x12) { 2141 printf("ATA66 controller\n"); 2142 sc->sc_wdcdev.UDMA_cap = 4; 2143 } else { 2144 printf("ATA33 controller\n"); 2145 sc->sc_wdcdev.UDMA_cap = 2; 2146 } 2147 break; 2148 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2149 printf("VT82C686A (Apollo KX133) "); 2150 if (PCI_REVISION(pcib_class) >= 0x40) { 2151 printf("ATA100 controller\n"); 2152 sc->sc_wdcdev.UDMA_cap = 5; 2153 } else { 2154 printf("ATA66 controller\n"); 2155 sc->sc_wdcdev.UDMA_cap = 4; 2156 } 2157 break; 2158 case PCI_PRODUCT_VIATECH_VT8233: 2159 printf("VT8233 ATA100 controller\n"); 2160 sc->sc_wdcdev.UDMA_cap = 5; 2161 break; 2162 default: 2163 printf("unknown ATA controller\n"); 2164 sc->sc_wdcdev.UDMA_cap = 0; 2165 } 2166 2167 printf("%s: bus-master DMA support present", 2168 sc->sc_wdcdev.sc_dev.dv_xname); 2169 pciide_mapreg_dma(sc, pa); 2170 printf("\n"); 2171 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2172 WDC_CAPABILITY_MODE; 2173 if (sc->sc_dma_ok) { 2174 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2175 sc->sc_wdcdev.irqack = pciide_irqack; 2176 if (sc->sc_wdcdev.UDMA_cap > 0) 2177 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2178 } 2179 sc->sc_wdcdev.PIO_cap = 4; 2180 sc->sc_wdcdev.DMA_cap = 2; 2181 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2182 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2183 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2184 2185 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2186 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2187 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2188 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2189 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2190 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2191 DEBUG_PROBE); 2192 2193 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2194 cp = &sc->pciide_channels[channel]; 2195 if (pciide_chansetup(sc, channel, interface) == 0) 2196 continue; 2197 2198 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2199 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2200 printf("%s: %s channel ignored (disabled)\n", 2201 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2202 continue; 2203 } 2204 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2205 pciide_pci_intr); 2206 if (cp->hw_ok == 0) 2207 continue; 2208 if (pciide_chan_candisable(cp)) { 2209 ideconf &= ~APO_IDECONF_EN(channel); 2210 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2211 ideconf); 2212 } 2213 pciide_map_compat_intr(pa, cp, channel, interface); 2214 2215 if (cp->hw_ok == 0) 2216 continue; 2217 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2218 } 2219 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2220 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2221 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2222 } 2223 2224 void 2225 apollo_setup_channel(chp) 2226 struct channel_softc *chp; 2227 { 2228 u_int32_t udmatim_reg, datatim_reg; 2229 u_int8_t idedma_ctl; 2230 int mode, drive; 2231 struct ata_drive_datas *drvp; 2232 struct pciide_channel *cp = (struct pciide_channel*)chp; 2233 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2234 2235 idedma_ctl = 0; 2236 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2237 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2238 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2239 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2240 2241 /* setup DMA if needed */ 2242 pciide_channel_dma_setup(cp); 2243 2244 for (drive = 0; drive < 2; drive++) { 2245 drvp = &chp->ch_drive[drive]; 2246 /* If no drive, skip */ 2247 if ((drvp->drive_flags & DRIVE) == 0) 2248 continue; 2249 /* add timing values, setup DMA if needed */ 2250 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2251 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2252 mode = drvp->PIO_mode; 2253 goto pio; 2254 } 2255 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2256 (drvp->drive_flags & DRIVE_UDMA)) { 2257 /* use Ultra/DMA */ 2258 drvp->drive_flags &= ~DRIVE_DMA; 2259 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2260 APO_UDMA_EN_MTH(chp->channel, drive); 2261 if (sc->sc_wdcdev.UDMA_cap == 5) { 2262 /* 686b */ 2263 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2264 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2265 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2266 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2267 /* 596b or 686a */ 2268 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2269 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2270 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2271 } else { 2272 /* 596a or 586b */ 2273 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2274 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2275 } 2276 /* can use PIO timings, MW DMA unused */ 2277 mode = drvp->PIO_mode; 2278 } else { 2279 /* use Multiword DMA */ 2280 drvp->drive_flags &= ~DRIVE_UDMA; 2281 /* mode = min(pio, dma+2) */ 2282 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2283 mode = drvp->PIO_mode; 2284 else 2285 mode = drvp->DMA_mode + 2; 2286 } 2287 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2288 2289 pio: /* setup PIO mode */ 2290 if (mode <= 2) { 2291 drvp->DMA_mode = 0; 2292 drvp->PIO_mode = 0; 2293 mode = 0; 2294 } else { 2295 drvp->PIO_mode = mode; 2296 drvp->DMA_mode = mode - 2; 2297 } 2298 datatim_reg |= 2299 APO_DATATIM_PULSE(chp->channel, drive, 2300 apollo_pio_set[mode]) | 2301 APO_DATATIM_RECOV(chp->channel, drive, 2302 apollo_pio_rec[mode]); 2303 } 2304 if (idedma_ctl != 0) { 2305 /* Add software bits in status register */ 2306 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2307 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2308 idedma_ctl); 2309 } 2310 pciide_print_modes(cp); 2311 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2312 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2313 } 2314 2315 void 2316 cmd_channel_map(pa, sc, channel) 2317 struct pci_attach_args *pa; 2318 struct pciide_softc *sc; 2319 int channel; 2320 { 2321 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2322 bus_size_t cmdsize, ctlsize; 2323 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2324 int interface, one_channel; 2325 2326 /* 2327 * The 0648/0649 can be told to identify as a RAID controller. 2328 * In this case, we have to fake interface 2329 */ 2330 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2331 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2332 PCIIDE_INTERFACE_SETTABLE(1); 2333 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2334 CMD_CONF_DSA1) 2335 interface |= PCIIDE_INTERFACE_PCI(0) | 2336 PCIIDE_INTERFACE_PCI(1); 2337 } else { 2338 interface = PCI_INTERFACE(pa->pa_class); 2339 } 2340 2341 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2342 cp->name = PCIIDE_CHANNEL_NAME(channel); 2343 cp->wdc_channel.channel = channel; 2344 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2345 2346 /* 2347 * Older CMD64X doesn't have independant channels 2348 */ 2349 switch (sc->sc_pp->ide_product) { 2350 case PCI_PRODUCT_CMDTECH_649: 2351 one_channel = 0; 2352 break; 2353 default: 2354 one_channel = 1; 2355 break; 2356 } 2357 2358 if (channel > 0 && one_channel) { 2359 cp->wdc_channel.ch_queue = 2360 sc->pciide_channels[0].wdc_channel.ch_queue; 2361 } else { 2362 cp->wdc_channel.ch_queue = 2363 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2364 } 2365 if (cp->wdc_channel.ch_queue == NULL) { 2366 printf("%s %s channel: " 2367 "can't allocate memory for command queue", 2368 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2369 return; 2370 } 2371 2372 printf("%s: %s channel %s to %s mode\n", 2373 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2374 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2375 "configured" : "wired", 2376 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2377 "native-PCI" : "compatibility"); 2378 2379 /* 2380 * with a CMD PCI64x, if we get here, the first channel is enabled: 2381 * there's no way to disable the first channel without disabling 2382 * the whole device 2383 */ 2384 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2385 printf("%s: %s channel ignored (disabled)\n", 2386 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2387 return; 2388 } 2389 2390 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2391 if (cp->hw_ok == 0) 2392 return; 2393 if (channel == 1) { 2394 if (pciide_chan_candisable(cp)) { 2395 ctrl &= ~CMD_CTRL_2PORT; 2396 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2397 CMD_CTRL, ctrl); 2398 } 2399 } 2400 pciide_map_compat_intr(pa, cp, channel, interface); 2401 } 2402 2403 int 2404 cmd_pci_intr(arg) 2405 void *arg; 2406 { 2407 struct pciide_softc *sc = arg; 2408 struct pciide_channel *cp; 2409 struct channel_softc *wdc_cp; 2410 int i, rv, crv; 2411 u_int32_t priirq, secirq; 2412 2413 rv = 0; 2414 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2415 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2416 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2417 cp = &sc->pciide_channels[i]; 2418 wdc_cp = &cp->wdc_channel; 2419 /* If a compat channel skip. */ 2420 if (cp->compat) 2421 continue; 2422 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2423 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2424 crv = wdcintr(wdc_cp); 2425 if (crv == 0) 2426 printf("%s:%d: bogus intr\n", 2427 sc->sc_wdcdev.sc_dev.dv_xname, i); 2428 else 2429 rv = 1; 2430 } 2431 } 2432 return rv; 2433 } 2434 2435 void 2436 cmd_chip_map(sc, pa) 2437 struct pciide_softc *sc; 2438 struct pci_attach_args *pa; 2439 { 2440 int channel; 2441 2442 /* 2443 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2444 * and base adresses registers can be disabled at 2445 * hardware level. In this case, the device is wired 2446 * in compat mode and its first channel is always enabled, 2447 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2448 * In fact, it seems that the first channel of the CMD PCI0640 2449 * can't be disabled. 2450 */ 2451 2452 #ifdef PCIIDE_CMD064x_DISABLE 2453 if (pciide_chipen(sc, pa) == 0) 2454 return; 2455 #endif 2456 2457 printf("%s: hardware does not support DMA\n", 2458 sc->sc_wdcdev.sc_dev.dv_xname); 2459 sc->sc_dma_ok = 0; 2460 2461 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2462 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2463 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2464 2465 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2466 cmd_channel_map(pa, sc, channel); 2467 } 2468 } 2469 2470 void 2471 cmd0643_9_chip_map(sc, pa) 2472 struct pciide_softc *sc; 2473 struct pci_attach_args *pa; 2474 { 2475 struct pciide_channel *cp; 2476 int channel; 2477 int rev = PCI_REVISION( 2478 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2479 2480 /* 2481 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2482 * and base adresses registers can be disabled at 2483 * hardware level. In this case, the device is wired 2484 * in compat mode and its first channel is always enabled, 2485 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2486 * In fact, it seems that the first channel of the CMD PCI0640 2487 * can't be disabled. 2488 */ 2489 2490 #ifdef PCIIDE_CMD064x_DISABLE 2491 if (pciide_chipen(sc, pa) == 0) 2492 return; 2493 #endif 2494 printf("%s: bus-master DMA support present", 2495 sc->sc_wdcdev.sc_dev.dv_xname); 2496 pciide_mapreg_dma(sc, pa); 2497 printf("\n"); 2498 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2499 WDC_CAPABILITY_MODE; 2500 if (sc->sc_dma_ok) { 2501 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2502 switch (sc->sc_pp->ide_product) { 2503 case PCI_PRODUCT_CMDTECH_649: 2504 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2505 sc->sc_wdcdev.UDMA_cap = 5; 2506 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2507 break; 2508 case PCI_PRODUCT_CMDTECH_648: 2509 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2510 sc->sc_wdcdev.UDMA_cap = 4; 2511 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2512 break; 2513 case PCI_PRODUCT_CMDTECH_646: 2514 if (rev >= CMD0646U2_REV) { 2515 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2516 sc->sc_wdcdev.UDMA_cap = 2; 2517 } else if (rev >= CMD0646U_REV) { 2518 /* 2519 * Linux's driver claims that the 646U is broken 2520 * with UDMA. Only enable it if we know what we're 2521 * doing 2522 */ 2523 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2524 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2525 sc->sc_wdcdev.UDMA_cap = 2; 2526 #endif 2527 /* explicitly disable UDMA */ 2528 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2529 CMD_UDMATIM(0), 0); 2530 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2531 CMD_UDMATIM(1), 0); 2532 } 2533 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2534 break; 2535 default: 2536 sc->sc_wdcdev.irqack = pciide_irqack; 2537 } 2538 } 2539 2540 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2541 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2542 sc->sc_wdcdev.PIO_cap = 4; 2543 sc->sc_wdcdev.DMA_cap = 2; 2544 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2545 2546 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2547 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2548 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2549 DEBUG_PROBE); 2550 2551 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2552 cp = &sc->pciide_channels[channel]; 2553 cmd_channel_map(pa, sc, channel); 2554 if (cp->hw_ok == 0) 2555 continue; 2556 cmd0643_9_setup_channel(&cp->wdc_channel); 2557 } 2558 /* 2559 * note - this also makes sure we clear the irq disable and reset 2560 * bits 2561 */ 2562 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2563 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2564 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2565 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2566 DEBUG_PROBE); 2567 } 2568 2569 void 2570 cmd0643_9_setup_channel(chp) 2571 struct channel_softc *chp; 2572 { 2573 struct ata_drive_datas *drvp; 2574 u_int8_t tim; 2575 u_int32_t idedma_ctl, udma_reg; 2576 int drive; 2577 struct pciide_channel *cp = (struct pciide_channel*)chp; 2578 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2579 2580 idedma_ctl = 0; 2581 /* setup DMA if needed */ 2582 pciide_channel_dma_setup(cp); 2583 2584 for (drive = 0; drive < 2; drive++) { 2585 drvp = &chp->ch_drive[drive]; 2586 /* If no drive, skip */ 2587 if ((drvp->drive_flags & DRIVE) == 0) 2588 continue; 2589 /* add timing values, setup DMA if needed */ 2590 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2591 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2592 if (drvp->drive_flags & DRIVE_UDMA) { 2593 /* UltraDMA on a 646U2, 0648 or 0649 */ 2594 drvp->drive_flags &= ~DRIVE_DMA; 2595 udma_reg = pciide_pci_read(sc->sc_pc, 2596 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2597 if (drvp->UDMA_mode > 2 && 2598 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2599 CMD_BICSR) & 2600 CMD_BICSR_80(chp->channel)) == 0) 2601 drvp->UDMA_mode = 2; 2602 if (drvp->UDMA_mode > 2) 2603 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2604 else if (sc->sc_wdcdev.UDMA_cap > 2) 2605 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2606 udma_reg |= CMD_UDMATIM_UDMA(drive); 2607 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2608 CMD_UDMATIM_TIM_OFF(drive)); 2609 udma_reg |= 2610 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2611 CMD_UDMATIM_TIM_OFF(drive)); 2612 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2613 CMD_UDMATIM(chp->channel), udma_reg); 2614 } else { 2615 /* 2616 * use Multiword DMA. 2617 * Timings will be used for both PIO and DMA, 2618 * so adjust DMA mode if needed 2619 * if we have a 0646U2/8/9, turn off UDMA 2620 */ 2621 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2622 udma_reg = pciide_pci_read(sc->sc_pc, 2623 sc->sc_tag, 2624 CMD_UDMATIM(chp->channel)); 2625 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2626 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2627 CMD_UDMATIM(chp->channel), 2628 udma_reg); 2629 } 2630 if (drvp->PIO_mode >= 3 && 2631 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2632 drvp->DMA_mode = drvp->PIO_mode - 2; 2633 } 2634 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2635 } 2636 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2637 } 2638 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2639 CMD_DATA_TIM(chp->channel, drive), tim); 2640 } 2641 if (idedma_ctl != 0) { 2642 /* Add software bits in status register */ 2643 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2644 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2645 idedma_ctl); 2646 } 2647 pciide_print_modes(cp); 2648 } 2649 2650 void 2651 cmd646_9_irqack(chp) 2652 struct channel_softc *chp; 2653 { 2654 u_int32_t priirq, secirq; 2655 struct pciide_channel *cp = (struct pciide_channel*)chp; 2656 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2657 2658 if (chp->channel == 0) { 2659 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2660 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2661 } else { 2662 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2663 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2664 } 2665 pciide_irqack(chp); 2666 } 2667 2668 void 2669 cy693_chip_map(sc, pa) 2670 struct pciide_softc *sc; 2671 struct pci_attach_args *pa; 2672 { 2673 struct pciide_channel *cp; 2674 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2675 bus_size_t cmdsize, ctlsize; 2676 2677 if (pciide_chipen(sc, pa) == 0) 2678 return; 2679 /* 2680 * this chip has 2 PCI IDE functions, one for primary and one for 2681 * secondary. So we need to call pciide_mapregs_compat() with 2682 * the real channel 2683 */ 2684 if (pa->pa_function == 1) { 2685 sc->sc_cy_compatchan = 0; 2686 } else if (pa->pa_function == 2) { 2687 sc->sc_cy_compatchan = 1; 2688 } else { 2689 printf("%s: unexpected PCI function %d\n", 2690 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2691 return; 2692 } 2693 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2694 printf("%s: bus-master DMA support present", 2695 sc->sc_wdcdev.sc_dev.dv_xname); 2696 pciide_mapreg_dma(sc, pa); 2697 } else { 2698 printf("%s: hardware does not support DMA", 2699 sc->sc_wdcdev.sc_dev.dv_xname); 2700 sc->sc_dma_ok = 0; 2701 } 2702 printf("\n"); 2703 2704 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2705 if (sc->sc_cy_handle == NULL) { 2706 printf("%s: unable to map hyperCache control registers\n", 2707 sc->sc_wdcdev.sc_dev.dv_xname); 2708 sc->sc_dma_ok = 0; 2709 } 2710 2711 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2712 WDC_CAPABILITY_MODE; 2713 if (sc->sc_dma_ok) { 2714 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2715 sc->sc_wdcdev.irqack = pciide_irqack; 2716 } 2717 sc->sc_wdcdev.PIO_cap = 4; 2718 sc->sc_wdcdev.DMA_cap = 2; 2719 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2720 2721 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2722 sc->sc_wdcdev.nchannels = 1; 2723 2724 /* Only one channel for this chip; if we are here it's enabled */ 2725 cp = &sc->pciide_channels[0]; 2726 sc->wdc_chanarray[0] = &cp->wdc_channel; 2727 cp->name = PCIIDE_CHANNEL_NAME(0); 2728 cp->wdc_channel.channel = 0; 2729 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2730 cp->wdc_channel.ch_queue = 2731 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2732 if (cp->wdc_channel.ch_queue == NULL) { 2733 printf("%s primary channel: " 2734 "can't allocate memory for command queue", 2735 sc->sc_wdcdev.sc_dev.dv_xname); 2736 return; 2737 } 2738 printf("%s: primary channel %s to ", 2739 sc->sc_wdcdev.sc_dev.dv_xname, 2740 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2741 "configured" : "wired"); 2742 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2743 printf("native-PCI"); 2744 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2745 pciide_pci_intr); 2746 } else { 2747 printf("compatibility"); 2748 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2749 &cmdsize, &ctlsize); 2750 } 2751 printf(" mode\n"); 2752 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2753 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2754 wdcattach(&cp->wdc_channel); 2755 if (pciide_chan_candisable(cp)) { 2756 pci_conf_write(sc->sc_pc, sc->sc_tag, 2757 PCI_COMMAND_STATUS_REG, 0); 2758 } 2759 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2760 if (cp->hw_ok == 0) 2761 return; 2762 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2763 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2764 cy693_setup_channel(&cp->wdc_channel); 2765 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2766 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2767 } 2768 2769 void 2770 cy693_setup_channel(chp) 2771 struct channel_softc *chp; 2772 { 2773 struct ata_drive_datas *drvp; 2774 int drive; 2775 u_int32_t cy_cmd_ctrl; 2776 u_int32_t idedma_ctl; 2777 struct pciide_channel *cp = (struct pciide_channel*)chp; 2778 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2779 int dma_mode = -1; 2780 2781 cy_cmd_ctrl = idedma_ctl = 0; 2782 2783 /* setup DMA if needed */ 2784 pciide_channel_dma_setup(cp); 2785 2786 for (drive = 0; drive < 2; drive++) { 2787 drvp = &chp->ch_drive[drive]; 2788 /* If no drive, skip */ 2789 if ((drvp->drive_flags & DRIVE) == 0) 2790 continue; 2791 /* add timing values, setup DMA if needed */ 2792 if (drvp->drive_flags & DRIVE_DMA) { 2793 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2794 /* use Multiword DMA */ 2795 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2796 dma_mode = drvp->DMA_mode; 2797 } 2798 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2799 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2800 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2801 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2802 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2803 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2804 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2805 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2806 } 2807 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2808 chp->ch_drive[0].DMA_mode = dma_mode; 2809 chp->ch_drive[1].DMA_mode = dma_mode; 2810 2811 if (dma_mode == -1) 2812 dma_mode = 0; 2813 2814 if (sc->sc_cy_handle != NULL) { 2815 /* Note: `multiple' is implied. */ 2816 cy82c693_write(sc->sc_cy_handle, 2817 (sc->sc_cy_compatchan == 0) ? 2818 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2819 } 2820 2821 pciide_print_modes(cp); 2822 2823 if (idedma_ctl != 0) { 2824 /* Add software bits in status register */ 2825 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2826 IDEDMA_CTL, idedma_ctl); 2827 } 2828 } 2829 2830 static int 2831 sis_hostbr_match(pa) 2832 struct pci_attach_args *pa; 2833 { 2834 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2835 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2836 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2837 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2838 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2839 } 2840 2841 void 2842 sis_chip_map(sc, pa) 2843 struct pciide_softc *sc; 2844 struct pci_attach_args *pa; 2845 { 2846 struct pciide_channel *cp; 2847 int channel; 2848 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2849 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2850 pcireg_t rev = PCI_REVISION(pa->pa_class); 2851 bus_size_t cmdsize, ctlsize; 2852 pcitag_t pchb_tag; 2853 pcireg_t pchb_id, pchb_class; 2854 2855 if (pciide_chipen(sc, pa) == 0) 2856 return; 2857 printf("%s: bus-master DMA support present", 2858 sc->sc_wdcdev.sc_dev.dv_xname); 2859 pciide_mapreg_dma(sc, pa); 2860 printf("\n"); 2861 2862 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2863 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2864 /* and read ID and rev of the ISA bridge */ 2865 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2866 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2867 2868 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2869 WDC_CAPABILITY_MODE; 2870 if (sc->sc_dma_ok) { 2871 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2872 sc->sc_wdcdev.irqack = pciide_irqack; 2873 /* 2874 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2875 * have problems with UDMA (info provided by Christos) 2876 */ 2877 if (rev >= 0xd0 && 2878 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2879 PCI_REVISION(pchb_class) >= 0x03)) 2880 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2881 } 2882 2883 sc->sc_wdcdev.PIO_cap = 4; 2884 sc->sc_wdcdev.DMA_cap = 2; 2885 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2886 /* 2887 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2888 * chipsets. 2889 */ 2890 sc->sc_wdcdev.UDMA_cap = 2891 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2892 sc->sc_wdcdev.set_modes = sis_setup_channel; 2893 2894 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2895 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2896 2897 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2898 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2899 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2900 2901 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2902 cp = &sc->pciide_channels[channel]; 2903 if (pciide_chansetup(sc, channel, interface) == 0) 2904 continue; 2905 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2906 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2907 printf("%s: %s channel ignored (disabled)\n", 2908 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2909 continue; 2910 } 2911 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2912 pciide_pci_intr); 2913 if (cp->hw_ok == 0) 2914 continue; 2915 if (pciide_chan_candisable(cp)) { 2916 if (channel == 0) 2917 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2918 else 2919 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2920 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2921 sis_ctr0); 2922 } 2923 pciide_map_compat_intr(pa, cp, channel, interface); 2924 if (cp->hw_ok == 0) 2925 continue; 2926 sis_setup_channel(&cp->wdc_channel); 2927 } 2928 } 2929 2930 void 2931 sis_setup_channel(chp) 2932 struct channel_softc *chp; 2933 { 2934 struct ata_drive_datas *drvp; 2935 int drive; 2936 u_int32_t sis_tim; 2937 u_int32_t idedma_ctl; 2938 struct pciide_channel *cp = (struct pciide_channel*)chp; 2939 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2940 2941 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2942 "channel %d 0x%x\n", chp->channel, 2943 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2944 DEBUG_PROBE); 2945 sis_tim = 0; 2946 idedma_ctl = 0; 2947 /* setup DMA if needed */ 2948 pciide_channel_dma_setup(cp); 2949 2950 for (drive = 0; drive < 2; drive++) { 2951 drvp = &chp->ch_drive[drive]; 2952 /* If no drive, skip */ 2953 if ((drvp->drive_flags & DRIVE) == 0) 2954 continue; 2955 /* add timing values, setup DMA if needed */ 2956 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2957 (drvp->drive_flags & DRIVE_UDMA) == 0) 2958 goto pio; 2959 2960 if (drvp->drive_flags & DRIVE_UDMA) { 2961 /* use Ultra/DMA */ 2962 drvp->drive_flags &= ~DRIVE_DMA; 2963 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2964 SIS_TIM_UDMA_TIME_OFF(drive); 2965 sis_tim |= SIS_TIM_UDMA_EN(drive); 2966 } else { 2967 /* 2968 * use Multiword DMA 2969 * Timings will be used for both PIO and DMA, 2970 * so adjust DMA mode if needed 2971 */ 2972 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2973 drvp->PIO_mode = drvp->DMA_mode + 2; 2974 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2975 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2976 drvp->PIO_mode - 2 : 0; 2977 if (drvp->DMA_mode == 0) 2978 drvp->PIO_mode = 0; 2979 } 2980 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2981 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2982 SIS_TIM_ACT_OFF(drive); 2983 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2984 SIS_TIM_REC_OFF(drive); 2985 } 2986 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2987 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2988 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2989 if (idedma_ctl != 0) { 2990 /* Add software bits in status register */ 2991 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2992 IDEDMA_CTL, idedma_ctl); 2993 } 2994 pciide_print_modes(cp); 2995 } 2996 2997 static int 2998 acer_isabr_match(pa) 2999 struct pci_attach_args *pa; 3000 { 3001 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 3002 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 3003 } 3004 3005 void 3006 acer_chip_map(sc, pa) 3007 struct pciide_softc *sc; 3008 struct pci_attach_args *pa; 3009 { 3010 struct pci_attach_args isa_pa; 3011 struct pciide_channel *cp; 3012 int channel; 3013 pcireg_t cr, interface; 3014 bus_size_t cmdsize, ctlsize; 3015 pcireg_t rev = PCI_REVISION(pa->pa_class); 3016 3017 if (pciide_chipen(sc, pa) == 0) 3018 return; 3019 printf("%s: bus-master DMA support present", 3020 sc->sc_wdcdev.sc_dev.dv_xname); 3021 pciide_mapreg_dma(sc, pa); 3022 printf("\n"); 3023 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3024 WDC_CAPABILITY_MODE; 3025 if (sc->sc_dma_ok) { 3026 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3027 if (rev >= 0x20) { 3028 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3029 if (rev >= 0xC4) 3030 sc->sc_wdcdev.UDMA_cap = 5; 3031 else if (rev >= 0xC2) 3032 sc->sc_wdcdev.UDMA_cap = 4; 3033 else 3034 sc->sc_wdcdev.UDMA_cap = 2; 3035 } 3036 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3037 sc->sc_wdcdev.irqack = pciide_irqack; 3038 } 3039 3040 sc->sc_wdcdev.PIO_cap = 4; 3041 sc->sc_wdcdev.DMA_cap = 2; 3042 sc->sc_wdcdev.set_modes = acer_setup_channel; 3043 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3044 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3045 3046 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3047 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3048 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3049 3050 /* Enable "microsoft register bits" R/W. */ 3051 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3052 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3053 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3054 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3055 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3056 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3057 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3058 ~ACER_CHANSTATUSREGS_RO); 3059 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3060 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3061 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3062 /* Don't use cr, re-read the real register content instead */ 3063 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3064 PCI_CLASS_REG)); 3065 3066 /* From linux: enable "Cable Detection" */ 3067 if (rev >= 0xC2) { 3068 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3069 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3070 | ACER_0x4B_CDETECT); 3071 /* set south-bridge's enable bit, m1533, 0x79 */ 3072 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 3073 printf("%s: can't find PCI/ISA bridge, downgrading " 3074 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 3075 sc->sc_wdcdev.UDMA_cap = 2; 3076 } else { 3077 if (rev == 0xC2) 3078 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3079 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3080 ACER_0x79, 3081 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3082 ACER_0x79) 3083 | ACER_0x79_REVC2_EN); 3084 else 3085 /* 1553/1535 (m1533, 0x79, bit 1) */ 3086 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3087 ACER_0x79, 3088 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3089 ACER_0x79) 3090 | ACER_0x79_EN); 3091 } 3092 } 3093 3094 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3095 cp = &sc->pciide_channels[channel]; 3096 if (pciide_chansetup(sc, channel, interface) == 0) 3097 continue; 3098 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3099 printf("%s: %s channel ignored (disabled)\n", 3100 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3101 continue; 3102 } 3103 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3104 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3105 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3106 if (cp->hw_ok == 0) 3107 continue; 3108 if (pciide_chan_candisable(cp)) { 3109 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3110 pci_conf_write(sc->sc_pc, sc->sc_tag, 3111 PCI_CLASS_REG, cr); 3112 } 3113 pciide_map_compat_intr(pa, cp, channel, interface); 3114 acer_setup_channel(&cp->wdc_channel); 3115 } 3116 } 3117 3118 void 3119 acer_setup_channel(chp) 3120 struct channel_softc *chp; 3121 { 3122 struct ata_drive_datas *drvp; 3123 int drive; 3124 u_int32_t acer_fifo_udma; 3125 u_int32_t idedma_ctl; 3126 struct pciide_channel *cp = (struct pciide_channel*)chp; 3127 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3128 3129 idedma_ctl = 0; 3130 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3131 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3132 acer_fifo_udma), DEBUG_PROBE); 3133 /* setup DMA if needed */ 3134 pciide_channel_dma_setup(cp); 3135 3136 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3137 DRIVE_UDMA) { /* check 80 pins cable */ 3138 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3139 ACER_0x4A_80PIN(chp->channel)) { 3140 if (chp->ch_drive[0].UDMA_mode > 2) 3141 chp->ch_drive[0].UDMA_mode = 2; 3142 if (chp->ch_drive[1].UDMA_mode > 2) 3143 chp->ch_drive[1].UDMA_mode = 2; 3144 } 3145 } 3146 3147 for (drive = 0; drive < 2; drive++) { 3148 drvp = &chp->ch_drive[drive]; 3149 /* If no drive, skip */ 3150 if ((drvp->drive_flags & DRIVE) == 0) 3151 continue; 3152 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3153 "channel %d drive %d 0x%x\n", chp->channel, drive, 3154 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3155 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3156 /* clear FIFO/DMA mode */ 3157 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3158 ACER_UDMA_EN(chp->channel, drive) | 3159 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3160 3161 /* add timing values, setup DMA if needed */ 3162 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3163 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3164 acer_fifo_udma |= 3165 ACER_FTH_OPL(chp->channel, drive, 0x1); 3166 goto pio; 3167 } 3168 3169 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3170 if (drvp->drive_flags & DRIVE_UDMA) { 3171 /* use Ultra/DMA */ 3172 drvp->drive_flags &= ~DRIVE_DMA; 3173 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3174 acer_fifo_udma |= 3175 ACER_UDMA_TIM(chp->channel, drive, 3176 acer_udma[drvp->UDMA_mode]); 3177 /* XXX disable if one drive < UDMA3 ? */ 3178 if (drvp->UDMA_mode >= 3) { 3179 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3180 ACER_0x4B, 3181 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3182 ACER_0x4B) | ACER_0x4B_UDMA66); 3183 } 3184 } else { 3185 /* 3186 * use Multiword DMA 3187 * Timings will be used for both PIO and DMA, 3188 * so adjust DMA mode if needed 3189 */ 3190 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3191 drvp->PIO_mode = drvp->DMA_mode + 2; 3192 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3193 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3194 drvp->PIO_mode - 2 : 0; 3195 if (drvp->DMA_mode == 0) 3196 drvp->PIO_mode = 0; 3197 } 3198 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3199 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3200 ACER_IDETIM(chp->channel, drive), 3201 acer_pio[drvp->PIO_mode]); 3202 } 3203 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3204 acer_fifo_udma), DEBUG_PROBE); 3205 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3206 if (idedma_ctl != 0) { 3207 /* Add software bits in status register */ 3208 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3209 IDEDMA_CTL, idedma_ctl); 3210 } 3211 pciide_print_modes(cp); 3212 } 3213 3214 int 3215 acer_pci_intr(arg) 3216 void *arg; 3217 { 3218 struct pciide_softc *sc = arg; 3219 struct pciide_channel *cp; 3220 struct channel_softc *wdc_cp; 3221 int i, rv, crv; 3222 u_int32_t chids; 3223 3224 rv = 0; 3225 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3226 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3227 cp = &sc->pciide_channels[i]; 3228 wdc_cp = &cp->wdc_channel; 3229 /* If a compat channel skip. */ 3230 if (cp->compat) 3231 continue; 3232 if (chids & ACER_CHIDS_INT(i)) { 3233 crv = wdcintr(wdc_cp); 3234 if (crv == 0) 3235 printf("%s:%d: bogus intr\n", 3236 sc->sc_wdcdev.sc_dev.dv_xname, i); 3237 else 3238 rv = 1; 3239 } 3240 } 3241 return rv; 3242 } 3243 3244 void 3245 hpt_chip_map(sc, pa) 3246 struct pciide_softc *sc; 3247 struct pci_attach_args *pa; 3248 { 3249 struct pciide_channel *cp; 3250 int i, compatchan, revision; 3251 pcireg_t interface; 3252 bus_size_t cmdsize, ctlsize; 3253 3254 if (pciide_chipen(sc, pa) == 0) 3255 return; 3256 revision = PCI_REVISION(pa->pa_class); 3257 printf(": Triones/Highpoint "); 3258 if (revision == HPT370_REV) 3259 printf("HPT370 IDE Controller\n"); 3260 else if (revision == HPT370A_REV) 3261 printf("HPT370A IDE Controller\n"); 3262 else if (revision == HPT366_REV) 3263 printf("HPT366 IDE Controller\n"); 3264 else 3265 printf("unknown HPT IDE controller rev %d\n", revision); 3266 3267 /* 3268 * when the chip is in native mode it identifies itself as a 3269 * 'misc mass storage'. Fake interface in this case. 3270 */ 3271 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3272 interface = PCI_INTERFACE(pa->pa_class); 3273 } else { 3274 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3275 PCIIDE_INTERFACE_PCI(0); 3276 if (revision == HPT370_REV || revision == HPT370A_REV) 3277 interface |= PCIIDE_INTERFACE_PCI(1); 3278 } 3279 3280 printf("%s: bus-master DMA support present", 3281 sc->sc_wdcdev.sc_dev.dv_xname); 3282 pciide_mapreg_dma(sc, pa); 3283 printf("\n"); 3284 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3285 WDC_CAPABILITY_MODE; 3286 if (sc->sc_dma_ok) { 3287 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3288 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3289 sc->sc_wdcdev.irqack = pciide_irqack; 3290 } 3291 sc->sc_wdcdev.PIO_cap = 4; 3292 sc->sc_wdcdev.DMA_cap = 2; 3293 3294 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3295 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3296 if (revision == HPT366_REV) { 3297 sc->sc_wdcdev.UDMA_cap = 4; 3298 /* 3299 * The 366 has 2 PCI IDE functions, one for primary and one 3300 * for secondary. So we need to call pciide_mapregs_compat() 3301 * with the real channel 3302 */ 3303 if (pa->pa_function == 0) { 3304 compatchan = 0; 3305 } else if (pa->pa_function == 1) { 3306 compatchan = 1; 3307 } else { 3308 printf("%s: unexpected PCI function %d\n", 3309 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3310 return; 3311 } 3312 sc->sc_wdcdev.nchannels = 1; 3313 } else { 3314 sc->sc_wdcdev.nchannels = 2; 3315 sc->sc_wdcdev.UDMA_cap = 5; 3316 } 3317 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3318 cp = &sc->pciide_channels[i]; 3319 if (sc->sc_wdcdev.nchannels > 1) { 3320 compatchan = i; 3321 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3322 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3323 printf("%s: %s channel ignored (disabled)\n", 3324 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3325 continue; 3326 } 3327 } 3328 if (pciide_chansetup(sc, i, interface) == 0) 3329 continue; 3330 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3331 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3332 &ctlsize, hpt_pci_intr); 3333 } else { 3334 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3335 &cmdsize, &ctlsize); 3336 } 3337 if (cp->hw_ok == 0) 3338 return; 3339 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3340 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3341 wdcattach(&cp->wdc_channel); 3342 hpt_setup_channel(&cp->wdc_channel); 3343 } 3344 if (revision == HPT370_REV || revision == HPT370A_REV) { 3345 /* 3346 * HPT370_REV has a bit to disable interrupts, make sure 3347 * to clear it 3348 */ 3349 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3350 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3351 ~HPT_CSEL_IRQDIS); 3352 } 3353 return; 3354 } 3355 3356 void 3357 hpt_setup_channel(chp) 3358 struct channel_softc *chp; 3359 { 3360 struct ata_drive_datas *drvp; 3361 int drive; 3362 int cable; 3363 u_int32_t before, after; 3364 u_int32_t idedma_ctl; 3365 struct pciide_channel *cp = (struct pciide_channel*)chp; 3366 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3367 3368 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3369 3370 /* setup DMA if needed */ 3371 pciide_channel_dma_setup(cp); 3372 3373 idedma_ctl = 0; 3374 3375 /* Per drive settings */ 3376 for (drive = 0; drive < 2; drive++) { 3377 drvp = &chp->ch_drive[drive]; 3378 /* If no drive, skip */ 3379 if ((drvp->drive_flags & DRIVE) == 0) 3380 continue; 3381 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3382 HPT_IDETIM(chp->channel, drive)); 3383 3384 /* add timing values, setup DMA if needed */ 3385 if (drvp->drive_flags & DRIVE_UDMA) { 3386 /* use Ultra/DMA */ 3387 drvp->drive_flags &= ~DRIVE_DMA; 3388 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3389 drvp->UDMA_mode > 2) 3390 drvp->UDMA_mode = 2; 3391 after = (sc->sc_wdcdev.nchannels == 2) ? 3392 hpt370_udma[drvp->UDMA_mode] : 3393 hpt366_udma[drvp->UDMA_mode]; 3394 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3395 } else if (drvp->drive_flags & DRIVE_DMA) { 3396 /* 3397 * use Multiword DMA. 3398 * Timings will be used for both PIO and DMA, so adjust 3399 * DMA mode if needed 3400 */ 3401 if (drvp->PIO_mode >= 3 && 3402 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3403 drvp->DMA_mode = drvp->PIO_mode - 2; 3404 } 3405 after = (sc->sc_wdcdev.nchannels == 2) ? 3406 hpt370_dma[drvp->DMA_mode] : 3407 hpt366_dma[drvp->DMA_mode]; 3408 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3409 } else { 3410 /* PIO only */ 3411 after = (sc->sc_wdcdev.nchannels == 2) ? 3412 hpt370_pio[drvp->PIO_mode] : 3413 hpt366_pio[drvp->PIO_mode]; 3414 } 3415 pci_conf_write(sc->sc_pc, sc->sc_tag, 3416 HPT_IDETIM(chp->channel, drive), after); 3417 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3418 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3419 after, before), DEBUG_PROBE); 3420 } 3421 if (idedma_ctl != 0) { 3422 /* Add software bits in status register */ 3423 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3424 IDEDMA_CTL, idedma_ctl); 3425 } 3426 pciide_print_modes(cp); 3427 } 3428 3429 int 3430 hpt_pci_intr(arg) 3431 void *arg; 3432 { 3433 struct pciide_softc *sc = arg; 3434 struct pciide_channel *cp; 3435 struct channel_softc *wdc_cp; 3436 int rv = 0; 3437 int dmastat, i, crv; 3438 3439 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3440 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3441 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3442 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3443 IDEDMA_CTL_INTR) 3444 continue; 3445 cp = &sc->pciide_channels[i]; 3446 wdc_cp = &cp->wdc_channel; 3447 crv = wdcintr(wdc_cp); 3448 if (crv == 0) { 3449 printf("%s:%d: bogus intr\n", 3450 sc->sc_wdcdev.sc_dev.dv_xname, i); 3451 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3452 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3453 } else 3454 rv = 1; 3455 } 3456 return rv; 3457 } 3458 3459 3460 /* Macros to test product */ 3461 #define PDC_IS_262(sc) \ 3462 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3463 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3464 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3465 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3466 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3467 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3468 #define PDC_IS_265(sc) \ 3469 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3470 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3471 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3472 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3473 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3474 #define PDC_IS_268(sc) \ 3475 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3476 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3477 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3478 3479 void 3480 pdc202xx_chip_map(sc, pa) 3481 struct pciide_softc *sc; 3482 struct pci_attach_args *pa; 3483 { 3484 struct pciide_channel *cp; 3485 int channel; 3486 pcireg_t interface, st, mode; 3487 bus_size_t cmdsize, ctlsize; 3488 3489 if (!PDC_IS_268(sc)) { 3490 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3491 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3492 st), DEBUG_PROBE); 3493 } 3494 if (pciide_chipen(sc, pa) == 0) 3495 return; 3496 3497 /* turn off RAID mode */ 3498 if (!PDC_IS_268(sc)) 3499 st &= ~PDC2xx_STATE_IDERAID; 3500 3501 /* 3502 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3503 * mode. We have to fake interface 3504 */ 3505 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3506 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3507 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3508 3509 printf("%s: bus-master DMA support present", 3510 sc->sc_wdcdev.sc_dev.dv_xname); 3511 pciide_mapreg_dma(sc, pa); 3512 printf("\n"); 3513 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3514 WDC_CAPABILITY_MODE; 3515 if (sc->sc_dma_ok) { 3516 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3517 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3518 sc->sc_wdcdev.irqack = pciide_irqack; 3519 } 3520 sc->sc_wdcdev.PIO_cap = 4; 3521 sc->sc_wdcdev.DMA_cap = 2; 3522 if (PDC_IS_265(sc)) 3523 sc->sc_wdcdev.UDMA_cap = 5; 3524 else if (PDC_IS_262(sc)) 3525 sc->sc_wdcdev.UDMA_cap = 4; 3526 else 3527 sc->sc_wdcdev.UDMA_cap = 2; 3528 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3529 pdc20268_setup_channel : pdc202xx_setup_channel; 3530 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3531 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3532 3533 if (!PDC_IS_268(sc)) { 3534 /* setup failsafe defaults */ 3535 mode = 0; 3536 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3537 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3538 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3539 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3540 for (channel = 0; 3541 channel < sc->sc_wdcdev.nchannels; 3542 channel++) { 3543 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3544 "drive 0 initial timings 0x%x, now 0x%x\n", 3545 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3546 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3547 DEBUG_PROBE); 3548 pci_conf_write(sc->sc_pc, sc->sc_tag, 3549 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3550 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3551 "drive 1 initial timings 0x%x, now 0x%x\n", 3552 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3553 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3554 pci_conf_write(sc->sc_pc, sc->sc_tag, 3555 PDC2xx_TIM(channel, 1), mode); 3556 } 3557 3558 mode = PDC2xx_SCR_DMA; 3559 if (PDC_IS_262(sc)) { 3560 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3561 } else { 3562 /* the BIOS set it up this way */ 3563 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3564 } 3565 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3566 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3567 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3568 "now 0x%x\n", 3569 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3570 PDC2xx_SCR), 3571 mode), DEBUG_PROBE); 3572 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3573 PDC2xx_SCR, mode); 3574 3575 /* controller initial state register is OK even without BIOS */ 3576 /* Set DMA mode to IDE DMA compatibility */ 3577 mode = 3578 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3579 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3580 DEBUG_PROBE); 3581 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3582 mode | 0x1); 3583 mode = 3584 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3585 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3586 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3587 mode | 0x1); 3588 } 3589 3590 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3591 cp = &sc->pciide_channels[channel]; 3592 if (pciide_chansetup(sc, channel, interface) == 0) 3593 continue; 3594 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3595 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3596 printf("%s: %s channel ignored (disabled)\n", 3597 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3598 continue; 3599 } 3600 if (PDC_IS_265(sc)) 3601 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3602 pdc20265_pci_intr); 3603 else 3604 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3605 pdc202xx_pci_intr); 3606 if (cp->hw_ok == 0) 3607 continue; 3608 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3609 st &= ~(PDC_IS_262(sc) ? 3610 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3611 pciide_map_compat_intr(pa, cp, channel, interface); 3612 pdc202xx_setup_channel(&cp->wdc_channel); 3613 } 3614 if (!PDC_IS_268(sc)) { 3615 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3616 "0x%x\n", st), DEBUG_PROBE); 3617 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3618 } 3619 return; 3620 } 3621 3622 void 3623 pdc202xx_setup_channel(chp) 3624 struct channel_softc *chp; 3625 { 3626 struct ata_drive_datas *drvp; 3627 int drive; 3628 pcireg_t mode, st; 3629 u_int32_t idedma_ctl, scr, atapi; 3630 struct pciide_channel *cp = (struct pciide_channel*)chp; 3631 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3632 int channel = chp->channel; 3633 3634 /* setup DMA if needed */ 3635 pciide_channel_dma_setup(cp); 3636 3637 idedma_ctl = 0; 3638 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3639 sc->sc_wdcdev.sc_dev.dv_xname, 3640 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3641 DEBUG_PROBE); 3642 3643 /* Per channel settings */ 3644 if (PDC_IS_262(sc)) { 3645 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3646 PDC262_U66); 3647 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3648 /* Trim UDMA mode */ 3649 if ((st & PDC262_STATE_80P(channel)) != 0 || 3650 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3651 chp->ch_drive[0].UDMA_mode <= 2) || 3652 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3653 chp->ch_drive[1].UDMA_mode <= 2)) { 3654 if (chp->ch_drive[0].UDMA_mode > 2) 3655 chp->ch_drive[0].UDMA_mode = 2; 3656 if (chp->ch_drive[1].UDMA_mode > 2) 3657 chp->ch_drive[1].UDMA_mode = 2; 3658 } 3659 /* Set U66 if needed */ 3660 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3661 chp->ch_drive[0].UDMA_mode > 2) || 3662 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3663 chp->ch_drive[1].UDMA_mode > 2)) 3664 scr |= PDC262_U66_EN(channel); 3665 else 3666 scr &= ~PDC262_U66_EN(channel); 3667 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3668 PDC262_U66, scr); 3669 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3670 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3671 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3672 PDC262_ATAPI(channel))), DEBUG_PROBE); 3673 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3674 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3675 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3676 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3677 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3678 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3679 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3680 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3681 atapi = 0; 3682 else 3683 atapi = PDC262_ATAPI_UDMA; 3684 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3685 PDC262_ATAPI(channel), atapi); 3686 } 3687 } 3688 for (drive = 0; drive < 2; drive++) { 3689 drvp = &chp->ch_drive[drive]; 3690 /* If no drive, skip */ 3691 if ((drvp->drive_flags & DRIVE) == 0) 3692 continue; 3693 mode = 0; 3694 if (drvp->drive_flags & DRIVE_UDMA) { 3695 /* use Ultra/DMA */ 3696 drvp->drive_flags &= ~DRIVE_DMA; 3697 mode = PDC2xx_TIM_SET_MB(mode, 3698 pdc2xx_udma_mb[drvp->UDMA_mode]); 3699 mode = PDC2xx_TIM_SET_MC(mode, 3700 pdc2xx_udma_mc[drvp->UDMA_mode]); 3701 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3702 } else if (drvp->drive_flags & DRIVE_DMA) { 3703 mode = PDC2xx_TIM_SET_MB(mode, 3704 pdc2xx_dma_mb[drvp->DMA_mode]); 3705 mode = PDC2xx_TIM_SET_MC(mode, 3706 pdc2xx_dma_mc[drvp->DMA_mode]); 3707 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3708 } else { 3709 mode = PDC2xx_TIM_SET_MB(mode, 3710 pdc2xx_dma_mb[0]); 3711 mode = PDC2xx_TIM_SET_MC(mode, 3712 pdc2xx_dma_mc[0]); 3713 } 3714 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3715 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3716 if (drvp->drive_flags & DRIVE_ATA) 3717 mode |= PDC2xx_TIM_PRE; 3718 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3719 if (drvp->PIO_mode >= 3) { 3720 mode |= PDC2xx_TIM_IORDY; 3721 if (drive == 0) 3722 mode |= PDC2xx_TIM_IORDYp; 3723 } 3724 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3725 "timings 0x%x\n", 3726 sc->sc_wdcdev.sc_dev.dv_xname, 3727 chp->channel, drive, mode), DEBUG_PROBE); 3728 pci_conf_write(sc->sc_pc, sc->sc_tag, 3729 PDC2xx_TIM(chp->channel, drive), mode); 3730 } 3731 if (idedma_ctl != 0) { 3732 /* Add software bits in status register */ 3733 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3734 IDEDMA_CTL, idedma_ctl); 3735 } 3736 pciide_print_modes(cp); 3737 } 3738 3739 void 3740 pdc20268_setup_channel(chp) 3741 struct channel_softc *chp; 3742 { 3743 struct ata_drive_datas *drvp; 3744 int drive; 3745 u_int32_t idedma_ctl; 3746 struct pciide_channel *cp = (struct pciide_channel*)chp; 3747 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3748 int u100; 3749 3750 /* setup DMA if needed */ 3751 pciide_channel_dma_setup(cp); 3752 3753 idedma_ctl = 0; 3754 3755 /* I don't know what this is for, FreeBSD does it ... */ 3756 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3757 IDEDMA_CMD + 0x1, 0x0b); 3758 3759 /* 3760 * I don't know what this is for; FreeBSD checks this ... this is not 3761 * cable type detect. 3762 */ 3763 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3764 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3765 3766 for (drive = 0; drive < 2; drive++) { 3767 drvp = &chp->ch_drive[drive]; 3768 /* If no drive, skip */ 3769 if ((drvp->drive_flags & DRIVE) == 0) 3770 continue; 3771 if (drvp->drive_flags & DRIVE_UDMA) { 3772 /* use Ultra/DMA */ 3773 drvp->drive_flags &= ~DRIVE_DMA; 3774 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3775 if (drvp->UDMA_mode > 2 && u100 == 0) 3776 drvp->UDMA_mode = 2; 3777 } else if (drvp->drive_flags & DRIVE_DMA) { 3778 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3779 } 3780 } 3781 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3782 if (idedma_ctl != 0) { 3783 /* Add software bits in status register */ 3784 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3785 IDEDMA_CTL, idedma_ctl); 3786 } 3787 pciide_print_modes(cp); 3788 } 3789 3790 int 3791 pdc202xx_pci_intr(arg) 3792 void *arg; 3793 { 3794 struct pciide_softc *sc = arg; 3795 struct pciide_channel *cp; 3796 struct channel_softc *wdc_cp; 3797 int i, rv, crv; 3798 u_int32_t scr; 3799 3800 rv = 0; 3801 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3802 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3803 cp = &sc->pciide_channels[i]; 3804 wdc_cp = &cp->wdc_channel; 3805 /* If a compat channel skip. */ 3806 if (cp->compat) 3807 continue; 3808 if (scr & PDC2xx_SCR_INT(i)) { 3809 crv = wdcintr(wdc_cp); 3810 if (crv == 0) 3811 printf("%s:%d: bogus intr (reg 0x%x)\n", 3812 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3813 else 3814 rv = 1; 3815 } 3816 } 3817 return rv; 3818 } 3819 3820 int 3821 pdc20265_pci_intr(arg) 3822 void *arg; 3823 { 3824 struct pciide_softc *sc = arg; 3825 struct pciide_channel *cp; 3826 struct channel_softc *wdc_cp; 3827 int i, rv, crv; 3828 u_int32_t dmastat; 3829 3830 rv = 0; 3831 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3832 cp = &sc->pciide_channels[i]; 3833 wdc_cp = &cp->wdc_channel; 3834 /* If a compat channel skip. */ 3835 if (cp->compat) 3836 continue; 3837 /* 3838 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3839 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3840 * So use it instead (requires 2 reg reads instead of 1, 3841 * but we can't do it another way). 3842 */ 3843 dmastat = bus_space_read_1(sc->sc_dma_iot, 3844 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3845 if((dmastat & IDEDMA_CTL_INTR) == 0) 3846 continue; 3847 crv = wdcintr(wdc_cp); 3848 if (crv == 0) 3849 printf("%s:%d: bogus intr\n", 3850 sc->sc_wdcdev.sc_dev.dv_xname, i); 3851 else 3852 rv = 1; 3853 } 3854 return rv; 3855 } 3856 3857 void 3858 opti_chip_map(sc, pa) 3859 struct pciide_softc *sc; 3860 struct pci_attach_args *pa; 3861 { 3862 struct pciide_channel *cp; 3863 bus_size_t cmdsize, ctlsize; 3864 pcireg_t interface; 3865 u_int8_t init_ctrl; 3866 int channel; 3867 3868 if (pciide_chipen(sc, pa) == 0) 3869 return; 3870 printf("%s: bus-master DMA support present", 3871 sc->sc_wdcdev.sc_dev.dv_xname); 3872 3873 /* 3874 * XXXSCW: 3875 * There seem to be a couple of buggy revisions/implementations 3876 * of the OPTi pciide chipset. This kludge seems to fix one of 3877 * the reported problems (PR/11644) but still fails for the 3878 * other (PR/13151), although the latter may be due to other 3879 * issues too... 3880 */ 3881 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3882 printf(" but disabled due to chip rev. <= 0x12"); 3883 sc->sc_dma_ok = 0; 3884 sc->sc_wdcdev.cap = 0; 3885 } else { 3886 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3887 pciide_mapreg_dma(sc, pa); 3888 } 3889 printf("\n"); 3890 3891 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3892 sc->sc_wdcdev.PIO_cap = 4; 3893 if (sc->sc_dma_ok) { 3894 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3895 sc->sc_wdcdev.irqack = pciide_irqack; 3896 sc->sc_wdcdev.DMA_cap = 2; 3897 } 3898 sc->sc_wdcdev.set_modes = opti_setup_channel; 3899 3900 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3901 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3902 3903 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3904 OPTI_REG_INIT_CONTROL); 3905 3906 interface = PCI_INTERFACE(pa->pa_class); 3907 3908 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3909 cp = &sc->pciide_channels[channel]; 3910 if (pciide_chansetup(sc, channel, interface) == 0) 3911 continue; 3912 if (channel == 1 && 3913 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3914 printf("%s: %s channel ignored (disabled)\n", 3915 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3916 continue; 3917 } 3918 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3919 pciide_pci_intr); 3920 if (cp->hw_ok == 0) 3921 continue; 3922 pciide_map_compat_intr(pa, cp, channel, interface); 3923 if (cp->hw_ok == 0) 3924 continue; 3925 opti_setup_channel(&cp->wdc_channel); 3926 } 3927 } 3928 3929 void 3930 opti_setup_channel(chp) 3931 struct channel_softc *chp; 3932 { 3933 struct ata_drive_datas *drvp; 3934 struct pciide_channel *cp = (struct pciide_channel*)chp; 3935 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3936 int drive, spd; 3937 int mode[2]; 3938 u_int8_t rv, mr; 3939 3940 /* 3941 * The `Delay' and `Address Setup Time' fields of the 3942 * Miscellaneous Register are always zero initially. 3943 */ 3944 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3945 mr &= ~(OPTI_MISC_DELAY_MASK | 3946 OPTI_MISC_ADDR_SETUP_MASK | 3947 OPTI_MISC_INDEX_MASK); 3948 3949 /* Prime the control register before setting timing values */ 3950 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3951 3952 /* Determine the clockrate of the PCIbus the chip is attached to */ 3953 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3954 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3955 3956 /* setup DMA if needed */ 3957 pciide_channel_dma_setup(cp); 3958 3959 for (drive = 0; drive < 2; drive++) { 3960 drvp = &chp->ch_drive[drive]; 3961 /* If no drive, skip */ 3962 if ((drvp->drive_flags & DRIVE) == 0) { 3963 mode[drive] = -1; 3964 continue; 3965 } 3966 3967 if ((drvp->drive_flags & DRIVE_DMA)) { 3968 /* 3969 * Timings will be used for both PIO and DMA, 3970 * so adjust DMA mode if needed 3971 */ 3972 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3973 drvp->PIO_mode = drvp->DMA_mode + 2; 3974 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3975 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3976 drvp->PIO_mode - 2 : 0; 3977 if (drvp->DMA_mode == 0) 3978 drvp->PIO_mode = 0; 3979 3980 mode[drive] = drvp->DMA_mode + 5; 3981 } else 3982 mode[drive] = drvp->PIO_mode; 3983 3984 if (drive && mode[0] >= 0 && 3985 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3986 /* 3987 * Can't have two drives using different values 3988 * for `Address Setup Time'. 3989 * Slow down the faster drive to compensate. 3990 */ 3991 int d = (opti_tim_as[spd][mode[0]] > 3992 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3993 3994 mode[d] = mode[1-d]; 3995 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3996 chp->ch_drive[d].DMA_mode = 0; 3997 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3998 } 3999 } 4000 4001 for (drive = 0; drive < 2; drive++) { 4002 int m; 4003 if ((m = mode[drive]) < 0) 4004 continue; 4005 4006 /* Set the Address Setup Time and select appropriate index */ 4007 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4008 rv |= OPTI_MISC_INDEX(drive); 4009 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4010 4011 /* Set the pulse width and recovery timing parameters */ 4012 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4013 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4014 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4015 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4016 4017 /* Set the Enhanced Mode register appropriately */ 4018 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4019 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4020 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4021 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4022 } 4023 4024 /* Finally, enable the timings */ 4025 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4026 4027 pciide_print_modes(cp); 4028 } 4029 4030 #define ACARD_IS_850(sc) \ 4031 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4032 4033 void 4034 acard_chip_map(sc, pa) 4035 struct pciide_softc *sc; 4036 struct pci_attach_args *pa; 4037 { 4038 struct pciide_channel *cp; 4039 int i; 4040 pcireg_t interface; 4041 bus_size_t cmdsize, ctlsize; 4042 4043 if (pciide_chipen(sc, pa) == 0) 4044 return; 4045 4046 /* 4047 * when the chip is in native mode it identifies itself as a 4048 * 'misc mass storage'. Fake interface in this case. 4049 */ 4050 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4051 interface = PCI_INTERFACE(pa->pa_class); 4052 } else { 4053 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4054 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4055 } 4056 4057 printf("%s: bus-master DMA support present", 4058 sc->sc_wdcdev.sc_dev.dv_xname); 4059 pciide_mapreg_dma(sc, pa); 4060 printf("\n"); 4061 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4062 WDC_CAPABILITY_MODE; 4063 4064 if (sc->sc_dma_ok) { 4065 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4066 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4067 sc->sc_wdcdev.irqack = pciide_irqack; 4068 } 4069 sc->sc_wdcdev.PIO_cap = 4; 4070 sc->sc_wdcdev.DMA_cap = 2; 4071 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4072 4073 sc->sc_wdcdev.set_modes = acard_setup_channel; 4074 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4075 sc->sc_wdcdev.nchannels = 2; 4076 4077 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4078 cp = &sc->pciide_channels[i]; 4079 if (pciide_chansetup(sc, i, interface) == 0) 4080 continue; 4081 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4082 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4083 &ctlsize, pciide_pci_intr); 4084 } else { 4085 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4086 &cmdsize, &ctlsize); 4087 } 4088 if (cp->hw_ok == 0) 4089 return; 4090 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4091 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4092 wdcattach(&cp->wdc_channel); 4093 acard_setup_channel(&cp->wdc_channel); 4094 } 4095 if (!ACARD_IS_850(sc)) { 4096 u_int32_t reg; 4097 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4098 reg &= ~ATP860_CTRL_INT; 4099 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4100 } 4101 } 4102 4103 void 4104 acard_setup_channel(chp) 4105 struct channel_softc *chp; 4106 { 4107 struct ata_drive_datas *drvp; 4108 struct pciide_channel *cp = (struct pciide_channel*)chp; 4109 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4110 int channel = chp->channel; 4111 int drive; 4112 u_int32_t idetime, udma_mode; 4113 u_int32_t idedma_ctl; 4114 4115 /* setup DMA if needed */ 4116 pciide_channel_dma_setup(cp); 4117 4118 if (ACARD_IS_850(sc)) { 4119 idetime = 0; 4120 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4121 udma_mode &= ~ATP850_UDMA_MASK(channel); 4122 } else { 4123 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4124 idetime &= ~ATP860_SETTIME_MASK(channel); 4125 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4126 udma_mode &= ~ATP860_UDMA_MASK(channel); 4127 4128 /* check 80 pins cable */ 4129 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4130 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4131 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4132 & ATP860_CTRL_80P(chp->channel)) { 4133 if (chp->ch_drive[0].UDMA_mode > 2) 4134 chp->ch_drive[0].UDMA_mode = 2; 4135 if (chp->ch_drive[1].UDMA_mode > 2) 4136 chp->ch_drive[1].UDMA_mode = 2; 4137 } 4138 } 4139 } 4140 4141 idedma_ctl = 0; 4142 4143 /* Per drive settings */ 4144 for (drive = 0; drive < 2; drive++) { 4145 drvp = &chp->ch_drive[drive]; 4146 /* If no drive, skip */ 4147 if ((drvp->drive_flags & DRIVE) == 0) 4148 continue; 4149 /* add timing values, setup DMA if needed */ 4150 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4151 (drvp->drive_flags & DRIVE_UDMA)) { 4152 /* use Ultra/DMA */ 4153 if (ACARD_IS_850(sc)) { 4154 idetime |= ATP850_SETTIME(drive, 4155 acard_act_udma[drvp->UDMA_mode], 4156 acard_rec_udma[drvp->UDMA_mode]); 4157 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4158 acard_udma_conf[drvp->UDMA_mode]); 4159 } else { 4160 idetime |= ATP860_SETTIME(channel, drive, 4161 acard_act_udma[drvp->UDMA_mode], 4162 acard_rec_udma[drvp->UDMA_mode]); 4163 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4164 acard_udma_conf[drvp->UDMA_mode]); 4165 } 4166 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4167 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4168 (drvp->drive_flags & DRIVE_DMA)) { 4169 /* use Multiword DMA */ 4170 drvp->drive_flags &= ~DRIVE_UDMA; 4171 if (ACARD_IS_850(sc)) { 4172 idetime |= ATP850_SETTIME(drive, 4173 acard_act_dma[drvp->DMA_mode], 4174 acard_rec_dma[drvp->DMA_mode]); 4175 } else { 4176 idetime |= ATP860_SETTIME(channel, drive, 4177 acard_act_dma[drvp->DMA_mode], 4178 acard_rec_dma[drvp->DMA_mode]); 4179 } 4180 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4181 } else { 4182 /* PIO only */ 4183 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4184 if (ACARD_IS_850(sc)) { 4185 idetime |= ATP850_SETTIME(drive, 4186 acard_act_pio[drvp->PIO_mode], 4187 acard_rec_pio[drvp->PIO_mode]); 4188 } else { 4189 idetime |= ATP860_SETTIME(channel, drive, 4190 acard_act_pio[drvp->PIO_mode], 4191 acard_rec_pio[drvp->PIO_mode]); 4192 } 4193 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4194 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4195 | ATP8x0_CTRL_EN(channel)); 4196 } 4197 } 4198 4199 if (idedma_ctl != 0) { 4200 /* Add software bits in status register */ 4201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4202 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4203 } 4204 pciide_print_modes(cp); 4205 4206 if (ACARD_IS_850(sc)) { 4207 pci_conf_write(sc->sc_pc, sc->sc_tag, 4208 ATP850_IDETIME(channel), idetime); 4209 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4210 } else { 4211 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4212 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4213 } 4214 } 4215 4216 int 4217 acard_pci_intr(arg) 4218 void *arg; 4219 { 4220 struct pciide_softc *sc = arg; 4221 struct pciide_channel *cp; 4222 struct channel_softc *wdc_cp; 4223 int rv = 0; 4224 int dmastat, i, crv; 4225 4226 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4227 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4228 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4229 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4230 continue; 4231 cp = &sc->pciide_channels[i]; 4232 wdc_cp = &cp->wdc_channel; 4233 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4234 (void)wdcintr(wdc_cp); 4235 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4236 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4237 continue; 4238 } 4239 crv = wdcintr(wdc_cp); 4240 if (crv == 0) 4241 printf("%s:%d: bogus intr\n", 4242 sc->sc_wdcdev.sc_dev.dv_xname, i); 4243 else if (crv == 1) 4244 rv = 1; 4245 else if (rv == 0) 4246 rv = crv; 4247 } 4248 return rv; 4249 } 4250 4251 static int 4252 sl82c105_bugchk(struct pci_attach_args *pa) 4253 { 4254 4255 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4256 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4257 return (0); 4258 4259 if (PCI_REVISION(pa->pa_class) <= 0x05) 4260 return (1); 4261 4262 return (0); 4263 } 4264 4265 void 4266 sl82c105_chip_map(sc, pa) 4267 struct pciide_softc *sc; 4268 struct pci_attach_args *pa; 4269 { 4270 struct pciide_channel *cp; 4271 bus_size_t cmdsize, ctlsize; 4272 pcireg_t interface, idecr; 4273 int channel; 4274 4275 if (pciide_chipen(sc, pa) == 0) 4276 return; 4277 4278 printf("%s: bus-master DMA support present", 4279 sc->sc_wdcdev.sc_dev.dv_xname); 4280 4281 /* 4282 * Check to see if we're part of the Winbond 83c553 Southbridge. 4283 * If so, we need to disable DMA on rev. <= 5 of that chip. 4284 */ 4285 if (pci_find_device(pa, sl82c105_bugchk)) { 4286 printf(" but disabled due to 83c553 rev. <= 0x05"); 4287 sc->sc_dma_ok = 0; 4288 } else 4289 pciide_mapreg_dma(sc, pa); 4290 printf("\n"); 4291 4292 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4293 WDC_CAPABILITY_MODE; 4294 sc->sc_wdcdev.PIO_cap = 4; 4295 if (sc->sc_dma_ok) { 4296 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4297 sc->sc_wdcdev.irqack = pciide_irqack; 4298 sc->sc_wdcdev.DMA_cap = 2; 4299 } 4300 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4301 4302 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4303 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4304 4305 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4306 4307 interface = PCI_INTERFACE(pa->pa_class); 4308 4309 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4310 cp = &sc->pciide_channels[channel]; 4311 if (pciide_chansetup(sc, channel, interface) == 0) 4312 continue; 4313 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4314 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4315 printf("%s: %s channel ignored (disabled)\n", 4316 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4317 continue; 4318 } 4319 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4320 pciide_pci_intr); 4321 if (cp->hw_ok == 0) 4322 continue; 4323 pciide_map_compat_intr(pa, cp, channel, interface); 4324 if (cp->hw_ok == 0) 4325 continue; 4326 sl82c105_setup_channel(&cp->wdc_channel); 4327 } 4328 } 4329 4330 void 4331 sl82c105_setup_channel(chp) 4332 struct channel_softc *chp; 4333 { 4334 struct ata_drive_datas *drvp; 4335 struct pciide_channel *cp = (struct pciide_channel*)chp; 4336 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4337 int pxdx_reg, drive; 4338 pcireg_t pxdx; 4339 4340 /* Set up DMA if needed. */ 4341 pciide_channel_dma_setup(cp); 4342 4343 for (drive = 0; drive < 2; drive++) { 4344 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4345 : SYMPH_P1D0CR) + (drive * 4); 4346 4347 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4348 4349 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4350 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4351 4352 drvp = &chp->ch_drive[drive]; 4353 /* If no drive, skip. */ 4354 if ((drvp->drive_flags & DRIVE) == 0) { 4355 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4356 continue; 4357 } 4358 4359 if (drvp->drive_flags & DRIVE_DMA) { 4360 /* 4361 * Timings will be used for both PIO and DMA, 4362 * so adjust DMA mode if needed. 4363 */ 4364 if (drvp->PIO_mode >= 3) { 4365 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4366 drvp->DMA_mode = drvp->PIO_mode - 2; 4367 if (drvp->DMA_mode < 1) { 4368 /* 4369 * Can't mix both PIO and DMA. 4370 * Disable DMA. 4371 */ 4372 drvp->drive_flags &= ~DRIVE_DMA; 4373 } 4374 } else { 4375 /* 4376 * Can't mix both PIO and DMA. Disable 4377 * DMA. 4378 */ 4379 drvp->drive_flags &= ~DRIVE_DMA; 4380 } 4381 } 4382 4383 if (drvp->drive_flags & DRIVE_DMA) { 4384 /* Use multi-word DMA. */ 4385 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4386 PxDx_CMD_ON_SHIFT; 4387 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4388 } else { 4389 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4390 PxDx_CMD_ON_SHIFT; 4391 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4392 } 4393 4394 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4395 4396 /* ...and set the mode for this drive. */ 4397 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4398 } 4399 4400 pciide_print_modes(cp); 4401 } 4402
Indexes created Thu Oct 02 10:09:58 GMT 2025