pciide.c revision 1.149
1 /* $NetBSD: pciide.c,v 1.149 2002/04/12 18:02:04 mycroft Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.149 2002/04/12 18:02:04 mycroft Exp $"); 81 82 #ifndef WDCDEBUG 83 #define WDCDEBUG 84 #endif 85 86 #define DEBUG_DMA 0x01 87 #define DEBUG_XFERS 0x02 88 #define DEBUG_FUNCS 0x08 89 #define DEBUG_PROBE 0x10 90 #ifdef WDCDEBUG 91 int wdcdebug_pciide_mask = 0; 92 #define WDCDEBUG_PRINT(args, level) \ 93 if (wdcdebug_pciide_mask & (level)) printf args 94 #else 95 #define WDCDEBUG_PRINT(args, level) 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 102 #include <uvm/uvm_extern.h> 103 104 #include <machine/endian.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 #include <dev/pci/pciide_opti_reg.h> 120 #include <dev/pci/pciide_hpt_reg.h> 121 #include <dev/pci/pciide_acard_reg.h> 122 #include <dev/pci/pciide_sl82c105_reg.h> 123 #include <dev/pci/cy82c693var.h> 124 125 #include "opt_pciide.h" 126 127 /* inlines for reading/writing 8-bit PCI registers */ 128 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 129 int)); 130 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 131 int, u_int8_t)); 132 133 static __inline u_int8_t 134 pciide_pci_read(pc, pa, reg) 135 pci_chipset_tag_t pc; 136 pcitag_t pa; 137 int reg; 138 { 139 140 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 141 ((reg & 0x03) * 8) & 0xff); 142 } 143 144 static __inline void 145 pciide_pci_write(pc, pa, reg, val) 146 pci_chipset_tag_t pc; 147 pcitag_t pa; 148 int reg; 149 u_int8_t val; 150 { 151 pcireg_t pcival; 152 153 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 154 pcival &= ~(0xff << ((reg & 0x03) * 8)); 155 pcival |= (val << ((reg & 0x03) * 8)); 156 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 157 } 158 159 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 161 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void piix_setup_channel __P((struct channel_softc*)); 163 void piix3_4_setup_channel __P((struct channel_softc*)); 164 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 165 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 166 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 167 168 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void amd7x6_setup_channel __P((struct channel_softc*)); 170 171 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void apollo_setup_channel __P((struct channel_softc*)); 173 174 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cmd0643_9_setup_channel __P((struct channel_softc*)); 177 void cmd_channel_map __P((struct pci_attach_args *, 178 struct pciide_softc *, int)); 179 int cmd_pci_intr __P((void *)); 180 void cmd646_9_irqack __P((struct channel_softc *)); 181 182 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void cy693_setup_channel __P((struct channel_softc*)); 184 185 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void sis_setup_channel __P((struct channel_softc*)); 187 static int sis_hostbr_match __P(( struct pci_attach_args *)); 188 189 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void acer_setup_channel __P((struct channel_softc*)); 191 int acer_pci_intr __P((void *)); 192 static int acer_isabr_match __P(( struct pci_attach_args *)); 193 194 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void pdc202xx_setup_channel __P((struct channel_softc*)); 196 void pdc20268_setup_channel __P((struct channel_softc*)); 197 int pdc202xx_pci_intr __P((void *)); 198 int pdc20265_pci_intr __P((void *)); 199 200 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void opti_setup_channel __P((struct channel_softc*)); 202 203 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 204 void hpt_setup_channel __P((struct channel_softc*)); 205 int hpt_pci_intr __P((void *)); 206 207 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 void acard_setup_channel __P((struct channel_softc*)); 209 int acard_pci_intr __P((void *)); 210 211 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 void serverworks_setup_channel __P((struct channel_softc*)); 213 int serverworks_pci_intr __P((void *)); 214 215 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 216 void sl82c105_setup_channel __P((struct channel_softc*)); 217 218 void pciide_channel_dma_setup __P((struct pciide_channel *)); 219 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 220 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 221 void pciide_dma_start __P((void*, int, int)); 222 int pciide_dma_finish __P((void*, int, int, int)); 223 void pciide_irqack __P((struct channel_softc *)); 224 void pciide_print_modes __P((struct pciide_channel *)); 225 226 struct pciide_product_desc { 227 u_int32_t ide_product; 228 int ide_flags; 229 const char *ide_name; 230 /* map and setup chip, probe drives */ 231 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 232 }; 233 234 /* Flags for ide_flags */ 235 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 236 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 237 238 /* Default product description for devices not known from this controller */ 239 const struct pciide_product_desc default_product_desc = { 240 0, 241 0, 242 "Generic PCI IDE controller", 243 default_chip_map, 244 }; 245 246 const struct pciide_product_desc pciide_intel_products[] = { 247 { PCI_PRODUCT_INTEL_82092AA, 248 0, 249 "Intel 82092AA IDE controller", 250 default_chip_map, 251 }, 252 { PCI_PRODUCT_INTEL_82371FB_IDE, 253 0, 254 "Intel 82371FB IDE controller (PIIX)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82371SB_IDE, 258 0, 259 "Intel 82371SB IDE Interface (PIIX3)", 260 piix_chip_map, 261 }, 262 { PCI_PRODUCT_INTEL_82371AB_IDE, 263 0, 264 "Intel 82371AB IDE controller (PIIX4)", 265 piix_chip_map, 266 }, 267 { PCI_PRODUCT_INTEL_82440MX_IDE, 268 0, 269 "Intel 82440MX IDE controller", 270 piix_chip_map 271 }, 272 { PCI_PRODUCT_INTEL_82801AA_IDE, 273 0, 274 "Intel 82801AA IDE Controller (ICH)", 275 piix_chip_map, 276 }, 277 { PCI_PRODUCT_INTEL_82801AB_IDE, 278 0, 279 "Intel 82801AB IDE Controller (ICH0)", 280 piix_chip_map, 281 }, 282 { PCI_PRODUCT_INTEL_82801BA_IDE, 283 0, 284 "Intel 82801BA IDE Controller (ICH2)", 285 piix_chip_map, 286 }, 287 { PCI_PRODUCT_INTEL_82801BAM_IDE, 288 0, 289 "Intel 82801BAM IDE Controller (ICH2)", 290 piix_chip_map, 291 }, 292 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 293 0, 294 "Intel 82201CA IDE Controller", 295 piix_chip_map, 296 }, 297 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 298 0, 299 "Intel 82201CA IDE Controller", 300 piix_chip_map, 301 }, 302 { 0, 303 0, 304 NULL, 305 NULL 306 } 307 }; 308 309 const struct pciide_product_desc pciide_amd_products[] = { 310 { PCI_PRODUCT_AMD_PBC756_IDE, 311 0, 312 "Advanced Micro Devices AMD756 IDE Controller", 313 amd7x6_chip_map 314 }, 315 { PCI_PRODUCT_AMD_PBC766_IDE, 316 0, 317 "Advanced Micro Devices AMD766 IDE Controller", 318 amd7x6_chip_map 319 }, 320 { PCI_PRODUCT_AMD_PBC768_IDE, 321 0, 322 "Advanced Micro Devices AMD768 IDE Controller", 323 amd7x6_chip_map 324 }, 325 { 0, 326 0, 327 NULL, 328 NULL 329 } 330 }; 331 332 const struct pciide_product_desc pciide_cmd_products[] = { 333 { PCI_PRODUCT_CMDTECH_640, 334 0, 335 "CMD Technology PCI0640", 336 cmd_chip_map 337 }, 338 { PCI_PRODUCT_CMDTECH_643, 339 0, 340 "CMD Technology PCI0643", 341 cmd0643_9_chip_map, 342 }, 343 { PCI_PRODUCT_CMDTECH_646, 344 0, 345 "CMD Technology PCI0646", 346 cmd0643_9_chip_map, 347 }, 348 { PCI_PRODUCT_CMDTECH_648, 349 IDE_PCI_CLASS_OVERRIDE, 350 "CMD Technology PCI0648", 351 cmd0643_9_chip_map, 352 }, 353 { PCI_PRODUCT_CMDTECH_649, 354 IDE_PCI_CLASS_OVERRIDE, 355 "CMD Technology PCI0649", 356 cmd0643_9_chip_map, 357 }, 358 { 0, 359 0, 360 NULL, 361 NULL 362 } 363 }; 364 365 const struct pciide_product_desc pciide_via_products[] = { 366 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 367 0, 368 NULL, 369 apollo_chip_map, 370 }, 371 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 372 0, 373 NULL, 374 apollo_chip_map, 375 }, 376 { 0, 377 0, 378 NULL, 379 NULL 380 } 381 }; 382 383 const struct pciide_product_desc pciide_cypress_products[] = { 384 { PCI_PRODUCT_CONTAQ_82C693, 385 IDE_16BIT_IOSPACE, 386 "Cypress 82C693 IDE Controller", 387 cy693_chip_map, 388 }, 389 { 0, 390 0, 391 NULL, 392 NULL 393 } 394 }; 395 396 const struct pciide_product_desc pciide_sis_products[] = { 397 { PCI_PRODUCT_SIS_5597_IDE, 398 0, 399 "Silicon Integrated System 5597/5598 IDE controller", 400 sis_chip_map, 401 }, 402 { 0, 403 0, 404 NULL, 405 NULL 406 } 407 }; 408 409 const struct pciide_product_desc pciide_acer_products[] = { 410 { PCI_PRODUCT_ALI_M5229, 411 0, 412 "Acer Labs M5229 UDMA IDE Controller", 413 acer_chip_map, 414 }, 415 { 0, 416 0, 417 NULL, 418 NULL 419 } 420 }; 421 422 const struct pciide_product_desc pciide_promise_products[] = { 423 { PCI_PRODUCT_PROMISE_ULTRA33, 424 IDE_PCI_CLASS_OVERRIDE, 425 "Promise Ultra33/ATA Bus Master IDE Accelerator", 426 pdc202xx_chip_map, 427 }, 428 { PCI_PRODUCT_PROMISE_ULTRA66, 429 IDE_PCI_CLASS_OVERRIDE, 430 "Promise Ultra66/ATA Bus Master IDE Accelerator", 431 pdc202xx_chip_map, 432 }, 433 { PCI_PRODUCT_PROMISE_ULTRA100, 434 IDE_PCI_CLASS_OVERRIDE, 435 "Promise Ultra100/ATA Bus Master IDE Accelerator", 436 pdc202xx_chip_map, 437 }, 438 { PCI_PRODUCT_PROMISE_ULTRA100X, 439 IDE_PCI_CLASS_OVERRIDE, 440 "Promise Ultra100/ATA Bus Master IDE Accelerator", 441 pdc202xx_chip_map, 442 }, 443 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 444 IDE_PCI_CLASS_OVERRIDE, 445 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 446 pdc202xx_chip_map, 447 }, 448 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 449 IDE_PCI_CLASS_OVERRIDE, 450 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 451 pdc202xx_chip_map, 452 }, 453 { PCI_PRODUCT_PROMISE_ULTRA133, 454 IDE_PCI_CLASS_OVERRIDE, 455 "Promise Ultra133/ATA Bus Master IDE Accelerator", 456 pdc202xx_chip_map, 457 }, 458 { 0, 459 0, 460 NULL, 461 NULL 462 } 463 }; 464 465 const struct pciide_product_desc pciide_opti_products[] = { 466 { PCI_PRODUCT_OPTI_82C621, 467 0, 468 "OPTi 82c621 PCI IDE controller", 469 opti_chip_map, 470 }, 471 { PCI_PRODUCT_OPTI_82C568, 472 0, 473 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 474 opti_chip_map, 475 }, 476 { PCI_PRODUCT_OPTI_82D568, 477 0, 478 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 479 opti_chip_map, 480 }, 481 { 0, 482 0, 483 NULL, 484 NULL 485 } 486 }; 487 488 const struct pciide_product_desc pciide_triones_products[] = { 489 { PCI_PRODUCT_TRIONES_HPT366, 490 IDE_PCI_CLASS_OVERRIDE, 491 NULL, 492 hpt_chip_map, 493 }, 494 { 0, 495 0, 496 NULL, 497 NULL 498 } 499 }; 500 501 const struct pciide_product_desc pciide_acard_products[] = { 502 { PCI_PRODUCT_ACARD_ATP850U, 503 IDE_PCI_CLASS_OVERRIDE, 504 "Acard ATP850U Ultra33 IDE Controller", 505 acard_chip_map, 506 }, 507 { PCI_PRODUCT_ACARD_ATP860, 508 IDE_PCI_CLASS_OVERRIDE, 509 "Acard ATP860 Ultra66 IDE Controller", 510 acard_chip_map, 511 }, 512 { PCI_PRODUCT_ACARD_ATP860A, 513 IDE_PCI_CLASS_OVERRIDE, 514 "Acard ATP860-A Ultra66 IDE Controller", 515 acard_chip_map, 516 }, 517 { 0, 518 0, 519 NULL, 520 NULL 521 } 522 }; 523 524 const struct pciide_product_desc pciide_serverworks_products[] = { 525 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 526 0, 527 "ServerWorks OSB4 IDE Controller", 528 serverworks_chip_map, 529 }, 530 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 531 0, 532 "ServerWorks CSB5 IDE Controller", 533 serverworks_chip_map, 534 }, 535 { 0, 536 0, 537 NULL, 538 } 539 }; 540 541 const struct pciide_product_desc pciide_symphony_products[] = { 542 { PCI_PRODUCT_SYMPHONY_82C105, 543 0, 544 "Symphony Labs 82C105 IDE controller", 545 sl82c105_chip_map, 546 }, 547 { 0, 548 0, 549 NULL, 550 } 551 }; 552 553 const struct pciide_product_desc pciide_winbond_products[] = { 554 { PCI_PRODUCT_WINBOND_W83C553F_1, 555 0, 556 "Winbond W83C553F IDE controller", 557 sl82c105_chip_map, 558 }, 559 { 0, 560 0, 561 NULL, 562 } 563 }; 564 565 struct pciide_vendor_desc { 566 u_int32_t ide_vendor; 567 const struct pciide_product_desc *ide_products; 568 }; 569 570 const struct pciide_vendor_desc pciide_vendors[] = { 571 { PCI_VENDOR_INTEL, pciide_intel_products }, 572 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 573 { PCI_VENDOR_VIATECH, pciide_via_products }, 574 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 575 { PCI_VENDOR_SIS, pciide_sis_products }, 576 { PCI_VENDOR_ALI, pciide_acer_products }, 577 { PCI_VENDOR_PROMISE, pciide_promise_products }, 578 { PCI_VENDOR_AMD, pciide_amd_products }, 579 { PCI_VENDOR_OPTI, pciide_opti_products }, 580 { PCI_VENDOR_TRIONES, pciide_triones_products }, 581 { PCI_VENDOR_ACARD, pciide_acard_products }, 582 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 583 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 584 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 585 { 0, NULL } 586 }; 587 588 /* options passed via the 'flags' config keyword */ 589 #define PCIIDE_OPTIONS_DMA 0x01 590 #define PCIIDE_OPTIONS_NODMA 0x02 591 592 int pciide_match __P((struct device *, struct cfdata *, void *)); 593 void pciide_attach __P((struct device *, struct device *, void *)); 594 595 struct cfattach pciide_ca = { 596 sizeof(struct pciide_softc), pciide_match, pciide_attach 597 }; 598 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 599 int pciide_mapregs_compat __P(( struct pci_attach_args *, 600 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 601 int pciide_mapregs_native __P((struct pci_attach_args *, 602 struct pciide_channel *, bus_size_t *, bus_size_t *, 603 int (*pci_intr) __P((void *)))); 604 void pciide_mapreg_dma __P((struct pciide_softc *, 605 struct pci_attach_args *)); 606 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 607 void pciide_mapchan __P((struct pci_attach_args *, 608 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 609 int (*pci_intr) __P((void *)))); 610 int pciide_chan_candisable __P((struct pciide_channel *)); 611 void pciide_map_compat_intr __P(( struct pci_attach_args *, 612 struct pciide_channel *, int, int)); 613 int pciide_compat_intr __P((void *)); 614 int pciide_pci_intr __P((void *)); 615 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 616 617 const struct pciide_product_desc * 618 pciide_lookup_product(id) 619 u_int32_t id; 620 { 621 const struct pciide_product_desc *pp; 622 const struct pciide_vendor_desc *vp; 623 624 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 625 if (PCI_VENDOR(id) == vp->ide_vendor) 626 break; 627 628 if ((pp = vp->ide_products) == NULL) 629 return NULL; 630 631 for (; pp->chip_map != NULL; pp++) 632 if (PCI_PRODUCT(id) == pp->ide_product) 633 break; 634 635 if (pp->chip_map == NULL) 636 return NULL; 637 return pp; 638 } 639 640 int 641 pciide_match(parent, match, aux) 642 struct device *parent; 643 struct cfdata *match; 644 void *aux; 645 { 646 struct pci_attach_args *pa = aux; 647 const struct pciide_product_desc *pp; 648 649 /* 650 * Check the ID register to see that it's a PCI IDE controller. 651 * If it is, we assume that we can deal with it; it _should_ 652 * work in a standardized way... 653 */ 654 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 655 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 656 return (1); 657 } 658 659 /* 660 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 661 * controllers. Let see if we can deal with it anyway. 662 */ 663 pp = pciide_lookup_product(pa->pa_id); 664 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 665 return (1); 666 } 667 668 return (0); 669 } 670 671 void 672 pciide_attach(parent, self, aux) 673 struct device *parent, *self; 674 void *aux; 675 { 676 struct pci_attach_args *pa = aux; 677 pci_chipset_tag_t pc = pa->pa_pc; 678 pcitag_t tag = pa->pa_tag; 679 struct pciide_softc *sc = (struct pciide_softc *)self; 680 pcireg_t csr; 681 char devinfo[256]; 682 const char *displaydev; 683 684 sc->sc_pp = pciide_lookup_product(pa->pa_id); 685 if (sc->sc_pp == NULL) { 686 sc->sc_pp = &default_product_desc; 687 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 688 displaydev = devinfo; 689 } else 690 displaydev = sc->sc_pp->ide_name; 691 692 /* if displaydev == NULL, printf is done in chip-specific map */ 693 if (displaydev) 694 printf(": %s (rev. 0x%02x)\n", displaydev, 695 PCI_REVISION(pa->pa_class)); 696 697 sc->sc_pc = pa->pa_pc; 698 sc->sc_tag = pa->pa_tag; 699 #ifdef WDCDEBUG 700 if (wdcdebug_pciide_mask & DEBUG_PROBE) 701 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 702 #endif 703 sc->sc_pp->chip_map(sc, pa); 704 705 if (sc->sc_dma_ok) { 706 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 707 csr |= PCI_COMMAND_MASTER_ENABLE; 708 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 709 } 710 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 711 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 712 } 713 714 /* tell wether the chip is enabled or not */ 715 int 716 pciide_chipen(sc, pa) 717 struct pciide_softc *sc; 718 struct pci_attach_args *pa; 719 { 720 pcireg_t csr; 721 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 722 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 723 PCI_COMMAND_STATUS_REG); 724 printf("%s: device disabled (at %s)\n", 725 sc->sc_wdcdev.sc_dev.dv_xname, 726 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 727 "device" : "bridge"); 728 return 0; 729 } 730 return 1; 731 } 732 733 int 734 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 735 struct pci_attach_args *pa; 736 struct pciide_channel *cp; 737 int compatchan; 738 bus_size_t *cmdsizep, *ctlsizep; 739 { 740 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 741 struct channel_softc *wdc_cp = &cp->wdc_channel; 742 743 cp->compat = 1; 744 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 745 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 746 747 wdc_cp->cmd_iot = pa->pa_iot; 748 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 749 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 750 printf("%s: couldn't map %s channel cmd regs\n", 751 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 752 return (0); 753 } 754 755 wdc_cp->ctl_iot = pa->pa_iot; 756 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 757 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 758 printf("%s: couldn't map %s channel ctl regs\n", 759 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 760 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 761 PCIIDE_COMPAT_CMD_SIZE); 762 return (0); 763 } 764 765 return (1); 766 } 767 768 int 769 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 770 struct pci_attach_args * pa; 771 struct pciide_channel *cp; 772 bus_size_t *cmdsizep, *ctlsizep; 773 int (*pci_intr) __P((void *)); 774 { 775 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 776 struct channel_softc *wdc_cp = &cp->wdc_channel; 777 const char *intrstr; 778 pci_intr_handle_t intrhandle; 779 780 cp->compat = 0; 781 782 if (sc->sc_pci_ih == NULL) { 783 if (pci_intr_map(pa, &intrhandle) != 0) { 784 printf("%s: couldn't map native-PCI interrupt\n", 785 sc->sc_wdcdev.sc_dev.dv_xname); 786 return 0; 787 } 788 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 789 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 790 intrhandle, IPL_BIO, pci_intr, sc); 791 if (sc->sc_pci_ih != NULL) { 792 printf("%s: using %s for native-PCI interrupt\n", 793 sc->sc_wdcdev.sc_dev.dv_xname, 794 intrstr ? intrstr : "unknown interrupt"); 795 } else { 796 printf("%s: couldn't establish native-PCI interrupt", 797 sc->sc_wdcdev.sc_dev.dv_xname); 798 if (intrstr != NULL) 799 printf(" at %s", intrstr); 800 printf("\n"); 801 return 0; 802 } 803 } 804 cp->ih = sc->sc_pci_ih; 805 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 806 PCI_MAPREG_TYPE_IO, 0, 807 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 808 printf("%s: couldn't map %s channel cmd regs\n", 809 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 810 return 0; 811 } 812 813 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 814 PCI_MAPREG_TYPE_IO, 0, 815 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 816 printf("%s: couldn't map %s channel ctl regs\n", 817 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 818 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 819 return 0; 820 } 821 /* 822 * In native mode, 4 bytes of I/O space are mapped for the control 823 * register, the control register is at offset 2. Pass the generic 824 * code a handle for only one byte at the rigth offset. 825 */ 826 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 827 &wdc_cp->ctl_ioh) != 0) { 828 printf("%s: unable to subregion %s channel ctl regs\n", 829 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 830 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 831 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 832 return 0; 833 } 834 return (1); 835 } 836 837 void 838 pciide_mapreg_dma(sc, pa) 839 struct pciide_softc *sc; 840 struct pci_attach_args *pa; 841 { 842 pcireg_t maptype; 843 bus_addr_t addr; 844 845 /* 846 * Map DMA registers 847 * 848 * Note that sc_dma_ok is the right variable to test to see if 849 * DMA can be done. If the interface doesn't support DMA, 850 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 851 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 852 * non-zero if the interface supports DMA and the registers 853 * could be mapped. 854 * 855 * XXX Note that despite the fact that the Bus Master IDE specs 856 * XXX say that "The bus master IDE function uses 16 bytes of IO 857 * XXX space," some controllers (at least the United 858 * XXX Microelectronics UM8886BF) place it in memory space. 859 */ 860 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 861 PCIIDE_REG_BUS_MASTER_DMA); 862 863 switch (maptype) { 864 case PCI_MAPREG_TYPE_IO: 865 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 866 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 867 &addr, NULL, NULL) == 0); 868 if (sc->sc_dma_ok == 0) { 869 printf(", but unused (couldn't query registers)"); 870 break; 871 } 872 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 873 && addr >= 0x10000) { 874 sc->sc_dma_ok = 0; 875 printf(", but unused (registers at unsafe address " 876 "%#lx)", (unsigned long)addr); 877 break; 878 } 879 /* FALLTHROUGH */ 880 881 case PCI_MAPREG_MEM_TYPE_32BIT: 882 sc->sc_dma_ok = (pci_mapreg_map(pa, 883 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 884 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 885 sc->sc_dmat = pa->pa_dmat; 886 if (sc->sc_dma_ok == 0) { 887 printf(", but unused (couldn't map registers)"); 888 } else { 889 sc->sc_wdcdev.dma_arg = sc; 890 sc->sc_wdcdev.dma_init = pciide_dma_init; 891 sc->sc_wdcdev.dma_start = pciide_dma_start; 892 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 893 } 894 895 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 896 PCIIDE_OPTIONS_NODMA) { 897 printf(", but unused (forced off by config file)"); 898 sc->sc_dma_ok = 0; 899 } 900 break; 901 902 default: 903 sc->sc_dma_ok = 0; 904 printf(", but unsupported register maptype (0x%x)", maptype); 905 } 906 } 907 908 int 909 pciide_compat_intr(arg) 910 void *arg; 911 { 912 struct pciide_channel *cp = arg; 913 914 #ifdef DIAGNOSTIC 915 /* should only be called for a compat channel */ 916 if (cp->compat == 0) 917 panic("pciide compat intr called for non-compat chan %p\n", cp); 918 #endif 919 return (wdcintr(&cp->wdc_channel)); 920 } 921 922 int 923 pciide_pci_intr(arg) 924 void *arg; 925 { 926 struct pciide_softc *sc = arg; 927 struct pciide_channel *cp; 928 struct channel_softc *wdc_cp; 929 int i, rv, crv; 930 931 rv = 0; 932 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 933 cp = &sc->pciide_channels[i]; 934 wdc_cp = &cp->wdc_channel; 935 936 /* If a compat channel skip. */ 937 if (cp->compat) 938 continue; 939 /* if this channel not waiting for intr, skip */ 940 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 941 continue; 942 943 crv = wdcintr(wdc_cp); 944 if (crv == 0) 945 ; /* leave rv alone */ 946 else if (crv == 1) 947 rv = 1; /* claim the intr */ 948 else if (rv == 0) /* crv should be -1 in this case */ 949 rv = crv; /* if we've done no better, take it */ 950 } 951 return (rv); 952 } 953 954 void 955 pciide_channel_dma_setup(cp) 956 struct pciide_channel *cp; 957 { 958 int drive; 959 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 960 struct ata_drive_datas *drvp; 961 962 for (drive = 0; drive < 2; drive++) { 963 drvp = &cp->wdc_channel.ch_drive[drive]; 964 /* If no drive, skip */ 965 if ((drvp->drive_flags & DRIVE) == 0) 966 continue; 967 /* setup DMA if needed */ 968 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 969 (drvp->drive_flags & DRIVE_UDMA) == 0) || 970 sc->sc_dma_ok == 0) { 971 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 972 continue; 973 } 974 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 975 != 0) { 976 /* Abort DMA setup */ 977 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 978 continue; 979 } 980 } 981 } 982 983 int 984 pciide_dma_table_setup(sc, channel, drive) 985 struct pciide_softc *sc; 986 int channel, drive; 987 { 988 bus_dma_segment_t seg; 989 int error, rseg; 990 const bus_size_t dma_table_size = 991 sizeof(struct idedma_table) * NIDEDMA_TABLES; 992 struct pciide_dma_maps *dma_maps = 993 &sc->pciide_channels[channel].dma_maps[drive]; 994 995 /* If table was already allocated, just return */ 996 if (dma_maps->dma_table) 997 return 0; 998 999 /* Allocate memory for the DMA tables and map it */ 1000 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1001 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1002 BUS_DMA_NOWAIT)) != 0) { 1003 printf("%s:%d: unable to allocate table DMA for " 1004 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1005 channel, drive, error); 1006 return error; 1007 } 1008 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1009 dma_table_size, 1010 (caddr_t *)&dma_maps->dma_table, 1011 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1012 printf("%s:%d: unable to map table DMA for" 1013 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1014 channel, drive, error); 1015 return error; 1016 } 1017 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1018 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1019 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1020 1021 /* Create and load table DMA map for this disk */ 1022 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1023 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1024 &dma_maps->dmamap_table)) != 0) { 1025 printf("%s:%d: unable to create table DMA map for " 1026 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1027 channel, drive, error); 1028 return error; 1029 } 1030 if ((error = bus_dmamap_load(sc->sc_dmat, 1031 dma_maps->dmamap_table, 1032 dma_maps->dma_table, 1033 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1034 printf("%s:%d: unable to load table DMA map for " 1035 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1036 channel, drive, error); 1037 return error; 1038 } 1039 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1040 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1041 DEBUG_PROBE); 1042 /* Create a xfer DMA map for this drive */ 1043 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1044 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1045 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1046 &dma_maps->dmamap_xfer)) != 0) { 1047 printf("%s:%d: unable to create xfer DMA map for " 1048 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1049 channel, drive, error); 1050 return error; 1051 } 1052 return 0; 1053 } 1054 1055 int 1056 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1057 void *v; 1058 int channel, drive; 1059 void *databuf; 1060 size_t datalen; 1061 int flags; 1062 { 1063 struct pciide_softc *sc = v; 1064 int error, seg; 1065 struct pciide_dma_maps *dma_maps = 1066 &sc->pciide_channels[channel].dma_maps[drive]; 1067 1068 error = bus_dmamap_load(sc->sc_dmat, 1069 dma_maps->dmamap_xfer, 1070 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1071 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1072 if (error) { 1073 printf("%s:%d: unable to load xfer DMA map for" 1074 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1075 channel, drive, error); 1076 return error; 1077 } 1078 1079 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1080 dma_maps->dmamap_xfer->dm_mapsize, 1081 (flags & WDC_DMA_READ) ? 1082 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1083 1084 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1085 #ifdef DIAGNOSTIC 1086 /* A segment must not cross a 64k boundary */ 1087 { 1088 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1089 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1090 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1091 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1092 printf("pciide_dma: segment %d physical addr 0x%lx" 1093 " len 0x%lx not properly aligned\n", 1094 seg, phys, len); 1095 panic("pciide_dma: buf align"); 1096 } 1097 } 1098 #endif 1099 dma_maps->dma_table[seg].base_addr = 1100 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1101 dma_maps->dma_table[seg].byte_count = 1102 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1103 IDEDMA_BYTE_COUNT_MASK); 1104 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1105 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1106 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1107 1108 } 1109 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1110 htole32(IDEDMA_BYTE_COUNT_EOT); 1111 1112 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1113 dma_maps->dmamap_table->dm_mapsize, 1114 BUS_DMASYNC_PREWRITE); 1115 1116 /* Maps are ready. Start DMA function */ 1117 #ifdef DIAGNOSTIC 1118 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1119 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1120 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1121 panic("pciide_dma_init: table align"); 1122 } 1123 #endif 1124 1125 /* Clear status bits */ 1126 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1127 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1128 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1129 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1130 /* Write table addr */ 1131 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1132 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1133 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1134 /* set read/write */ 1135 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1136 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1137 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1138 /* remember flags */ 1139 dma_maps->dma_flags = flags; 1140 return 0; 1141 } 1142 1143 void 1144 pciide_dma_start(v, channel, drive) 1145 void *v; 1146 int channel, drive; 1147 { 1148 struct pciide_softc *sc = v; 1149 1150 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1151 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1152 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1153 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1154 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1155 } 1156 1157 int 1158 pciide_dma_finish(v, channel, drive, force) 1159 void *v; 1160 int channel, drive; 1161 int force; 1162 { 1163 struct pciide_softc *sc = v; 1164 u_int8_t status; 1165 int error = 0; 1166 struct pciide_dma_maps *dma_maps = 1167 &sc->pciide_channels[channel].dma_maps[drive]; 1168 1169 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1170 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1171 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1172 DEBUG_XFERS); 1173 1174 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1175 return WDC_DMAST_NOIRQ; 1176 1177 /* stop DMA channel */ 1178 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1179 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1180 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1181 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1182 1183 /* Unload the map of the data buffer */ 1184 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1185 dma_maps->dmamap_xfer->dm_mapsize, 1186 (dma_maps->dma_flags & WDC_DMA_READ) ? 1187 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1188 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1189 1190 if ((status & IDEDMA_CTL_ERR) != 0) { 1191 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1192 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1193 error |= WDC_DMAST_ERR; 1194 } 1195 1196 if ((status & IDEDMA_CTL_INTR) == 0) { 1197 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1198 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1199 drive, status); 1200 error |= WDC_DMAST_NOIRQ; 1201 } 1202 1203 if ((status & IDEDMA_CTL_ACT) != 0) { 1204 /* data underrun, may be a valid condition for ATAPI */ 1205 error |= WDC_DMAST_UNDER; 1206 } 1207 return error; 1208 } 1209 1210 void 1211 pciide_irqack(chp) 1212 struct channel_softc *chp; 1213 { 1214 struct pciide_channel *cp = (struct pciide_channel*)chp; 1215 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1216 1217 /* clear status bits in IDE DMA registers */ 1218 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1219 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1220 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1221 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1222 } 1223 1224 /* some common code used by several chip_map */ 1225 int 1226 pciide_chansetup(sc, channel, interface) 1227 struct pciide_softc *sc; 1228 int channel; 1229 pcireg_t interface; 1230 { 1231 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1232 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1233 cp->name = PCIIDE_CHANNEL_NAME(channel); 1234 cp->wdc_channel.channel = channel; 1235 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1236 cp->wdc_channel.ch_queue = 1237 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1238 if (cp->wdc_channel.ch_queue == NULL) { 1239 printf("%s %s channel: " 1240 "can't allocate memory for command queue", 1241 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1242 return 0; 1243 } 1244 printf("%s: %s channel %s to %s mode\n", 1245 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1246 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1247 "configured" : "wired", 1248 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1249 "native-PCI" : "compatibility"); 1250 return 1; 1251 } 1252 1253 /* some common code used by several chip channel_map */ 1254 void 1255 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1256 struct pci_attach_args *pa; 1257 struct pciide_channel *cp; 1258 pcireg_t interface; 1259 bus_size_t *cmdsizep, *ctlsizep; 1260 int (*pci_intr) __P((void *)); 1261 { 1262 struct channel_softc *wdc_cp = &cp->wdc_channel; 1263 1264 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1265 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1266 pci_intr); 1267 else 1268 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1269 wdc_cp->channel, cmdsizep, ctlsizep); 1270 1271 if (cp->hw_ok == 0) 1272 return; 1273 wdc_cp->data32iot = wdc_cp->cmd_iot; 1274 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1275 wdcattach(wdc_cp); 1276 } 1277 1278 /* 1279 * Generic code to call to know if a channel can be disabled. Return 1 1280 * if channel can be disabled, 0 if not 1281 */ 1282 int 1283 pciide_chan_candisable(cp) 1284 struct pciide_channel *cp; 1285 { 1286 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1287 struct channel_softc *wdc_cp = &cp->wdc_channel; 1288 1289 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1290 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1291 printf("%s: disabling %s channel (no drives)\n", 1292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1293 cp->hw_ok = 0; 1294 return 1; 1295 } 1296 return 0; 1297 } 1298 1299 /* 1300 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1301 * Set hw_ok=0 on failure 1302 */ 1303 void 1304 pciide_map_compat_intr(pa, cp, compatchan, interface) 1305 struct pci_attach_args *pa; 1306 struct pciide_channel *cp; 1307 int compatchan, interface; 1308 { 1309 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1310 struct channel_softc *wdc_cp = &cp->wdc_channel; 1311 1312 if (cp->hw_ok == 0) 1313 return; 1314 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1315 return; 1316 1317 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1318 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1319 pa, compatchan, pciide_compat_intr, cp); 1320 if (cp->ih == NULL) { 1321 #endif 1322 printf("%s: no compatibility interrupt for use by %s " 1323 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1324 cp->hw_ok = 0; 1325 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1326 } 1327 #endif 1328 } 1329 1330 void 1331 pciide_print_modes(cp) 1332 struct pciide_channel *cp; 1333 { 1334 wdc_print_modes(&cp->wdc_channel); 1335 } 1336 1337 void 1338 default_chip_map(sc, pa) 1339 struct pciide_softc *sc; 1340 struct pci_attach_args *pa; 1341 { 1342 struct pciide_channel *cp; 1343 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1344 pcireg_t csr; 1345 int channel, drive; 1346 struct ata_drive_datas *drvp; 1347 u_int8_t idedma_ctl; 1348 bus_size_t cmdsize, ctlsize; 1349 char *failreason; 1350 1351 if (pciide_chipen(sc, pa) == 0) 1352 return; 1353 1354 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1355 printf("%s: bus-master DMA support present", 1356 sc->sc_wdcdev.sc_dev.dv_xname); 1357 if (sc->sc_pp == &default_product_desc && 1358 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1359 PCIIDE_OPTIONS_DMA) == 0) { 1360 printf(", but unused (no driver support)"); 1361 sc->sc_dma_ok = 0; 1362 } else { 1363 pciide_mapreg_dma(sc, pa); 1364 if (sc->sc_dma_ok != 0) 1365 printf(", used without full driver " 1366 "support"); 1367 } 1368 } else { 1369 printf("%s: hardware does not support DMA", 1370 sc->sc_wdcdev.sc_dev.dv_xname); 1371 sc->sc_dma_ok = 0; 1372 } 1373 printf("\n"); 1374 if (sc->sc_dma_ok) { 1375 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1376 sc->sc_wdcdev.irqack = pciide_irqack; 1377 } 1378 sc->sc_wdcdev.PIO_cap = 0; 1379 sc->sc_wdcdev.DMA_cap = 0; 1380 1381 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1382 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1383 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1384 1385 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1386 cp = &sc->pciide_channels[channel]; 1387 if (pciide_chansetup(sc, channel, interface) == 0) 1388 continue; 1389 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1390 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1391 &ctlsize, pciide_pci_intr); 1392 } else { 1393 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1394 channel, &cmdsize, &ctlsize); 1395 } 1396 if (cp->hw_ok == 0) 1397 continue; 1398 /* 1399 * Check to see if something appears to be there. 1400 */ 1401 failreason = NULL; 1402 if (!wdcprobe(&cp->wdc_channel)) { 1403 failreason = "not responding; disabled or no drives?"; 1404 goto next; 1405 } 1406 /* 1407 * Now, make sure it's actually attributable to this PCI IDE 1408 * channel by trying to access the channel again while the 1409 * PCI IDE controller's I/O space is disabled. (If the 1410 * channel no longer appears to be there, it belongs to 1411 * this controller.) YUCK! 1412 */ 1413 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1414 PCI_COMMAND_STATUS_REG); 1415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1416 csr & ~PCI_COMMAND_IO_ENABLE); 1417 if (wdcprobe(&cp->wdc_channel)) 1418 failreason = "other hardware responding at addresses"; 1419 pci_conf_write(sc->sc_pc, sc->sc_tag, 1420 PCI_COMMAND_STATUS_REG, csr); 1421 next: 1422 if (failreason) { 1423 printf("%s: %s channel ignored (%s)\n", 1424 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1425 failreason); 1426 cp->hw_ok = 0; 1427 bus_space_unmap(cp->wdc_channel.cmd_iot, 1428 cp->wdc_channel.cmd_ioh, cmdsize); 1429 bus_space_unmap(cp->wdc_channel.ctl_iot, 1430 cp->wdc_channel.ctl_ioh, ctlsize); 1431 } else { 1432 pciide_map_compat_intr(pa, cp, channel, interface); 1433 } 1434 if (cp->hw_ok) { 1435 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1436 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1437 wdcattach(&cp->wdc_channel); 1438 } 1439 } 1440 1441 if (sc->sc_dma_ok == 0) 1442 return; 1443 1444 /* Allocate DMA maps */ 1445 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1446 idedma_ctl = 0; 1447 cp = &sc->pciide_channels[channel]; 1448 for (drive = 0; drive < 2; drive++) { 1449 drvp = &cp->wdc_channel.ch_drive[drive]; 1450 /* If no drive, skip */ 1451 if ((drvp->drive_flags & DRIVE) == 0) 1452 continue; 1453 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1454 continue; 1455 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1456 /* Abort DMA setup */ 1457 printf("%s:%d:%d: can't allocate DMA maps, " 1458 "using PIO transfers\n", 1459 sc->sc_wdcdev.sc_dev.dv_xname, 1460 channel, drive); 1461 drvp->drive_flags &= ~DRIVE_DMA; 1462 } 1463 printf("%s:%d:%d: using DMA data transfers\n", 1464 sc->sc_wdcdev.sc_dev.dv_xname, 1465 channel, drive); 1466 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1467 } 1468 if (idedma_ctl != 0) { 1469 /* Add software bits in status register */ 1470 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1471 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1472 idedma_ctl); 1473 } 1474 } 1475 } 1476 1477 void 1478 piix_chip_map(sc, pa) 1479 struct pciide_softc *sc; 1480 struct pci_attach_args *pa; 1481 { 1482 struct pciide_channel *cp; 1483 int channel; 1484 u_int32_t idetim; 1485 bus_size_t cmdsize, ctlsize; 1486 1487 if (pciide_chipen(sc, pa) == 0) 1488 return; 1489 1490 printf("%s: bus-master DMA support present", 1491 sc->sc_wdcdev.sc_dev.dv_xname); 1492 pciide_mapreg_dma(sc, pa); 1493 printf("\n"); 1494 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1495 WDC_CAPABILITY_MODE; 1496 if (sc->sc_dma_ok) { 1497 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1498 sc->sc_wdcdev.irqack = pciide_irqack; 1499 switch(sc->sc_pp->ide_product) { 1500 case PCI_PRODUCT_INTEL_82371AB_IDE: 1501 case PCI_PRODUCT_INTEL_82440MX_IDE: 1502 case PCI_PRODUCT_INTEL_82801AA_IDE: 1503 case PCI_PRODUCT_INTEL_82801AB_IDE: 1504 case PCI_PRODUCT_INTEL_82801BA_IDE: 1505 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1506 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1507 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1508 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1509 } 1510 } 1511 sc->sc_wdcdev.PIO_cap = 4; 1512 sc->sc_wdcdev.DMA_cap = 2; 1513 switch(sc->sc_pp->ide_product) { 1514 case PCI_PRODUCT_INTEL_82801AA_IDE: 1515 sc->sc_wdcdev.UDMA_cap = 4; 1516 break; 1517 case PCI_PRODUCT_INTEL_82801BA_IDE: 1518 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1519 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1520 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1521 sc->sc_wdcdev.UDMA_cap = 5; 1522 break; 1523 default: 1524 sc->sc_wdcdev.UDMA_cap = 2; 1525 } 1526 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1527 sc->sc_wdcdev.set_modes = piix_setup_channel; 1528 else 1529 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1530 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1531 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1532 1533 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1534 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1535 DEBUG_PROBE); 1536 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1537 WDCDEBUG_PRINT((", sidetim=0x%x", 1538 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1539 DEBUG_PROBE); 1540 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1541 WDCDEBUG_PRINT((", udamreg 0x%x", 1542 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1543 DEBUG_PROBE); 1544 } 1545 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1551 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1552 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1553 DEBUG_PROBE); 1554 } 1555 1556 } 1557 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1558 1559 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1560 cp = &sc->pciide_channels[channel]; 1561 /* PIIX is compat-only */ 1562 if (pciide_chansetup(sc, channel, 0) == 0) 1563 continue; 1564 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1565 if ((PIIX_IDETIM_READ(idetim, channel) & 1566 PIIX_IDETIM_IDE) == 0) { 1567 printf("%s: %s channel ignored (disabled)\n", 1568 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1569 continue; 1570 } 1571 /* PIIX are compat-only pciide devices */ 1572 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1573 if (cp->hw_ok == 0) 1574 continue; 1575 if (pciide_chan_candisable(cp)) { 1576 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1577 channel); 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1579 idetim); 1580 } 1581 pciide_map_compat_intr(pa, cp, channel, 0); 1582 if (cp->hw_ok == 0) 1583 continue; 1584 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1585 } 1586 1587 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1588 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1589 DEBUG_PROBE); 1590 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1591 WDCDEBUG_PRINT((", sidetim=0x%x", 1592 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1593 DEBUG_PROBE); 1594 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1595 WDCDEBUG_PRINT((", udamreg 0x%x", 1596 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1597 DEBUG_PROBE); 1598 } 1599 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1600 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1601 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1602 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1603 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1604 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1605 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1606 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1607 DEBUG_PROBE); 1608 } 1609 } 1610 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1611 } 1612 1613 void 1614 piix_setup_channel(chp) 1615 struct channel_softc *chp; 1616 { 1617 u_int8_t mode[2], drive; 1618 u_int32_t oidetim, idetim, idedma_ctl; 1619 struct pciide_channel *cp = (struct pciide_channel*)chp; 1620 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1621 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1622 1623 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1624 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1625 idedma_ctl = 0; 1626 1627 /* set up new idetim: Enable IDE registers decode */ 1628 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1629 chp->channel); 1630 1631 /* setup DMA */ 1632 pciide_channel_dma_setup(cp); 1633 1634 /* 1635 * Here we have to mess up with drives mode: PIIX can't have 1636 * different timings for master and slave drives. 1637 * We need to find the best combination. 1638 */ 1639 1640 /* If both drives supports DMA, take the lower mode */ 1641 if ((drvp[0].drive_flags & DRIVE_DMA) && 1642 (drvp[1].drive_flags & DRIVE_DMA)) { 1643 mode[0] = mode[1] = 1644 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1645 drvp[0].DMA_mode = mode[0]; 1646 drvp[1].DMA_mode = mode[1]; 1647 goto ok; 1648 } 1649 /* 1650 * If only one drive supports DMA, use its mode, and 1651 * put the other one in PIO mode 0 if mode not compatible 1652 */ 1653 if (drvp[0].drive_flags & DRIVE_DMA) { 1654 mode[0] = drvp[0].DMA_mode; 1655 mode[1] = drvp[1].PIO_mode; 1656 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1657 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1658 mode[1] = drvp[1].PIO_mode = 0; 1659 goto ok; 1660 } 1661 if (drvp[1].drive_flags & DRIVE_DMA) { 1662 mode[1] = drvp[1].DMA_mode; 1663 mode[0] = drvp[0].PIO_mode; 1664 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1665 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1666 mode[0] = drvp[0].PIO_mode = 0; 1667 goto ok; 1668 } 1669 /* 1670 * If both drives are not DMA, takes the lower mode, unless 1671 * one of them is PIO mode < 2 1672 */ 1673 if (drvp[0].PIO_mode < 2) { 1674 mode[0] = drvp[0].PIO_mode = 0; 1675 mode[1] = drvp[1].PIO_mode; 1676 } else if (drvp[1].PIO_mode < 2) { 1677 mode[1] = drvp[1].PIO_mode = 0; 1678 mode[0] = drvp[0].PIO_mode; 1679 } else { 1680 mode[0] = mode[1] = 1681 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1682 drvp[0].PIO_mode = mode[0]; 1683 drvp[1].PIO_mode = mode[1]; 1684 } 1685 ok: /* The modes are setup */ 1686 for (drive = 0; drive < 2; drive++) { 1687 if (drvp[drive].drive_flags & DRIVE_DMA) { 1688 idetim |= piix_setup_idetim_timings( 1689 mode[drive], 1, chp->channel); 1690 goto end; 1691 } 1692 } 1693 /* If we are there, none of the drives are DMA */ 1694 if (mode[0] >= 2) 1695 idetim |= piix_setup_idetim_timings( 1696 mode[0], 0, chp->channel); 1697 else 1698 idetim |= piix_setup_idetim_timings( 1699 mode[1], 0, chp->channel); 1700 end: /* 1701 * timing mode is now set up in the controller. Enable 1702 * it per-drive 1703 */ 1704 for (drive = 0; drive < 2; drive++) { 1705 /* If no drive, skip */ 1706 if ((drvp[drive].drive_flags & DRIVE) == 0) 1707 continue; 1708 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1709 if (drvp[drive].drive_flags & DRIVE_DMA) 1710 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1711 } 1712 if (idedma_ctl != 0) { 1713 /* Add software bits in status register */ 1714 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1715 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1716 idedma_ctl); 1717 } 1718 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1719 pciide_print_modes(cp); 1720 } 1721 1722 void 1723 piix3_4_setup_channel(chp) 1724 struct channel_softc *chp; 1725 { 1726 struct ata_drive_datas *drvp; 1727 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1728 struct pciide_channel *cp = (struct pciide_channel*)chp; 1729 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1730 int drive; 1731 int channel = chp->channel; 1732 1733 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1734 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1735 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1736 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1737 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1738 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1739 PIIX_SIDETIM_RTC_MASK(channel)); 1740 1741 idedma_ctl = 0; 1742 /* If channel disabled, no need to go further */ 1743 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1744 return; 1745 /* set up new idetim: Enable IDE registers decode */ 1746 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1747 1748 /* setup DMA if needed */ 1749 pciide_channel_dma_setup(cp); 1750 1751 for (drive = 0; drive < 2; drive++) { 1752 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1753 PIIX_UDMATIM_SET(0x3, channel, drive)); 1754 drvp = &chp->ch_drive[drive]; 1755 /* If no drive, skip */ 1756 if ((drvp->drive_flags & DRIVE) == 0) 1757 continue; 1758 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1759 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1760 goto pio; 1761 1762 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1763 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1764 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1765 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1766 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1767 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1768 ideconf |= PIIX_CONFIG_PINGPONG; 1769 } 1770 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1771 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1772 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1773 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1774 /* setup Ultra/100 */ 1775 if (drvp->UDMA_mode > 2 && 1776 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1777 drvp->UDMA_mode = 2; 1778 if (drvp->UDMA_mode > 4) { 1779 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1780 } else { 1781 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1782 if (drvp->UDMA_mode > 2) { 1783 ideconf |= PIIX_CONFIG_UDMA66(channel, 1784 drive); 1785 } else { 1786 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1787 drive); 1788 } 1789 } 1790 } 1791 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1792 /* setup Ultra/66 */ 1793 if (drvp->UDMA_mode > 2 && 1794 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1795 drvp->UDMA_mode = 2; 1796 if (drvp->UDMA_mode > 2) 1797 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1798 else 1799 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1800 } 1801 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1802 (drvp->drive_flags & DRIVE_UDMA)) { 1803 /* use Ultra/DMA */ 1804 drvp->drive_flags &= ~DRIVE_DMA; 1805 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1806 udmareg |= PIIX_UDMATIM_SET( 1807 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1808 } else { 1809 /* use Multiword DMA */ 1810 drvp->drive_flags &= ~DRIVE_UDMA; 1811 if (drive == 0) { 1812 idetim |= piix_setup_idetim_timings( 1813 drvp->DMA_mode, 1, channel); 1814 } else { 1815 sidetim |= piix_setup_sidetim_timings( 1816 drvp->DMA_mode, 1, channel); 1817 idetim =PIIX_IDETIM_SET(idetim, 1818 PIIX_IDETIM_SITRE, channel); 1819 } 1820 } 1821 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1822 1823 pio: /* use PIO mode */ 1824 idetim |= piix_setup_idetim_drvs(drvp); 1825 if (drive == 0) { 1826 idetim |= piix_setup_idetim_timings( 1827 drvp->PIO_mode, 0, channel); 1828 } else { 1829 sidetim |= piix_setup_sidetim_timings( 1830 drvp->PIO_mode, 0, channel); 1831 idetim =PIIX_IDETIM_SET(idetim, 1832 PIIX_IDETIM_SITRE, channel); 1833 } 1834 } 1835 if (idedma_ctl != 0) { 1836 /* Add software bits in status register */ 1837 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1838 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1839 idedma_ctl); 1840 } 1841 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1842 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1843 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1844 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1845 pciide_print_modes(cp); 1846 } 1847 1848 1849 /* setup ISP and RTC fields, based on mode */ 1850 static u_int32_t 1851 piix_setup_idetim_timings(mode, dma, channel) 1852 u_int8_t mode; 1853 u_int8_t dma; 1854 u_int8_t channel; 1855 { 1856 1857 if (dma) 1858 return PIIX_IDETIM_SET(0, 1859 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1860 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1861 channel); 1862 else 1863 return PIIX_IDETIM_SET(0, 1864 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1865 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1866 channel); 1867 } 1868 1869 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1870 static u_int32_t 1871 piix_setup_idetim_drvs(drvp) 1872 struct ata_drive_datas *drvp; 1873 { 1874 u_int32_t ret = 0; 1875 struct channel_softc *chp = drvp->chnl_softc; 1876 u_int8_t channel = chp->channel; 1877 u_int8_t drive = drvp->drive; 1878 1879 /* 1880 * If drive is using UDMA, timings setups are independant 1881 * So just check DMA and PIO here. 1882 */ 1883 if (drvp->drive_flags & DRIVE_DMA) { 1884 /* if mode = DMA mode 0, use compatible timings */ 1885 if ((drvp->drive_flags & DRIVE_DMA) && 1886 drvp->DMA_mode == 0) { 1887 drvp->PIO_mode = 0; 1888 return ret; 1889 } 1890 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1891 /* 1892 * PIO and DMA timings are the same, use fast timings for PIO 1893 * too, else use compat timings. 1894 */ 1895 if ((piix_isp_pio[drvp->PIO_mode] != 1896 piix_isp_dma[drvp->DMA_mode]) || 1897 (piix_rtc_pio[drvp->PIO_mode] != 1898 piix_rtc_dma[drvp->DMA_mode])) 1899 drvp->PIO_mode = 0; 1900 /* if PIO mode <= 2, use compat timings for PIO */ 1901 if (drvp->PIO_mode <= 2) { 1902 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1903 channel); 1904 return ret; 1905 } 1906 } 1907 1908 /* 1909 * Now setup PIO modes. If mode < 2, use compat timings. 1910 * Else enable fast timings. Enable IORDY and prefetch/post 1911 * if PIO mode >= 3. 1912 */ 1913 1914 if (drvp->PIO_mode < 2) 1915 return ret; 1916 1917 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1918 if (drvp->PIO_mode >= 3) { 1919 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1920 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1921 } 1922 return ret; 1923 } 1924 1925 /* setup values in SIDETIM registers, based on mode */ 1926 static u_int32_t 1927 piix_setup_sidetim_timings(mode, dma, channel) 1928 u_int8_t mode; 1929 u_int8_t dma; 1930 u_int8_t channel; 1931 { 1932 if (dma) 1933 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1934 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1935 else 1936 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1937 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1938 } 1939 1940 void 1941 amd7x6_chip_map(sc, pa) 1942 struct pciide_softc *sc; 1943 struct pci_attach_args *pa; 1944 { 1945 struct pciide_channel *cp; 1946 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1947 int channel; 1948 pcireg_t chanenable; 1949 bus_size_t cmdsize, ctlsize; 1950 1951 if (pciide_chipen(sc, pa) == 0) 1952 return; 1953 printf("%s: bus-master DMA support present", 1954 sc->sc_wdcdev.sc_dev.dv_xname); 1955 pciide_mapreg_dma(sc, pa); 1956 printf("\n"); 1957 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1958 WDC_CAPABILITY_MODE; 1959 if (sc->sc_dma_ok) { 1960 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1961 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1962 sc->sc_wdcdev.irqack = pciide_irqack; 1963 } 1964 sc->sc_wdcdev.PIO_cap = 4; 1965 sc->sc_wdcdev.DMA_cap = 2; 1966 1967 switch (sc->sc_pp->ide_product) { 1968 case PCI_PRODUCT_AMD_PBC766_IDE: 1969 case PCI_PRODUCT_AMD_PBC768_IDE: 1970 sc->sc_wdcdev.UDMA_cap = 5; 1971 break; 1972 default: 1973 sc->sc_wdcdev.UDMA_cap = 4; 1974 } 1975 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1976 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1977 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1978 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1979 1980 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1981 DEBUG_PROBE); 1982 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1983 cp = &sc->pciide_channels[channel]; 1984 if (pciide_chansetup(sc, channel, interface) == 0) 1985 continue; 1986 1987 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1988 printf("%s: %s channel ignored (disabled)\n", 1989 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1990 continue; 1991 } 1992 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1993 pciide_pci_intr); 1994 1995 if (pciide_chan_candisable(cp)) 1996 chanenable &= ~AMD7X6_CHAN_EN(channel); 1997 pciide_map_compat_intr(pa, cp, channel, interface); 1998 if (cp->hw_ok == 0) 1999 continue; 2000 2001 amd7x6_setup_channel(&cp->wdc_channel); 2002 } 2003 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2004 chanenable); 2005 return; 2006 } 2007 2008 void 2009 amd7x6_setup_channel(chp) 2010 struct channel_softc *chp; 2011 { 2012 u_int32_t udmatim_reg, datatim_reg; 2013 u_int8_t idedma_ctl; 2014 int mode, drive; 2015 struct ata_drive_datas *drvp; 2016 struct pciide_channel *cp = (struct pciide_channel*)chp; 2017 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2018 #ifndef PCIIDE_AMD756_ENABLEDMA 2019 int rev = PCI_REVISION( 2020 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2021 #endif 2022 2023 idedma_ctl = 0; 2024 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2025 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2026 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2027 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2028 2029 /* setup DMA if needed */ 2030 pciide_channel_dma_setup(cp); 2031 2032 for (drive = 0; drive < 2; drive++) { 2033 drvp = &chp->ch_drive[drive]; 2034 /* If no drive, skip */ 2035 if ((drvp->drive_flags & DRIVE) == 0) 2036 continue; 2037 /* add timing values, setup DMA if needed */ 2038 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2039 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2040 mode = drvp->PIO_mode; 2041 goto pio; 2042 } 2043 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2044 (drvp->drive_flags & DRIVE_UDMA)) { 2045 /* use Ultra/DMA */ 2046 drvp->drive_flags &= ~DRIVE_DMA; 2047 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2048 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2049 AMD7X6_UDMA_TIME(chp->channel, drive, 2050 amd7x6_udma_tim[drvp->UDMA_mode]); 2051 /* can use PIO timings, MW DMA unused */ 2052 mode = drvp->PIO_mode; 2053 } else { 2054 /* use Multiword DMA, but only if revision is OK */ 2055 drvp->drive_flags &= ~DRIVE_UDMA; 2056 #ifndef PCIIDE_AMD756_ENABLEDMA 2057 /* 2058 * The workaround doesn't seem to be necessary 2059 * with all drives, so it can be disabled by 2060 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2061 * triggered. 2062 */ 2063 if (sc->sc_pp->ide_product == 2064 PCI_PRODUCT_AMD_PBC756_IDE && 2065 AMD756_CHIPREV_DISABLEDMA(rev)) { 2066 printf("%s:%d:%d: multi-word DMA disabled due " 2067 "to chip revision\n", 2068 sc->sc_wdcdev.sc_dev.dv_xname, 2069 chp->channel, drive); 2070 mode = drvp->PIO_mode; 2071 drvp->drive_flags &= ~DRIVE_DMA; 2072 goto pio; 2073 } 2074 #endif 2075 /* mode = min(pio, dma+2) */ 2076 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2077 mode = drvp->PIO_mode; 2078 else 2079 mode = drvp->DMA_mode + 2; 2080 } 2081 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2082 2083 pio: /* setup PIO mode */ 2084 if (mode <= 2) { 2085 drvp->DMA_mode = 0; 2086 drvp->PIO_mode = 0; 2087 mode = 0; 2088 } else { 2089 drvp->PIO_mode = mode; 2090 drvp->DMA_mode = mode - 2; 2091 } 2092 datatim_reg |= 2093 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2094 amd7x6_pio_set[mode]) | 2095 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2096 amd7x6_pio_rec[mode]); 2097 } 2098 if (idedma_ctl != 0) { 2099 /* Add software bits in status register */ 2100 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2101 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2102 idedma_ctl); 2103 } 2104 pciide_print_modes(cp); 2105 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2106 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2107 } 2108 2109 void 2110 apollo_chip_map(sc, pa) 2111 struct pciide_softc *sc; 2112 struct pci_attach_args *pa; 2113 { 2114 struct pciide_channel *cp; 2115 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2116 int channel; 2117 u_int32_t ideconf; 2118 bus_size_t cmdsize, ctlsize; 2119 pcitag_t pcib_tag; 2120 pcireg_t pcib_id, pcib_class; 2121 2122 if (pciide_chipen(sc, pa) == 0) 2123 return; 2124 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2125 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2126 /* and read ID and rev of the ISA bridge */ 2127 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2128 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2129 printf(": VIA Technologies "); 2130 switch (PCI_PRODUCT(pcib_id)) { 2131 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2132 printf("VT82C586 (Apollo VP) "); 2133 if(PCI_REVISION(pcib_class) >= 0x02) { 2134 printf("ATA33 controller\n"); 2135 sc->sc_wdcdev.UDMA_cap = 2; 2136 } else { 2137 printf("controller\n"); 2138 sc->sc_wdcdev.UDMA_cap = 0; 2139 } 2140 break; 2141 case PCI_PRODUCT_VIATECH_VT82C596A: 2142 printf("VT82C596A (Apollo Pro) "); 2143 if (PCI_REVISION(pcib_class) >= 0x12) { 2144 printf("ATA66 controller\n"); 2145 sc->sc_wdcdev.UDMA_cap = 4; 2146 } else { 2147 printf("ATA33 controller\n"); 2148 sc->sc_wdcdev.UDMA_cap = 2; 2149 } 2150 break; 2151 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2152 printf("VT82C686A (Apollo KX133) "); 2153 if (PCI_REVISION(pcib_class) >= 0x40) { 2154 printf("ATA100 controller\n"); 2155 sc->sc_wdcdev.UDMA_cap = 5; 2156 } else { 2157 printf("ATA66 controller\n"); 2158 sc->sc_wdcdev.UDMA_cap = 4; 2159 } 2160 break; 2161 case PCI_PRODUCT_VIATECH_VT8233: 2162 printf("VT8233 ATA100 controller\n"); 2163 sc->sc_wdcdev.UDMA_cap = 5; 2164 break; 2165 default: 2166 printf("unknown ATA controller\n"); 2167 sc->sc_wdcdev.UDMA_cap = 0; 2168 } 2169 2170 printf("%s: bus-master DMA support present", 2171 sc->sc_wdcdev.sc_dev.dv_xname); 2172 pciide_mapreg_dma(sc, pa); 2173 printf("\n"); 2174 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2175 WDC_CAPABILITY_MODE; 2176 if (sc->sc_dma_ok) { 2177 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2178 sc->sc_wdcdev.irqack = pciide_irqack; 2179 if (sc->sc_wdcdev.UDMA_cap > 0) 2180 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2181 } 2182 sc->sc_wdcdev.PIO_cap = 4; 2183 sc->sc_wdcdev.DMA_cap = 2; 2184 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2185 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2186 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2187 2188 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2189 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2190 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2191 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2192 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2193 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2194 DEBUG_PROBE); 2195 2196 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2197 cp = &sc->pciide_channels[channel]; 2198 if (pciide_chansetup(sc, channel, interface) == 0) 2199 continue; 2200 2201 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2202 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2203 printf("%s: %s channel ignored (disabled)\n", 2204 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2205 continue; 2206 } 2207 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2208 pciide_pci_intr); 2209 if (cp->hw_ok == 0) 2210 continue; 2211 if (pciide_chan_candisable(cp)) { 2212 ideconf &= ~APO_IDECONF_EN(channel); 2213 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2214 ideconf); 2215 } 2216 pciide_map_compat_intr(pa, cp, channel, interface); 2217 2218 if (cp->hw_ok == 0) 2219 continue; 2220 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2221 } 2222 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2223 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2224 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2225 } 2226 2227 void 2228 apollo_setup_channel(chp) 2229 struct channel_softc *chp; 2230 { 2231 u_int32_t udmatim_reg, datatim_reg; 2232 u_int8_t idedma_ctl; 2233 int mode, drive; 2234 struct ata_drive_datas *drvp; 2235 struct pciide_channel *cp = (struct pciide_channel*)chp; 2236 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2237 2238 idedma_ctl = 0; 2239 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2240 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2241 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2242 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2243 2244 /* setup DMA if needed */ 2245 pciide_channel_dma_setup(cp); 2246 2247 for (drive = 0; drive < 2; drive++) { 2248 drvp = &chp->ch_drive[drive]; 2249 /* If no drive, skip */ 2250 if ((drvp->drive_flags & DRIVE) == 0) 2251 continue; 2252 /* add timing values, setup DMA if needed */ 2253 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2254 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2255 mode = drvp->PIO_mode; 2256 goto pio; 2257 } 2258 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2259 (drvp->drive_flags & DRIVE_UDMA)) { 2260 /* use Ultra/DMA */ 2261 drvp->drive_flags &= ~DRIVE_DMA; 2262 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2263 APO_UDMA_EN_MTH(chp->channel, drive); 2264 if (sc->sc_wdcdev.UDMA_cap == 5) { 2265 /* 686b */ 2266 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2267 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2268 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2269 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2270 /* 596b or 686a */ 2271 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2272 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2273 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2274 } else { 2275 /* 596a or 586b */ 2276 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2277 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2278 } 2279 /* can use PIO timings, MW DMA unused */ 2280 mode = drvp->PIO_mode; 2281 } else { 2282 /* use Multiword DMA */ 2283 drvp->drive_flags &= ~DRIVE_UDMA; 2284 /* mode = min(pio, dma+2) */ 2285 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2286 mode = drvp->PIO_mode; 2287 else 2288 mode = drvp->DMA_mode + 2; 2289 } 2290 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2291 2292 pio: /* setup PIO mode */ 2293 if (mode <= 2) { 2294 drvp->DMA_mode = 0; 2295 drvp->PIO_mode = 0; 2296 mode = 0; 2297 } else { 2298 drvp->PIO_mode = mode; 2299 drvp->DMA_mode = mode - 2; 2300 } 2301 datatim_reg |= 2302 APO_DATATIM_PULSE(chp->channel, drive, 2303 apollo_pio_set[mode]) | 2304 APO_DATATIM_RECOV(chp->channel, drive, 2305 apollo_pio_rec[mode]); 2306 } 2307 if (idedma_ctl != 0) { 2308 /* Add software bits in status register */ 2309 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2310 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2311 idedma_ctl); 2312 } 2313 pciide_print_modes(cp); 2314 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2315 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2316 } 2317 2318 void 2319 cmd_channel_map(pa, sc, channel) 2320 struct pci_attach_args *pa; 2321 struct pciide_softc *sc; 2322 int channel; 2323 { 2324 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2325 bus_size_t cmdsize, ctlsize; 2326 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2327 int interface, one_channel; 2328 2329 /* 2330 * The 0648/0649 can be told to identify as a RAID controller. 2331 * In this case, we have to fake interface 2332 */ 2333 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2334 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2335 PCIIDE_INTERFACE_SETTABLE(1); 2336 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2337 CMD_CONF_DSA1) 2338 interface |= PCIIDE_INTERFACE_PCI(0) | 2339 PCIIDE_INTERFACE_PCI(1); 2340 } else { 2341 interface = PCI_INTERFACE(pa->pa_class); 2342 } 2343 2344 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2345 cp->name = PCIIDE_CHANNEL_NAME(channel); 2346 cp->wdc_channel.channel = channel; 2347 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2348 2349 /* 2350 * Older CMD64X doesn't have independant channels 2351 */ 2352 switch (sc->sc_pp->ide_product) { 2353 case PCI_PRODUCT_CMDTECH_649: 2354 one_channel = 0; 2355 break; 2356 default: 2357 one_channel = 1; 2358 break; 2359 } 2360 2361 if (channel > 0 && one_channel) { 2362 cp->wdc_channel.ch_queue = 2363 sc->pciide_channels[0].wdc_channel.ch_queue; 2364 } else { 2365 cp->wdc_channel.ch_queue = 2366 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2367 } 2368 if (cp->wdc_channel.ch_queue == NULL) { 2369 printf("%s %s channel: " 2370 "can't allocate memory for command queue", 2371 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2372 return; 2373 } 2374 2375 printf("%s: %s channel %s to %s mode\n", 2376 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2377 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2378 "configured" : "wired", 2379 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2380 "native-PCI" : "compatibility"); 2381 2382 /* 2383 * with a CMD PCI64x, if we get here, the first channel is enabled: 2384 * there's no way to disable the first channel without disabling 2385 * the whole device 2386 */ 2387 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2388 printf("%s: %s channel ignored (disabled)\n", 2389 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2390 return; 2391 } 2392 2393 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2394 if (cp->hw_ok == 0) 2395 return; 2396 if (channel == 1) { 2397 if (pciide_chan_candisable(cp)) { 2398 ctrl &= ~CMD_CTRL_2PORT; 2399 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2400 CMD_CTRL, ctrl); 2401 } 2402 } 2403 pciide_map_compat_intr(pa, cp, channel, interface); 2404 } 2405 2406 int 2407 cmd_pci_intr(arg) 2408 void *arg; 2409 { 2410 struct pciide_softc *sc = arg; 2411 struct pciide_channel *cp; 2412 struct channel_softc *wdc_cp; 2413 int i, rv, crv; 2414 u_int32_t priirq, secirq; 2415 2416 rv = 0; 2417 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2418 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2419 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2420 cp = &sc->pciide_channels[i]; 2421 wdc_cp = &cp->wdc_channel; 2422 /* If a compat channel skip. */ 2423 if (cp->compat) 2424 continue; 2425 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2426 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2427 crv = wdcintr(wdc_cp); 2428 if (crv == 0) 2429 printf("%s:%d: bogus intr\n", 2430 sc->sc_wdcdev.sc_dev.dv_xname, i); 2431 else 2432 rv = 1; 2433 } 2434 } 2435 return rv; 2436 } 2437 2438 void 2439 cmd_chip_map(sc, pa) 2440 struct pciide_softc *sc; 2441 struct pci_attach_args *pa; 2442 { 2443 int channel; 2444 2445 /* 2446 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2447 * and base adresses registers can be disabled at 2448 * hardware level. In this case, the device is wired 2449 * in compat mode and its first channel is always enabled, 2450 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2451 * In fact, it seems that the first channel of the CMD PCI0640 2452 * can't be disabled. 2453 */ 2454 2455 #ifdef PCIIDE_CMD064x_DISABLE 2456 if (pciide_chipen(sc, pa) == 0) 2457 return; 2458 #endif 2459 2460 printf("%s: hardware does not support DMA\n", 2461 sc->sc_wdcdev.sc_dev.dv_xname); 2462 sc->sc_dma_ok = 0; 2463 2464 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2465 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2466 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2467 2468 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2469 cmd_channel_map(pa, sc, channel); 2470 } 2471 } 2472 2473 void 2474 cmd0643_9_chip_map(sc, pa) 2475 struct pciide_softc *sc; 2476 struct pci_attach_args *pa; 2477 { 2478 struct pciide_channel *cp; 2479 int channel; 2480 pcireg_t rev = PCI_REVISION(pa->pa_class); 2481 2482 /* 2483 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2484 * and base adresses registers can be disabled at 2485 * hardware level. In this case, the device is wired 2486 * in compat mode and its first channel is always enabled, 2487 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2488 * In fact, it seems that the first channel of the CMD PCI0640 2489 * can't be disabled. 2490 */ 2491 2492 #ifdef PCIIDE_CMD064x_DISABLE 2493 if (pciide_chipen(sc, pa) == 0) 2494 return; 2495 #endif 2496 printf("%s: bus-master DMA support present", 2497 sc->sc_wdcdev.sc_dev.dv_xname); 2498 pciide_mapreg_dma(sc, pa); 2499 printf("\n"); 2500 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2501 WDC_CAPABILITY_MODE; 2502 if (sc->sc_dma_ok) { 2503 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2504 switch (sc->sc_pp->ide_product) { 2505 case PCI_PRODUCT_CMDTECH_649: 2506 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2507 sc->sc_wdcdev.UDMA_cap = 5; 2508 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2509 break; 2510 case PCI_PRODUCT_CMDTECH_648: 2511 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2512 sc->sc_wdcdev.UDMA_cap = 4; 2513 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2514 break; 2515 case PCI_PRODUCT_CMDTECH_646: 2516 if (rev >= CMD0646U2_REV) { 2517 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2518 sc->sc_wdcdev.UDMA_cap = 2; 2519 } else if (rev >= CMD0646U_REV) { 2520 /* 2521 * Linux's driver claims that the 646U is broken 2522 * with UDMA. Only enable it if we know what we're 2523 * doing 2524 */ 2525 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2526 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2527 sc->sc_wdcdev.UDMA_cap = 2; 2528 #endif 2529 /* explicitly disable UDMA */ 2530 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2531 CMD_UDMATIM(0), 0); 2532 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2533 CMD_UDMATIM(1), 0); 2534 } 2535 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2536 break; 2537 default: 2538 sc->sc_wdcdev.irqack = pciide_irqack; 2539 } 2540 } 2541 2542 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2543 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2544 sc->sc_wdcdev.PIO_cap = 4; 2545 sc->sc_wdcdev.DMA_cap = 2; 2546 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2547 2548 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2549 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2550 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2551 DEBUG_PROBE); 2552 2553 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2554 cp = &sc->pciide_channels[channel]; 2555 cmd_channel_map(pa, sc, channel); 2556 if (cp->hw_ok == 0) 2557 continue; 2558 cmd0643_9_setup_channel(&cp->wdc_channel); 2559 } 2560 /* 2561 * note - this also makes sure we clear the irq disable and reset 2562 * bits 2563 */ 2564 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2565 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2566 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2567 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2568 DEBUG_PROBE); 2569 } 2570 2571 void 2572 cmd0643_9_setup_channel(chp) 2573 struct channel_softc *chp; 2574 { 2575 struct ata_drive_datas *drvp; 2576 u_int8_t tim; 2577 u_int32_t idedma_ctl, udma_reg; 2578 int drive; 2579 struct pciide_channel *cp = (struct pciide_channel*)chp; 2580 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2581 2582 idedma_ctl = 0; 2583 /* setup DMA if needed */ 2584 pciide_channel_dma_setup(cp); 2585 2586 for (drive = 0; drive < 2; drive++) { 2587 drvp = &chp->ch_drive[drive]; 2588 /* If no drive, skip */ 2589 if ((drvp->drive_flags & DRIVE) == 0) 2590 continue; 2591 /* add timing values, setup DMA if needed */ 2592 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2593 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2594 if (drvp->drive_flags & DRIVE_UDMA) { 2595 /* UltraDMA on a 646U2, 0648 or 0649 */ 2596 drvp->drive_flags &= ~DRIVE_DMA; 2597 udma_reg = pciide_pci_read(sc->sc_pc, 2598 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2599 if (drvp->UDMA_mode > 2 && 2600 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2601 CMD_BICSR) & 2602 CMD_BICSR_80(chp->channel)) == 0) 2603 drvp->UDMA_mode = 2; 2604 if (drvp->UDMA_mode > 2) 2605 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2606 else if (sc->sc_wdcdev.UDMA_cap > 2) 2607 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2608 udma_reg |= CMD_UDMATIM_UDMA(drive); 2609 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2610 CMD_UDMATIM_TIM_OFF(drive)); 2611 udma_reg |= 2612 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2613 CMD_UDMATIM_TIM_OFF(drive)); 2614 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2615 CMD_UDMATIM(chp->channel), udma_reg); 2616 } else { 2617 /* 2618 * use Multiword DMA. 2619 * Timings will be used for both PIO and DMA, 2620 * so adjust DMA mode if needed 2621 * if we have a 0646U2/8/9, turn off UDMA 2622 */ 2623 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2624 udma_reg = pciide_pci_read(sc->sc_pc, 2625 sc->sc_tag, 2626 CMD_UDMATIM(chp->channel)); 2627 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2628 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2629 CMD_UDMATIM(chp->channel), 2630 udma_reg); 2631 } 2632 if (drvp->PIO_mode >= 3 && 2633 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2634 drvp->DMA_mode = drvp->PIO_mode - 2; 2635 } 2636 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2637 } 2638 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2639 } 2640 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2641 CMD_DATA_TIM(chp->channel, drive), tim); 2642 } 2643 if (idedma_ctl != 0) { 2644 /* Add software bits in status register */ 2645 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2646 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2647 idedma_ctl); 2648 } 2649 pciide_print_modes(cp); 2650 } 2651 2652 void 2653 cmd646_9_irqack(chp) 2654 struct channel_softc *chp; 2655 { 2656 u_int32_t priirq, secirq; 2657 struct pciide_channel *cp = (struct pciide_channel*)chp; 2658 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2659 2660 if (chp->channel == 0) { 2661 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2662 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2663 } else { 2664 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2665 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2666 } 2667 pciide_irqack(chp); 2668 } 2669 2670 void 2671 cy693_chip_map(sc, pa) 2672 struct pciide_softc *sc; 2673 struct pci_attach_args *pa; 2674 { 2675 struct pciide_channel *cp; 2676 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2677 bus_size_t cmdsize, ctlsize; 2678 2679 if (pciide_chipen(sc, pa) == 0) 2680 return; 2681 /* 2682 * this chip has 2 PCI IDE functions, one for primary and one for 2683 * secondary. So we need to call pciide_mapregs_compat() with 2684 * the real channel 2685 */ 2686 if (pa->pa_function == 1) { 2687 sc->sc_cy_compatchan = 0; 2688 } else if (pa->pa_function == 2) { 2689 sc->sc_cy_compatchan = 1; 2690 } else { 2691 printf("%s: unexpected PCI function %d\n", 2692 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2693 return; 2694 } 2695 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2696 printf("%s: bus-master DMA support present", 2697 sc->sc_wdcdev.sc_dev.dv_xname); 2698 pciide_mapreg_dma(sc, pa); 2699 } else { 2700 printf("%s: hardware does not support DMA", 2701 sc->sc_wdcdev.sc_dev.dv_xname); 2702 sc->sc_dma_ok = 0; 2703 } 2704 printf("\n"); 2705 2706 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2707 if (sc->sc_cy_handle == NULL) { 2708 printf("%s: unable to map hyperCache control registers\n", 2709 sc->sc_wdcdev.sc_dev.dv_xname); 2710 sc->sc_dma_ok = 0; 2711 } 2712 2713 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2714 WDC_CAPABILITY_MODE; 2715 if (sc->sc_dma_ok) { 2716 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2717 sc->sc_wdcdev.irqack = pciide_irqack; 2718 } 2719 sc->sc_wdcdev.PIO_cap = 4; 2720 sc->sc_wdcdev.DMA_cap = 2; 2721 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2722 2723 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2724 sc->sc_wdcdev.nchannels = 1; 2725 2726 /* Only one channel for this chip; if we are here it's enabled */ 2727 cp = &sc->pciide_channels[0]; 2728 sc->wdc_chanarray[0] = &cp->wdc_channel; 2729 cp->name = PCIIDE_CHANNEL_NAME(0); 2730 cp->wdc_channel.channel = 0; 2731 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2732 cp->wdc_channel.ch_queue = 2733 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2734 if (cp->wdc_channel.ch_queue == NULL) { 2735 printf("%s primary channel: " 2736 "can't allocate memory for command queue", 2737 sc->sc_wdcdev.sc_dev.dv_xname); 2738 return; 2739 } 2740 printf("%s: primary channel %s to ", 2741 sc->sc_wdcdev.sc_dev.dv_xname, 2742 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2743 "configured" : "wired"); 2744 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2745 printf("native-PCI"); 2746 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2747 pciide_pci_intr); 2748 } else { 2749 printf("compatibility"); 2750 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2751 &cmdsize, &ctlsize); 2752 } 2753 printf(" mode\n"); 2754 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2755 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2756 wdcattach(&cp->wdc_channel); 2757 if (pciide_chan_candisable(cp)) { 2758 pci_conf_write(sc->sc_pc, sc->sc_tag, 2759 PCI_COMMAND_STATUS_REG, 0); 2760 } 2761 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2762 if (cp->hw_ok == 0) 2763 return; 2764 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2765 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2766 cy693_setup_channel(&cp->wdc_channel); 2767 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2768 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2769 } 2770 2771 void 2772 cy693_setup_channel(chp) 2773 struct channel_softc *chp; 2774 { 2775 struct ata_drive_datas *drvp; 2776 int drive; 2777 u_int32_t cy_cmd_ctrl; 2778 u_int32_t idedma_ctl; 2779 struct pciide_channel *cp = (struct pciide_channel*)chp; 2780 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2781 int dma_mode = -1; 2782 2783 cy_cmd_ctrl = idedma_ctl = 0; 2784 2785 /* setup DMA if needed */ 2786 pciide_channel_dma_setup(cp); 2787 2788 for (drive = 0; drive < 2; drive++) { 2789 drvp = &chp->ch_drive[drive]; 2790 /* If no drive, skip */ 2791 if ((drvp->drive_flags & DRIVE) == 0) 2792 continue; 2793 /* add timing values, setup DMA if needed */ 2794 if (drvp->drive_flags & DRIVE_DMA) { 2795 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2796 /* use Multiword DMA */ 2797 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2798 dma_mode = drvp->DMA_mode; 2799 } 2800 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2801 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2802 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2803 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2804 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2805 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2806 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2807 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2808 } 2809 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2810 chp->ch_drive[0].DMA_mode = dma_mode; 2811 chp->ch_drive[1].DMA_mode = dma_mode; 2812 2813 if (dma_mode == -1) 2814 dma_mode = 0; 2815 2816 if (sc->sc_cy_handle != NULL) { 2817 /* Note: `multiple' is implied. */ 2818 cy82c693_write(sc->sc_cy_handle, 2819 (sc->sc_cy_compatchan == 0) ? 2820 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2821 } 2822 2823 pciide_print_modes(cp); 2824 2825 if (idedma_ctl != 0) { 2826 /* Add software bits in status register */ 2827 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2828 IDEDMA_CTL, idedma_ctl); 2829 } 2830 } 2831 2832 static int 2833 sis_hostbr_match(pa) 2834 struct pci_attach_args *pa; 2835 { 2836 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2837 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2838 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2839 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2840 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2841 } 2842 2843 void 2844 sis_chip_map(sc, pa) 2845 struct pciide_softc *sc; 2846 struct pci_attach_args *pa; 2847 { 2848 struct pciide_channel *cp; 2849 int channel; 2850 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2851 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2852 pcireg_t rev = PCI_REVISION(pa->pa_class); 2853 bus_size_t cmdsize, ctlsize; 2854 pcitag_t pchb_tag; 2855 pcireg_t pchb_id, pchb_class; 2856 2857 if (pciide_chipen(sc, pa) == 0) 2858 return; 2859 printf("%s: bus-master DMA support present", 2860 sc->sc_wdcdev.sc_dev.dv_xname); 2861 pciide_mapreg_dma(sc, pa); 2862 printf("\n"); 2863 2864 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2865 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2866 /* and read ID and rev of the ISA bridge */ 2867 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2868 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2869 2870 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2871 WDC_CAPABILITY_MODE; 2872 if (sc->sc_dma_ok) { 2873 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2874 sc->sc_wdcdev.irqack = pciide_irqack; 2875 /* 2876 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2877 * have problems with UDMA (info provided by Christos) 2878 */ 2879 if (rev >= 0xd0 && 2880 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2881 PCI_REVISION(pchb_class) >= 0x03)) 2882 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2883 } 2884 2885 sc->sc_wdcdev.PIO_cap = 4; 2886 sc->sc_wdcdev.DMA_cap = 2; 2887 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2888 /* 2889 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2890 * chipsets. 2891 */ 2892 sc->sc_wdcdev.UDMA_cap = 2893 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2894 sc->sc_wdcdev.set_modes = sis_setup_channel; 2895 2896 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2897 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2898 2899 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2900 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2901 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2902 2903 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2904 cp = &sc->pciide_channels[channel]; 2905 if (pciide_chansetup(sc, channel, interface) == 0) 2906 continue; 2907 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2908 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2909 printf("%s: %s channel ignored (disabled)\n", 2910 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2911 continue; 2912 } 2913 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2914 pciide_pci_intr); 2915 if (cp->hw_ok == 0) 2916 continue; 2917 if (pciide_chan_candisable(cp)) { 2918 if (channel == 0) 2919 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2920 else 2921 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2922 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2923 sis_ctr0); 2924 } 2925 pciide_map_compat_intr(pa, cp, channel, interface); 2926 if (cp->hw_ok == 0) 2927 continue; 2928 sis_setup_channel(&cp->wdc_channel); 2929 } 2930 } 2931 2932 void 2933 sis_setup_channel(chp) 2934 struct channel_softc *chp; 2935 { 2936 struct ata_drive_datas *drvp; 2937 int drive; 2938 u_int32_t sis_tim; 2939 u_int32_t idedma_ctl; 2940 struct pciide_channel *cp = (struct pciide_channel*)chp; 2941 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2942 2943 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2944 "channel %d 0x%x\n", chp->channel, 2945 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2946 DEBUG_PROBE); 2947 sis_tim = 0; 2948 idedma_ctl = 0; 2949 /* setup DMA if needed */ 2950 pciide_channel_dma_setup(cp); 2951 2952 for (drive = 0; drive < 2; drive++) { 2953 drvp = &chp->ch_drive[drive]; 2954 /* If no drive, skip */ 2955 if ((drvp->drive_flags & DRIVE) == 0) 2956 continue; 2957 /* add timing values, setup DMA if needed */ 2958 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2959 (drvp->drive_flags & DRIVE_UDMA) == 0) 2960 goto pio; 2961 2962 if (drvp->drive_flags & DRIVE_UDMA) { 2963 /* use Ultra/DMA */ 2964 drvp->drive_flags &= ~DRIVE_DMA; 2965 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2966 SIS_TIM_UDMA_TIME_OFF(drive); 2967 sis_tim |= SIS_TIM_UDMA_EN(drive); 2968 } else { 2969 /* 2970 * use Multiword DMA 2971 * Timings will be used for both PIO and DMA, 2972 * so adjust DMA mode if needed 2973 */ 2974 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2975 drvp->PIO_mode = drvp->DMA_mode + 2; 2976 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2977 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2978 drvp->PIO_mode - 2 : 0; 2979 if (drvp->DMA_mode == 0) 2980 drvp->PIO_mode = 0; 2981 } 2982 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2983 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2984 SIS_TIM_ACT_OFF(drive); 2985 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2986 SIS_TIM_REC_OFF(drive); 2987 } 2988 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2989 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2990 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2991 if (idedma_ctl != 0) { 2992 /* Add software bits in status register */ 2993 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2994 IDEDMA_CTL, idedma_ctl); 2995 } 2996 pciide_print_modes(cp); 2997 } 2998 2999 static int 3000 acer_isabr_match(pa) 3001 struct pci_attach_args *pa; 3002 { 3003 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 3004 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 3005 } 3006 3007 void 3008 acer_chip_map(sc, pa) 3009 struct pciide_softc *sc; 3010 struct pci_attach_args *pa; 3011 { 3012 struct pci_attach_args isa_pa; 3013 struct pciide_channel *cp; 3014 int channel; 3015 pcireg_t cr, interface; 3016 bus_size_t cmdsize, ctlsize; 3017 pcireg_t rev = PCI_REVISION(pa->pa_class); 3018 3019 if (pciide_chipen(sc, pa) == 0) 3020 return; 3021 printf("%s: bus-master DMA support present", 3022 sc->sc_wdcdev.sc_dev.dv_xname); 3023 pciide_mapreg_dma(sc, pa); 3024 printf("\n"); 3025 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3026 WDC_CAPABILITY_MODE; 3027 if (sc->sc_dma_ok) { 3028 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3029 if (rev >= 0x20) { 3030 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3031 if (rev >= 0xC4) 3032 sc->sc_wdcdev.UDMA_cap = 5; 3033 else if (rev >= 0xC2) 3034 sc->sc_wdcdev.UDMA_cap = 4; 3035 else 3036 sc->sc_wdcdev.UDMA_cap = 2; 3037 } 3038 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3039 sc->sc_wdcdev.irqack = pciide_irqack; 3040 } 3041 3042 sc->sc_wdcdev.PIO_cap = 4; 3043 sc->sc_wdcdev.DMA_cap = 2; 3044 sc->sc_wdcdev.set_modes = acer_setup_channel; 3045 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3046 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3047 3048 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3049 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3050 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3051 3052 /* Enable "microsoft register bits" R/W. */ 3053 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3054 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3055 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3056 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3057 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3058 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3059 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3060 ~ACER_CHANSTATUSREGS_RO); 3061 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3062 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3063 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3064 /* Don't use cr, re-read the real register content instead */ 3065 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3066 PCI_CLASS_REG)); 3067 3068 /* From linux: enable "Cable Detection" */ 3069 if (rev >= 0xC2) { 3070 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3071 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3072 | ACER_0x4B_CDETECT); 3073 /* set south-bridge's enable bit, m1533, 0x79 */ 3074 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 3075 printf("%s: can't find PCI/ISA bridge, downgrading " 3076 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 3077 sc->sc_wdcdev.UDMA_cap = 2; 3078 } else { 3079 if (rev == 0xC2) 3080 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3081 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3082 ACER_0x79, 3083 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3084 ACER_0x79) 3085 | ACER_0x79_REVC2_EN); 3086 else 3087 /* 1553/1535 (m1533, 0x79, bit 1) */ 3088 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3089 ACER_0x79, 3090 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3091 ACER_0x79) 3092 | ACER_0x79_EN); 3093 } 3094 } 3095 3096 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3097 cp = &sc->pciide_channels[channel]; 3098 if (pciide_chansetup(sc, channel, interface) == 0) 3099 continue; 3100 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3101 printf("%s: %s channel ignored (disabled)\n", 3102 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3103 continue; 3104 } 3105 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3106 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3107 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3108 if (cp->hw_ok == 0) 3109 continue; 3110 if (pciide_chan_candisable(cp)) { 3111 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3112 pci_conf_write(sc->sc_pc, sc->sc_tag, 3113 PCI_CLASS_REG, cr); 3114 } 3115 pciide_map_compat_intr(pa, cp, channel, interface); 3116 acer_setup_channel(&cp->wdc_channel); 3117 } 3118 } 3119 3120 void 3121 acer_setup_channel(chp) 3122 struct channel_softc *chp; 3123 { 3124 struct ata_drive_datas *drvp; 3125 int drive; 3126 u_int32_t acer_fifo_udma; 3127 u_int32_t idedma_ctl; 3128 struct pciide_channel *cp = (struct pciide_channel*)chp; 3129 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3130 3131 idedma_ctl = 0; 3132 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3133 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3134 acer_fifo_udma), DEBUG_PROBE); 3135 /* setup DMA if needed */ 3136 pciide_channel_dma_setup(cp); 3137 3138 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3139 DRIVE_UDMA) { /* check 80 pins cable */ 3140 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3141 ACER_0x4A_80PIN(chp->channel)) { 3142 if (chp->ch_drive[0].UDMA_mode > 2) 3143 chp->ch_drive[0].UDMA_mode = 2; 3144 if (chp->ch_drive[1].UDMA_mode > 2) 3145 chp->ch_drive[1].UDMA_mode = 2; 3146 } 3147 } 3148 3149 for (drive = 0; drive < 2; drive++) { 3150 drvp = &chp->ch_drive[drive]; 3151 /* If no drive, skip */ 3152 if ((drvp->drive_flags & DRIVE) == 0) 3153 continue; 3154 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3155 "channel %d drive %d 0x%x\n", chp->channel, drive, 3156 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3157 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3158 /* clear FIFO/DMA mode */ 3159 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3160 ACER_UDMA_EN(chp->channel, drive) | 3161 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3162 3163 /* add timing values, setup DMA if needed */ 3164 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3165 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3166 acer_fifo_udma |= 3167 ACER_FTH_OPL(chp->channel, drive, 0x1); 3168 goto pio; 3169 } 3170 3171 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3172 if (drvp->drive_flags & DRIVE_UDMA) { 3173 /* use Ultra/DMA */ 3174 drvp->drive_flags &= ~DRIVE_DMA; 3175 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3176 acer_fifo_udma |= 3177 ACER_UDMA_TIM(chp->channel, drive, 3178 acer_udma[drvp->UDMA_mode]); 3179 /* XXX disable if one drive < UDMA3 ? */ 3180 if (drvp->UDMA_mode >= 3) { 3181 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3182 ACER_0x4B, 3183 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3184 ACER_0x4B) | ACER_0x4B_UDMA66); 3185 } 3186 } else { 3187 /* 3188 * use Multiword DMA 3189 * Timings will be used for both PIO and DMA, 3190 * so adjust DMA mode if needed 3191 */ 3192 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3193 drvp->PIO_mode = drvp->DMA_mode + 2; 3194 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3195 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3196 drvp->PIO_mode - 2 : 0; 3197 if (drvp->DMA_mode == 0) 3198 drvp->PIO_mode = 0; 3199 } 3200 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3201 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3202 ACER_IDETIM(chp->channel, drive), 3203 acer_pio[drvp->PIO_mode]); 3204 } 3205 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3206 acer_fifo_udma), DEBUG_PROBE); 3207 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3208 if (idedma_ctl != 0) { 3209 /* Add software bits in status register */ 3210 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3211 IDEDMA_CTL, idedma_ctl); 3212 } 3213 pciide_print_modes(cp); 3214 } 3215 3216 int 3217 acer_pci_intr(arg) 3218 void *arg; 3219 { 3220 struct pciide_softc *sc = arg; 3221 struct pciide_channel *cp; 3222 struct channel_softc *wdc_cp; 3223 int i, rv, crv; 3224 u_int32_t chids; 3225 3226 rv = 0; 3227 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3228 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3229 cp = &sc->pciide_channels[i]; 3230 wdc_cp = &cp->wdc_channel; 3231 /* If a compat channel skip. */ 3232 if (cp->compat) 3233 continue; 3234 if (chids & ACER_CHIDS_INT(i)) { 3235 crv = wdcintr(wdc_cp); 3236 if (crv == 0) 3237 printf("%s:%d: bogus intr\n", 3238 sc->sc_wdcdev.sc_dev.dv_xname, i); 3239 else 3240 rv = 1; 3241 } 3242 } 3243 return rv; 3244 } 3245 3246 void 3247 hpt_chip_map(sc, pa) 3248 struct pciide_softc *sc; 3249 struct pci_attach_args *pa; 3250 { 3251 struct pciide_channel *cp; 3252 int i, compatchan, revision; 3253 pcireg_t interface; 3254 bus_size_t cmdsize, ctlsize; 3255 3256 if (pciide_chipen(sc, pa) == 0) 3257 return; 3258 revision = PCI_REVISION(pa->pa_class); 3259 printf(": Triones/Highpoint "); 3260 if (revision == HPT370_REV) 3261 printf("HPT370 IDE Controller\n"); 3262 else if (revision == HPT370A_REV) 3263 printf("HPT370A IDE Controller\n"); 3264 else if (revision == HPT366_REV) 3265 printf("HPT366 IDE Controller\n"); 3266 else 3267 printf("unknown HPT IDE controller rev %d\n", revision); 3268 3269 /* 3270 * when the chip is in native mode it identifies itself as a 3271 * 'misc mass storage'. Fake interface in this case. 3272 */ 3273 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3274 interface = PCI_INTERFACE(pa->pa_class); 3275 } else { 3276 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3277 PCIIDE_INTERFACE_PCI(0); 3278 if (revision == HPT370_REV || revision == HPT370A_REV) 3279 interface |= PCIIDE_INTERFACE_PCI(1); 3280 } 3281 3282 printf("%s: bus-master DMA support present", 3283 sc->sc_wdcdev.sc_dev.dv_xname); 3284 pciide_mapreg_dma(sc, pa); 3285 printf("\n"); 3286 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3287 WDC_CAPABILITY_MODE; 3288 if (sc->sc_dma_ok) { 3289 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3290 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3291 sc->sc_wdcdev.irqack = pciide_irqack; 3292 } 3293 sc->sc_wdcdev.PIO_cap = 4; 3294 sc->sc_wdcdev.DMA_cap = 2; 3295 3296 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3297 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3298 if (revision == HPT366_REV) { 3299 sc->sc_wdcdev.UDMA_cap = 4; 3300 /* 3301 * The 366 has 2 PCI IDE functions, one for primary and one 3302 * for secondary. So we need to call pciide_mapregs_compat() 3303 * with the real channel 3304 */ 3305 if (pa->pa_function == 0) { 3306 compatchan = 0; 3307 } else if (pa->pa_function == 1) { 3308 compatchan = 1; 3309 } else { 3310 printf("%s: unexpected PCI function %d\n", 3311 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3312 return; 3313 } 3314 sc->sc_wdcdev.nchannels = 1; 3315 } else { 3316 sc->sc_wdcdev.nchannels = 2; 3317 sc->sc_wdcdev.UDMA_cap = 5; 3318 } 3319 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3320 cp = &sc->pciide_channels[i]; 3321 if (sc->sc_wdcdev.nchannels > 1) { 3322 compatchan = i; 3323 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3324 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3325 printf("%s: %s channel ignored (disabled)\n", 3326 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3327 continue; 3328 } 3329 } 3330 if (pciide_chansetup(sc, i, interface) == 0) 3331 continue; 3332 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3333 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3334 &ctlsize, hpt_pci_intr); 3335 } else { 3336 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3337 &cmdsize, &ctlsize); 3338 } 3339 if (cp->hw_ok == 0) 3340 return; 3341 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3342 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3343 wdcattach(&cp->wdc_channel); 3344 hpt_setup_channel(&cp->wdc_channel); 3345 } 3346 if (revision == HPT370_REV || revision == HPT370A_REV) { 3347 /* 3348 * HPT370_REV has a bit to disable interrupts, make sure 3349 * to clear it 3350 */ 3351 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3352 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3353 ~HPT_CSEL_IRQDIS); 3354 } 3355 return; 3356 } 3357 3358 void 3359 hpt_setup_channel(chp) 3360 struct channel_softc *chp; 3361 { 3362 struct ata_drive_datas *drvp; 3363 int drive; 3364 int cable; 3365 u_int32_t before, after; 3366 u_int32_t idedma_ctl; 3367 struct pciide_channel *cp = (struct pciide_channel*)chp; 3368 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3369 3370 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3371 3372 /* setup DMA if needed */ 3373 pciide_channel_dma_setup(cp); 3374 3375 idedma_ctl = 0; 3376 3377 /* Per drive settings */ 3378 for (drive = 0; drive < 2; drive++) { 3379 drvp = &chp->ch_drive[drive]; 3380 /* If no drive, skip */ 3381 if ((drvp->drive_flags & DRIVE) == 0) 3382 continue; 3383 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3384 HPT_IDETIM(chp->channel, drive)); 3385 3386 /* add timing values, setup DMA if needed */ 3387 if (drvp->drive_flags & DRIVE_UDMA) { 3388 /* use Ultra/DMA */ 3389 drvp->drive_flags &= ~DRIVE_DMA; 3390 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3391 drvp->UDMA_mode > 2) 3392 drvp->UDMA_mode = 2; 3393 after = (sc->sc_wdcdev.nchannels == 2) ? 3394 hpt370_udma[drvp->UDMA_mode] : 3395 hpt366_udma[drvp->UDMA_mode]; 3396 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3397 } else if (drvp->drive_flags & DRIVE_DMA) { 3398 /* 3399 * use Multiword DMA. 3400 * Timings will be used for both PIO and DMA, so adjust 3401 * DMA mode if needed 3402 */ 3403 if (drvp->PIO_mode >= 3 && 3404 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3405 drvp->DMA_mode = drvp->PIO_mode - 2; 3406 } 3407 after = (sc->sc_wdcdev.nchannels == 2) ? 3408 hpt370_dma[drvp->DMA_mode] : 3409 hpt366_dma[drvp->DMA_mode]; 3410 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3411 } else { 3412 /* PIO only */ 3413 after = (sc->sc_wdcdev.nchannels == 2) ? 3414 hpt370_pio[drvp->PIO_mode] : 3415 hpt366_pio[drvp->PIO_mode]; 3416 } 3417 pci_conf_write(sc->sc_pc, sc->sc_tag, 3418 HPT_IDETIM(chp->channel, drive), after); 3419 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3420 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3421 after, before), DEBUG_PROBE); 3422 } 3423 if (idedma_ctl != 0) { 3424 /* Add software bits in status register */ 3425 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3426 IDEDMA_CTL, idedma_ctl); 3427 } 3428 pciide_print_modes(cp); 3429 } 3430 3431 int 3432 hpt_pci_intr(arg) 3433 void *arg; 3434 { 3435 struct pciide_softc *sc = arg; 3436 struct pciide_channel *cp; 3437 struct channel_softc *wdc_cp; 3438 int rv = 0; 3439 int dmastat, i, crv; 3440 3441 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3442 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3443 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3444 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3445 IDEDMA_CTL_INTR) 3446 continue; 3447 cp = &sc->pciide_channels[i]; 3448 wdc_cp = &cp->wdc_channel; 3449 crv = wdcintr(wdc_cp); 3450 if (crv == 0) { 3451 printf("%s:%d: bogus intr\n", 3452 sc->sc_wdcdev.sc_dev.dv_xname, i); 3453 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3454 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3455 } else 3456 rv = 1; 3457 } 3458 return rv; 3459 } 3460 3461 3462 /* Macros to test product */ 3463 #define PDC_IS_262(sc) \ 3464 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3465 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3466 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3467 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3468 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3469 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3470 #define PDC_IS_265(sc) \ 3471 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3472 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3473 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3474 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3475 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3476 #define PDC_IS_268(sc) \ 3477 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3478 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3479 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3480 3481 void 3482 pdc202xx_chip_map(sc, pa) 3483 struct pciide_softc *sc; 3484 struct pci_attach_args *pa; 3485 { 3486 struct pciide_channel *cp; 3487 int channel; 3488 pcireg_t interface, st, mode; 3489 bus_size_t cmdsize, ctlsize; 3490 3491 if (!PDC_IS_268(sc)) { 3492 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3493 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3494 st), DEBUG_PROBE); 3495 } 3496 if (pciide_chipen(sc, pa) == 0) 3497 return; 3498 3499 /* turn off RAID mode */ 3500 if (!PDC_IS_268(sc)) 3501 st &= ~PDC2xx_STATE_IDERAID; 3502 3503 /* 3504 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3505 * mode. We have to fake interface 3506 */ 3507 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3508 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3509 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3510 3511 printf("%s: bus-master DMA support present", 3512 sc->sc_wdcdev.sc_dev.dv_xname); 3513 pciide_mapreg_dma(sc, pa); 3514 printf("\n"); 3515 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3516 WDC_CAPABILITY_MODE; 3517 if (sc->sc_dma_ok) { 3518 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3519 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3520 sc->sc_wdcdev.irqack = pciide_irqack; 3521 } 3522 sc->sc_wdcdev.PIO_cap = 4; 3523 sc->sc_wdcdev.DMA_cap = 2; 3524 if (PDC_IS_265(sc)) 3525 sc->sc_wdcdev.UDMA_cap = 5; 3526 else if (PDC_IS_262(sc)) 3527 sc->sc_wdcdev.UDMA_cap = 4; 3528 else 3529 sc->sc_wdcdev.UDMA_cap = 2; 3530 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3531 pdc20268_setup_channel : pdc202xx_setup_channel; 3532 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3533 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3534 3535 if (!PDC_IS_268(sc)) { 3536 /* setup failsafe defaults */ 3537 mode = 0; 3538 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3539 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3540 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3541 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3542 for (channel = 0; 3543 channel < sc->sc_wdcdev.nchannels; 3544 channel++) { 3545 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3546 "drive 0 initial timings 0x%x, now 0x%x\n", 3547 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3548 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3549 DEBUG_PROBE); 3550 pci_conf_write(sc->sc_pc, sc->sc_tag, 3551 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3552 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3553 "drive 1 initial timings 0x%x, now 0x%x\n", 3554 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3555 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3556 pci_conf_write(sc->sc_pc, sc->sc_tag, 3557 PDC2xx_TIM(channel, 1), mode); 3558 } 3559 3560 mode = PDC2xx_SCR_DMA; 3561 if (PDC_IS_262(sc)) { 3562 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3563 } else { 3564 /* the BIOS set it up this way */ 3565 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3566 } 3567 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3568 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3569 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3570 "now 0x%x\n", 3571 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3572 PDC2xx_SCR), 3573 mode), DEBUG_PROBE); 3574 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3575 PDC2xx_SCR, mode); 3576 3577 /* controller initial state register is OK even without BIOS */ 3578 /* Set DMA mode to IDE DMA compatibility */ 3579 mode = 3580 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3581 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3582 DEBUG_PROBE); 3583 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3584 mode | 0x1); 3585 mode = 3586 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3587 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3588 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3589 mode | 0x1); 3590 } 3591 3592 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3593 cp = &sc->pciide_channels[channel]; 3594 if (pciide_chansetup(sc, channel, interface) == 0) 3595 continue; 3596 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3597 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3598 printf("%s: %s channel ignored (disabled)\n", 3599 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3600 continue; 3601 } 3602 if (PDC_IS_265(sc)) 3603 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3604 pdc20265_pci_intr); 3605 else 3606 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3607 pdc202xx_pci_intr); 3608 if (cp->hw_ok == 0) 3609 continue; 3610 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3611 st &= ~(PDC_IS_262(sc) ? 3612 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3613 pciide_map_compat_intr(pa, cp, channel, interface); 3614 pdc202xx_setup_channel(&cp->wdc_channel); 3615 } 3616 if (!PDC_IS_268(sc)) { 3617 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3618 "0x%x\n", st), DEBUG_PROBE); 3619 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3620 } 3621 return; 3622 } 3623 3624 void 3625 pdc202xx_setup_channel(chp) 3626 struct channel_softc *chp; 3627 { 3628 struct ata_drive_datas *drvp; 3629 int drive; 3630 pcireg_t mode, st; 3631 u_int32_t idedma_ctl, scr, atapi; 3632 struct pciide_channel *cp = (struct pciide_channel*)chp; 3633 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3634 int channel = chp->channel; 3635 3636 /* setup DMA if needed */ 3637 pciide_channel_dma_setup(cp); 3638 3639 idedma_ctl = 0; 3640 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3641 sc->sc_wdcdev.sc_dev.dv_xname, 3642 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3643 DEBUG_PROBE); 3644 3645 /* Per channel settings */ 3646 if (PDC_IS_262(sc)) { 3647 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3648 PDC262_U66); 3649 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3650 /* Trim UDMA mode */ 3651 if ((st & PDC262_STATE_80P(channel)) != 0 || 3652 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3653 chp->ch_drive[0].UDMA_mode <= 2) || 3654 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3655 chp->ch_drive[1].UDMA_mode <= 2)) { 3656 if (chp->ch_drive[0].UDMA_mode > 2) 3657 chp->ch_drive[0].UDMA_mode = 2; 3658 if (chp->ch_drive[1].UDMA_mode > 2) 3659 chp->ch_drive[1].UDMA_mode = 2; 3660 } 3661 /* Set U66 if needed */ 3662 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3663 chp->ch_drive[0].UDMA_mode > 2) || 3664 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3665 chp->ch_drive[1].UDMA_mode > 2)) 3666 scr |= PDC262_U66_EN(channel); 3667 else 3668 scr &= ~PDC262_U66_EN(channel); 3669 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3670 PDC262_U66, scr); 3671 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3672 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3673 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3674 PDC262_ATAPI(channel))), DEBUG_PROBE); 3675 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3676 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3677 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3678 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3679 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3680 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3681 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3682 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3683 atapi = 0; 3684 else 3685 atapi = PDC262_ATAPI_UDMA; 3686 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3687 PDC262_ATAPI(channel), atapi); 3688 } 3689 } 3690 for (drive = 0; drive < 2; drive++) { 3691 drvp = &chp->ch_drive[drive]; 3692 /* If no drive, skip */ 3693 if ((drvp->drive_flags & DRIVE) == 0) 3694 continue; 3695 mode = 0; 3696 if (drvp->drive_flags & DRIVE_UDMA) { 3697 /* use Ultra/DMA */ 3698 drvp->drive_flags &= ~DRIVE_DMA; 3699 mode = PDC2xx_TIM_SET_MB(mode, 3700 pdc2xx_udma_mb[drvp->UDMA_mode]); 3701 mode = PDC2xx_TIM_SET_MC(mode, 3702 pdc2xx_udma_mc[drvp->UDMA_mode]); 3703 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3704 } else if (drvp->drive_flags & DRIVE_DMA) { 3705 mode = PDC2xx_TIM_SET_MB(mode, 3706 pdc2xx_dma_mb[drvp->DMA_mode]); 3707 mode = PDC2xx_TIM_SET_MC(mode, 3708 pdc2xx_dma_mc[drvp->DMA_mode]); 3709 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3710 } else { 3711 mode = PDC2xx_TIM_SET_MB(mode, 3712 pdc2xx_dma_mb[0]); 3713 mode = PDC2xx_TIM_SET_MC(mode, 3714 pdc2xx_dma_mc[0]); 3715 } 3716 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3717 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3718 if (drvp->drive_flags & DRIVE_ATA) 3719 mode |= PDC2xx_TIM_PRE; 3720 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3721 if (drvp->PIO_mode >= 3) { 3722 mode |= PDC2xx_TIM_IORDY; 3723 if (drive == 0) 3724 mode |= PDC2xx_TIM_IORDYp; 3725 } 3726 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3727 "timings 0x%x\n", 3728 sc->sc_wdcdev.sc_dev.dv_xname, 3729 chp->channel, drive, mode), DEBUG_PROBE); 3730 pci_conf_write(sc->sc_pc, sc->sc_tag, 3731 PDC2xx_TIM(chp->channel, drive), mode); 3732 } 3733 if (idedma_ctl != 0) { 3734 /* Add software bits in status register */ 3735 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3736 IDEDMA_CTL, idedma_ctl); 3737 } 3738 pciide_print_modes(cp); 3739 } 3740 3741 void 3742 pdc20268_setup_channel(chp) 3743 struct channel_softc *chp; 3744 { 3745 struct ata_drive_datas *drvp; 3746 int drive; 3747 u_int32_t idedma_ctl; 3748 struct pciide_channel *cp = (struct pciide_channel*)chp; 3749 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3750 int u100; 3751 3752 /* setup DMA if needed */ 3753 pciide_channel_dma_setup(cp); 3754 3755 idedma_ctl = 0; 3756 3757 /* I don't know what this is for, FreeBSD does it ... */ 3758 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3759 IDEDMA_CMD + 0x1, 0x0b); 3760 3761 /* 3762 * I don't know what this is for; FreeBSD checks this ... this is not 3763 * cable type detect. 3764 */ 3765 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3766 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3767 3768 for (drive = 0; drive < 2; drive++) { 3769 drvp = &chp->ch_drive[drive]; 3770 /* If no drive, skip */ 3771 if ((drvp->drive_flags & DRIVE) == 0) 3772 continue; 3773 if (drvp->drive_flags & DRIVE_UDMA) { 3774 /* use Ultra/DMA */ 3775 drvp->drive_flags &= ~DRIVE_DMA; 3776 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3777 if (drvp->UDMA_mode > 2 && u100 == 0) 3778 drvp->UDMA_mode = 2; 3779 } else if (drvp->drive_flags & DRIVE_DMA) { 3780 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3781 } 3782 } 3783 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3784 if (idedma_ctl != 0) { 3785 /* Add software bits in status register */ 3786 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3787 IDEDMA_CTL, idedma_ctl); 3788 } 3789 pciide_print_modes(cp); 3790 } 3791 3792 int 3793 pdc202xx_pci_intr(arg) 3794 void *arg; 3795 { 3796 struct pciide_softc *sc = arg; 3797 struct pciide_channel *cp; 3798 struct channel_softc *wdc_cp; 3799 int i, rv, crv; 3800 u_int32_t scr; 3801 3802 rv = 0; 3803 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3804 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3805 cp = &sc->pciide_channels[i]; 3806 wdc_cp = &cp->wdc_channel; 3807 /* If a compat channel skip. */ 3808 if (cp->compat) 3809 continue; 3810 if (scr & PDC2xx_SCR_INT(i)) { 3811 crv = wdcintr(wdc_cp); 3812 if (crv == 0) 3813 printf("%s:%d: bogus intr (reg 0x%x)\n", 3814 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3815 else 3816 rv = 1; 3817 } 3818 } 3819 return rv; 3820 } 3821 3822 int 3823 pdc20265_pci_intr(arg) 3824 void *arg; 3825 { 3826 struct pciide_softc *sc = arg; 3827 struct pciide_channel *cp; 3828 struct channel_softc *wdc_cp; 3829 int i, rv, crv; 3830 u_int32_t dmastat; 3831 3832 rv = 0; 3833 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3834 cp = &sc->pciide_channels[i]; 3835 wdc_cp = &cp->wdc_channel; 3836 /* If a compat channel skip. */ 3837 if (cp->compat) 3838 continue; 3839 /* 3840 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3841 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3842 * So use it instead (requires 2 reg reads instead of 1, 3843 * but we can't do it another way). 3844 */ 3845 dmastat = bus_space_read_1(sc->sc_dma_iot, 3846 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3847 if((dmastat & IDEDMA_CTL_INTR) == 0) 3848 continue; 3849 crv = wdcintr(wdc_cp); 3850 if (crv == 0) 3851 printf("%s:%d: bogus intr\n", 3852 sc->sc_wdcdev.sc_dev.dv_xname, i); 3853 else 3854 rv = 1; 3855 } 3856 return rv; 3857 } 3858 3859 void 3860 opti_chip_map(sc, pa) 3861 struct pciide_softc *sc; 3862 struct pci_attach_args *pa; 3863 { 3864 struct pciide_channel *cp; 3865 bus_size_t cmdsize, ctlsize; 3866 pcireg_t interface; 3867 u_int8_t init_ctrl; 3868 int channel; 3869 3870 if (pciide_chipen(sc, pa) == 0) 3871 return; 3872 printf("%s: bus-master DMA support present", 3873 sc->sc_wdcdev.sc_dev.dv_xname); 3874 3875 /* 3876 * XXXSCW: 3877 * There seem to be a couple of buggy revisions/implementations 3878 * of the OPTi pciide chipset. This kludge seems to fix one of 3879 * the reported problems (PR/11644) but still fails for the 3880 * other (PR/13151), although the latter may be due to other 3881 * issues too... 3882 */ 3883 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3884 printf(" but disabled due to chip rev. <= 0x12"); 3885 sc->sc_dma_ok = 0; 3886 sc->sc_wdcdev.cap = 0; 3887 } else { 3888 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3889 pciide_mapreg_dma(sc, pa); 3890 } 3891 printf("\n"); 3892 3893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3894 sc->sc_wdcdev.PIO_cap = 4; 3895 if (sc->sc_dma_ok) { 3896 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3897 sc->sc_wdcdev.irqack = pciide_irqack; 3898 sc->sc_wdcdev.DMA_cap = 2; 3899 } 3900 sc->sc_wdcdev.set_modes = opti_setup_channel; 3901 3902 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3903 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3904 3905 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3906 OPTI_REG_INIT_CONTROL); 3907 3908 interface = PCI_INTERFACE(pa->pa_class); 3909 3910 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3911 cp = &sc->pciide_channels[channel]; 3912 if (pciide_chansetup(sc, channel, interface) == 0) 3913 continue; 3914 if (channel == 1 && 3915 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3916 printf("%s: %s channel ignored (disabled)\n", 3917 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3918 continue; 3919 } 3920 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3921 pciide_pci_intr); 3922 if (cp->hw_ok == 0) 3923 continue; 3924 pciide_map_compat_intr(pa, cp, channel, interface); 3925 if (cp->hw_ok == 0) 3926 continue; 3927 opti_setup_channel(&cp->wdc_channel); 3928 } 3929 } 3930 3931 void 3932 opti_setup_channel(chp) 3933 struct channel_softc *chp; 3934 { 3935 struct ata_drive_datas *drvp; 3936 struct pciide_channel *cp = (struct pciide_channel*)chp; 3937 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3938 int drive, spd; 3939 int mode[2]; 3940 u_int8_t rv, mr; 3941 3942 /* 3943 * The `Delay' and `Address Setup Time' fields of the 3944 * Miscellaneous Register are always zero initially. 3945 */ 3946 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3947 mr &= ~(OPTI_MISC_DELAY_MASK | 3948 OPTI_MISC_ADDR_SETUP_MASK | 3949 OPTI_MISC_INDEX_MASK); 3950 3951 /* Prime the control register before setting timing values */ 3952 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3953 3954 /* Determine the clockrate of the PCIbus the chip is attached to */ 3955 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3956 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3957 3958 /* setup DMA if needed */ 3959 pciide_channel_dma_setup(cp); 3960 3961 for (drive = 0; drive < 2; drive++) { 3962 drvp = &chp->ch_drive[drive]; 3963 /* If no drive, skip */ 3964 if ((drvp->drive_flags & DRIVE) == 0) { 3965 mode[drive] = -1; 3966 continue; 3967 } 3968 3969 if ((drvp->drive_flags & DRIVE_DMA)) { 3970 /* 3971 * Timings will be used for both PIO and DMA, 3972 * so adjust DMA mode if needed 3973 */ 3974 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3975 drvp->PIO_mode = drvp->DMA_mode + 2; 3976 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3977 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3978 drvp->PIO_mode - 2 : 0; 3979 if (drvp->DMA_mode == 0) 3980 drvp->PIO_mode = 0; 3981 3982 mode[drive] = drvp->DMA_mode + 5; 3983 } else 3984 mode[drive] = drvp->PIO_mode; 3985 3986 if (drive && mode[0] >= 0 && 3987 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3988 /* 3989 * Can't have two drives using different values 3990 * for `Address Setup Time'. 3991 * Slow down the faster drive to compensate. 3992 */ 3993 int d = (opti_tim_as[spd][mode[0]] > 3994 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3995 3996 mode[d] = mode[1-d]; 3997 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3998 chp->ch_drive[d].DMA_mode = 0; 3999 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 4000 } 4001 } 4002 4003 for (drive = 0; drive < 2; drive++) { 4004 int m; 4005 if ((m = mode[drive]) < 0) 4006 continue; 4007 4008 /* Set the Address Setup Time and select appropriate index */ 4009 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4010 rv |= OPTI_MISC_INDEX(drive); 4011 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4012 4013 /* Set the pulse width and recovery timing parameters */ 4014 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4015 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4016 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4017 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4018 4019 /* Set the Enhanced Mode register appropriately */ 4020 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4021 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4022 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4023 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4024 } 4025 4026 /* Finally, enable the timings */ 4027 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4028 4029 pciide_print_modes(cp); 4030 } 4031 4032 #define ACARD_IS_850(sc) \ 4033 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4034 4035 void 4036 acard_chip_map(sc, pa) 4037 struct pciide_softc *sc; 4038 struct pci_attach_args *pa; 4039 { 4040 struct pciide_channel *cp; 4041 int i; 4042 pcireg_t interface; 4043 bus_size_t cmdsize, ctlsize; 4044 4045 if (pciide_chipen(sc, pa) == 0) 4046 return; 4047 4048 /* 4049 * when the chip is in native mode it identifies itself as a 4050 * 'misc mass storage'. Fake interface in this case. 4051 */ 4052 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4053 interface = PCI_INTERFACE(pa->pa_class); 4054 } else { 4055 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4056 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4057 } 4058 4059 printf("%s: bus-master DMA support present", 4060 sc->sc_wdcdev.sc_dev.dv_xname); 4061 pciide_mapreg_dma(sc, pa); 4062 printf("\n"); 4063 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4064 WDC_CAPABILITY_MODE; 4065 4066 if (sc->sc_dma_ok) { 4067 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4068 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4069 sc->sc_wdcdev.irqack = pciide_irqack; 4070 } 4071 sc->sc_wdcdev.PIO_cap = 4; 4072 sc->sc_wdcdev.DMA_cap = 2; 4073 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4074 4075 sc->sc_wdcdev.set_modes = acard_setup_channel; 4076 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4077 sc->sc_wdcdev.nchannels = 2; 4078 4079 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4080 cp = &sc->pciide_channels[i]; 4081 if (pciide_chansetup(sc, i, interface) == 0) 4082 continue; 4083 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4084 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4085 &ctlsize, pciide_pci_intr); 4086 } else { 4087 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4088 &cmdsize, &ctlsize); 4089 } 4090 if (cp->hw_ok == 0) 4091 return; 4092 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4093 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4094 wdcattach(&cp->wdc_channel); 4095 acard_setup_channel(&cp->wdc_channel); 4096 } 4097 if (!ACARD_IS_850(sc)) { 4098 u_int32_t reg; 4099 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4100 reg &= ~ATP860_CTRL_INT; 4101 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4102 } 4103 } 4104 4105 void 4106 acard_setup_channel(chp) 4107 struct channel_softc *chp; 4108 { 4109 struct ata_drive_datas *drvp; 4110 struct pciide_channel *cp = (struct pciide_channel*)chp; 4111 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4112 int channel = chp->channel; 4113 int drive; 4114 u_int32_t idetime, udma_mode; 4115 u_int32_t idedma_ctl; 4116 4117 /* setup DMA if needed */ 4118 pciide_channel_dma_setup(cp); 4119 4120 if (ACARD_IS_850(sc)) { 4121 idetime = 0; 4122 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4123 udma_mode &= ~ATP850_UDMA_MASK(channel); 4124 } else { 4125 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4126 idetime &= ~ATP860_SETTIME_MASK(channel); 4127 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4128 udma_mode &= ~ATP860_UDMA_MASK(channel); 4129 4130 /* check 80 pins cable */ 4131 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4132 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4133 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4134 & ATP860_CTRL_80P(chp->channel)) { 4135 if (chp->ch_drive[0].UDMA_mode > 2) 4136 chp->ch_drive[0].UDMA_mode = 2; 4137 if (chp->ch_drive[1].UDMA_mode > 2) 4138 chp->ch_drive[1].UDMA_mode = 2; 4139 } 4140 } 4141 } 4142 4143 idedma_ctl = 0; 4144 4145 /* Per drive settings */ 4146 for (drive = 0; drive < 2; drive++) { 4147 drvp = &chp->ch_drive[drive]; 4148 /* If no drive, skip */ 4149 if ((drvp->drive_flags & DRIVE) == 0) 4150 continue; 4151 /* add timing values, setup DMA if needed */ 4152 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4153 (drvp->drive_flags & DRIVE_UDMA)) { 4154 /* use Ultra/DMA */ 4155 if (ACARD_IS_850(sc)) { 4156 idetime |= ATP850_SETTIME(drive, 4157 acard_act_udma[drvp->UDMA_mode], 4158 acard_rec_udma[drvp->UDMA_mode]); 4159 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4160 acard_udma_conf[drvp->UDMA_mode]); 4161 } else { 4162 idetime |= ATP860_SETTIME(channel, drive, 4163 acard_act_udma[drvp->UDMA_mode], 4164 acard_rec_udma[drvp->UDMA_mode]); 4165 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4166 acard_udma_conf[drvp->UDMA_mode]); 4167 } 4168 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4169 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4170 (drvp->drive_flags & DRIVE_DMA)) { 4171 /* use Multiword DMA */ 4172 drvp->drive_flags &= ~DRIVE_UDMA; 4173 if (ACARD_IS_850(sc)) { 4174 idetime |= ATP850_SETTIME(drive, 4175 acard_act_dma[drvp->DMA_mode], 4176 acard_rec_dma[drvp->DMA_mode]); 4177 } else { 4178 idetime |= ATP860_SETTIME(channel, drive, 4179 acard_act_dma[drvp->DMA_mode], 4180 acard_rec_dma[drvp->DMA_mode]); 4181 } 4182 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4183 } else { 4184 /* PIO only */ 4185 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4186 if (ACARD_IS_850(sc)) { 4187 idetime |= ATP850_SETTIME(drive, 4188 acard_act_pio[drvp->PIO_mode], 4189 acard_rec_pio[drvp->PIO_mode]); 4190 } else { 4191 idetime |= ATP860_SETTIME(channel, drive, 4192 acard_act_pio[drvp->PIO_mode], 4193 acard_rec_pio[drvp->PIO_mode]); 4194 } 4195 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4196 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4197 | ATP8x0_CTRL_EN(channel)); 4198 } 4199 } 4200 4201 if (idedma_ctl != 0) { 4202 /* Add software bits in status register */ 4203 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4204 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4205 } 4206 pciide_print_modes(cp); 4207 4208 if (ACARD_IS_850(sc)) { 4209 pci_conf_write(sc->sc_pc, sc->sc_tag, 4210 ATP850_IDETIME(channel), idetime); 4211 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4212 } else { 4213 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4214 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4215 } 4216 } 4217 4218 int 4219 acard_pci_intr(arg) 4220 void *arg; 4221 { 4222 struct pciide_softc *sc = arg; 4223 struct pciide_channel *cp; 4224 struct channel_softc *wdc_cp; 4225 int rv = 0; 4226 int dmastat, i, crv; 4227 4228 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4229 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4230 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4231 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4232 continue; 4233 cp = &sc->pciide_channels[i]; 4234 wdc_cp = &cp->wdc_channel; 4235 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4236 (void)wdcintr(wdc_cp); 4237 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4238 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4239 continue; 4240 } 4241 crv = wdcintr(wdc_cp); 4242 if (crv == 0) 4243 printf("%s:%d: bogus intr\n", 4244 sc->sc_wdcdev.sc_dev.dv_xname, i); 4245 else if (crv == 1) 4246 rv = 1; 4247 else if (rv == 0) 4248 rv = crv; 4249 } 4250 return rv; 4251 } 4252 4253 static int 4254 sl82c105_bugchk(struct pci_attach_args *pa) 4255 { 4256 4257 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4258 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4259 return (0); 4260 4261 if (PCI_REVISION(pa->pa_class) <= 0x05) 4262 return (1); 4263 4264 return (0); 4265 } 4266 4267 void 4268 sl82c105_chip_map(sc, pa) 4269 struct pciide_softc *sc; 4270 struct pci_attach_args *pa; 4271 { 4272 struct pciide_channel *cp; 4273 bus_size_t cmdsize, ctlsize; 4274 pcireg_t interface, idecr; 4275 int channel; 4276 4277 if (pciide_chipen(sc, pa) == 0) 4278 return; 4279 4280 printf("%s: bus-master DMA support present", 4281 sc->sc_wdcdev.sc_dev.dv_xname); 4282 4283 /* 4284 * Check to see if we're part of the Winbond 83c553 Southbridge. 4285 * If so, we need to disable DMA on rev. <= 5 of that chip. 4286 */ 4287 if (pci_find_device(pa, sl82c105_bugchk)) { 4288 printf(" but disabled due to 83c553 rev. <= 0x05"); 4289 sc->sc_dma_ok = 0; 4290 } else 4291 pciide_mapreg_dma(sc, pa); 4292 printf("\n"); 4293 4294 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4295 WDC_CAPABILITY_MODE; 4296 sc->sc_wdcdev.PIO_cap = 4; 4297 if (sc->sc_dma_ok) { 4298 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4299 sc->sc_wdcdev.irqack = pciide_irqack; 4300 sc->sc_wdcdev.DMA_cap = 2; 4301 } 4302 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4303 4304 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4305 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4306 4307 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4308 4309 interface = PCI_INTERFACE(pa->pa_class); 4310 4311 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4312 cp = &sc->pciide_channels[channel]; 4313 if (pciide_chansetup(sc, channel, interface) == 0) 4314 continue; 4315 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4316 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4317 printf("%s: %s channel ignored (disabled)\n", 4318 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4319 continue; 4320 } 4321 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4322 pciide_pci_intr); 4323 if (cp->hw_ok == 0) 4324 continue; 4325 pciide_map_compat_intr(pa, cp, channel, interface); 4326 if (cp->hw_ok == 0) 4327 continue; 4328 sl82c105_setup_channel(&cp->wdc_channel); 4329 } 4330 } 4331 4332 void 4333 sl82c105_setup_channel(chp) 4334 struct channel_softc *chp; 4335 { 4336 struct ata_drive_datas *drvp; 4337 struct pciide_channel *cp = (struct pciide_channel*)chp; 4338 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4339 int pxdx_reg, drive; 4340 pcireg_t pxdx; 4341 4342 /* Set up DMA if needed. */ 4343 pciide_channel_dma_setup(cp); 4344 4345 for (drive = 0; drive < 2; drive++) { 4346 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4347 : SYMPH_P1D0CR) + (drive * 4); 4348 4349 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4350 4351 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4352 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4353 4354 drvp = &chp->ch_drive[drive]; 4355 /* If no drive, skip. */ 4356 if ((drvp->drive_flags & DRIVE) == 0) { 4357 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4358 continue; 4359 } 4360 4361 if (drvp->drive_flags & DRIVE_DMA) { 4362 /* 4363 * Timings will be used for both PIO and DMA, 4364 * so adjust DMA mode if needed. 4365 */ 4366 if (drvp->PIO_mode >= 3) { 4367 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4368 drvp->DMA_mode = drvp->PIO_mode - 2; 4369 if (drvp->DMA_mode < 1) { 4370 /* 4371 * Can't mix both PIO and DMA. 4372 * Disable DMA. 4373 */ 4374 drvp->drive_flags &= ~DRIVE_DMA; 4375 } 4376 } else { 4377 /* 4378 * Can't mix both PIO and DMA. Disable 4379 * DMA. 4380 */ 4381 drvp->drive_flags &= ~DRIVE_DMA; 4382 } 4383 } 4384 4385 if (drvp->drive_flags & DRIVE_DMA) { 4386 /* Use multi-word DMA. */ 4387 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4388 PxDx_CMD_ON_SHIFT; 4389 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4390 } else { 4391 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4392 PxDx_CMD_ON_SHIFT; 4393 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4394 } 4395 4396 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4397 4398 /* ...and set the mode for this drive. */ 4399 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4400 } 4401 4402 pciide_print_modes(cp); 4403 } 4404 4405 void 4406 serverworks_chip_map(sc, pa) 4407 struct pciide_softc *sc; 4408 struct pci_attach_args *pa; 4409 { 4410 struct pciide_channel *cp; 4411 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4412 pcitag_t pcib_tag; 4413 int channel; 4414 bus_size_t cmdsize, ctlsize; 4415 4416 if (pciide_chipen(sc, pa) == 0) 4417 return; 4418 4419 printf("%s: bus-master DMA support present", 4420 sc->sc_wdcdev.sc_dev.dv_xname); 4421 pciide_mapreg_dma(sc, pa); 4422 printf("\n"); 4423 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4424 WDC_CAPABILITY_MODE; 4425 4426 if (sc->sc_dma_ok) { 4427 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4428 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4429 sc->sc_wdcdev.irqack = pciide_irqack; 4430 } 4431 sc->sc_wdcdev.PIO_cap = 4; 4432 sc->sc_wdcdev.DMA_cap = 2; 4433 switch (sc->sc_pp->ide_product) { 4434 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4435 sc->sc_wdcdev.UDMA_cap = 2; 4436 break; 4437 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4438 if (PCI_REVISION(pa->pa_class) < 0x92) 4439 sc->sc_wdcdev.UDMA_cap = 4; 4440 else 4441 sc->sc_wdcdev.UDMA_cap = 5; 4442 break; 4443 } 4444 4445 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4446 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4447 sc->sc_wdcdev.nchannels = 2; 4448 4449 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4450 cp = &sc->pciide_channels[channel]; 4451 if (pciide_chansetup(sc, channel, interface) == 0) 4452 continue; 4453 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4454 serverworks_pci_intr); 4455 if (cp->hw_ok == 0) 4456 return; 4457 pciide_map_compat_intr(pa, cp, channel, interface); 4458 if (cp->hw_ok == 0) 4459 return; 4460 serverworks_setup_channel(&cp->wdc_channel); 4461 } 4462 4463 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4464 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4465 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4466 } 4467 4468 void 4469 serverworks_setup_channel(chp) 4470 struct channel_softc *chp; 4471 { 4472 struct ata_drive_datas *drvp; 4473 struct pciide_channel *cp = (struct pciide_channel*)chp; 4474 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4475 int channel = chp->channel; 4476 int drive, unit; 4477 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4478 u_int32_t idedma_ctl; 4479 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4480 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4481 4482 /* setup DMA if needed */ 4483 pciide_channel_dma_setup(cp); 4484 4485 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4486 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4487 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4488 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4489 4490 pio_time &= ~(0xffff << (16 * channel)); 4491 dma_time &= ~(0xffff << (16 * channel)); 4492 pio_mode &= ~(0xff << (8 * channel + 16)); 4493 udma_mode &= ~(0xff << (8 * channel + 16)); 4494 udma_mode &= ~(3 << (2 * channel)); 4495 4496 idedma_ctl = 0; 4497 4498 /* Per drive settings */ 4499 for (drive = 0; drive < 2; drive++) { 4500 drvp = &chp->ch_drive[drive]; 4501 /* If no drive, skip */ 4502 if ((drvp->drive_flags & DRIVE) == 0) 4503 continue; 4504 unit = drive + 2 * channel; 4505 /* add timing values, setup DMA if needed */ 4506 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4507 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4508 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4509 (drvp->drive_flags & DRIVE_UDMA)) { 4510 /* use Ultra/DMA, check for 80-pin cable */ 4511 if (drvp->UDMA_mode > 2 && 4512 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4513 drvp->UDMA_mode = 2; 4514 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4515 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4516 udma_mode |= 1 << unit; 4517 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4518 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4519 (drvp->drive_flags & DRIVE_DMA)) { 4520 /* use Multiword DMA */ 4521 drvp->drive_flags &= ~DRIVE_UDMA; 4522 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4523 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4524 } else { 4525 /* PIO only */ 4526 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4527 } 4528 } 4529 4530 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4531 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4532 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4533 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4534 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4535 4536 if (idedma_ctl != 0) { 4537 /* Add software bits in status register */ 4538 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4539 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4540 } 4541 pciide_print_modes(cp); 4542 } 4543 4544 int 4545 serverworks_pci_intr(arg) 4546 void *arg; 4547 { 4548 struct pciide_softc *sc = arg; 4549 struct pciide_channel *cp; 4550 struct channel_softc *wdc_cp; 4551 int rv = 0; 4552 int dmastat, i, crv; 4553 4554 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4555 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4556 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4557 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4558 IDEDMA_CTL_INTR) 4559 continue; 4560 cp = &sc->pciide_channels[i]; 4561 wdc_cp = &cp->wdc_channel; 4562 crv = wdcintr(wdc_cp); 4563 if (crv == 0) { 4564 printf("%s:%d: bogus intr\n", 4565 sc->sc_wdcdev.sc_dev.dv_xname, i); 4566 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4567 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4568 } else 4569 rv = 1; 4570 } 4571 return rv; 4572 } 4573
Indexes created Tue Sep 23 23:09:58 GMT 2025