pciide.c revision 1.151
1 /* $NetBSD: pciide.c,v 1.151 2002/04/23 20:41:17 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.151 2002/04/23 20:41:17 bouyer Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 static int acer_isabr_match __P(( struct pci_attach_args *)); 192 193 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void pdc202xx_setup_channel __P((struct channel_softc*)); 195 void pdc20268_setup_channel __P((struct channel_softc*)); 196 int pdc202xx_pci_intr __P((void *)); 197 int pdc20265_pci_intr __P((void *)); 198 199 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void opti_setup_channel __P((struct channel_softc*)); 201 202 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void hpt_setup_channel __P((struct channel_softc*)); 204 int hpt_pci_intr __P((void *)); 205 206 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 207 void acard_setup_channel __P((struct channel_softc*)); 208 int acard_pci_intr __P((void *)); 209 210 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 211 void serverworks_setup_channel __P((struct channel_softc*)); 212 int serverworks_pci_intr __P((void *)); 213 214 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 215 void sl82c105_setup_channel __P((struct channel_softc*)); 216 217 void pciide_channel_dma_setup __P((struct pciide_channel *)); 218 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 219 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 220 void pciide_dma_start __P((void*, int, int)); 221 int pciide_dma_finish __P((void*, int, int, int)); 222 void pciide_irqack __P((struct channel_softc *)); 223 void pciide_print_modes __P((struct pciide_channel *)); 224 225 struct pciide_product_desc { 226 u_int32_t ide_product; 227 int ide_flags; 228 const char *ide_name; 229 /* map and setup chip, probe drives */ 230 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 231 }; 232 233 /* Flags for ide_flags */ 234 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 235 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 236 237 /* Default product description for devices not known from this controller */ 238 const struct pciide_product_desc default_product_desc = { 239 0, 240 0, 241 "Generic PCI IDE controller", 242 default_chip_map, 243 }; 244 245 const struct pciide_product_desc pciide_intel_products[] = { 246 { PCI_PRODUCT_INTEL_82092AA, 247 0, 248 "Intel 82092AA IDE controller", 249 default_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82371FB_IDE, 252 0, 253 "Intel 82371FB IDE controller (PIIX)", 254 piix_chip_map, 255 }, 256 { PCI_PRODUCT_INTEL_82371SB_IDE, 257 0, 258 "Intel 82371SB IDE Interface (PIIX3)", 259 piix_chip_map, 260 }, 261 { PCI_PRODUCT_INTEL_82371AB_IDE, 262 0, 263 "Intel 82371AB IDE controller (PIIX4)", 264 piix_chip_map, 265 }, 266 { PCI_PRODUCT_INTEL_82440MX_IDE, 267 0, 268 "Intel 82440MX IDE controller", 269 piix_chip_map 270 }, 271 { PCI_PRODUCT_INTEL_82801AA_IDE, 272 0, 273 "Intel 82801AA IDE Controller (ICH)", 274 piix_chip_map, 275 }, 276 { PCI_PRODUCT_INTEL_82801AB_IDE, 277 0, 278 "Intel 82801AB IDE Controller (ICH0)", 279 piix_chip_map, 280 }, 281 { PCI_PRODUCT_INTEL_82801BA_IDE, 282 0, 283 "Intel 82801BA IDE Controller (ICH2)", 284 piix_chip_map, 285 }, 286 { PCI_PRODUCT_INTEL_82801BAM_IDE, 287 0, 288 "Intel 82801BAM IDE Controller (ICH2)", 289 piix_chip_map, 290 }, 291 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 292 0, 293 "Intel 82201CA IDE Controller", 294 piix_chip_map, 295 }, 296 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 297 0, 298 "Intel 82201CA IDE Controller", 299 piix_chip_map, 300 }, 301 { 0, 302 0, 303 NULL, 304 NULL 305 } 306 }; 307 308 const struct pciide_product_desc pciide_amd_products[] = { 309 { PCI_PRODUCT_AMD_PBC756_IDE, 310 0, 311 "Advanced Micro Devices AMD756 IDE Controller", 312 amd7x6_chip_map 313 }, 314 { PCI_PRODUCT_AMD_PBC766_IDE, 315 0, 316 "Advanced Micro Devices AMD766 IDE Controller", 317 amd7x6_chip_map 318 }, 319 { PCI_PRODUCT_AMD_PBC768_IDE, 320 0, 321 "Advanced Micro Devices AMD768 IDE Controller", 322 amd7x6_chip_map 323 }, 324 { 0, 325 0, 326 NULL, 327 NULL 328 } 329 }; 330 331 const struct pciide_product_desc pciide_cmd_products[] = { 332 { PCI_PRODUCT_CMDTECH_640, 333 0, 334 "CMD Technology PCI0640", 335 cmd_chip_map 336 }, 337 { PCI_PRODUCT_CMDTECH_643, 338 0, 339 "CMD Technology PCI0643", 340 cmd0643_9_chip_map, 341 }, 342 { PCI_PRODUCT_CMDTECH_646, 343 0, 344 "CMD Technology PCI0646", 345 cmd0643_9_chip_map, 346 }, 347 { PCI_PRODUCT_CMDTECH_648, 348 IDE_PCI_CLASS_OVERRIDE, 349 "CMD Technology PCI0648", 350 cmd0643_9_chip_map, 351 }, 352 { PCI_PRODUCT_CMDTECH_649, 353 IDE_PCI_CLASS_OVERRIDE, 354 "CMD Technology PCI0649", 355 cmd0643_9_chip_map, 356 }, 357 { 0, 358 0, 359 NULL, 360 NULL 361 } 362 }; 363 364 const struct pciide_product_desc pciide_via_products[] = { 365 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 366 0, 367 NULL, 368 apollo_chip_map, 369 }, 370 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 371 0, 372 NULL, 373 apollo_chip_map, 374 }, 375 { 0, 376 0, 377 NULL, 378 NULL 379 } 380 }; 381 382 const struct pciide_product_desc pciide_cypress_products[] = { 383 { PCI_PRODUCT_CONTAQ_82C693, 384 IDE_16BIT_IOSPACE, 385 "Cypress 82C693 IDE Controller", 386 cy693_chip_map, 387 }, 388 { 0, 389 0, 390 NULL, 391 NULL 392 } 393 }; 394 395 const struct pciide_product_desc pciide_sis_products[] = { 396 { PCI_PRODUCT_SIS_5597_IDE, 397 0, 398 "Silicon Integrated System 5597/5598 IDE controller", 399 sis_chip_map, 400 }, 401 { 0, 402 0, 403 NULL, 404 NULL 405 } 406 }; 407 408 const struct pciide_product_desc pciide_acer_products[] = { 409 { PCI_PRODUCT_ALI_M5229, 410 0, 411 "Acer Labs M5229 UDMA IDE Controller", 412 acer_chip_map, 413 }, 414 { 0, 415 0, 416 NULL, 417 NULL 418 } 419 }; 420 421 const struct pciide_product_desc pciide_promise_products[] = { 422 { PCI_PRODUCT_PROMISE_ULTRA33, 423 IDE_PCI_CLASS_OVERRIDE, 424 "Promise Ultra33/ATA Bus Master IDE Accelerator", 425 pdc202xx_chip_map, 426 }, 427 { PCI_PRODUCT_PROMISE_ULTRA66, 428 IDE_PCI_CLASS_OVERRIDE, 429 "Promise Ultra66/ATA Bus Master IDE Accelerator", 430 pdc202xx_chip_map, 431 }, 432 { PCI_PRODUCT_PROMISE_ULTRA100, 433 IDE_PCI_CLASS_OVERRIDE, 434 "Promise Ultra100/ATA Bus Master IDE Accelerator", 435 pdc202xx_chip_map, 436 }, 437 { PCI_PRODUCT_PROMISE_ULTRA100X, 438 IDE_PCI_CLASS_OVERRIDE, 439 "Promise Ultra100/ATA Bus Master IDE Accelerator", 440 pdc202xx_chip_map, 441 }, 442 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 443 IDE_PCI_CLASS_OVERRIDE, 444 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 445 pdc202xx_chip_map, 446 }, 447 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 448 IDE_PCI_CLASS_OVERRIDE, 449 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 450 pdc202xx_chip_map, 451 }, 452 { PCI_PRODUCT_PROMISE_ULTRA133, 453 IDE_PCI_CLASS_OVERRIDE, 454 "Promise Ultra133/ATA Bus Master IDE Accelerator", 455 pdc202xx_chip_map, 456 }, 457 { 0, 458 0, 459 NULL, 460 NULL 461 } 462 }; 463 464 const struct pciide_product_desc pciide_opti_products[] = { 465 { PCI_PRODUCT_OPTI_82C621, 466 0, 467 "OPTi 82c621 PCI IDE controller", 468 opti_chip_map, 469 }, 470 { PCI_PRODUCT_OPTI_82C568, 471 0, 472 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 473 opti_chip_map, 474 }, 475 { PCI_PRODUCT_OPTI_82D568, 476 0, 477 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 478 opti_chip_map, 479 }, 480 { 0, 481 0, 482 NULL, 483 NULL 484 } 485 }; 486 487 const struct pciide_product_desc pciide_triones_products[] = { 488 { PCI_PRODUCT_TRIONES_HPT366, 489 IDE_PCI_CLASS_OVERRIDE, 490 NULL, 491 hpt_chip_map, 492 }, 493 { 0, 494 0, 495 NULL, 496 NULL 497 } 498 }; 499 500 const struct pciide_product_desc pciide_acard_products[] = { 501 { PCI_PRODUCT_ACARD_ATP850U, 502 IDE_PCI_CLASS_OVERRIDE, 503 "Acard ATP850U Ultra33 IDE Controller", 504 acard_chip_map, 505 }, 506 { PCI_PRODUCT_ACARD_ATP860, 507 IDE_PCI_CLASS_OVERRIDE, 508 "Acard ATP860 Ultra66 IDE Controller", 509 acard_chip_map, 510 }, 511 { PCI_PRODUCT_ACARD_ATP860A, 512 IDE_PCI_CLASS_OVERRIDE, 513 "Acard ATP860-A Ultra66 IDE Controller", 514 acard_chip_map, 515 }, 516 { 0, 517 0, 518 NULL, 519 NULL 520 } 521 }; 522 523 const struct pciide_product_desc pciide_serverworks_products[] = { 524 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 525 0, 526 "ServerWorks OSB4 IDE Controller", 527 serverworks_chip_map, 528 }, 529 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 530 0, 531 "ServerWorks CSB5 IDE Controller", 532 serverworks_chip_map, 533 }, 534 { 0, 535 0, 536 NULL, 537 } 538 }; 539 540 const struct pciide_product_desc pciide_symphony_products[] = { 541 { PCI_PRODUCT_SYMPHONY_82C105, 542 0, 543 "Symphony Labs 82C105 IDE controller", 544 sl82c105_chip_map, 545 }, 546 { 0, 547 0, 548 NULL, 549 } 550 }; 551 552 const struct pciide_product_desc pciide_winbond_products[] = { 553 { PCI_PRODUCT_WINBOND_W83C553F_1, 554 0, 555 "Winbond W83C553F IDE controller", 556 sl82c105_chip_map, 557 }, 558 { 0, 559 0, 560 NULL, 561 } 562 }; 563 564 struct pciide_vendor_desc { 565 u_int32_t ide_vendor; 566 const struct pciide_product_desc *ide_products; 567 }; 568 569 const struct pciide_vendor_desc pciide_vendors[] = { 570 { PCI_VENDOR_INTEL, pciide_intel_products }, 571 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 572 { PCI_VENDOR_VIATECH, pciide_via_products }, 573 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 574 { PCI_VENDOR_SIS, pciide_sis_products }, 575 { PCI_VENDOR_ALI, pciide_acer_products }, 576 { PCI_VENDOR_PROMISE, pciide_promise_products }, 577 { PCI_VENDOR_AMD, pciide_amd_products }, 578 { PCI_VENDOR_OPTI, pciide_opti_products }, 579 { PCI_VENDOR_TRIONES, pciide_triones_products }, 580 { PCI_VENDOR_ACARD, pciide_acard_products }, 581 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 582 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 583 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 584 { 0, NULL } 585 }; 586 587 /* options passed via the 'flags' config keyword */ 588 #define PCIIDE_OPTIONS_DMA 0x01 589 #define PCIIDE_OPTIONS_NODMA 0x02 590 591 int pciide_match __P((struct device *, struct cfdata *, void *)); 592 void pciide_attach __P((struct device *, struct device *, void *)); 593 594 struct cfattach pciide_ca = { 595 sizeof(struct pciide_softc), pciide_match, pciide_attach 596 }; 597 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 598 int pciide_mapregs_compat __P(( struct pci_attach_args *, 599 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 600 int pciide_mapregs_native __P((struct pci_attach_args *, 601 struct pciide_channel *, bus_size_t *, bus_size_t *, 602 int (*pci_intr) __P((void *)))); 603 void pciide_mapreg_dma __P((struct pciide_softc *, 604 struct pci_attach_args *)); 605 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 606 void pciide_mapchan __P((struct pci_attach_args *, 607 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 608 int (*pci_intr) __P((void *)))); 609 int pciide_chan_candisable __P((struct pciide_channel *)); 610 void pciide_map_compat_intr __P(( struct pci_attach_args *, 611 struct pciide_channel *, int, int)); 612 int pciide_compat_intr __P((void *)); 613 int pciide_pci_intr __P((void *)); 614 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 615 616 const struct pciide_product_desc * 617 pciide_lookup_product(id) 618 u_int32_t id; 619 { 620 const struct pciide_product_desc *pp; 621 const struct pciide_vendor_desc *vp; 622 623 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 624 if (PCI_VENDOR(id) == vp->ide_vendor) 625 break; 626 627 if ((pp = vp->ide_products) == NULL) 628 return NULL; 629 630 for (; pp->chip_map != NULL; pp++) 631 if (PCI_PRODUCT(id) == pp->ide_product) 632 break; 633 634 if (pp->chip_map == NULL) 635 return NULL; 636 return pp; 637 } 638 639 int 640 pciide_match(parent, match, aux) 641 struct device *parent; 642 struct cfdata *match; 643 void *aux; 644 { 645 struct pci_attach_args *pa = aux; 646 const struct pciide_product_desc *pp; 647 648 /* 649 * Check the ID register to see that it's a PCI IDE controller. 650 * If it is, we assume that we can deal with it; it _should_ 651 * work in a standardized way... 652 */ 653 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 654 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 655 return (1); 656 } 657 658 /* 659 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 660 * controllers. Let see if we can deal with it anyway. 661 */ 662 pp = pciide_lookup_product(pa->pa_id); 663 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 664 return (1); 665 } 666 667 return (0); 668 } 669 670 void 671 pciide_attach(parent, self, aux) 672 struct device *parent, *self; 673 void *aux; 674 { 675 struct pci_attach_args *pa = aux; 676 pci_chipset_tag_t pc = pa->pa_pc; 677 pcitag_t tag = pa->pa_tag; 678 struct pciide_softc *sc = (struct pciide_softc *)self; 679 pcireg_t csr; 680 char devinfo[256]; 681 const char *displaydev; 682 683 sc->sc_pp = pciide_lookup_product(pa->pa_id); 684 if (sc->sc_pp == NULL) { 685 sc->sc_pp = &default_product_desc; 686 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 687 displaydev = devinfo; 688 } else 689 displaydev = sc->sc_pp->ide_name; 690 691 /* if displaydev == NULL, printf is done in chip-specific map */ 692 if (displaydev) 693 printf(": %s (rev. 0x%02x)\n", displaydev, 694 PCI_REVISION(pa->pa_class)); 695 696 sc->sc_pc = pa->pa_pc; 697 sc->sc_tag = pa->pa_tag; 698 #ifdef WDCDEBUG 699 if (wdcdebug_pciide_mask & DEBUG_PROBE) 700 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 701 #endif 702 sc->sc_pp->chip_map(sc, pa); 703 704 if (sc->sc_dma_ok) { 705 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 706 csr |= PCI_COMMAND_MASTER_ENABLE; 707 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 708 } 709 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 710 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 711 } 712 713 /* tell wether the chip is enabled or not */ 714 int 715 pciide_chipen(sc, pa) 716 struct pciide_softc *sc; 717 struct pci_attach_args *pa; 718 { 719 pcireg_t csr; 720 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 721 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 722 PCI_COMMAND_STATUS_REG); 723 printf("%s: device disabled (at %s)\n", 724 sc->sc_wdcdev.sc_dev.dv_xname, 725 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 726 "device" : "bridge"); 727 return 0; 728 } 729 return 1; 730 } 731 732 int 733 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 734 struct pci_attach_args *pa; 735 struct pciide_channel *cp; 736 int compatchan; 737 bus_size_t *cmdsizep, *ctlsizep; 738 { 739 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 740 struct channel_softc *wdc_cp = &cp->wdc_channel; 741 742 cp->compat = 1; 743 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 744 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 745 746 wdc_cp->cmd_iot = pa->pa_iot; 747 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 748 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 749 printf("%s: couldn't map %s channel cmd regs\n", 750 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 751 return (0); 752 } 753 754 wdc_cp->ctl_iot = pa->pa_iot; 755 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 756 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 757 printf("%s: couldn't map %s channel ctl regs\n", 758 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 759 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 760 PCIIDE_COMPAT_CMD_SIZE); 761 return (0); 762 } 763 764 return (1); 765 } 766 767 int 768 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 769 struct pci_attach_args * pa; 770 struct pciide_channel *cp; 771 bus_size_t *cmdsizep, *ctlsizep; 772 int (*pci_intr) __P((void *)); 773 { 774 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 775 struct channel_softc *wdc_cp = &cp->wdc_channel; 776 const char *intrstr; 777 pci_intr_handle_t intrhandle; 778 779 cp->compat = 0; 780 781 if (sc->sc_pci_ih == NULL) { 782 if (pci_intr_map(pa, &intrhandle) != 0) { 783 printf("%s: couldn't map native-PCI interrupt\n", 784 sc->sc_wdcdev.sc_dev.dv_xname); 785 return 0; 786 } 787 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 788 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 789 intrhandle, IPL_BIO, pci_intr, sc); 790 if (sc->sc_pci_ih != NULL) { 791 printf("%s: using %s for native-PCI interrupt\n", 792 sc->sc_wdcdev.sc_dev.dv_xname, 793 intrstr ? intrstr : "unknown interrupt"); 794 } else { 795 printf("%s: couldn't establish native-PCI interrupt", 796 sc->sc_wdcdev.sc_dev.dv_xname); 797 if (intrstr != NULL) 798 printf(" at %s", intrstr); 799 printf("\n"); 800 return 0; 801 } 802 } 803 cp->ih = sc->sc_pci_ih; 804 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 805 PCI_MAPREG_TYPE_IO, 0, 806 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 807 printf("%s: couldn't map %s channel cmd regs\n", 808 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 809 return 0; 810 } 811 812 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 813 PCI_MAPREG_TYPE_IO, 0, 814 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 815 printf("%s: couldn't map %s channel ctl regs\n", 816 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 817 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 818 return 0; 819 } 820 /* 821 * In native mode, 4 bytes of I/O space are mapped for the control 822 * register, the control register is at offset 2. Pass the generic 823 * code a handle for only one byte at the rigth offset. 824 */ 825 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 826 &wdc_cp->ctl_ioh) != 0) { 827 printf("%s: unable to subregion %s channel ctl regs\n", 828 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 829 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 830 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 831 return 0; 832 } 833 return (1); 834 } 835 836 void 837 pciide_mapreg_dma(sc, pa) 838 struct pciide_softc *sc; 839 struct pci_attach_args *pa; 840 { 841 pcireg_t maptype; 842 bus_addr_t addr; 843 844 /* 845 * Map DMA registers 846 * 847 * Note that sc_dma_ok is the right variable to test to see if 848 * DMA can be done. If the interface doesn't support DMA, 849 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 850 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 851 * non-zero if the interface supports DMA and the registers 852 * could be mapped. 853 * 854 * XXX Note that despite the fact that the Bus Master IDE specs 855 * XXX say that "The bus master IDE function uses 16 bytes of IO 856 * XXX space," some controllers (at least the United 857 * XXX Microelectronics UM8886BF) place it in memory space. 858 */ 859 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 860 PCIIDE_REG_BUS_MASTER_DMA); 861 862 switch (maptype) { 863 case PCI_MAPREG_TYPE_IO: 864 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 865 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 866 &addr, NULL, NULL) == 0); 867 if (sc->sc_dma_ok == 0) { 868 printf(", but unused (couldn't query registers)"); 869 break; 870 } 871 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 872 && addr >= 0x10000) { 873 sc->sc_dma_ok = 0; 874 printf(", but unused (registers at unsafe address " 875 "%#lx)", (unsigned long)addr); 876 break; 877 } 878 /* FALLTHROUGH */ 879 880 case PCI_MAPREG_MEM_TYPE_32BIT: 881 sc->sc_dma_ok = (pci_mapreg_map(pa, 882 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 883 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 884 sc->sc_dmat = pa->pa_dmat; 885 if (sc->sc_dma_ok == 0) { 886 printf(", but unused (couldn't map registers)"); 887 } else { 888 sc->sc_wdcdev.dma_arg = sc; 889 sc->sc_wdcdev.dma_init = pciide_dma_init; 890 sc->sc_wdcdev.dma_start = pciide_dma_start; 891 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 892 } 893 894 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 895 PCIIDE_OPTIONS_NODMA) { 896 printf(", but unused (forced off by config file)"); 897 sc->sc_dma_ok = 0; 898 } 899 break; 900 901 default: 902 sc->sc_dma_ok = 0; 903 printf(", but unsupported register maptype (0x%x)", maptype); 904 } 905 } 906 907 int 908 pciide_compat_intr(arg) 909 void *arg; 910 { 911 struct pciide_channel *cp = arg; 912 913 #ifdef DIAGNOSTIC 914 /* should only be called for a compat channel */ 915 if (cp->compat == 0) 916 panic("pciide compat intr called for non-compat chan %p\n", cp); 917 #endif 918 return (wdcintr(&cp->wdc_channel)); 919 } 920 921 int 922 pciide_pci_intr(arg) 923 void *arg; 924 { 925 struct pciide_softc *sc = arg; 926 struct pciide_channel *cp; 927 struct channel_softc *wdc_cp; 928 int i, rv, crv; 929 930 rv = 0; 931 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 932 cp = &sc->pciide_channels[i]; 933 wdc_cp = &cp->wdc_channel; 934 935 /* If a compat channel skip. */ 936 if (cp->compat) 937 continue; 938 /* if this channel not waiting for intr, skip */ 939 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 940 continue; 941 942 crv = wdcintr(wdc_cp); 943 if (crv == 0) 944 ; /* leave rv alone */ 945 else if (crv == 1) 946 rv = 1; /* claim the intr */ 947 else if (rv == 0) /* crv should be -1 in this case */ 948 rv = crv; /* if we've done no better, take it */ 949 } 950 return (rv); 951 } 952 953 void 954 pciide_channel_dma_setup(cp) 955 struct pciide_channel *cp; 956 { 957 int drive; 958 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 959 struct ata_drive_datas *drvp; 960 961 for (drive = 0; drive < 2; drive++) { 962 drvp = &cp->wdc_channel.ch_drive[drive]; 963 /* If no drive, skip */ 964 if ((drvp->drive_flags & DRIVE) == 0) 965 continue; 966 /* setup DMA if needed */ 967 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 968 (drvp->drive_flags & DRIVE_UDMA) == 0) || 969 sc->sc_dma_ok == 0) { 970 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 971 continue; 972 } 973 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 974 != 0) { 975 /* Abort DMA setup */ 976 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 977 continue; 978 } 979 } 980 } 981 982 int 983 pciide_dma_table_setup(sc, channel, drive) 984 struct pciide_softc *sc; 985 int channel, drive; 986 { 987 bus_dma_segment_t seg; 988 int error, rseg; 989 const bus_size_t dma_table_size = 990 sizeof(struct idedma_table) * NIDEDMA_TABLES; 991 struct pciide_dma_maps *dma_maps = 992 &sc->pciide_channels[channel].dma_maps[drive]; 993 994 /* If table was already allocated, just return */ 995 if (dma_maps->dma_table) 996 return 0; 997 998 /* Allocate memory for the DMA tables and map it */ 999 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1000 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1001 BUS_DMA_NOWAIT)) != 0) { 1002 printf("%s:%d: unable to allocate table DMA for " 1003 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1004 channel, drive, error); 1005 return error; 1006 } 1007 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1008 dma_table_size, 1009 (caddr_t *)&dma_maps->dma_table, 1010 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1011 printf("%s:%d: unable to map table DMA for" 1012 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1013 channel, drive, error); 1014 return error; 1015 } 1016 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1017 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1018 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1019 1020 /* Create and load table DMA map for this disk */ 1021 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1022 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1023 &dma_maps->dmamap_table)) != 0) { 1024 printf("%s:%d: unable to create table DMA map for " 1025 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1026 channel, drive, error); 1027 return error; 1028 } 1029 if ((error = bus_dmamap_load(sc->sc_dmat, 1030 dma_maps->dmamap_table, 1031 dma_maps->dma_table, 1032 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1033 printf("%s:%d: unable to load table DMA map for " 1034 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1035 channel, drive, error); 1036 return error; 1037 } 1038 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1039 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1040 DEBUG_PROBE); 1041 /* Create a xfer DMA map for this drive */ 1042 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1043 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1044 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1045 &dma_maps->dmamap_xfer)) != 0) { 1046 printf("%s:%d: unable to create xfer DMA map for " 1047 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1048 channel, drive, error); 1049 return error; 1050 } 1051 return 0; 1052 } 1053 1054 int 1055 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1056 void *v; 1057 int channel, drive; 1058 void *databuf; 1059 size_t datalen; 1060 int flags; 1061 { 1062 struct pciide_softc *sc = v; 1063 int error, seg; 1064 struct pciide_dma_maps *dma_maps = 1065 &sc->pciide_channels[channel].dma_maps[drive]; 1066 1067 error = bus_dmamap_load(sc->sc_dmat, 1068 dma_maps->dmamap_xfer, 1069 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1070 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1071 if (error) { 1072 printf("%s:%d: unable to load xfer DMA map for" 1073 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1074 channel, drive, error); 1075 return error; 1076 } 1077 1078 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1079 dma_maps->dmamap_xfer->dm_mapsize, 1080 (flags & WDC_DMA_READ) ? 1081 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1082 1083 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1084 #ifdef DIAGNOSTIC 1085 /* A segment must not cross a 64k boundary */ 1086 { 1087 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1088 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1089 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1090 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1091 printf("pciide_dma: segment %d physical addr 0x%lx" 1092 " len 0x%lx not properly aligned\n", 1093 seg, phys, len); 1094 panic("pciide_dma: buf align"); 1095 } 1096 } 1097 #endif 1098 dma_maps->dma_table[seg].base_addr = 1099 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1100 dma_maps->dma_table[seg].byte_count = 1101 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1102 IDEDMA_BYTE_COUNT_MASK); 1103 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1104 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1105 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1106 1107 } 1108 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1109 htole32(IDEDMA_BYTE_COUNT_EOT); 1110 1111 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1112 dma_maps->dmamap_table->dm_mapsize, 1113 BUS_DMASYNC_PREWRITE); 1114 1115 /* Maps are ready. Start DMA function */ 1116 #ifdef DIAGNOSTIC 1117 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1118 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1119 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1120 panic("pciide_dma_init: table align"); 1121 } 1122 #endif 1123 1124 /* Clear status bits */ 1125 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1126 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1127 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1128 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1129 /* Write table addr */ 1130 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1131 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1132 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1133 /* set read/write */ 1134 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1135 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1136 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1137 /* remember flags */ 1138 dma_maps->dma_flags = flags; 1139 return 0; 1140 } 1141 1142 void 1143 pciide_dma_start(v, channel, drive) 1144 void *v; 1145 int channel, drive; 1146 { 1147 struct pciide_softc *sc = v; 1148 1149 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1150 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1151 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1152 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1153 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1154 } 1155 1156 int 1157 pciide_dma_finish(v, channel, drive, force) 1158 void *v; 1159 int channel, drive; 1160 int force; 1161 { 1162 struct pciide_softc *sc = v; 1163 u_int8_t status; 1164 int error = 0; 1165 struct pciide_dma_maps *dma_maps = 1166 &sc->pciide_channels[channel].dma_maps[drive]; 1167 1168 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1169 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1170 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1171 DEBUG_XFERS); 1172 1173 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1174 return WDC_DMAST_NOIRQ; 1175 1176 /* stop DMA channel */ 1177 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1178 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1179 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1180 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1181 1182 /* Unload the map of the data buffer */ 1183 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1184 dma_maps->dmamap_xfer->dm_mapsize, 1185 (dma_maps->dma_flags & WDC_DMA_READ) ? 1186 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1187 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1188 1189 if ((status & IDEDMA_CTL_ERR) != 0) { 1190 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1191 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1192 error |= WDC_DMAST_ERR; 1193 } 1194 1195 if ((status & IDEDMA_CTL_INTR) == 0) { 1196 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1197 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1198 drive, status); 1199 error |= WDC_DMAST_NOIRQ; 1200 } 1201 1202 if ((status & IDEDMA_CTL_ACT) != 0) { 1203 /* data underrun, may be a valid condition for ATAPI */ 1204 error |= WDC_DMAST_UNDER; 1205 } 1206 return error; 1207 } 1208 1209 void 1210 pciide_irqack(chp) 1211 struct channel_softc *chp; 1212 { 1213 struct pciide_channel *cp = (struct pciide_channel*)chp; 1214 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1215 1216 /* clear status bits in IDE DMA registers */ 1217 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1218 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1219 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1220 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1221 } 1222 1223 /* some common code used by several chip_map */ 1224 int 1225 pciide_chansetup(sc, channel, interface) 1226 struct pciide_softc *sc; 1227 int channel; 1228 pcireg_t interface; 1229 { 1230 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1231 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1232 cp->name = PCIIDE_CHANNEL_NAME(channel); 1233 cp->wdc_channel.channel = channel; 1234 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1235 cp->wdc_channel.ch_queue = 1236 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1237 if (cp->wdc_channel.ch_queue == NULL) { 1238 printf("%s %s channel: " 1239 "can't allocate memory for command queue", 1240 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1241 return 0; 1242 } 1243 printf("%s: %s channel %s to %s mode\n", 1244 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1245 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1246 "configured" : "wired", 1247 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1248 "native-PCI" : "compatibility"); 1249 return 1; 1250 } 1251 1252 /* some common code used by several chip channel_map */ 1253 void 1254 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1255 struct pci_attach_args *pa; 1256 struct pciide_channel *cp; 1257 pcireg_t interface; 1258 bus_size_t *cmdsizep, *ctlsizep; 1259 int (*pci_intr) __P((void *)); 1260 { 1261 struct channel_softc *wdc_cp = &cp->wdc_channel; 1262 1263 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1264 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1265 pci_intr); 1266 else 1267 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1268 wdc_cp->channel, cmdsizep, ctlsizep); 1269 1270 if (cp->hw_ok == 0) 1271 return; 1272 wdc_cp->data32iot = wdc_cp->cmd_iot; 1273 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1274 wdcattach(wdc_cp); 1275 } 1276 1277 /* 1278 * Generic code to call to know if a channel can be disabled. Return 1 1279 * if channel can be disabled, 0 if not 1280 */ 1281 int 1282 pciide_chan_candisable(cp) 1283 struct pciide_channel *cp; 1284 { 1285 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1286 struct channel_softc *wdc_cp = &cp->wdc_channel; 1287 1288 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1289 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1290 printf("%s: disabling %s channel (no drives)\n", 1291 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1292 cp->hw_ok = 0; 1293 return 1; 1294 } 1295 return 0; 1296 } 1297 1298 /* 1299 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1300 * Set hw_ok=0 on failure 1301 */ 1302 void 1303 pciide_map_compat_intr(pa, cp, compatchan, interface) 1304 struct pci_attach_args *pa; 1305 struct pciide_channel *cp; 1306 int compatchan, interface; 1307 { 1308 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1309 struct channel_softc *wdc_cp = &cp->wdc_channel; 1310 1311 if (cp->hw_ok == 0) 1312 return; 1313 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1314 return; 1315 1316 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1317 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1318 pa, compatchan, pciide_compat_intr, cp); 1319 if (cp->ih == NULL) { 1320 #endif 1321 printf("%s: no compatibility interrupt for use by %s " 1322 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1323 cp->hw_ok = 0; 1324 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1325 } 1326 #endif 1327 } 1328 1329 void 1330 pciide_print_modes(cp) 1331 struct pciide_channel *cp; 1332 { 1333 wdc_print_modes(&cp->wdc_channel); 1334 } 1335 1336 void 1337 default_chip_map(sc, pa) 1338 struct pciide_softc *sc; 1339 struct pci_attach_args *pa; 1340 { 1341 struct pciide_channel *cp; 1342 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1343 pcireg_t csr; 1344 int channel, drive; 1345 struct ata_drive_datas *drvp; 1346 u_int8_t idedma_ctl; 1347 bus_size_t cmdsize, ctlsize; 1348 char *failreason; 1349 1350 if (pciide_chipen(sc, pa) == 0) 1351 return; 1352 1353 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1354 printf("%s: bus-master DMA support present", 1355 sc->sc_wdcdev.sc_dev.dv_xname); 1356 if (sc->sc_pp == &default_product_desc && 1357 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1358 PCIIDE_OPTIONS_DMA) == 0) { 1359 printf(", but unused (no driver support)"); 1360 sc->sc_dma_ok = 0; 1361 } else { 1362 pciide_mapreg_dma(sc, pa); 1363 if (sc->sc_dma_ok != 0) 1364 printf(", used without full driver " 1365 "support"); 1366 } 1367 } else { 1368 printf("%s: hardware does not support DMA", 1369 sc->sc_wdcdev.sc_dev.dv_xname); 1370 sc->sc_dma_ok = 0; 1371 } 1372 printf("\n"); 1373 if (sc->sc_dma_ok) { 1374 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1375 sc->sc_wdcdev.irqack = pciide_irqack; 1376 } 1377 sc->sc_wdcdev.PIO_cap = 0; 1378 sc->sc_wdcdev.DMA_cap = 0; 1379 1380 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1381 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1382 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1383 1384 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1385 cp = &sc->pciide_channels[channel]; 1386 if (pciide_chansetup(sc, channel, interface) == 0) 1387 continue; 1388 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1389 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1390 &ctlsize, pciide_pci_intr); 1391 } else { 1392 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1393 channel, &cmdsize, &ctlsize); 1394 } 1395 if (cp->hw_ok == 0) 1396 continue; 1397 /* 1398 * Check to see if something appears to be there. 1399 */ 1400 failreason = NULL; 1401 if (!wdcprobe(&cp->wdc_channel)) { 1402 failreason = "not responding; disabled or no drives?"; 1403 goto next; 1404 } 1405 /* 1406 * Now, make sure it's actually attributable to this PCI IDE 1407 * channel by trying to access the channel again while the 1408 * PCI IDE controller's I/O space is disabled. (If the 1409 * channel no longer appears to be there, it belongs to 1410 * this controller.) YUCK! 1411 */ 1412 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1413 PCI_COMMAND_STATUS_REG); 1414 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1415 csr & ~PCI_COMMAND_IO_ENABLE); 1416 if (wdcprobe(&cp->wdc_channel)) 1417 failreason = "other hardware responding at addresses"; 1418 pci_conf_write(sc->sc_pc, sc->sc_tag, 1419 PCI_COMMAND_STATUS_REG, csr); 1420 next: 1421 if (failreason) { 1422 printf("%s: %s channel ignored (%s)\n", 1423 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1424 failreason); 1425 cp->hw_ok = 0; 1426 bus_space_unmap(cp->wdc_channel.cmd_iot, 1427 cp->wdc_channel.cmd_ioh, cmdsize); 1428 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1429 bus_space_unmap(cp->wdc_channel.ctl_iot, 1430 cp->ctl_baseioh, ctlsize); 1431 else 1432 bus_space_unmap(cp->wdc_channel.ctl_iot, 1433 cp->wdc_channel.ctl_ioh, ctlsize); 1434 } else { 1435 pciide_map_compat_intr(pa, cp, channel, interface); 1436 } 1437 if (cp->hw_ok) { 1438 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1439 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1440 wdcattach(&cp->wdc_channel); 1441 } 1442 } 1443 1444 if (sc->sc_dma_ok == 0) 1445 return; 1446 1447 /* Allocate DMA maps */ 1448 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1449 idedma_ctl = 0; 1450 cp = &sc->pciide_channels[channel]; 1451 for (drive = 0; drive < 2; drive++) { 1452 drvp = &cp->wdc_channel.ch_drive[drive]; 1453 /* If no drive, skip */ 1454 if ((drvp->drive_flags & DRIVE) == 0) 1455 continue; 1456 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1457 continue; 1458 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1459 /* Abort DMA setup */ 1460 printf("%s:%d:%d: can't allocate DMA maps, " 1461 "using PIO transfers\n", 1462 sc->sc_wdcdev.sc_dev.dv_xname, 1463 channel, drive); 1464 drvp->drive_flags &= ~DRIVE_DMA; 1465 } 1466 printf("%s:%d:%d: using DMA data transfers\n", 1467 sc->sc_wdcdev.sc_dev.dv_xname, 1468 channel, drive); 1469 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1470 } 1471 if (idedma_ctl != 0) { 1472 /* Add software bits in status register */ 1473 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1474 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1475 idedma_ctl); 1476 } 1477 } 1478 } 1479 1480 void 1481 piix_chip_map(sc, pa) 1482 struct pciide_softc *sc; 1483 struct pci_attach_args *pa; 1484 { 1485 struct pciide_channel *cp; 1486 int channel; 1487 u_int32_t idetim; 1488 bus_size_t cmdsize, ctlsize; 1489 1490 if (pciide_chipen(sc, pa) == 0) 1491 return; 1492 1493 printf("%s: bus-master DMA support present", 1494 sc->sc_wdcdev.sc_dev.dv_xname); 1495 pciide_mapreg_dma(sc, pa); 1496 printf("\n"); 1497 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1498 WDC_CAPABILITY_MODE; 1499 if (sc->sc_dma_ok) { 1500 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1501 sc->sc_wdcdev.irqack = pciide_irqack; 1502 switch(sc->sc_pp->ide_product) { 1503 case PCI_PRODUCT_INTEL_82371AB_IDE: 1504 case PCI_PRODUCT_INTEL_82440MX_IDE: 1505 case PCI_PRODUCT_INTEL_82801AA_IDE: 1506 case PCI_PRODUCT_INTEL_82801AB_IDE: 1507 case PCI_PRODUCT_INTEL_82801BA_IDE: 1508 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1509 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1510 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1511 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1512 } 1513 } 1514 sc->sc_wdcdev.PIO_cap = 4; 1515 sc->sc_wdcdev.DMA_cap = 2; 1516 switch(sc->sc_pp->ide_product) { 1517 case PCI_PRODUCT_INTEL_82801AA_IDE: 1518 sc->sc_wdcdev.UDMA_cap = 4; 1519 break; 1520 case PCI_PRODUCT_INTEL_82801BA_IDE: 1521 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1522 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1523 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1524 sc->sc_wdcdev.UDMA_cap = 5; 1525 break; 1526 default: 1527 sc->sc_wdcdev.UDMA_cap = 2; 1528 } 1529 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1530 sc->sc_wdcdev.set_modes = piix_setup_channel; 1531 else 1532 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1533 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1534 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1535 1536 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1537 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1538 DEBUG_PROBE); 1539 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1540 WDCDEBUG_PRINT((", sidetim=0x%x", 1541 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1542 DEBUG_PROBE); 1543 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1544 WDCDEBUG_PRINT((", udamreg 0x%x", 1545 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1546 DEBUG_PROBE); 1547 } 1548 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1554 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1555 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1556 DEBUG_PROBE); 1557 } 1558 1559 } 1560 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1561 1562 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1563 cp = &sc->pciide_channels[channel]; 1564 /* PIIX is compat-only */ 1565 if (pciide_chansetup(sc, channel, 0) == 0) 1566 continue; 1567 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1568 if ((PIIX_IDETIM_READ(idetim, channel) & 1569 PIIX_IDETIM_IDE) == 0) { 1570 printf("%s: %s channel ignored (disabled)\n", 1571 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1572 continue; 1573 } 1574 /* PIIX are compat-only pciide devices */ 1575 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1576 if (cp->hw_ok == 0) 1577 continue; 1578 if (pciide_chan_candisable(cp)) { 1579 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1580 channel); 1581 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1582 idetim); 1583 } 1584 pciide_map_compat_intr(pa, cp, channel, 0); 1585 if (cp->hw_ok == 0) 1586 continue; 1587 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1588 } 1589 1590 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1591 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1592 DEBUG_PROBE); 1593 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1594 WDCDEBUG_PRINT((", sidetim=0x%x", 1595 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1596 DEBUG_PROBE); 1597 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1598 WDCDEBUG_PRINT((", udamreg 0x%x", 1599 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1600 DEBUG_PROBE); 1601 } 1602 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1603 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1604 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1605 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1606 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1608 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1609 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1610 DEBUG_PROBE); 1611 } 1612 } 1613 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1614 } 1615 1616 void 1617 piix_setup_channel(chp) 1618 struct channel_softc *chp; 1619 { 1620 u_int8_t mode[2], drive; 1621 u_int32_t oidetim, idetim, idedma_ctl; 1622 struct pciide_channel *cp = (struct pciide_channel*)chp; 1623 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1624 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1625 1626 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1627 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1628 idedma_ctl = 0; 1629 1630 /* set up new idetim: Enable IDE registers decode */ 1631 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1632 chp->channel); 1633 1634 /* setup DMA */ 1635 pciide_channel_dma_setup(cp); 1636 1637 /* 1638 * Here we have to mess up with drives mode: PIIX can't have 1639 * different timings for master and slave drives. 1640 * We need to find the best combination. 1641 */ 1642 1643 /* If both drives supports DMA, take the lower mode */ 1644 if ((drvp[0].drive_flags & DRIVE_DMA) && 1645 (drvp[1].drive_flags & DRIVE_DMA)) { 1646 mode[0] = mode[1] = 1647 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1648 drvp[0].DMA_mode = mode[0]; 1649 drvp[1].DMA_mode = mode[1]; 1650 goto ok; 1651 } 1652 /* 1653 * If only one drive supports DMA, use its mode, and 1654 * put the other one in PIO mode 0 if mode not compatible 1655 */ 1656 if (drvp[0].drive_flags & DRIVE_DMA) { 1657 mode[0] = drvp[0].DMA_mode; 1658 mode[1] = drvp[1].PIO_mode; 1659 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1660 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1661 mode[1] = drvp[1].PIO_mode = 0; 1662 goto ok; 1663 } 1664 if (drvp[1].drive_flags & DRIVE_DMA) { 1665 mode[1] = drvp[1].DMA_mode; 1666 mode[0] = drvp[0].PIO_mode; 1667 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1668 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1669 mode[0] = drvp[0].PIO_mode = 0; 1670 goto ok; 1671 } 1672 /* 1673 * If both drives are not DMA, takes the lower mode, unless 1674 * one of them is PIO mode < 2 1675 */ 1676 if (drvp[0].PIO_mode < 2) { 1677 mode[0] = drvp[0].PIO_mode = 0; 1678 mode[1] = drvp[1].PIO_mode; 1679 } else if (drvp[1].PIO_mode < 2) { 1680 mode[1] = drvp[1].PIO_mode = 0; 1681 mode[0] = drvp[0].PIO_mode; 1682 } else { 1683 mode[0] = mode[1] = 1684 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1685 drvp[0].PIO_mode = mode[0]; 1686 drvp[1].PIO_mode = mode[1]; 1687 } 1688 ok: /* The modes are setup */ 1689 for (drive = 0; drive < 2; drive++) { 1690 if (drvp[drive].drive_flags & DRIVE_DMA) { 1691 idetim |= piix_setup_idetim_timings( 1692 mode[drive], 1, chp->channel); 1693 goto end; 1694 } 1695 } 1696 /* If we are there, none of the drives are DMA */ 1697 if (mode[0] >= 2) 1698 idetim |= piix_setup_idetim_timings( 1699 mode[0], 0, chp->channel); 1700 else 1701 idetim |= piix_setup_idetim_timings( 1702 mode[1], 0, chp->channel); 1703 end: /* 1704 * timing mode is now set up in the controller. Enable 1705 * it per-drive 1706 */ 1707 for (drive = 0; drive < 2; drive++) { 1708 /* If no drive, skip */ 1709 if ((drvp[drive].drive_flags & DRIVE) == 0) 1710 continue; 1711 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1712 if (drvp[drive].drive_flags & DRIVE_DMA) 1713 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1714 } 1715 if (idedma_ctl != 0) { 1716 /* Add software bits in status register */ 1717 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1718 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1719 idedma_ctl); 1720 } 1721 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1722 pciide_print_modes(cp); 1723 } 1724 1725 void 1726 piix3_4_setup_channel(chp) 1727 struct channel_softc *chp; 1728 { 1729 struct ata_drive_datas *drvp; 1730 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1731 struct pciide_channel *cp = (struct pciide_channel*)chp; 1732 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1733 int drive; 1734 int channel = chp->channel; 1735 1736 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1737 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1738 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1739 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1740 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1741 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1742 PIIX_SIDETIM_RTC_MASK(channel)); 1743 1744 idedma_ctl = 0; 1745 /* If channel disabled, no need to go further */ 1746 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1747 return; 1748 /* set up new idetim: Enable IDE registers decode */ 1749 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1750 1751 /* setup DMA if needed */ 1752 pciide_channel_dma_setup(cp); 1753 1754 for (drive = 0; drive < 2; drive++) { 1755 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1756 PIIX_UDMATIM_SET(0x3, channel, drive)); 1757 drvp = &chp->ch_drive[drive]; 1758 /* If no drive, skip */ 1759 if ((drvp->drive_flags & DRIVE) == 0) 1760 continue; 1761 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1762 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1763 goto pio; 1764 1765 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1766 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1767 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1768 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1769 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1770 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1771 ideconf |= PIIX_CONFIG_PINGPONG; 1772 } 1773 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1774 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1775 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1776 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1777 /* setup Ultra/100 */ 1778 if (drvp->UDMA_mode > 2 && 1779 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1780 drvp->UDMA_mode = 2; 1781 if (drvp->UDMA_mode > 4) { 1782 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1783 } else { 1784 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1785 if (drvp->UDMA_mode > 2) { 1786 ideconf |= PIIX_CONFIG_UDMA66(channel, 1787 drive); 1788 } else { 1789 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1790 drive); 1791 } 1792 } 1793 } 1794 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1795 /* setup Ultra/66 */ 1796 if (drvp->UDMA_mode > 2 && 1797 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1798 drvp->UDMA_mode = 2; 1799 if (drvp->UDMA_mode > 2) 1800 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1801 else 1802 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1803 } 1804 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1805 (drvp->drive_flags & DRIVE_UDMA)) { 1806 /* use Ultra/DMA */ 1807 drvp->drive_flags &= ~DRIVE_DMA; 1808 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1809 udmareg |= PIIX_UDMATIM_SET( 1810 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1811 } else { 1812 /* use Multiword DMA */ 1813 drvp->drive_flags &= ~DRIVE_UDMA; 1814 if (drive == 0) { 1815 idetim |= piix_setup_idetim_timings( 1816 drvp->DMA_mode, 1, channel); 1817 } else { 1818 sidetim |= piix_setup_sidetim_timings( 1819 drvp->DMA_mode, 1, channel); 1820 idetim =PIIX_IDETIM_SET(idetim, 1821 PIIX_IDETIM_SITRE, channel); 1822 } 1823 } 1824 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1825 1826 pio: /* use PIO mode */ 1827 idetim |= piix_setup_idetim_drvs(drvp); 1828 if (drive == 0) { 1829 idetim |= piix_setup_idetim_timings( 1830 drvp->PIO_mode, 0, channel); 1831 } else { 1832 sidetim |= piix_setup_sidetim_timings( 1833 drvp->PIO_mode, 0, channel); 1834 idetim =PIIX_IDETIM_SET(idetim, 1835 PIIX_IDETIM_SITRE, channel); 1836 } 1837 } 1838 if (idedma_ctl != 0) { 1839 /* Add software bits in status register */ 1840 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1841 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1842 idedma_ctl); 1843 } 1844 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1845 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1846 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1847 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1848 pciide_print_modes(cp); 1849 } 1850 1851 1852 /* setup ISP and RTC fields, based on mode */ 1853 static u_int32_t 1854 piix_setup_idetim_timings(mode, dma, channel) 1855 u_int8_t mode; 1856 u_int8_t dma; 1857 u_int8_t channel; 1858 { 1859 1860 if (dma) 1861 return PIIX_IDETIM_SET(0, 1862 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1863 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1864 channel); 1865 else 1866 return PIIX_IDETIM_SET(0, 1867 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1868 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1869 channel); 1870 } 1871 1872 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1873 static u_int32_t 1874 piix_setup_idetim_drvs(drvp) 1875 struct ata_drive_datas *drvp; 1876 { 1877 u_int32_t ret = 0; 1878 struct channel_softc *chp = drvp->chnl_softc; 1879 u_int8_t channel = chp->channel; 1880 u_int8_t drive = drvp->drive; 1881 1882 /* 1883 * If drive is using UDMA, timings setups are independant 1884 * So just check DMA and PIO here. 1885 */ 1886 if (drvp->drive_flags & DRIVE_DMA) { 1887 /* if mode = DMA mode 0, use compatible timings */ 1888 if ((drvp->drive_flags & DRIVE_DMA) && 1889 drvp->DMA_mode == 0) { 1890 drvp->PIO_mode = 0; 1891 return ret; 1892 } 1893 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1894 /* 1895 * PIO and DMA timings are the same, use fast timings for PIO 1896 * too, else use compat timings. 1897 */ 1898 if ((piix_isp_pio[drvp->PIO_mode] != 1899 piix_isp_dma[drvp->DMA_mode]) || 1900 (piix_rtc_pio[drvp->PIO_mode] != 1901 piix_rtc_dma[drvp->DMA_mode])) 1902 drvp->PIO_mode = 0; 1903 /* if PIO mode <= 2, use compat timings for PIO */ 1904 if (drvp->PIO_mode <= 2) { 1905 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1906 channel); 1907 return ret; 1908 } 1909 } 1910 1911 /* 1912 * Now setup PIO modes. If mode < 2, use compat timings. 1913 * Else enable fast timings. Enable IORDY and prefetch/post 1914 * if PIO mode >= 3. 1915 */ 1916 1917 if (drvp->PIO_mode < 2) 1918 return ret; 1919 1920 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1921 if (drvp->PIO_mode >= 3) { 1922 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1923 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1924 } 1925 return ret; 1926 } 1927 1928 /* setup values in SIDETIM registers, based on mode */ 1929 static u_int32_t 1930 piix_setup_sidetim_timings(mode, dma, channel) 1931 u_int8_t mode; 1932 u_int8_t dma; 1933 u_int8_t channel; 1934 { 1935 if (dma) 1936 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1937 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1938 else 1939 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1940 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1941 } 1942 1943 void 1944 amd7x6_chip_map(sc, pa) 1945 struct pciide_softc *sc; 1946 struct pci_attach_args *pa; 1947 { 1948 struct pciide_channel *cp; 1949 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1950 int channel; 1951 pcireg_t chanenable; 1952 bus_size_t cmdsize, ctlsize; 1953 1954 if (pciide_chipen(sc, pa) == 0) 1955 return; 1956 printf("%s: bus-master DMA support present", 1957 sc->sc_wdcdev.sc_dev.dv_xname); 1958 pciide_mapreg_dma(sc, pa); 1959 printf("\n"); 1960 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1961 WDC_CAPABILITY_MODE; 1962 if (sc->sc_dma_ok) { 1963 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1964 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1965 sc->sc_wdcdev.irqack = pciide_irqack; 1966 } 1967 sc->sc_wdcdev.PIO_cap = 4; 1968 sc->sc_wdcdev.DMA_cap = 2; 1969 1970 switch (sc->sc_pp->ide_product) { 1971 case PCI_PRODUCT_AMD_PBC766_IDE: 1972 case PCI_PRODUCT_AMD_PBC768_IDE: 1973 sc->sc_wdcdev.UDMA_cap = 5; 1974 break; 1975 default: 1976 sc->sc_wdcdev.UDMA_cap = 4; 1977 } 1978 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1979 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1980 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1981 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1982 1983 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1984 DEBUG_PROBE); 1985 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1986 cp = &sc->pciide_channels[channel]; 1987 if (pciide_chansetup(sc, channel, interface) == 0) 1988 continue; 1989 1990 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1991 printf("%s: %s channel ignored (disabled)\n", 1992 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1993 continue; 1994 } 1995 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1996 pciide_pci_intr); 1997 1998 if (pciide_chan_candisable(cp)) 1999 chanenable &= ~AMD7X6_CHAN_EN(channel); 2000 pciide_map_compat_intr(pa, cp, channel, interface); 2001 if (cp->hw_ok == 0) 2002 continue; 2003 2004 amd7x6_setup_channel(&cp->wdc_channel); 2005 } 2006 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2007 chanenable); 2008 return; 2009 } 2010 2011 void 2012 amd7x6_setup_channel(chp) 2013 struct channel_softc *chp; 2014 { 2015 u_int32_t udmatim_reg, datatim_reg; 2016 u_int8_t idedma_ctl; 2017 int mode, drive; 2018 struct ata_drive_datas *drvp; 2019 struct pciide_channel *cp = (struct pciide_channel*)chp; 2020 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2021 #ifndef PCIIDE_AMD756_ENABLEDMA 2022 int rev = PCI_REVISION( 2023 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2024 #endif 2025 2026 idedma_ctl = 0; 2027 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2028 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2029 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2030 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2031 2032 /* setup DMA if needed */ 2033 pciide_channel_dma_setup(cp); 2034 2035 for (drive = 0; drive < 2; drive++) { 2036 drvp = &chp->ch_drive[drive]; 2037 /* If no drive, skip */ 2038 if ((drvp->drive_flags & DRIVE) == 0) 2039 continue; 2040 /* add timing values, setup DMA if needed */ 2041 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2042 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2043 mode = drvp->PIO_mode; 2044 goto pio; 2045 } 2046 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2047 (drvp->drive_flags & DRIVE_UDMA)) { 2048 /* use Ultra/DMA */ 2049 drvp->drive_flags &= ~DRIVE_DMA; 2050 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2051 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2052 AMD7X6_UDMA_TIME(chp->channel, drive, 2053 amd7x6_udma_tim[drvp->UDMA_mode]); 2054 /* can use PIO timings, MW DMA unused */ 2055 mode = drvp->PIO_mode; 2056 } else { 2057 /* use Multiword DMA, but only if revision is OK */ 2058 drvp->drive_flags &= ~DRIVE_UDMA; 2059 #ifndef PCIIDE_AMD756_ENABLEDMA 2060 /* 2061 * The workaround doesn't seem to be necessary 2062 * with all drives, so it can be disabled by 2063 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2064 * triggered. 2065 */ 2066 if (sc->sc_pp->ide_product == 2067 PCI_PRODUCT_AMD_PBC756_IDE && 2068 AMD756_CHIPREV_DISABLEDMA(rev)) { 2069 printf("%s:%d:%d: multi-word DMA disabled due " 2070 "to chip revision\n", 2071 sc->sc_wdcdev.sc_dev.dv_xname, 2072 chp->channel, drive); 2073 mode = drvp->PIO_mode; 2074 drvp->drive_flags &= ~DRIVE_DMA; 2075 goto pio; 2076 } 2077 #endif 2078 /* mode = min(pio, dma+2) */ 2079 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2080 mode = drvp->PIO_mode; 2081 else 2082 mode = drvp->DMA_mode + 2; 2083 } 2084 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2085 2086 pio: /* setup PIO mode */ 2087 if (mode <= 2) { 2088 drvp->DMA_mode = 0; 2089 drvp->PIO_mode = 0; 2090 mode = 0; 2091 } else { 2092 drvp->PIO_mode = mode; 2093 drvp->DMA_mode = mode - 2; 2094 } 2095 datatim_reg |= 2096 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2097 amd7x6_pio_set[mode]) | 2098 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2099 amd7x6_pio_rec[mode]); 2100 } 2101 if (idedma_ctl != 0) { 2102 /* Add software bits in status register */ 2103 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2104 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2105 idedma_ctl); 2106 } 2107 pciide_print_modes(cp); 2108 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2109 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2110 } 2111 2112 void 2113 apollo_chip_map(sc, pa) 2114 struct pciide_softc *sc; 2115 struct pci_attach_args *pa; 2116 { 2117 struct pciide_channel *cp; 2118 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2119 int channel; 2120 u_int32_t ideconf; 2121 bus_size_t cmdsize, ctlsize; 2122 pcitag_t pcib_tag; 2123 pcireg_t pcib_id, pcib_class; 2124 2125 if (pciide_chipen(sc, pa) == 0) 2126 return; 2127 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2128 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2129 /* and read ID and rev of the ISA bridge */ 2130 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2131 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2132 printf(": VIA Technologies "); 2133 switch (PCI_PRODUCT(pcib_id)) { 2134 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2135 printf("VT82C586 (Apollo VP) "); 2136 if(PCI_REVISION(pcib_class) >= 0x02) { 2137 printf("ATA33 controller\n"); 2138 sc->sc_wdcdev.UDMA_cap = 2; 2139 } else { 2140 printf("controller\n"); 2141 sc->sc_wdcdev.UDMA_cap = 0; 2142 } 2143 break; 2144 case PCI_PRODUCT_VIATECH_VT82C596A: 2145 printf("VT82C596A (Apollo Pro) "); 2146 if (PCI_REVISION(pcib_class) >= 0x12) { 2147 printf("ATA66 controller\n"); 2148 sc->sc_wdcdev.UDMA_cap = 4; 2149 } else { 2150 printf("ATA33 controller\n"); 2151 sc->sc_wdcdev.UDMA_cap = 2; 2152 } 2153 break; 2154 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2155 printf("VT82C686A (Apollo KX133) "); 2156 if (PCI_REVISION(pcib_class) >= 0x40) { 2157 printf("ATA100 controller\n"); 2158 sc->sc_wdcdev.UDMA_cap = 5; 2159 } else { 2160 printf("ATA66 controller\n"); 2161 sc->sc_wdcdev.UDMA_cap = 4; 2162 } 2163 break; 2164 case PCI_PRODUCT_VIATECH_VT8233: 2165 printf("VT8233 ATA100 controller\n"); 2166 sc->sc_wdcdev.UDMA_cap = 5; 2167 break; 2168 default: 2169 printf("unknown ATA controller\n"); 2170 sc->sc_wdcdev.UDMA_cap = 0; 2171 } 2172 2173 printf("%s: bus-master DMA support present", 2174 sc->sc_wdcdev.sc_dev.dv_xname); 2175 pciide_mapreg_dma(sc, pa); 2176 printf("\n"); 2177 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2178 WDC_CAPABILITY_MODE; 2179 if (sc->sc_dma_ok) { 2180 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2181 sc->sc_wdcdev.irqack = pciide_irqack; 2182 if (sc->sc_wdcdev.UDMA_cap > 0) 2183 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2184 } 2185 sc->sc_wdcdev.PIO_cap = 4; 2186 sc->sc_wdcdev.DMA_cap = 2; 2187 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2188 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2189 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2190 2191 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2192 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2193 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2194 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2195 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2196 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2197 DEBUG_PROBE); 2198 2199 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2200 cp = &sc->pciide_channels[channel]; 2201 if (pciide_chansetup(sc, channel, interface) == 0) 2202 continue; 2203 2204 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2205 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2206 printf("%s: %s channel ignored (disabled)\n", 2207 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2208 continue; 2209 } 2210 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2211 pciide_pci_intr); 2212 if (cp->hw_ok == 0) 2213 continue; 2214 if (pciide_chan_candisable(cp)) { 2215 ideconf &= ~APO_IDECONF_EN(channel); 2216 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2217 ideconf); 2218 } 2219 pciide_map_compat_intr(pa, cp, channel, interface); 2220 2221 if (cp->hw_ok == 0) 2222 continue; 2223 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2224 } 2225 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2226 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2227 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2228 } 2229 2230 void 2231 apollo_setup_channel(chp) 2232 struct channel_softc *chp; 2233 { 2234 u_int32_t udmatim_reg, datatim_reg; 2235 u_int8_t idedma_ctl; 2236 int mode, drive; 2237 struct ata_drive_datas *drvp; 2238 struct pciide_channel *cp = (struct pciide_channel*)chp; 2239 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2240 2241 idedma_ctl = 0; 2242 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2243 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2244 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2245 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2246 2247 /* setup DMA if needed */ 2248 pciide_channel_dma_setup(cp); 2249 2250 for (drive = 0; drive < 2; drive++) { 2251 drvp = &chp->ch_drive[drive]; 2252 /* If no drive, skip */ 2253 if ((drvp->drive_flags & DRIVE) == 0) 2254 continue; 2255 /* add timing values, setup DMA if needed */ 2256 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2257 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2258 mode = drvp->PIO_mode; 2259 goto pio; 2260 } 2261 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2262 (drvp->drive_flags & DRIVE_UDMA)) { 2263 /* use Ultra/DMA */ 2264 drvp->drive_flags &= ~DRIVE_DMA; 2265 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2266 APO_UDMA_EN_MTH(chp->channel, drive); 2267 if (sc->sc_wdcdev.UDMA_cap == 5) { 2268 /* 686b */ 2269 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2270 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2271 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2272 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2273 /* 596b or 686a */ 2274 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2275 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2276 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2277 } else { 2278 /* 596a or 586b */ 2279 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2280 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2281 } 2282 /* can use PIO timings, MW DMA unused */ 2283 mode = drvp->PIO_mode; 2284 } else { 2285 /* use Multiword DMA */ 2286 drvp->drive_flags &= ~DRIVE_UDMA; 2287 /* mode = min(pio, dma+2) */ 2288 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2289 mode = drvp->PIO_mode; 2290 else 2291 mode = drvp->DMA_mode + 2; 2292 } 2293 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2294 2295 pio: /* setup PIO mode */ 2296 if (mode <= 2) { 2297 drvp->DMA_mode = 0; 2298 drvp->PIO_mode = 0; 2299 mode = 0; 2300 } else { 2301 drvp->PIO_mode = mode; 2302 drvp->DMA_mode = mode - 2; 2303 } 2304 datatim_reg |= 2305 APO_DATATIM_PULSE(chp->channel, drive, 2306 apollo_pio_set[mode]) | 2307 APO_DATATIM_RECOV(chp->channel, drive, 2308 apollo_pio_rec[mode]); 2309 } 2310 if (idedma_ctl != 0) { 2311 /* Add software bits in status register */ 2312 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2313 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2314 idedma_ctl); 2315 } 2316 pciide_print_modes(cp); 2317 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2318 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2319 } 2320 2321 void 2322 cmd_channel_map(pa, sc, channel) 2323 struct pci_attach_args *pa; 2324 struct pciide_softc *sc; 2325 int channel; 2326 { 2327 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2328 bus_size_t cmdsize, ctlsize; 2329 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2330 int interface, one_channel; 2331 2332 /* 2333 * The 0648/0649 can be told to identify as a RAID controller. 2334 * In this case, we have to fake interface 2335 */ 2336 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2337 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2338 PCIIDE_INTERFACE_SETTABLE(1); 2339 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2340 CMD_CONF_DSA1) 2341 interface |= PCIIDE_INTERFACE_PCI(0) | 2342 PCIIDE_INTERFACE_PCI(1); 2343 } else { 2344 interface = PCI_INTERFACE(pa->pa_class); 2345 } 2346 2347 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2348 cp->name = PCIIDE_CHANNEL_NAME(channel); 2349 cp->wdc_channel.channel = channel; 2350 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2351 2352 /* 2353 * Older CMD64X doesn't have independant channels 2354 */ 2355 switch (sc->sc_pp->ide_product) { 2356 case PCI_PRODUCT_CMDTECH_649: 2357 one_channel = 0; 2358 break; 2359 default: 2360 one_channel = 1; 2361 break; 2362 } 2363 2364 if (channel > 0 && one_channel) { 2365 cp->wdc_channel.ch_queue = 2366 sc->pciide_channels[0].wdc_channel.ch_queue; 2367 } else { 2368 cp->wdc_channel.ch_queue = 2369 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2370 } 2371 if (cp->wdc_channel.ch_queue == NULL) { 2372 printf("%s %s channel: " 2373 "can't allocate memory for command queue", 2374 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2375 return; 2376 } 2377 2378 printf("%s: %s channel %s to %s mode\n", 2379 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2380 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2381 "configured" : "wired", 2382 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2383 "native-PCI" : "compatibility"); 2384 2385 /* 2386 * with a CMD PCI64x, if we get here, the first channel is enabled: 2387 * there's no way to disable the first channel without disabling 2388 * the whole device 2389 */ 2390 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2391 printf("%s: %s channel ignored (disabled)\n", 2392 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2393 return; 2394 } 2395 2396 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2397 if (cp->hw_ok == 0) 2398 return; 2399 if (channel == 1) { 2400 if (pciide_chan_candisable(cp)) { 2401 ctrl &= ~CMD_CTRL_2PORT; 2402 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2403 CMD_CTRL, ctrl); 2404 } 2405 } 2406 pciide_map_compat_intr(pa, cp, channel, interface); 2407 } 2408 2409 int 2410 cmd_pci_intr(arg) 2411 void *arg; 2412 { 2413 struct pciide_softc *sc = arg; 2414 struct pciide_channel *cp; 2415 struct channel_softc *wdc_cp; 2416 int i, rv, crv; 2417 u_int32_t priirq, secirq; 2418 2419 rv = 0; 2420 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2421 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2422 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2423 cp = &sc->pciide_channels[i]; 2424 wdc_cp = &cp->wdc_channel; 2425 /* If a compat channel skip. */ 2426 if (cp->compat) 2427 continue; 2428 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2429 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2430 crv = wdcintr(wdc_cp); 2431 if (crv == 0) 2432 printf("%s:%d: bogus intr\n", 2433 sc->sc_wdcdev.sc_dev.dv_xname, i); 2434 else 2435 rv = 1; 2436 } 2437 } 2438 return rv; 2439 } 2440 2441 void 2442 cmd_chip_map(sc, pa) 2443 struct pciide_softc *sc; 2444 struct pci_attach_args *pa; 2445 { 2446 int channel; 2447 2448 /* 2449 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2450 * and base adresses registers can be disabled at 2451 * hardware level. In this case, the device is wired 2452 * in compat mode and its first channel is always enabled, 2453 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2454 * In fact, it seems that the first channel of the CMD PCI0640 2455 * can't be disabled. 2456 */ 2457 2458 #ifdef PCIIDE_CMD064x_DISABLE 2459 if (pciide_chipen(sc, pa) == 0) 2460 return; 2461 #endif 2462 2463 printf("%s: hardware does not support DMA\n", 2464 sc->sc_wdcdev.sc_dev.dv_xname); 2465 sc->sc_dma_ok = 0; 2466 2467 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2468 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2469 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2470 2471 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2472 cmd_channel_map(pa, sc, channel); 2473 } 2474 } 2475 2476 void 2477 cmd0643_9_chip_map(sc, pa) 2478 struct pciide_softc *sc; 2479 struct pci_attach_args *pa; 2480 { 2481 struct pciide_channel *cp; 2482 int channel; 2483 pcireg_t rev = PCI_REVISION(pa->pa_class); 2484 2485 /* 2486 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2487 * and base adresses registers can be disabled at 2488 * hardware level. In this case, the device is wired 2489 * in compat mode and its first channel is always enabled, 2490 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2491 * In fact, it seems that the first channel of the CMD PCI0640 2492 * can't be disabled. 2493 */ 2494 2495 #ifdef PCIIDE_CMD064x_DISABLE 2496 if (pciide_chipen(sc, pa) == 0) 2497 return; 2498 #endif 2499 printf("%s: bus-master DMA support present", 2500 sc->sc_wdcdev.sc_dev.dv_xname); 2501 pciide_mapreg_dma(sc, pa); 2502 printf("\n"); 2503 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2504 WDC_CAPABILITY_MODE; 2505 if (sc->sc_dma_ok) { 2506 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2507 switch (sc->sc_pp->ide_product) { 2508 case PCI_PRODUCT_CMDTECH_649: 2509 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2510 sc->sc_wdcdev.UDMA_cap = 5; 2511 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2512 break; 2513 case PCI_PRODUCT_CMDTECH_648: 2514 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2515 sc->sc_wdcdev.UDMA_cap = 4; 2516 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2517 break; 2518 case PCI_PRODUCT_CMDTECH_646: 2519 if (rev >= CMD0646U2_REV) { 2520 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2521 sc->sc_wdcdev.UDMA_cap = 2; 2522 } else if (rev >= CMD0646U_REV) { 2523 /* 2524 * Linux's driver claims that the 646U is broken 2525 * with UDMA. Only enable it if we know what we're 2526 * doing 2527 */ 2528 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2529 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2530 sc->sc_wdcdev.UDMA_cap = 2; 2531 #endif 2532 /* explicitly disable UDMA */ 2533 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2534 CMD_UDMATIM(0), 0); 2535 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2536 CMD_UDMATIM(1), 0); 2537 } 2538 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2539 break; 2540 default: 2541 sc->sc_wdcdev.irqack = pciide_irqack; 2542 } 2543 } 2544 2545 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2546 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2547 sc->sc_wdcdev.PIO_cap = 4; 2548 sc->sc_wdcdev.DMA_cap = 2; 2549 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2550 2551 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2552 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2553 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2554 DEBUG_PROBE); 2555 2556 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2557 cp = &sc->pciide_channels[channel]; 2558 cmd_channel_map(pa, sc, channel); 2559 if (cp->hw_ok == 0) 2560 continue; 2561 cmd0643_9_setup_channel(&cp->wdc_channel); 2562 } 2563 /* 2564 * note - this also makes sure we clear the irq disable and reset 2565 * bits 2566 */ 2567 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2568 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2569 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2570 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2571 DEBUG_PROBE); 2572 } 2573 2574 void 2575 cmd0643_9_setup_channel(chp) 2576 struct channel_softc *chp; 2577 { 2578 struct ata_drive_datas *drvp; 2579 u_int8_t tim; 2580 u_int32_t idedma_ctl, udma_reg; 2581 int drive; 2582 struct pciide_channel *cp = (struct pciide_channel*)chp; 2583 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2584 2585 idedma_ctl = 0; 2586 /* setup DMA if needed */ 2587 pciide_channel_dma_setup(cp); 2588 2589 for (drive = 0; drive < 2; drive++) { 2590 drvp = &chp->ch_drive[drive]; 2591 /* If no drive, skip */ 2592 if ((drvp->drive_flags & DRIVE) == 0) 2593 continue; 2594 /* add timing values, setup DMA if needed */ 2595 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2596 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2597 if (drvp->drive_flags & DRIVE_UDMA) { 2598 /* UltraDMA on a 646U2, 0648 or 0649 */ 2599 drvp->drive_flags &= ~DRIVE_DMA; 2600 udma_reg = pciide_pci_read(sc->sc_pc, 2601 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2602 if (drvp->UDMA_mode > 2 && 2603 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2604 CMD_BICSR) & 2605 CMD_BICSR_80(chp->channel)) == 0) 2606 drvp->UDMA_mode = 2; 2607 if (drvp->UDMA_mode > 2) 2608 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2609 else if (sc->sc_wdcdev.UDMA_cap > 2) 2610 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2611 udma_reg |= CMD_UDMATIM_UDMA(drive); 2612 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2613 CMD_UDMATIM_TIM_OFF(drive)); 2614 udma_reg |= 2615 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2616 CMD_UDMATIM_TIM_OFF(drive)); 2617 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2618 CMD_UDMATIM(chp->channel), udma_reg); 2619 } else { 2620 /* 2621 * use Multiword DMA. 2622 * Timings will be used for both PIO and DMA, 2623 * so adjust DMA mode if needed 2624 * if we have a 0646U2/8/9, turn off UDMA 2625 */ 2626 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2627 udma_reg = pciide_pci_read(sc->sc_pc, 2628 sc->sc_tag, 2629 CMD_UDMATIM(chp->channel)); 2630 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2631 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2632 CMD_UDMATIM(chp->channel), 2633 udma_reg); 2634 } 2635 if (drvp->PIO_mode >= 3 && 2636 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2637 drvp->DMA_mode = drvp->PIO_mode - 2; 2638 } 2639 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2640 } 2641 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2642 } 2643 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2644 CMD_DATA_TIM(chp->channel, drive), tim); 2645 } 2646 if (idedma_ctl != 0) { 2647 /* Add software bits in status register */ 2648 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2649 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2650 idedma_ctl); 2651 } 2652 pciide_print_modes(cp); 2653 } 2654 2655 void 2656 cmd646_9_irqack(chp) 2657 struct channel_softc *chp; 2658 { 2659 u_int32_t priirq, secirq; 2660 struct pciide_channel *cp = (struct pciide_channel*)chp; 2661 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2662 2663 if (chp->channel == 0) { 2664 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2665 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2666 } else { 2667 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2668 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2669 } 2670 pciide_irqack(chp); 2671 } 2672 2673 void 2674 cy693_chip_map(sc, pa) 2675 struct pciide_softc *sc; 2676 struct pci_attach_args *pa; 2677 { 2678 struct pciide_channel *cp; 2679 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2680 bus_size_t cmdsize, ctlsize; 2681 2682 if (pciide_chipen(sc, pa) == 0) 2683 return; 2684 /* 2685 * this chip has 2 PCI IDE functions, one for primary and one for 2686 * secondary. So we need to call pciide_mapregs_compat() with 2687 * the real channel 2688 */ 2689 if (pa->pa_function == 1) { 2690 sc->sc_cy_compatchan = 0; 2691 } else if (pa->pa_function == 2) { 2692 sc->sc_cy_compatchan = 1; 2693 } else { 2694 printf("%s: unexpected PCI function %d\n", 2695 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2696 return; 2697 } 2698 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2699 printf("%s: bus-master DMA support present", 2700 sc->sc_wdcdev.sc_dev.dv_xname); 2701 pciide_mapreg_dma(sc, pa); 2702 } else { 2703 printf("%s: hardware does not support DMA", 2704 sc->sc_wdcdev.sc_dev.dv_xname); 2705 sc->sc_dma_ok = 0; 2706 } 2707 printf("\n"); 2708 2709 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2710 if (sc->sc_cy_handle == NULL) { 2711 printf("%s: unable to map hyperCache control registers\n", 2712 sc->sc_wdcdev.sc_dev.dv_xname); 2713 sc->sc_dma_ok = 0; 2714 } 2715 2716 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2717 WDC_CAPABILITY_MODE; 2718 if (sc->sc_dma_ok) { 2719 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2720 sc->sc_wdcdev.irqack = pciide_irqack; 2721 } 2722 sc->sc_wdcdev.PIO_cap = 4; 2723 sc->sc_wdcdev.DMA_cap = 2; 2724 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2725 2726 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2727 sc->sc_wdcdev.nchannels = 1; 2728 2729 /* Only one channel for this chip; if we are here it's enabled */ 2730 cp = &sc->pciide_channels[0]; 2731 sc->wdc_chanarray[0] = &cp->wdc_channel; 2732 cp->name = PCIIDE_CHANNEL_NAME(0); 2733 cp->wdc_channel.channel = 0; 2734 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2735 cp->wdc_channel.ch_queue = 2736 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2737 if (cp->wdc_channel.ch_queue == NULL) { 2738 printf("%s primary channel: " 2739 "can't allocate memory for command queue", 2740 sc->sc_wdcdev.sc_dev.dv_xname); 2741 return; 2742 } 2743 printf("%s: primary channel %s to ", 2744 sc->sc_wdcdev.sc_dev.dv_xname, 2745 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2746 "configured" : "wired"); 2747 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2748 printf("native-PCI"); 2749 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2750 pciide_pci_intr); 2751 } else { 2752 printf("compatibility"); 2753 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2754 &cmdsize, &ctlsize); 2755 } 2756 printf(" mode\n"); 2757 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2758 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2759 wdcattach(&cp->wdc_channel); 2760 if (pciide_chan_candisable(cp)) { 2761 pci_conf_write(sc->sc_pc, sc->sc_tag, 2762 PCI_COMMAND_STATUS_REG, 0); 2763 } 2764 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2765 if (cp->hw_ok == 0) 2766 return; 2767 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2768 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2769 cy693_setup_channel(&cp->wdc_channel); 2770 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2771 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2772 } 2773 2774 void 2775 cy693_setup_channel(chp) 2776 struct channel_softc *chp; 2777 { 2778 struct ata_drive_datas *drvp; 2779 int drive; 2780 u_int32_t cy_cmd_ctrl; 2781 u_int32_t idedma_ctl; 2782 struct pciide_channel *cp = (struct pciide_channel*)chp; 2783 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2784 int dma_mode = -1; 2785 2786 cy_cmd_ctrl = idedma_ctl = 0; 2787 2788 /* setup DMA if needed */ 2789 pciide_channel_dma_setup(cp); 2790 2791 for (drive = 0; drive < 2; drive++) { 2792 drvp = &chp->ch_drive[drive]; 2793 /* If no drive, skip */ 2794 if ((drvp->drive_flags & DRIVE) == 0) 2795 continue; 2796 /* add timing values, setup DMA if needed */ 2797 if (drvp->drive_flags & DRIVE_DMA) { 2798 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2799 /* use Multiword DMA */ 2800 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2801 dma_mode = drvp->DMA_mode; 2802 } 2803 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2804 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2805 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2806 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2807 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2808 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2809 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2810 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2811 } 2812 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2813 chp->ch_drive[0].DMA_mode = dma_mode; 2814 chp->ch_drive[1].DMA_mode = dma_mode; 2815 2816 if (dma_mode == -1) 2817 dma_mode = 0; 2818 2819 if (sc->sc_cy_handle != NULL) { 2820 /* Note: `multiple' is implied. */ 2821 cy82c693_write(sc->sc_cy_handle, 2822 (sc->sc_cy_compatchan == 0) ? 2823 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2824 } 2825 2826 pciide_print_modes(cp); 2827 2828 if (idedma_ctl != 0) { 2829 /* Add software bits in status register */ 2830 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2831 IDEDMA_CTL, idedma_ctl); 2832 } 2833 } 2834 2835 static int 2836 sis_hostbr_match(pa) 2837 struct pci_attach_args *pa; 2838 { 2839 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2840 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2841 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2842 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2843 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2844 } 2845 2846 void 2847 sis_chip_map(sc, pa) 2848 struct pciide_softc *sc; 2849 struct pci_attach_args *pa; 2850 { 2851 struct pciide_channel *cp; 2852 int channel; 2853 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2854 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2855 pcireg_t rev = PCI_REVISION(pa->pa_class); 2856 bus_size_t cmdsize, ctlsize; 2857 pcitag_t pchb_tag; 2858 pcireg_t pchb_id, pchb_class; 2859 2860 if (pciide_chipen(sc, pa) == 0) 2861 return; 2862 printf("%s: bus-master DMA support present", 2863 sc->sc_wdcdev.sc_dev.dv_xname); 2864 pciide_mapreg_dma(sc, pa); 2865 printf("\n"); 2866 2867 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2868 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2869 /* and read ID and rev of the ISA bridge */ 2870 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2871 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2872 2873 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2874 WDC_CAPABILITY_MODE; 2875 if (sc->sc_dma_ok) { 2876 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2877 sc->sc_wdcdev.irqack = pciide_irqack; 2878 /* 2879 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2880 * have problems with UDMA (info provided by Christos) 2881 */ 2882 if (rev >= 0xd0 && 2883 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2884 PCI_REVISION(pchb_class) >= 0x03)) 2885 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2886 } 2887 2888 sc->sc_wdcdev.PIO_cap = 4; 2889 sc->sc_wdcdev.DMA_cap = 2; 2890 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2891 /* 2892 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2893 * chipsets. 2894 */ 2895 sc->sc_wdcdev.UDMA_cap = 2896 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2897 sc->sc_wdcdev.set_modes = sis_setup_channel; 2898 2899 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2900 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2901 2902 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2903 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2904 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2905 2906 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2907 cp = &sc->pciide_channels[channel]; 2908 if (pciide_chansetup(sc, channel, interface) == 0) 2909 continue; 2910 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2911 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2912 printf("%s: %s channel ignored (disabled)\n", 2913 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2914 continue; 2915 } 2916 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2917 pciide_pci_intr); 2918 if (cp->hw_ok == 0) 2919 continue; 2920 if (pciide_chan_candisable(cp)) { 2921 if (channel == 0) 2922 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2923 else 2924 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2925 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2926 sis_ctr0); 2927 } 2928 pciide_map_compat_intr(pa, cp, channel, interface); 2929 if (cp->hw_ok == 0) 2930 continue; 2931 sis_setup_channel(&cp->wdc_channel); 2932 } 2933 } 2934 2935 void 2936 sis_setup_channel(chp) 2937 struct channel_softc *chp; 2938 { 2939 struct ata_drive_datas *drvp; 2940 int drive; 2941 u_int32_t sis_tim; 2942 u_int32_t idedma_ctl; 2943 struct pciide_channel *cp = (struct pciide_channel*)chp; 2944 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2945 2946 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2947 "channel %d 0x%x\n", chp->channel, 2948 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2949 DEBUG_PROBE); 2950 sis_tim = 0; 2951 idedma_ctl = 0; 2952 /* setup DMA if needed */ 2953 pciide_channel_dma_setup(cp); 2954 2955 for (drive = 0; drive < 2; drive++) { 2956 drvp = &chp->ch_drive[drive]; 2957 /* If no drive, skip */ 2958 if ((drvp->drive_flags & DRIVE) == 0) 2959 continue; 2960 /* add timing values, setup DMA if needed */ 2961 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2962 (drvp->drive_flags & DRIVE_UDMA) == 0) 2963 goto pio; 2964 2965 if (drvp->drive_flags & DRIVE_UDMA) { 2966 /* use Ultra/DMA */ 2967 drvp->drive_flags &= ~DRIVE_DMA; 2968 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2969 SIS_TIM_UDMA_TIME_OFF(drive); 2970 sis_tim |= SIS_TIM_UDMA_EN(drive); 2971 } else { 2972 /* 2973 * use Multiword DMA 2974 * Timings will be used for both PIO and DMA, 2975 * so adjust DMA mode if needed 2976 */ 2977 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2978 drvp->PIO_mode = drvp->DMA_mode + 2; 2979 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2980 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2981 drvp->PIO_mode - 2 : 0; 2982 if (drvp->DMA_mode == 0) 2983 drvp->PIO_mode = 0; 2984 } 2985 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2986 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2987 SIS_TIM_ACT_OFF(drive); 2988 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2989 SIS_TIM_REC_OFF(drive); 2990 } 2991 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2992 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2993 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2994 if (idedma_ctl != 0) { 2995 /* Add software bits in status register */ 2996 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2997 IDEDMA_CTL, idedma_ctl); 2998 } 2999 pciide_print_modes(cp); 3000 } 3001 3002 static int 3003 acer_isabr_match(pa) 3004 struct pci_attach_args *pa; 3005 { 3006 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI) && 3007 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)); 3008 } 3009 3010 void 3011 acer_chip_map(sc, pa) 3012 struct pciide_softc *sc; 3013 struct pci_attach_args *pa; 3014 { 3015 struct pci_attach_args isa_pa; 3016 struct pciide_channel *cp; 3017 int channel; 3018 pcireg_t cr, interface; 3019 bus_size_t cmdsize, ctlsize; 3020 pcireg_t rev = PCI_REVISION(pa->pa_class); 3021 3022 if (pciide_chipen(sc, pa) == 0) 3023 return; 3024 printf("%s: bus-master DMA support present", 3025 sc->sc_wdcdev.sc_dev.dv_xname); 3026 pciide_mapreg_dma(sc, pa); 3027 printf("\n"); 3028 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3029 WDC_CAPABILITY_MODE; 3030 if (sc->sc_dma_ok) { 3031 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3032 if (rev >= 0x20) { 3033 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3034 if (rev >= 0xC4) 3035 sc->sc_wdcdev.UDMA_cap = 5; 3036 else if (rev >= 0xC2) 3037 sc->sc_wdcdev.UDMA_cap = 4; 3038 else 3039 sc->sc_wdcdev.UDMA_cap = 2; 3040 } 3041 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3042 sc->sc_wdcdev.irqack = pciide_irqack; 3043 } 3044 3045 sc->sc_wdcdev.PIO_cap = 4; 3046 sc->sc_wdcdev.DMA_cap = 2; 3047 sc->sc_wdcdev.set_modes = acer_setup_channel; 3048 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3049 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3050 3051 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3052 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3053 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3054 3055 /* Enable "microsoft register bits" R/W. */ 3056 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3057 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3058 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3059 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3060 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3061 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3062 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3063 ~ACER_CHANSTATUSREGS_RO); 3064 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3065 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3066 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3067 /* Don't use cr, re-read the real register content instead */ 3068 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3069 PCI_CLASS_REG)); 3070 3071 /* From linux: enable "Cable Detection" */ 3072 if (rev >= 0xC2) { 3073 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3074 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3075 | ACER_0x4B_CDETECT); 3076 /* set south-bridge's enable bit, m1533, 0x79 */ 3077 if (pci_find_device(&isa_pa, acer_isabr_match) == 0) { 3078 printf("%s: can't find PCI/ISA bridge, downgrading " 3079 "to Ultra/33\n", sc->sc_wdcdev.sc_dev.dv_xname); 3080 sc->sc_wdcdev.UDMA_cap = 2; 3081 } else { 3082 if (rev == 0xC2) 3083 /* 1543C-B0 (m1533, 0x79, bit 2) */ 3084 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3085 ACER_0x79, 3086 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3087 ACER_0x79) 3088 | ACER_0x79_REVC2_EN); 3089 else 3090 /* 1553/1535 (m1533, 0x79, bit 1) */ 3091 pciide_pci_write(isa_pa.pa_pc, isa_pa.pa_tag, 3092 ACER_0x79, 3093 pciide_pci_read(isa_pa.pa_pc, isa_pa.pa_tag, 3094 ACER_0x79) 3095 | ACER_0x79_EN); 3096 } 3097 } 3098 3099 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3100 cp = &sc->pciide_channels[channel]; 3101 if (pciide_chansetup(sc, channel, interface) == 0) 3102 continue; 3103 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3104 printf("%s: %s channel ignored (disabled)\n", 3105 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3106 continue; 3107 } 3108 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3109 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3110 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3111 if (cp->hw_ok == 0) 3112 continue; 3113 if (pciide_chan_candisable(cp)) { 3114 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3115 pci_conf_write(sc->sc_pc, sc->sc_tag, 3116 PCI_CLASS_REG, cr); 3117 } 3118 pciide_map_compat_intr(pa, cp, channel, interface); 3119 acer_setup_channel(&cp->wdc_channel); 3120 } 3121 } 3122 3123 void 3124 acer_setup_channel(chp) 3125 struct channel_softc *chp; 3126 { 3127 struct ata_drive_datas *drvp; 3128 int drive; 3129 u_int32_t acer_fifo_udma; 3130 u_int32_t idedma_ctl; 3131 struct pciide_channel *cp = (struct pciide_channel*)chp; 3132 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3133 3134 idedma_ctl = 0; 3135 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3136 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3137 acer_fifo_udma), DEBUG_PROBE); 3138 /* setup DMA if needed */ 3139 pciide_channel_dma_setup(cp); 3140 3141 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3142 DRIVE_UDMA) { /* check 80 pins cable */ 3143 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3144 ACER_0x4A_80PIN(chp->channel)) { 3145 if (chp->ch_drive[0].UDMA_mode > 2) 3146 chp->ch_drive[0].UDMA_mode = 2; 3147 if (chp->ch_drive[1].UDMA_mode > 2) 3148 chp->ch_drive[1].UDMA_mode = 2; 3149 } 3150 } 3151 3152 for (drive = 0; drive < 2; drive++) { 3153 drvp = &chp->ch_drive[drive]; 3154 /* If no drive, skip */ 3155 if ((drvp->drive_flags & DRIVE) == 0) 3156 continue; 3157 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3158 "channel %d drive %d 0x%x\n", chp->channel, drive, 3159 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3160 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3161 /* clear FIFO/DMA mode */ 3162 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3163 ACER_UDMA_EN(chp->channel, drive) | 3164 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3165 3166 /* add timing values, setup DMA if needed */ 3167 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3168 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3169 acer_fifo_udma |= 3170 ACER_FTH_OPL(chp->channel, drive, 0x1); 3171 goto pio; 3172 } 3173 3174 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3175 if (drvp->drive_flags & DRIVE_UDMA) { 3176 /* use Ultra/DMA */ 3177 drvp->drive_flags &= ~DRIVE_DMA; 3178 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3179 acer_fifo_udma |= 3180 ACER_UDMA_TIM(chp->channel, drive, 3181 acer_udma[drvp->UDMA_mode]); 3182 /* XXX disable if one drive < UDMA3 ? */ 3183 if (drvp->UDMA_mode >= 3) { 3184 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3185 ACER_0x4B, 3186 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3187 ACER_0x4B) | ACER_0x4B_UDMA66); 3188 } 3189 } else { 3190 /* 3191 * use Multiword DMA 3192 * Timings will be used for both PIO and DMA, 3193 * so adjust DMA mode if needed 3194 */ 3195 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3196 drvp->PIO_mode = drvp->DMA_mode + 2; 3197 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3198 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3199 drvp->PIO_mode - 2 : 0; 3200 if (drvp->DMA_mode == 0) 3201 drvp->PIO_mode = 0; 3202 } 3203 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3204 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3205 ACER_IDETIM(chp->channel, drive), 3206 acer_pio[drvp->PIO_mode]); 3207 } 3208 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3209 acer_fifo_udma), DEBUG_PROBE); 3210 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3211 if (idedma_ctl != 0) { 3212 /* Add software bits in status register */ 3213 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3214 IDEDMA_CTL, idedma_ctl); 3215 } 3216 pciide_print_modes(cp); 3217 } 3218 3219 int 3220 acer_pci_intr(arg) 3221 void *arg; 3222 { 3223 struct pciide_softc *sc = arg; 3224 struct pciide_channel *cp; 3225 struct channel_softc *wdc_cp; 3226 int i, rv, crv; 3227 u_int32_t chids; 3228 3229 rv = 0; 3230 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3231 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3232 cp = &sc->pciide_channels[i]; 3233 wdc_cp = &cp->wdc_channel; 3234 /* If a compat channel skip. */ 3235 if (cp->compat) 3236 continue; 3237 if (chids & ACER_CHIDS_INT(i)) { 3238 crv = wdcintr(wdc_cp); 3239 if (crv == 0) 3240 printf("%s:%d: bogus intr\n", 3241 sc->sc_wdcdev.sc_dev.dv_xname, i); 3242 else 3243 rv = 1; 3244 } 3245 } 3246 return rv; 3247 } 3248 3249 void 3250 hpt_chip_map(sc, pa) 3251 struct pciide_softc *sc; 3252 struct pci_attach_args *pa; 3253 { 3254 struct pciide_channel *cp; 3255 int i, compatchan, revision; 3256 pcireg_t interface; 3257 bus_size_t cmdsize, ctlsize; 3258 3259 if (pciide_chipen(sc, pa) == 0) 3260 return; 3261 revision = PCI_REVISION(pa->pa_class); 3262 printf(": Triones/Highpoint "); 3263 if (revision == HPT370_REV) 3264 printf("HPT370 IDE Controller\n"); 3265 else if (revision == HPT370A_REV) 3266 printf("HPT370A IDE Controller\n"); 3267 else if (revision == HPT366_REV) 3268 printf("HPT366 IDE Controller\n"); 3269 else 3270 printf("unknown HPT IDE controller rev %d\n", revision); 3271 3272 /* 3273 * when the chip is in native mode it identifies itself as a 3274 * 'misc mass storage'. Fake interface in this case. 3275 */ 3276 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3277 interface = PCI_INTERFACE(pa->pa_class); 3278 } else { 3279 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3280 PCIIDE_INTERFACE_PCI(0); 3281 if (revision == HPT370_REV || revision == HPT370A_REV) 3282 interface |= PCIIDE_INTERFACE_PCI(1); 3283 } 3284 3285 printf("%s: bus-master DMA support present", 3286 sc->sc_wdcdev.sc_dev.dv_xname); 3287 pciide_mapreg_dma(sc, pa); 3288 printf("\n"); 3289 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3290 WDC_CAPABILITY_MODE; 3291 if (sc->sc_dma_ok) { 3292 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3293 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3294 sc->sc_wdcdev.irqack = pciide_irqack; 3295 } 3296 sc->sc_wdcdev.PIO_cap = 4; 3297 sc->sc_wdcdev.DMA_cap = 2; 3298 3299 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3300 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3301 if (revision == HPT366_REV) { 3302 sc->sc_wdcdev.UDMA_cap = 4; 3303 /* 3304 * The 366 has 2 PCI IDE functions, one for primary and one 3305 * for secondary. So we need to call pciide_mapregs_compat() 3306 * with the real channel 3307 */ 3308 if (pa->pa_function == 0) { 3309 compatchan = 0; 3310 } else if (pa->pa_function == 1) { 3311 compatchan = 1; 3312 } else { 3313 printf("%s: unexpected PCI function %d\n", 3314 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3315 return; 3316 } 3317 sc->sc_wdcdev.nchannels = 1; 3318 } else { 3319 sc->sc_wdcdev.nchannels = 2; 3320 sc->sc_wdcdev.UDMA_cap = 5; 3321 } 3322 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3323 cp = &sc->pciide_channels[i]; 3324 if (sc->sc_wdcdev.nchannels > 1) { 3325 compatchan = i; 3326 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3327 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3328 printf("%s: %s channel ignored (disabled)\n", 3329 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3330 continue; 3331 } 3332 } 3333 if (pciide_chansetup(sc, i, interface) == 0) 3334 continue; 3335 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3336 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3337 &ctlsize, hpt_pci_intr); 3338 } else { 3339 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3340 &cmdsize, &ctlsize); 3341 } 3342 if (cp->hw_ok == 0) 3343 return; 3344 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3345 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3346 wdcattach(&cp->wdc_channel); 3347 hpt_setup_channel(&cp->wdc_channel); 3348 } 3349 if (revision == HPT370_REV || revision == HPT370A_REV) { 3350 /* 3351 * HPT370_REV has a bit to disable interrupts, make sure 3352 * to clear it 3353 */ 3354 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3355 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3356 ~HPT_CSEL_IRQDIS); 3357 } 3358 return; 3359 } 3360 3361 void 3362 hpt_setup_channel(chp) 3363 struct channel_softc *chp; 3364 { 3365 struct ata_drive_datas *drvp; 3366 int drive; 3367 int cable; 3368 u_int32_t before, after; 3369 u_int32_t idedma_ctl; 3370 struct pciide_channel *cp = (struct pciide_channel*)chp; 3371 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3372 3373 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3374 3375 /* setup DMA if needed */ 3376 pciide_channel_dma_setup(cp); 3377 3378 idedma_ctl = 0; 3379 3380 /* Per drive settings */ 3381 for (drive = 0; drive < 2; drive++) { 3382 drvp = &chp->ch_drive[drive]; 3383 /* If no drive, skip */ 3384 if ((drvp->drive_flags & DRIVE) == 0) 3385 continue; 3386 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3387 HPT_IDETIM(chp->channel, drive)); 3388 3389 /* add timing values, setup DMA if needed */ 3390 if (drvp->drive_flags & DRIVE_UDMA) { 3391 /* use Ultra/DMA */ 3392 drvp->drive_flags &= ~DRIVE_DMA; 3393 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3394 drvp->UDMA_mode > 2) 3395 drvp->UDMA_mode = 2; 3396 after = (sc->sc_wdcdev.nchannels == 2) ? 3397 hpt370_udma[drvp->UDMA_mode] : 3398 hpt366_udma[drvp->UDMA_mode]; 3399 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3400 } else if (drvp->drive_flags & DRIVE_DMA) { 3401 /* 3402 * use Multiword DMA. 3403 * Timings will be used for both PIO and DMA, so adjust 3404 * DMA mode if needed 3405 */ 3406 if (drvp->PIO_mode >= 3 && 3407 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3408 drvp->DMA_mode = drvp->PIO_mode - 2; 3409 } 3410 after = (sc->sc_wdcdev.nchannels == 2) ? 3411 hpt370_dma[drvp->DMA_mode] : 3412 hpt366_dma[drvp->DMA_mode]; 3413 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3414 } else { 3415 /* PIO only */ 3416 after = (sc->sc_wdcdev.nchannels == 2) ? 3417 hpt370_pio[drvp->PIO_mode] : 3418 hpt366_pio[drvp->PIO_mode]; 3419 } 3420 pci_conf_write(sc->sc_pc, sc->sc_tag, 3421 HPT_IDETIM(chp->channel, drive), after); 3422 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3423 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3424 after, before), DEBUG_PROBE); 3425 } 3426 if (idedma_ctl != 0) { 3427 /* Add software bits in status register */ 3428 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3429 IDEDMA_CTL, idedma_ctl); 3430 } 3431 pciide_print_modes(cp); 3432 } 3433 3434 int 3435 hpt_pci_intr(arg) 3436 void *arg; 3437 { 3438 struct pciide_softc *sc = arg; 3439 struct pciide_channel *cp; 3440 struct channel_softc *wdc_cp; 3441 int rv = 0; 3442 int dmastat, i, crv; 3443 3444 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3445 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3446 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3447 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3448 IDEDMA_CTL_INTR) 3449 continue; 3450 cp = &sc->pciide_channels[i]; 3451 wdc_cp = &cp->wdc_channel; 3452 crv = wdcintr(wdc_cp); 3453 if (crv == 0) { 3454 printf("%s:%d: bogus intr\n", 3455 sc->sc_wdcdev.sc_dev.dv_xname, i); 3456 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3457 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3458 } else 3459 rv = 1; 3460 } 3461 return rv; 3462 } 3463 3464 3465 /* Macros to test product */ 3466 #define PDC_IS_262(sc) \ 3467 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3468 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3469 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3470 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3471 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3472 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3473 #define PDC_IS_265(sc) \ 3474 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3475 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3476 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3477 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3478 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3479 #define PDC_IS_268(sc) \ 3480 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3481 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3482 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3483 3484 void 3485 pdc202xx_chip_map(sc, pa) 3486 struct pciide_softc *sc; 3487 struct pci_attach_args *pa; 3488 { 3489 struct pciide_channel *cp; 3490 int channel; 3491 pcireg_t interface, st, mode; 3492 bus_size_t cmdsize, ctlsize; 3493 3494 if (!PDC_IS_268(sc)) { 3495 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3496 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3497 st), DEBUG_PROBE); 3498 } 3499 if (pciide_chipen(sc, pa) == 0) 3500 return; 3501 3502 /* turn off RAID mode */ 3503 if (!PDC_IS_268(sc)) 3504 st &= ~PDC2xx_STATE_IDERAID; 3505 3506 /* 3507 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3508 * mode. We have to fake interface 3509 */ 3510 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3511 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3512 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3513 3514 printf("%s: bus-master DMA support present", 3515 sc->sc_wdcdev.sc_dev.dv_xname); 3516 pciide_mapreg_dma(sc, pa); 3517 printf("\n"); 3518 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3519 WDC_CAPABILITY_MODE; 3520 if (sc->sc_dma_ok) { 3521 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3522 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3523 sc->sc_wdcdev.irqack = pciide_irqack; 3524 } 3525 sc->sc_wdcdev.PIO_cap = 4; 3526 sc->sc_wdcdev.DMA_cap = 2; 3527 if (PDC_IS_265(sc)) 3528 sc->sc_wdcdev.UDMA_cap = 5; 3529 else if (PDC_IS_262(sc)) 3530 sc->sc_wdcdev.UDMA_cap = 4; 3531 else 3532 sc->sc_wdcdev.UDMA_cap = 2; 3533 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3534 pdc20268_setup_channel : pdc202xx_setup_channel; 3535 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3536 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3537 3538 if (!PDC_IS_268(sc)) { 3539 /* setup failsafe defaults */ 3540 mode = 0; 3541 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3542 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3543 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3544 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3545 for (channel = 0; 3546 channel < sc->sc_wdcdev.nchannels; 3547 channel++) { 3548 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3549 "drive 0 initial timings 0x%x, now 0x%x\n", 3550 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3551 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3552 DEBUG_PROBE); 3553 pci_conf_write(sc->sc_pc, sc->sc_tag, 3554 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3555 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3556 "drive 1 initial timings 0x%x, now 0x%x\n", 3557 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3558 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3559 pci_conf_write(sc->sc_pc, sc->sc_tag, 3560 PDC2xx_TIM(channel, 1), mode); 3561 } 3562 3563 mode = PDC2xx_SCR_DMA; 3564 if (PDC_IS_262(sc)) { 3565 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3566 } else { 3567 /* the BIOS set it up this way */ 3568 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3569 } 3570 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3571 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3572 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3573 "now 0x%x\n", 3574 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3575 PDC2xx_SCR), 3576 mode), DEBUG_PROBE); 3577 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3578 PDC2xx_SCR, mode); 3579 3580 /* controller initial state register is OK even without BIOS */ 3581 /* Set DMA mode to IDE DMA compatibility */ 3582 mode = 3583 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3584 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3585 DEBUG_PROBE); 3586 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3587 mode | 0x1); 3588 mode = 3589 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3590 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3591 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3592 mode | 0x1); 3593 } 3594 3595 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3596 cp = &sc->pciide_channels[channel]; 3597 if (pciide_chansetup(sc, channel, interface) == 0) 3598 continue; 3599 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3600 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3601 printf("%s: %s channel ignored (disabled)\n", 3602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3603 continue; 3604 } 3605 if (PDC_IS_265(sc)) 3606 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3607 pdc20265_pci_intr); 3608 else 3609 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3610 pdc202xx_pci_intr); 3611 if (cp->hw_ok == 0) 3612 continue; 3613 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3614 st &= ~(PDC_IS_262(sc) ? 3615 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3616 pciide_map_compat_intr(pa, cp, channel, interface); 3617 pdc202xx_setup_channel(&cp->wdc_channel); 3618 } 3619 if (!PDC_IS_268(sc)) { 3620 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3621 "0x%x\n", st), DEBUG_PROBE); 3622 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3623 } 3624 return; 3625 } 3626 3627 void 3628 pdc202xx_setup_channel(chp) 3629 struct channel_softc *chp; 3630 { 3631 struct ata_drive_datas *drvp; 3632 int drive; 3633 pcireg_t mode, st; 3634 u_int32_t idedma_ctl, scr, atapi; 3635 struct pciide_channel *cp = (struct pciide_channel*)chp; 3636 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3637 int channel = chp->channel; 3638 3639 /* setup DMA if needed */ 3640 pciide_channel_dma_setup(cp); 3641 3642 idedma_ctl = 0; 3643 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3644 sc->sc_wdcdev.sc_dev.dv_xname, 3645 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3646 DEBUG_PROBE); 3647 3648 /* Per channel settings */ 3649 if (PDC_IS_262(sc)) { 3650 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3651 PDC262_U66); 3652 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3653 /* Trim UDMA mode */ 3654 if ((st & PDC262_STATE_80P(channel)) != 0 || 3655 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3656 chp->ch_drive[0].UDMA_mode <= 2) || 3657 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3658 chp->ch_drive[1].UDMA_mode <= 2)) { 3659 if (chp->ch_drive[0].UDMA_mode > 2) 3660 chp->ch_drive[0].UDMA_mode = 2; 3661 if (chp->ch_drive[1].UDMA_mode > 2) 3662 chp->ch_drive[1].UDMA_mode = 2; 3663 } 3664 /* Set U66 if needed */ 3665 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3666 chp->ch_drive[0].UDMA_mode > 2) || 3667 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3668 chp->ch_drive[1].UDMA_mode > 2)) 3669 scr |= PDC262_U66_EN(channel); 3670 else 3671 scr &= ~PDC262_U66_EN(channel); 3672 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3673 PDC262_U66, scr); 3674 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3675 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3676 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3677 PDC262_ATAPI(channel))), DEBUG_PROBE); 3678 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3679 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3680 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3681 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3682 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3683 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3684 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3685 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3686 atapi = 0; 3687 else 3688 atapi = PDC262_ATAPI_UDMA; 3689 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3690 PDC262_ATAPI(channel), atapi); 3691 } 3692 } 3693 for (drive = 0; drive < 2; drive++) { 3694 drvp = &chp->ch_drive[drive]; 3695 /* If no drive, skip */ 3696 if ((drvp->drive_flags & DRIVE) == 0) 3697 continue; 3698 mode = 0; 3699 if (drvp->drive_flags & DRIVE_UDMA) { 3700 /* use Ultra/DMA */ 3701 drvp->drive_flags &= ~DRIVE_DMA; 3702 mode = PDC2xx_TIM_SET_MB(mode, 3703 pdc2xx_udma_mb[drvp->UDMA_mode]); 3704 mode = PDC2xx_TIM_SET_MC(mode, 3705 pdc2xx_udma_mc[drvp->UDMA_mode]); 3706 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3707 } else if (drvp->drive_flags & DRIVE_DMA) { 3708 mode = PDC2xx_TIM_SET_MB(mode, 3709 pdc2xx_dma_mb[drvp->DMA_mode]); 3710 mode = PDC2xx_TIM_SET_MC(mode, 3711 pdc2xx_dma_mc[drvp->DMA_mode]); 3712 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3713 } else { 3714 mode = PDC2xx_TIM_SET_MB(mode, 3715 pdc2xx_dma_mb[0]); 3716 mode = PDC2xx_TIM_SET_MC(mode, 3717 pdc2xx_dma_mc[0]); 3718 } 3719 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3720 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3721 if (drvp->drive_flags & DRIVE_ATA) 3722 mode |= PDC2xx_TIM_PRE; 3723 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3724 if (drvp->PIO_mode >= 3) { 3725 mode |= PDC2xx_TIM_IORDY; 3726 if (drive == 0) 3727 mode |= PDC2xx_TIM_IORDYp; 3728 } 3729 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3730 "timings 0x%x\n", 3731 sc->sc_wdcdev.sc_dev.dv_xname, 3732 chp->channel, drive, mode), DEBUG_PROBE); 3733 pci_conf_write(sc->sc_pc, sc->sc_tag, 3734 PDC2xx_TIM(chp->channel, drive), mode); 3735 } 3736 if (idedma_ctl != 0) { 3737 /* Add software bits in status register */ 3738 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3739 IDEDMA_CTL, idedma_ctl); 3740 } 3741 pciide_print_modes(cp); 3742 } 3743 3744 void 3745 pdc20268_setup_channel(chp) 3746 struct channel_softc *chp; 3747 { 3748 struct ata_drive_datas *drvp; 3749 int drive; 3750 u_int32_t idedma_ctl; 3751 struct pciide_channel *cp = (struct pciide_channel*)chp; 3752 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3753 int u100; 3754 3755 /* setup DMA if needed */ 3756 pciide_channel_dma_setup(cp); 3757 3758 idedma_ctl = 0; 3759 3760 /* I don't know what this is for, FreeBSD does it ... */ 3761 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3762 IDEDMA_CMD + 0x1, 0x0b); 3763 3764 /* 3765 * I don't know what this is for; FreeBSD checks this ... this is not 3766 * cable type detect. 3767 */ 3768 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3769 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3770 3771 for (drive = 0; drive < 2; drive++) { 3772 drvp = &chp->ch_drive[drive]; 3773 /* If no drive, skip */ 3774 if ((drvp->drive_flags & DRIVE) == 0) 3775 continue; 3776 if (drvp->drive_flags & DRIVE_UDMA) { 3777 /* use Ultra/DMA */ 3778 drvp->drive_flags &= ~DRIVE_DMA; 3779 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3780 if (drvp->UDMA_mode > 2 && u100 == 0) 3781 drvp->UDMA_mode = 2; 3782 } else if (drvp->drive_flags & DRIVE_DMA) { 3783 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3784 } 3785 } 3786 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3787 if (idedma_ctl != 0) { 3788 /* Add software bits in status register */ 3789 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3790 IDEDMA_CTL, idedma_ctl); 3791 } 3792 pciide_print_modes(cp); 3793 } 3794 3795 int 3796 pdc202xx_pci_intr(arg) 3797 void *arg; 3798 { 3799 struct pciide_softc *sc = arg; 3800 struct pciide_channel *cp; 3801 struct channel_softc *wdc_cp; 3802 int i, rv, crv; 3803 u_int32_t scr; 3804 3805 rv = 0; 3806 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3807 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3808 cp = &sc->pciide_channels[i]; 3809 wdc_cp = &cp->wdc_channel; 3810 /* If a compat channel skip. */ 3811 if (cp->compat) 3812 continue; 3813 if (scr & PDC2xx_SCR_INT(i)) { 3814 crv = wdcintr(wdc_cp); 3815 if (crv == 0) 3816 printf("%s:%d: bogus intr (reg 0x%x)\n", 3817 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3818 else 3819 rv = 1; 3820 } 3821 } 3822 return rv; 3823 } 3824 3825 int 3826 pdc20265_pci_intr(arg) 3827 void *arg; 3828 { 3829 struct pciide_softc *sc = arg; 3830 struct pciide_channel *cp; 3831 struct channel_softc *wdc_cp; 3832 int i, rv, crv; 3833 u_int32_t dmastat; 3834 3835 rv = 0; 3836 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3837 cp = &sc->pciide_channels[i]; 3838 wdc_cp = &cp->wdc_channel; 3839 /* If a compat channel skip. */ 3840 if (cp->compat) 3841 continue; 3842 /* 3843 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3844 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3845 * So use it instead (requires 2 reg reads instead of 1, 3846 * but we can't do it another way). 3847 */ 3848 dmastat = bus_space_read_1(sc->sc_dma_iot, 3849 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3850 if((dmastat & IDEDMA_CTL_INTR) == 0) 3851 continue; 3852 crv = wdcintr(wdc_cp); 3853 if (crv == 0) 3854 printf("%s:%d: bogus intr\n", 3855 sc->sc_wdcdev.sc_dev.dv_xname, i); 3856 else 3857 rv = 1; 3858 } 3859 return rv; 3860 } 3861 3862 void 3863 opti_chip_map(sc, pa) 3864 struct pciide_softc *sc; 3865 struct pci_attach_args *pa; 3866 { 3867 struct pciide_channel *cp; 3868 bus_size_t cmdsize, ctlsize; 3869 pcireg_t interface; 3870 u_int8_t init_ctrl; 3871 int channel; 3872 3873 if (pciide_chipen(sc, pa) == 0) 3874 return; 3875 printf("%s: bus-master DMA support present", 3876 sc->sc_wdcdev.sc_dev.dv_xname); 3877 3878 /* 3879 * XXXSCW: 3880 * There seem to be a couple of buggy revisions/implementations 3881 * of the OPTi pciide chipset. This kludge seems to fix one of 3882 * the reported problems (PR/11644) but still fails for the 3883 * other (PR/13151), although the latter may be due to other 3884 * issues too... 3885 */ 3886 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3887 printf(" but disabled due to chip rev. <= 0x12"); 3888 sc->sc_dma_ok = 0; 3889 sc->sc_wdcdev.cap = 0; 3890 } else { 3891 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3892 pciide_mapreg_dma(sc, pa); 3893 } 3894 printf("\n"); 3895 3896 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3897 sc->sc_wdcdev.PIO_cap = 4; 3898 if (sc->sc_dma_ok) { 3899 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3900 sc->sc_wdcdev.irqack = pciide_irqack; 3901 sc->sc_wdcdev.DMA_cap = 2; 3902 } 3903 sc->sc_wdcdev.set_modes = opti_setup_channel; 3904 3905 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3906 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3907 3908 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3909 OPTI_REG_INIT_CONTROL); 3910 3911 interface = PCI_INTERFACE(pa->pa_class); 3912 3913 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3914 cp = &sc->pciide_channels[channel]; 3915 if (pciide_chansetup(sc, channel, interface) == 0) 3916 continue; 3917 if (channel == 1 && 3918 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3919 printf("%s: %s channel ignored (disabled)\n", 3920 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3921 continue; 3922 } 3923 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3924 pciide_pci_intr); 3925 if (cp->hw_ok == 0) 3926 continue; 3927 pciide_map_compat_intr(pa, cp, channel, interface); 3928 if (cp->hw_ok == 0) 3929 continue; 3930 opti_setup_channel(&cp->wdc_channel); 3931 } 3932 } 3933 3934 void 3935 opti_setup_channel(chp) 3936 struct channel_softc *chp; 3937 { 3938 struct ata_drive_datas *drvp; 3939 struct pciide_channel *cp = (struct pciide_channel*)chp; 3940 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3941 int drive, spd; 3942 int mode[2]; 3943 u_int8_t rv, mr; 3944 3945 /* 3946 * The `Delay' and `Address Setup Time' fields of the 3947 * Miscellaneous Register are always zero initially. 3948 */ 3949 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3950 mr &= ~(OPTI_MISC_DELAY_MASK | 3951 OPTI_MISC_ADDR_SETUP_MASK | 3952 OPTI_MISC_INDEX_MASK); 3953 3954 /* Prime the control register before setting timing values */ 3955 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3956 3957 /* Determine the clockrate of the PCIbus the chip is attached to */ 3958 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3959 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3960 3961 /* setup DMA if needed */ 3962 pciide_channel_dma_setup(cp); 3963 3964 for (drive = 0; drive < 2; drive++) { 3965 drvp = &chp->ch_drive[drive]; 3966 /* If no drive, skip */ 3967 if ((drvp->drive_flags & DRIVE) == 0) { 3968 mode[drive] = -1; 3969 continue; 3970 } 3971 3972 if ((drvp->drive_flags & DRIVE_DMA)) { 3973 /* 3974 * Timings will be used for both PIO and DMA, 3975 * so adjust DMA mode if needed 3976 */ 3977 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3978 drvp->PIO_mode = drvp->DMA_mode + 2; 3979 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3980 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3981 drvp->PIO_mode - 2 : 0; 3982 if (drvp->DMA_mode == 0) 3983 drvp->PIO_mode = 0; 3984 3985 mode[drive] = drvp->DMA_mode + 5; 3986 } else 3987 mode[drive] = drvp->PIO_mode; 3988 3989 if (drive && mode[0] >= 0 && 3990 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3991 /* 3992 * Can't have two drives using different values 3993 * for `Address Setup Time'. 3994 * Slow down the faster drive to compensate. 3995 */ 3996 int d = (opti_tim_as[spd][mode[0]] > 3997 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3998 3999 mode[d] = mode[1-d]; 4000 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4001 chp->ch_drive[d].DMA_mode = 0; 4002 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 4003 } 4004 } 4005 4006 for (drive = 0; drive < 2; drive++) { 4007 int m; 4008 if ((m = mode[drive]) < 0) 4009 continue; 4010 4011 /* Set the Address Setup Time and select appropriate index */ 4012 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4013 rv |= OPTI_MISC_INDEX(drive); 4014 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4015 4016 /* Set the pulse width and recovery timing parameters */ 4017 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4018 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4019 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4020 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4021 4022 /* Set the Enhanced Mode register appropriately */ 4023 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4024 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4025 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4026 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4027 } 4028 4029 /* Finally, enable the timings */ 4030 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4031 4032 pciide_print_modes(cp); 4033 } 4034 4035 #define ACARD_IS_850(sc) \ 4036 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4037 4038 void 4039 acard_chip_map(sc, pa) 4040 struct pciide_softc *sc; 4041 struct pci_attach_args *pa; 4042 { 4043 struct pciide_channel *cp; 4044 int i; 4045 pcireg_t interface; 4046 bus_size_t cmdsize, ctlsize; 4047 4048 if (pciide_chipen(sc, pa) == 0) 4049 return; 4050 4051 /* 4052 * when the chip is in native mode it identifies itself as a 4053 * 'misc mass storage'. Fake interface in this case. 4054 */ 4055 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4056 interface = PCI_INTERFACE(pa->pa_class); 4057 } else { 4058 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4059 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4060 } 4061 4062 printf("%s: bus-master DMA support present", 4063 sc->sc_wdcdev.sc_dev.dv_xname); 4064 pciide_mapreg_dma(sc, pa); 4065 printf("\n"); 4066 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4067 WDC_CAPABILITY_MODE; 4068 4069 if (sc->sc_dma_ok) { 4070 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4071 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4072 sc->sc_wdcdev.irqack = pciide_irqack; 4073 } 4074 sc->sc_wdcdev.PIO_cap = 4; 4075 sc->sc_wdcdev.DMA_cap = 2; 4076 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4077 4078 sc->sc_wdcdev.set_modes = acard_setup_channel; 4079 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4080 sc->sc_wdcdev.nchannels = 2; 4081 4082 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4083 cp = &sc->pciide_channels[i]; 4084 if (pciide_chansetup(sc, i, interface) == 0) 4085 continue; 4086 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4087 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4088 &ctlsize, pciide_pci_intr); 4089 } else { 4090 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4091 &cmdsize, &ctlsize); 4092 } 4093 if (cp->hw_ok == 0) 4094 return; 4095 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4096 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4097 wdcattach(&cp->wdc_channel); 4098 acard_setup_channel(&cp->wdc_channel); 4099 } 4100 if (!ACARD_IS_850(sc)) { 4101 u_int32_t reg; 4102 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4103 reg &= ~ATP860_CTRL_INT; 4104 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4105 } 4106 } 4107 4108 void 4109 acard_setup_channel(chp) 4110 struct channel_softc *chp; 4111 { 4112 struct ata_drive_datas *drvp; 4113 struct pciide_channel *cp = (struct pciide_channel*)chp; 4114 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4115 int channel = chp->channel; 4116 int drive; 4117 u_int32_t idetime, udma_mode; 4118 u_int32_t idedma_ctl; 4119 4120 /* setup DMA if needed */ 4121 pciide_channel_dma_setup(cp); 4122 4123 if (ACARD_IS_850(sc)) { 4124 idetime = 0; 4125 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4126 udma_mode &= ~ATP850_UDMA_MASK(channel); 4127 } else { 4128 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4129 idetime &= ~ATP860_SETTIME_MASK(channel); 4130 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4131 udma_mode &= ~ATP860_UDMA_MASK(channel); 4132 4133 /* check 80 pins cable */ 4134 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4135 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4136 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4137 & ATP860_CTRL_80P(chp->channel)) { 4138 if (chp->ch_drive[0].UDMA_mode > 2) 4139 chp->ch_drive[0].UDMA_mode = 2; 4140 if (chp->ch_drive[1].UDMA_mode > 2) 4141 chp->ch_drive[1].UDMA_mode = 2; 4142 } 4143 } 4144 } 4145 4146 idedma_ctl = 0; 4147 4148 /* Per drive settings */ 4149 for (drive = 0; drive < 2; drive++) { 4150 drvp = &chp->ch_drive[drive]; 4151 /* If no drive, skip */ 4152 if ((drvp->drive_flags & DRIVE) == 0) 4153 continue; 4154 /* add timing values, setup DMA if needed */ 4155 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4156 (drvp->drive_flags & DRIVE_UDMA)) { 4157 /* use Ultra/DMA */ 4158 if (ACARD_IS_850(sc)) { 4159 idetime |= ATP850_SETTIME(drive, 4160 acard_act_udma[drvp->UDMA_mode], 4161 acard_rec_udma[drvp->UDMA_mode]); 4162 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4163 acard_udma_conf[drvp->UDMA_mode]); 4164 } else { 4165 idetime |= ATP860_SETTIME(channel, drive, 4166 acard_act_udma[drvp->UDMA_mode], 4167 acard_rec_udma[drvp->UDMA_mode]); 4168 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4169 acard_udma_conf[drvp->UDMA_mode]); 4170 } 4171 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4172 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4173 (drvp->drive_flags & DRIVE_DMA)) { 4174 /* use Multiword DMA */ 4175 drvp->drive_flags &= ~DRIVE_UDMA; 4176 if (ACARD_IS_850(sc)) { 4177 idetime |= ATP850_SETTIME(drive, 4178 acard_act_dma[drvp->DMA_mode], 4179 acard_rec_dma[drvp->DMA_mode]); 4180 } else { 4181 idetime |= ATP860_SETTIME(channel, drive, 4182 acard_act_dma[drvp->DMA_mode], 4183 acard_rec_dma[drvp->DMA_mode]); 4184 } 4185 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4186 } else { 4187 /* PIO only */ 4188 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4189 if (ACARD_IS_850(sc)) { 4190 idetime |= ATP850_SETTIME(drive, 4191 acard_act_pio[drvp->PIO_mode], 4192 acard_rec_pio[drvp->PIO_mode]); 4193 } else { 4194 idetime |= ATP860_SETTIME(channel, drive, 4195 acard_act_pio[drvp->PIO_mode], 4196 acard_rec_pio[drvp->PIO_mode]); 4197 } 4198 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4199 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4200 | ATP8x0_CTRL_EN(channel)); 4201 } 4202 } 4203 4204 if (idedma_ctl != 0) { 4205 /* Add software bits in status register */ 4206 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4207 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4208 } 4209 pciide_print_modes(cp); 4210 4211 if (ACARD_IS_850(sc)) { 4212 pci_conf_write(sc->sc_pc, sc->sc_tag, 4213 ATP850_IDETIME(channel), idetime); 4214 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4215 } else { 4216 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4217 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4218 } 4219 } 4220 4221 int 4222 acard_pci_intr(arg) 4223 void *arg; 4224 { 4225 struct pciide_softc *sc = arg; 4226 struct pciide_channel *cp; 4227 struct channel_softc *wdc_cp; 4228 int rv = 0; 4229 int dmastat, i, crv; 4230 4231 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4232 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4233 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4234 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4235 continue; 4236 cp = &sc->pciide_channels[i]; 4237 wdc_cp = &cp->wdc_channel; 4238 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4239 (void)wdcintr(wdc_cp); 4240 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4241 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4242 continue; 4243 } 4244 crv = wdcintr(wdc_cp); 4245 if (crv == 0) 4246 printf("%s:%d: bogus intr\n", 4247 sc->sc_wdcdev.sc_dev.dv_xname, i); 4248 else if (crv == 1) 4249 rv = 1; 4250 else if (rv == 0) 4251 rv = crv; 4252 } 4253 return rv; 4254 } 4255 4256 static int 4257 sl82c105_bugchk(struct pci_attach_args *pa) 4258 { 4259 4260 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4261 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4262 return (0); 4263 4264 if (PCI_REVISION(pa->pa_class) <= 0x05) 4265 return (1); 4266 4267 return (0); 4268 } 4269 4270 void 4271 sl82c105_chip_map(sc, pa) 4272 struct pciide_softc *sc; 4273 struct pci_attach_args *pa; 4274 { 4275 struct pciide_channel *cp; 4276 bus_size_t cmdsize, ctlsize; 4277 pcireg_t interface, idecr; 4278 int channel; 4279 4280 if (pciide_chipen(sc, pa) == 0) 4281 return; 4282 4283 printf("%s: bus-master DMA support present", 4284 sc->sc_wdcdev.sc_dev.dv_xname); 4285 4286 /* 4287 * Check to see if we're part of the Winbond 83c553 Southbridge. 4288 * If so, we need to disable DMA on rev. <= 5 of that chip. 4289 */ 4290 if (pci_find_device(pa, sl82c105_bugchk)) { 4291 printf(" but disabled due to 83c553 rev. <= 0x05"); 4292 sc->sc_dma_ok = 0; 4293 } else 4294 pciide_mapreg_dma(sc, pa); 4295 printf("\n"); 4296 4297 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4298 WDC_CAPABILITY_MODE; 4299 sc->sc_wdcdev.PIO_cap = 4; 4300 if (sc->sc_dma_ok) { 4301 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4302 sc->sc_wdcdev.irqack = pciide_irqack; 4303 sc->sc_wdcdev.DMA_cap = 2; 4304 } 4305 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4306 4307 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4308 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4309 4310 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4311 4312 interface = PCI_INTERFACE(pa->pa_class); 4313 4314 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4315 cp = &sc->pciide_channels[channel]; 4316 if (pciide_chansetup(sc, channel, interface) == 0) 4317 continue; 4318 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4319 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4320 printf("%s: %s channel ignored (disabled)\n", 4321 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4322 continue; 4323 } 4324 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4325 pciide_pci_intr); 4326 if (cp->hw_ok == 0) 4327 continue; 4328 pciide_map_compat_intr(pa, cp, channel, interface); 4329 if (cp->hw_ok == 0) 4330 continue; 4331 sl82c105_setup_channel(&cp->wdc_channel); 4332 } 4333 } 4334 4335 void 4336 sl82c105_setup_channel(chp) 4337 struct channel_softc *chp; 4338 { 4339 struct ata_drive_datas *drvp; 4340 struct pciide_channel *cp = (struct pciide_channel*)chp; 4341 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4342 int pxdx_reg, drive; 4343 pcireg_t pxdx; 4344 4345 /* Set up DMA if needed. */ 4346 pciide_channel_dma_setup(cp); 4347 4348 for (drive = 0; drive < 2; drive++) { 4349 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4350 : SYMPH_P1D0CR) + (drive * 4); 4351 4352 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4353 4354 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4355 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4356 4357 drvp = &chp->ch_drive[drive]; 4358 /* If no drive, skip. */ 4359 if ((drvp->drive_flags & DRIVE) == 0) { 4360 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4361 continue; 4362 } 4363 4364 if (drvp->drive_flags & DRIVE_DMA) { 4365 /* 4366 * Timings will be used for both PIO and DMA, 4367 * so adjust DMA mode if needed. 4368 */ 4369 if (drvp->PIO_mode >= 3) { 4370 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4371 drvp->DMA_mode = drvp->PIO_mode - 2; 4372 if (drvp->DMA_mode < 1) { 4373 /* 4374 * Can't mix both PIO and DMA. 4375 * Disable DMA. 4376 */ 4377 drvp->drive_flags &= ~DRIVE_DMA; 4378 } 4379 } else { 4380 /* 4381 * Can't mix both PIO and DMA. Disable 4382 * DMA. 4383 */ 4384 drvp->drive_flags &= ~DRIVE_DMA; 4385 } 4386 } 4387 4388 if (drvp->drive_flags & DRIVE_DMA) { 4389 /* Use multi-word DMA. */ 4390 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4391 PxDx_CMD_ON_SHIFT; 4392 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4393 } else { 4394 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4395 PxDx_CMD_ON_SHIFT; 4396 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4397 } 4398 4399 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4400 4401 /* ...and set the mode for this drive. */ 4402 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4403 } 4404 4405 pciide_print_modes(cp); 4406 } 4407 4408 void 4409 serverworks_chip_map(sc, pa) 4410 struct pciide_softc *sc; 4411 struct pci_attach_args *pa; 4412 { 4413 struct pciide_channel *cp; 4414 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4415 pcitag_t pcib_tag; 4416 int channel; 4417 bus_size_t cmdsize, ctlsize; 4418 4419 if (pciide_chipen(sc, pa) == 0) 4420 return; 4421 4422 printf("%s: bus-master DMA support present", 4423 sc->sc_wdcdev.sc_dev.dv_xname); 4424 pciide_mapreg_dma(sc, pa); 4425 printf("\n"); 4426 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4427 WDC_CAPABILITY_MODE; 4428 4429 if (sc->sc_dma_ok) { 4430 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4431 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4432 sc->sc_wdcdev.irqack = pciide_irqack; 4433 } 4434 sc->sc_wdcdev.PIO_cap = 4; 4435 sc->sc_wdcdev.DMA_cap = 2; 4436 switch (sc->sc_pp->ide_product) { 4437 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4438 sc->sc_wdcdev.UDMA_cap = 2; 4439 break; 4440 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4441 if (PCI_REVISION(pa->pa_class) < 0x92) 4442 sc->sc_wdcdev.UDMA_cap = 4; 4443 else 4444 sc->sc_wdcdev.UDMA_cap = 5; 4445 break; 4446 } 4447 4448 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4449 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4450 sc->sc_wdcdev.nchannels = 2; 4451 4452 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4453 cp = &sc->pciide_channels[channel]; 4454 if (pciide_chansetup(sc, channel, interface) == 0) 4455 continue; 4456 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4457 serverworks_pci_intr); 4458 if (cp->hw_ok == 0) 4459 return; 4460 pciide_map_compat_intr(pa, cp, channel, interface); 4461 if (cp->hw_ok == 0) 4462 return; 4463 serverworks_setup_channel(&cp->wdc_channel); 4464 } 4465 4466 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4467 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4468 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4469 } 4470 4471 void 4472 serverworks_setup_channel(chp) 4473 struct channel_softc *chp; 4474 { 4475 struct ata_drive_datas *drvp; 4476 struct pciide_channel *cp = (struct pciide_channel*)chp; 4477 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4478 int channel = chp->channel; 4479 int drive, unit; 4480 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4481 u_int32_t idedma_ctl; 4482 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4483 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4484 4485 /* setup DMA if needed */ 4486 pciide_channel_dma_setup(cp); 4487 4488 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4489 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4490 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4491 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4492 4493 pio_time &= ~(0xffff << (16 * channel)); 4494 dma_time &= ~(0xffff << (16 * channel)); 4495 pio_mode &= ~(0xff << (8 * channel + 16)); 4496 udma_mode &= ~(0xff << (8 * channel + 16)); 4497 udma_mode &= ~(3 << (2 * channel)); 4498 4499 idedma_ctl = 0; 4500 4501 /* Per drive settings */ 4502 for (drive = 0; drive < 2; drive++) { 4503 drvp = &chp->ch_drive[drive]; 4504 /* If no drive, skip */ 4505 if ((drvp->drive_flags & DRIVE) == 0) 4506 continue; 4507 unit = drive + 2 * channel; 4508 /* add timing values, setup DMA if needed */ 4509 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4510 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4511 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4512 (drvp->drive_flags & DRIVE_UDMA)) { 4513 /* use Ultra/DMA, check for 80-pin cable */ 4514 if (drvp->UDMA_mode > 2 && 4515 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4516 drvp->UDMA_mode = 2; 4517 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4518 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4519 udma_mode |= 1 << unit; 4520 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4521 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4522 (drvp->drive_flags & DRIVE_DMA)) { 4523 /* use Multiword DMA */ 4524 drvp->drive_flags &= ~DRIVE_UDMA; 4525 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4526 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4527 } else { 4528 /* PIO only */ 4529 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4530 } 4531 } 4532 4533 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4534 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4535 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4536 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4537 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4538 4539 if (idedma_ctl != 0) { 4540 /* Add software bits in status register */ 4541 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4542 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4543 } 4544 pciide_print_modes(cp); 4545 } 4546 4547 int 4548 serverworks_pci_intr(arg) 4549 void *arg; 4550 { 4551 struct pciide_softc *sc = arg; 4552 struct pciide_channel *cp; 4553 struct channel_softc *wdc_cp; 4554 int rv = 0; 4555 int dmastat, i, crv; 4556 4557 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4558 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4559 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4560 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4561 IDEDMA_CTL_INTR) 4562 continue; 4563 cp = &sc->pciide_channels[i]; 4564 wdc_cp = &cp->wdc_channel; 4565 crv = wdcintr(wdc_cp); 4566 if (crv == 0) { 4567 printf("%s:%d: bogus intr\n", 4568 sc->sc_wdcdev.sc_dev.dv_xname, i); 4569 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4570 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4571 } else 4572 rv = 1; 4573 } 4574 return rv; 4575 } 4576
Indexes created Mon Sep 22 13:09:51 GMT 2025