pciide.c revision 1.153.2.12
1 /* $NetBSD: pciide.c,v 1.153.2.12 2003/06/16 21:13:25 grant Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.153.2.12 2003/06/16 21:13:25 grant Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 void sis96x_setup_channel __P((struct channel_softc*)); 187 static int sis_hostbr_match __P(( struct pci_attach_args *)); 188 static int sis_south_match __P(( struct pci_attach_args *)); 189 190 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void acer_setup_channel __P((struct channel_softc*)); 192 int acer_pci_intr __P((void *)); 193 194 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void pdc202xx_setup_channel __P((struct channel_softc*)); 196 void pdc20268_setup_channel __P((struct channel_softc*)); 197 int pdc202xx_pci_intr __P((void *)); 198 int pdc20265_pci_intr __P((void *)); 199 static void pdc20262_dma_start __P((void*, int, int)); 200 static int pdc20262_dma_finish __P((void*, int, int, int)); 201 202 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void opti_setup_channel __P((struct channel_softc*)); 204 205 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void hpt_setup_channel __P((struct channel_softc*)); 207 int hpt_pci_intr __P((void *)); 208 209 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void acard_setup_channel __P((struct channel_softc*)); 211 int acard_pci_intr __P((void *)); 212 213 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void serverworks_setup_channel __P((struct channel_softc*)); 215 int serverworks_pci_intr __P((void *)); 216 217 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 218 void sl82c105_setup_channel __P((struct channel_softc*)); 219 220 void pciide_channel_dma_setup __P((struct pciide_channel *)); 221 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 222 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 223 void pciide_dma_start __P((void*, int, int)); 224 int pciide_dma_finish __P((void*, int, int, int)); 225 void pciide_irqack __P((struct channel_softc *)); 226 void pciide_print_modes __P((struct pciide_channel *)); 227 228 struct pciide_product_desc { 229 u_int32_t ide_product; 230 int ide_flags; 231 const char *ide_name; 232 /* map and setup chip, probe drives */ 233 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 234 }; 235 236 /* Flags for ide_flags */ 237 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 238 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 239 240 /* Default product description for devices not known from this controller */ 241 const struct pciide_product_desc default_product_desc = { 242 0, 243 0, 244 "Generic PCI IDE controller", 245 default_chip_map, 246 }; 247 248 const struct pciide_product_desc pciide_intel_products[] = { 249 { PCI_PRODUCT_INTEL_82092AA, 250 0, 251 "Intel 82092AA IDE controller", 252 default_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82371FB_IDE, 255 0, 256 "Intel 82371FB IDE controller (PIIX)", 257 piix_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82371SB_IDE, 260 0, 261 "Intel 82371SB IDE Interface (PIIX3)", 262 piix_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_82371AB_IDE, 265 0, 266 "Intel 82371AB IDE controller (PIIX4)", 267 piix_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82440MX_IDE, 270 0, 271 "Intel 82440MX IDE controller", 272 piix_chip_map 273 }, 274 { PCI_PRODUCT_INTEL_82801AA_IDE, 275 0, 276 "Intel 82801AA IDE Controller (ICH)", 277 piix_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_82801AB_IDE, 280 0, 281 "Intel 82801AB IDE Controller (ICH0)", 282 piix_chip_map, 283 }, 284 { PCI_PRODUCT_INTEL_82801BA_IDE, 285 0, 286 "Intel 82801BA IDE Controller (ICH2)", 287 piix_chip_map, 288 }, 289 { PCI_PRODUCT_INTEL_82801BAM_IDE, 290 0, 291 "Intel 82801BAM IDE Controller (ICH2)", 292 piix_chip_map, 293 }, 294 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 295 0, 296 "Intel 82801CA IDE Controller", 297 piix_chip_map, 298 }, 299 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 300 0, 301 "Intel 82801CA IDE Controller", 302 piix_chip_map, 303 }, 304 { PCI_PRODUCT_INTEL_82801DB_IDE, 305 0, 306 "Intel 82801DB IDE Controller (ICH4)", 307 piix_chip_map, 308 }, 309 { 0, 310 0, 311 NULL, 312 NULL 313 } 314 }; 315 316 const struct pciide_product_desc pciide_amd_products[] = { 317 { PCI_PRODUCT_AMD_PBC756_IDE, 318 0, 319 "Advanced Micro Devices AMD756 IDE Controller", 320 amd7x6_chip_map 321 }, 322 { PCI_PRODUCT_AMD_PBC766_IDE, 323 0, 324 "Advanced Micro Devices AMD766 IDE Controller", 325 amd7x6_chip_map 326 }, 327 { PCI_PRODUCT_AMD_PBC768_IDE, 328 0, 329 "Advanced Micro Devices AMD768 IDE Controller", 330 amd7x6_chip_map 331 }, 332 { 0, 333 0, 334 NULL, 335 NULL 336 } 337 }; 338 339 const struct pciide_product_desc pciide_cmd_products[] = { 340 { PCI_PRODUCT_CMDTECH_640, 341 0, 342 "CMD Technology PCI0640", 343 cmd_chip_map 344 }, 345 { PCI_PRODUCT_CMDTECH_643, 346 0, 347 "CMD Technology PCI0643", 348 cmd0643_9_chip_map, 349 }, 350 { PCI_PRODUCT_CMDTECH_646, 351 0, 352 "CMD Technology PCI0646", 353 cmd0643_9_chip_map, 354 }, 355 { PCI_PRODUCT_CMDTECH_648, 356 IDE_PCI_CLASS_OVERRIDE, 357 "CMD Technology PCI0648", 358 cmd0643_9_chip_map, 359 }, 360 { PCI_PRODUCT_CMDTECH_649, 361 IDE_PCI_CLASS_OVERRIDE, 362 "CMD Technology PCI0649", 363 cmd0643_9_chip_map, 364 }, 365 { 0, 366 0, 367 NULL, 368 NULL 369 } 370 }; 371 372 const struct pciide_product_desc pciide_via_products[] = { 373 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 374 0, 375 NULL, 376 apollo_chip_map, 377 }, 378 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 379 0, 380 NULL, 381 apollo_chip_map, 382 }, 383 { 0, 384 0, 385 NULL, 386 NULL 387 } 388 }; 389 390 const struct pciide_product_desc pciide_cypress_products[] = { 391 { PCI_PRODUCT_CONTAQ_82C693, 392 IDE_16BIT_IOSPACE, 393 "Cypress 82C693 IDE Controller", 394 cy693_chip_map, 395 }, 396 { 0, 397 0, 398 NULL, 399 NULL 400 } 401 }; 402 403 const struct pciide_product_desc pciide_sis_products[] = { 404 { PCI_PRODUCT_SIS_5597_IDE, 405 0, 406 NULL, 407 sis_chip_map, 408 }, 409 { 0, 410 0, 411 NULL, 412 NULL 413 } 414 }; 415 416 const struct pciide_product_desc pciide_acer_products[] = { 417 { PCI_PRODUCT_ALI_M5229, 418 0, 419 "Acer Labs M5229 UDMA IDE Controller", 420 acer_chip_map, 421 }, 422 { 0, 423 0, 424 NULL, 425 NULL 426 } 427 }; 428 429 const struct pciide_product_desc pciide_promise_products[] = { 430 { PCI_PRODUCT_PROMISE_ULTRA33, 431 IDE_PCI_CLASS_OVERRIDE, 432 "Promise Ultra33/ATA Bus Master IDE Accelerator", 433 pdc202xx_chip_map, 434 }, 435 { PCI_PRODUCT_PROMISE_ULTRA66, 436 IDE_PCI_CLASS_OVERRIDE, 437 "Promise Ultra66/ATA Bus Master IDE Accelerator", 438 pdc202xx_chip_map, 439 }, 440 { PCI_PRODUCT_PROMISE_ULTRA100, 441 IDE_PCI_CLASS_OVERRIDE, 442 "Promise Ultra100/ATA Bus Master IDE Accelerator", 443 pdc202xx_chip_map, 444 }, 445 { PCI_PRODUCT_PROMISE_ULTRA100X, 446 IDE_PCI_CLASS_OVERRIDE, 447 "Promise Ultra100/ATA Bus Master IDE Accelerator", 448 pdc202xx_chip_map, 449 }, 450 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 451 IDE_PCI_CLASS_OVERRIDE, 452 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 453 pdc202xx_chip_map, 454 }, 455 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 456 IDE_PCI_CLASS_OVERRIDE, 457 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 458 pdc202xx_chip_map, 459 }, 460 { PCI_PRODUCT_PROMISE_ULTRA133, 461 IDE_PCI_CLASS_OVERRIDE, 462 "Promise Ultra133/ATA Bus Master IDE Accelerator", 463 pdc202xx_chip_map, 464 }, 465 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 466 IDE_PCI_CLASS_OVERRIDE, 467 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 468 pdc202xx_chip_map, 469 }, 470 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 471 IDE_PCI_CLASS_OVERRIDE, 472 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 473 pdc202xx_chip_map, 474 }, 475 { 0, 476 0, 477 NULL, 478 NULL 479 } 480 }; 481 482 const struct pciide_product_desc pciide_opti_products[] = { 483 { PCI_PRODUCT_OPTI_82C621, 484 0, 485 "OPTi 82c621 PCI IDE controller", 486 opti_chip_map, 487 }, 488 { PCI_PRODUCT_OPTI_82C568, 489 0, 490 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 491 opti_chip_map, 492 }, 493 { PCI_PRODUCT_OPTI_82D568, 494 0, 495 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 496 opti_chip_map, 497 }, 498 { 0, 499 0, 500 NULL, 501 NULL 502 } 503 }; 504 505 const struct pciide_product_desc pciide_triones_products[] = { 506 { PCI_PRODUCT_TRIONES_HPT366, 507 IDE_PCI_CLASS_OVERRIDE, 508 NULL, 509 hpt_chip_map, 510 }, 511 { PCI_PRODUCT_TRIONES_HPT372, 512 IDE_PCI_CLASS_OVERRIDE, 513 NULL, 514 hpt_chip_map 515 }, 516 { PCI_PRODUCT_TRIONES_HPT374, 517 IDE_PCI_CLASS_OVERRIDE, 518 NULL, 519 hpt_chip_map 520 }, 521 { 0, 522 0, 523 NULL, 524 NULL 525 } 526 }; 527 528 const struct pciide_product_desc pciide_acard_products[] = { 529 { PCI_PRODUCT_ACARD_ATP850U, 530 IDE_PCI_CLASS_OVERRIDE, 531 "Acard ATP850U Ultra33 IDE Controller", 532 acard_chip_map, 533 }, 534 { PCI_PRODUCT_ACARD_ATP860, 535 IDE_PCI_CLASS_OVERRIDE, 536 "Acard ATP860 Ultra66 IDE Controller", 537 acard_chip_map, 538 }, 539 { PCI_PRODUCT_ACARD_ATP860A, 540 IDE_PCI_CLASS_OVERRIDE, 541 "Acard ATP860-A Ultra66 IDE Controller", 542 acard_chip_map, 543 }, 544 { 0, 545 0, 546 NULL, 547 NULL 548 } 549 }; 550 551 const struct pciide_product_desc pciide_serverworks_products[] = { 552 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 553 0, 554 "ServerWorks OSB4 IDE Controller", 555 serverworks_chip_map, 556 }, 557 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 558 0, 559 "ServerWorks CSB5 IDE Controller", 560 serverworks_chip_map, 561 }, 562 { 0, 563 0, 564 NULL, 565 } 566 }; 567 568 const struct pciide_product_desc pciide_symphony_products[] = { 569 { PCI_PRODUCT_SYMPHONY_82C105, 570 0, 571 "Symphony Labs 82C105 IDE controller", 572 sl82c105_chip_map, 573 }, 574 { 0, 575 0, 576 NULL, 577 } 578 }; 579 580 const struct pciide_product_desc pciide_winbond_products[] = { 581 { PCI_PRODUCT_WINBOND_W83C553F_1, 582 0, 583 "Winbond W83C553F IDE controller", 584 sl82c105_chip_map, 585 }, 586 { 0, 587 0, 588 NULL, 589 } 590 }; 591 592 struct pciide_vendor_desc { 593 u_int32_t ide_vendor; 594 const struct pciide_product_desc *ide_products; 595 }; 596 597 const struct pciide_vendor_desc pciide_vendors[] = { 598 { PCI_VENDOR_INTEL, pciide_intel_products }, 599 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 600 { PCI_VENDOR_VIATECH, pciide_via_products }, 601 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 602 { PCI_VENDOR_SIS, pciide_sis_products }, 603 { PCI_VENDOR_ALI, pciide_acer_products }, 604 { PCI_VENDOR_PROMISE, pciide_promise_products }, 605 { PCI_VENDOR_AMD, pciide_amd_products }, 606 { PCI_VENDOR_OPTI, pciide_opti_products }, 607 { PCI_VENDOR_TRIONES, pciide_triones_products }, 608 { PCI_VENDOR_ACARD, pciide_acard_products }, 609 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 610 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 611 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 612 { 0, NULL } 613 }; 614 615 /* options passed via the 'flags' config keyword */ 616 #define PCIIDE_OPTIONS_DMA 0x01 617 #define PCIIDE_OPTIONS_NODMA 0x02 618 619 int pciide_match __P((struct device *, struct cfdata *, void *)); 620 void pciide_attach __P((struct device *, struct device *, void *)); 621 622 struct cfattach pciide_ca = { 623 sizeof(struct pciide_softc), pciide_match, pciide_attach 624 }; 625 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 626 int pciide_mapregs_compat __P(( struct pci_attach_args *, 627 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 628 int pciide_mapregs_native __P((struct pci_attach_args *, 629 struct pciide_channel *, bus_size_t *, bus_size_t *, 630 int (*pci_intr) __P((void *)))); 631 void pciide_mapreg_dma __P((struct pciide_softc *, 632 struct pci_attach_args *)); 633 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 634 void pciide_mapchan __P((struct pci_attach_args *, 635 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 636 int (*pci_intr) __P((void *)))); 637 int pciide_chan_candisable __P((struct pciide_channel *)); 638 void pciide_map_compat_intr __P(( struct pci_attach_args *, 639 struct pciide_channel *, int, int)); 640 int pciide_compat_intr __P((void *)); 641 int pciide_pci_intr __P((void *)); 642 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 643 644 const struct pciide_product_desc * 645 pciide_lookup_product(id) 646 u_int32_t id; 647 { 648 const struct pciide_product_desc *pp; 649 const struct pciide_vendor_desc *vp; 650 651 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 652 if (PCI_VENDOR(id) == vp->ide_vendor) 653 break; 654 655 if ((pp = vp->ide_products) == NULL) 656 return NULL; 657 658 for (; pp->chip_map != NULL; pp++) 659 if (PCI_PRODUCT(id) == pp->ide_product) 660 break; 661 662 if (pp->chip_map == NULL) 663 return NULL; 664 return pp; 665 } 666 667 int 668 pciide_match(parent, match, aux) 669 struct device *parent; 670 struct cfdata *match; 671 void *aux; 672 { 673 struct pci_attach_args *pa = aux; 674 const struct pciide_product_desc *pp; 675 676 /* 677 * Check the ID register to see that it's a PCI IDE controller. 678 * If it is, we assume that we can deal with it; it _should_ 679 * work in a standardized way... 680 */ 681 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 682 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 683 return (1); 684 } 685 686 /* 687 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 688 * controllers. Let see if we can deal with it anyway. 689 */ 690 pp = pciide_lookup_product(pa->pa_id); 691 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 692 return (1); 693 } 694 695 return (0); 696 } 697 698 void 699 pciide_attach(parent, self, aux) 700 struct device *parent, *self; 701 void *aux; 702 { 703 struct pci_attach_args *pa = aux; 704 pci_chipset_tag_t pc = pa->pa_pc; 705 pcitag_t tag = pa->pa_tag; 706 struct pciide_softc *sc = (struct pciide_softc *)self; 707 pcireg_t csr; 708 char devinfo[256]; 709 const char *displaydev; 710 711 sc->sc_pp = pciide_lookup_product(pa->pa_id); 712 if (sc->sc_pp == NULL) { 713 sc->sc_pp = &default_product_desc; 714 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 715 displaydev = devinfo; 716 } else 717 displaydev = sc->sc_pp->ide_name; 718 719 /* if displaydev == NULL, printf is done in chip-specific map */ 720 if (displaydev) 721 printf(": %s (rev. 0x%02x)\n", displaydev, 722 PCI_REVISION(pa->pa_class)); 723 724 sc->sc_pc = pa->pa_pc; 725 sc->sc_tag = pa->pa_tag; 726 #ifdef WDCDEBUG 727 if (wdcdebug_pciide_mask & DEBUG_PROBE) 728 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 729 #endif 730 sc->sc_pp->chip_map(sc, pa); 731 732 if (sc->sc_dma_ok) { 733 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 734 csr |= PCI_COMMAND_MASTER_ENABLE; 735 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 736 } 737 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 738 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 739 } 740 741 /* tell wether the chip is enabled or not */ 742 int 743 pciide_chipen(sc, pa) 744 struct pciide_softc *sc; 745 struct pci_attach_args *pa; 746 { 747 pcireg_t csr; 748 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 749 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 750 PCI_COMMAND_STATUS_REG); 751 printf("%s: device disabled (at %s)\n", 752 sc->sc_wdcdev.sc_dev.dv_xname, 753 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 754 "device" : "bridge"); 755 return 0; 756 } 757 return 1; 758 } 759 760 int 761 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 762 struct pci_attach_args *pa; 763 struct pciide_channel *cp; 764 int compatchan; 765 bus_size_t *cmdsizep, *ctlsizep; 766 { 767 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 768 struct channel_softc *wdc_cp = &cp->wdc_channel; 769 770 cp->compat = 1; 771 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 772 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 773 774 wdc_cp->cmd_iot = pa->pa_iot; 775 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 776 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 777 printf("%s: couldn't map %s channel cmd regs\n", 778 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 779 return (0); 780 } 781 782 wdc_cp->ctl_iot = pa->pa_iot; 783 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 784 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 785 printf("%s: couldn't map %s channel ctl regs\n", 786 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 787 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 788 PCIIDE_COMPAT_CMD_SIZE); 789 return (0); 790 } 791 792 return (1); 793 } 794 795 int 796 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 797 struct pci_attach_args * pa; 798 struct pciide_channel *cp; 799 bus_size_t *cmdsizep, *ctlsizep; 800 int (*pci_intr) __P((void *)); 801 { 802 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 803 struct channel_softc *wdc_cp = &cp->wdc_channel; 804 const char *intrstr; 805 pci_intr_handle_t intrhandle; 806 807 cp->compat = 0; 808 809 if (sc->sc_pci_ih == NULL) { 810 if (pci_intr_map(pa, &intrhandle) != 0) { 811 printf("%s: couldn't map native-PCI interrupt\n", 812 sc->sc_wdcdev.sc_dev.dv_xname); 813 return 0; 814 } 815 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 816 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 817 intrhandle, IPL_BIO, pci_intr, sc); 818 if (sc->sc_pci_ih != NULL) { 819 printf("%s: using %s for native-PCI interrupt\n", 820 sc->sc_wdcdev.sc_dev.dv_xname, 821 intrstr ? intrstr : "unknown interrupt"); 822 } else { 823 printf("%s: couldn't establish native-PCI interrupt", 824 sc->sc_wdcdev.sc_dev.dv_xname); 825 if (intrstr != NULL) 826 printf(" at %s", intrstr); 827 printf("\n"); 828 return 0; 829 } 830 } 831 cp->ih = sc->sc_pci_ih; 832 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 833 PCI_MAPREG_TYPE_IO, 0, 834 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 835 printf("%s: couldn't map %s channel cmd regs\n", 836 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 837 return 0; 838 } 839 840 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 841 PCI_MAPREG_TYPE_IO, 0, 842 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 843 printf("%s: couldn't map %s channel ctl regs\n", 844 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 845 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 846 return 0; 847 } 848 /* 849 * In native mode, 4 bytes of I/O space are mapped for the control 850 * register, the control register is at offset 2. Pass the generic 851 * code a handle for only one byte at the rigth offset. 852 */ 853 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 854 &wdc_cp->ctl_ioh) != 0) { 855 printf("%s: unable to subregion %s channel ctl regs\n", 856 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 857 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 858 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 859 return 0; 860 } 861 return (1); 862 } 863 864 void 865 pciide_mapreg_dma(sc, pa) 866 struct pciide_softc *sc; 867 struct pci_attach_args *pa; 868 { 869 pcireg_t maptype; 870 bus_addr_t addr; 871 872 /* 873 * Map DMA registers 874 * 875 * Note that sc_dma_ok is the right variable to test to see if 876 * DMA can be done. If the interface doesn't support DMA, 877 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 878 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 879 * non-zero if the interface supports DMA and the registers 880 * could be mapped. 881 * 882 * XXX Note that despite the fact that the Bus Master IDE specs 883 * XXX say that "The bus master IDE function uses 16 bytes of IO 884 * XXX space," some controllers (at least the United 885 * XXX Microelectronics UM8886BF) place it in memory space. 886 */ 887 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 888 PCIIDE_REG_BUS_MASTER_DMA); 889 890 switch (maptype) { 891 case PCI_MAPREG_TYPE_IO: 892 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 893 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 894 &addr, NULL, NULL) == 0); 895 if (sc->sc_dma_ok == 0) { 896 printf(", but unused (couldn't query registers)"); 897 break; 898 } 899 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 900 && addr >= 0x10000) { 901 sc->sc_dma_ok = 0; 902 printf(", but unused (registers at unsafe address " 903 "%#lx)", (unsigned long)addr); 904 break; 905 } 906 /* FALLTHROUGH */ 907 908 case PCI_MAPREG_MEM_TYPE_32BIT: 909 sc->sc_dma_ok = (pci_mapreg_map(pa, 910 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 911 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 912 sc->sc_dmat = pa->pa_dmat; 913 if (sc->sc_dma_ok == 0) { 914 printf(", but unused (couldn't map registers)"); 915 } else { 916 sc->sc_wdcdev.dma_arg = sc; 917 sc->sc_wdcdev.dma_init = pciide_dma_init; 918 sc->sc_wdcdev.dma_start = pciide_dma_start; 919 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 920 } 921 922 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 923 PCIIDE_OPTIONS_NODMA) { 924 printf(", but unused (forced off by config file)"); 925 sc->sc_dma_ok = 0; 926 } 927 break; 928 929 default: 930 sc->sc_dma_ok = 0; 931 printf(", but unsupported register maptype (0x%x)", maptype); 932 } 933 } 934 935 int 936 pciide_compat_intr(arg) 937 void *arg; 938 { 939 struct pciide_channel *cp = arg; 940 941 #ifdef DIAGNOSTIC 942 /* should only be called for a compat channel */ 943 if (cp->compat == 0) 944 panic("pciide compat intr called for non-compat chan %p\n", cp); 945 #endif 946 return (wdcintr(&cp->wdc_channel)); 947 } 948 949 int 950 pciide_pci_intr(arg) 951 void *arg; 952 { 953 struct pciide_softc *sc = arg; 954 struct pciide_channel *cp; 955 struct channel_softc *wdc_cp; 956 int i, rv, crv; 957 958 rv = 0; 959 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 960 cp = &sc->pciide_channels[i]; 961 wdc_cp = &cp->wdc_channel; 962 963 /* If a compat channel skip. */ 964 if (cp->compat) 965 continue; 966 /* if this channel not waiting for intr, skip */ 967 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 968 continue; 969 970 crv = wdcintr(wdc_cp); 971 if (crv == 0) 972 ; /* leave rv alone */ 973 else if (crv == 1) 974 rv = 1; /* claim the intr */ 975 else if (rv == 0) /* crv should be -1 in this case */ 976 rv = crv; /* if we've done no better, take it */ 977 } 978 return (rv); 979 } 980 981 void 982 pciide_channel_dma_setup(cp) 983 struct pciide_channel *cp; 984 { 985 int drive; 986 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 987 struct ata_drive_datas *drvp; 988 989 for (drive = 0; drive < 2; drive++) { 990 drvp = &cp->wdc_channel.ch_drive[drive]; 991 /* If no drive, skip */ 992 if ((drvp->drive_flags & DRIVE) == 0) 993 continue; 994 /* setup DMA if needed */ 995 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 996 (drvp->drive_flags & DRIVE_UDMA) == 0) || 997 sc->sc_dma_ok == 0) { 998 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 999 continue; 1000 } 1001 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1002 != 0) { 1003 /* Abort DMA setup */ 1004 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1005 continue; 1006 } 1007 } 1008 } 1009 1010 int 1011 pciide_dma_table_setup(sc, channel, drive) 1012 struct pciide_softc *sc; 1013 int channel, drive; 1014 { 1015 bus_dma_segment_t seg; 1016 int error, rseg; 1017 const bus_size_t dma_table_size = 1018 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1019 struct pciide_dma_maps *dma_maps = 1020 &sc->pciide_channels[channel].dma_maps[drive]; 1021 1022 /* If table was already allocated, just return */ 1023 if (dma_maps->dma_table) 1024 return 0; 1025 1026 /* Allocate memory for the DMA tables and map it */ 1027 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1028 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1029 BUS_DMA_NOWAIT)) != 0) { 1030 printf("%s:%d: unable to allocate table DMA for " 1031 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1032 channel, drive, error); 1033 return error; 1034 } 1035 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1036 dma_table_size, 1037 (caddr_t *)&dma_maps->dma_table, 1038 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1039 printf("%s:%d: unable to map table DMA for" 1040 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1041 channel, drive, error); 1042 return error; 1043 } 1044 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1045 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1046 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1047 1048 /* Create and load table DMA map for this disk */ 1049 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1050 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1051 &dma_maps->dmamap_table)) != 0) { 1052 printf("%s:%d: unable to create table DMA map for " 1053 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1054 channel, drive, error); 1055 return error; 1056 } 1057 if ((error = bus_dmamap_load(sc->sc_dmat, 1058 dma_maps->dmamap_table, 1059 dma_maps->dma_table, 1060 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1061 printf("%s:%d: unable to load table DMA map for " 1062 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1063 channel, drive, error); 1064 return error; 1065 } 1066 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1067 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1068 DEBUG_PROBE); 1069 /* Create a xfer DMA map for this drive */ 1070 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1071 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1072 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1073 &dma_maps->dmamap_xfer)) != 0) { 1074 printf("%s:%d: unable to create xfer DMA map for " 1075 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1076 channel, drive, error); 1077 return error; 1078 } 1079 return 0; 1080 } 1081 1082 int 1083 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1084 void *v; 1085 int channel, drive; 1086 void *databuf; 1087 size_t datalen; 1088 int flags; 1089 { 1090 struct pciide_softc *sc = v; 1091 int error, seg; 1092 struct pciide_dma_maps *dma_maps = 1093 &sc->pciide_channels[channel].dma_maps[drive]; 1094 1095 error = bus_dmamap_load(sc->sc_dmat, 1096 dma_maps->dmamap_xfer, 1097 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1098 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1099 if (error) { 1100 printf("%s:%d: unable to load xfer DMA map for" 1101 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1102 channel, drive, error); 1103 return error; 1104 } 1105 1106 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1107 dma_maps->dmamap_xfer->dm_mapsize, 1108 (flags & WDC_DMA_READ) ? 1109 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1110 1111 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1112 #ifdef DIAGNOSTIC 1113 /* A segment must not cross a 64k boundary */ 1114 { 1115 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1116 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1117 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1118 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1119 printf("pciide_dma: segment %d physical addr 0x%lx" 1120 " len 0x%lx not properly aligned\n", 1121 seg, phys, len); 1122 panic("pciide_dma: buf align"); 1123 } 1124 } 1125 #endif 1126 dma_maps->dma_table[seg].base_addr = 1127 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1128 dma_maps->dma_table[seg].byte_count = 1129 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1130 IDEDMA_BYTE_COUNT_MASK); 1131 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1132 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1133 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1134 1135 } 1136 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1137 htole32(IDEDMA_BYTE_COUNT_EOT); 1138 1139 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1140 dma_maps->dmamap_table->dm_mapsize, 1141 BUS_DMASYNC_PREWRITE); 1142 1143 /* Maps are ready. Start DMA function */ 1144 #ifdef DIAGNOSTIC 1145 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1146 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1147 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1148 panic("pciide_dma_init: table align"); 1149 } 1150 #endif 1151 1152 /* Clear status bits */ 1153 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1154 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1155 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1156 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1157 /* Write table addr */ 1158 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1159 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1160 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1161 /* set read/write */ 1162 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1163 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1164 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1165 /* remember flags */ 1166 dma_maps->dma_flags = flags; 1167 return 0; 1168 } 1169 1170 void 1171 pciide_dma_start(v, channel, drive) 1172 void *v; 1173 int channel, drive; 1174 { 1175 struct pciide_softc *sc = v; 1176 1177 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1178 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1179 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1180 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1181 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1182 } 1183 1184 int 1185 pciide_dma_finish(v, channel, drive, force) 1186 void *v; 1187 int channel, drive; 1188 int force; 1189 { 1190 struct pciide_softc *sc = v; 1191 u_int8_t status; 1192 int error = 0; 1193 struct pciide_dma_maps *dma_maps = 1194 &sc->pciide_channels[channel].dma_maps[drive]; 1195 1196 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1197 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1198 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1199 DEBUG_XFERS); 1200 1201 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1202 return WDC_DMAST_NOIRQ; 1203 1204 /* stop DMA channel */ 1205 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1206 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1207 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1208 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1209 1210 /* Unload the map of the data buffer */ 1211 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1212 dma_maps->dmamap_xfer->dm_mapsize, 1213 (dma_maps->dma_flags & WDC_DMA_READ) ? 1214 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1215 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1216 1217 if ((status & IDEDMA_CTL_ERR) != 0) { 1218 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1219 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1220 error |= WDC_DMAST_ERR; 1221 } 1222 1223 if ((status & IDEDMA_CTL_INTR) == 0) { 1224 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1225 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1226 drive, status); 1227 error |= WDC_DMAST_NOIRQ; 1228 } 1229 1230 if ((status & IDEDMA_CTL_ACT) != 0) { 1231 /* data underrun, may be a valid condition for ATAPI */ 1232 error |= WDC_DMAST_UNDER; 1233 } 1234 return error; 1235 } 1236 1237 void 1238 pciide_irqack(chp) 1239 struct channel_softc *chp; 1240 { 1241 struct pciide_channel *cp = (struct pciide_channel*)chp; 1242 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1243 1244 /* clear status bits in IDE DMA registers */ 1245 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1246 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1247 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1248 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1249 } 1250 1251 /* some common code used by several chip_map */ 1252 int 1253 pciide_chansetup(sc, channel, interface) 1254 struct pciide_softc *sc; 1255 int channel; 1256 pcireg_t interface; 1257 { 1258 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1259 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1260 cp->name = PCIIDE_CHANNEL_NAME(channel); 1261 cp->wdc_channel.channel = channel; 1262 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1263 cp->wdc_channel.ch_queue = 1264 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1265 if (cp->wdc_channel.ch_queue == NULL) { 1266 printf("%s %s channel: " 1267 "can't allocate memory for command queue", 1268 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1269 return 0; 1270 } 1271 printf("%s: %s channel %s to %s mode\n", 1272 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1273 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1274 "configured" : "wired", 1275 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1276 "native-PCI" : "compatibility"); 1277 return 1; 1278 } 1279 1280 /* some common code used by several chip channel_map */ 1281 void 1282 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1283 struct pci_attach_args *pa; 1284 struct pciide_channel *cp; 1285 pcireg_t interface; 1286 bus_size_t *cmdsizep, *ctlsizep; 1287 int (*pci_intr) __P((void *)); 1288 { 1289 struct channel_softc *wdc_cp = &cp->wdc_channel; 1290 1291 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1292 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1293 pci_intr); 1294 else 1295 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1296 wdc_cp->channel, cmdsizep, ctlsizep); 1297 1298 if (cp->hw_ok == 0) 1299 return; 1300 wdc_cp->data32iot = wdc_cp->cmd_iot; 1301 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1302 wdcattach(wdc_cp); 1303 } 1304 1305 /* 1306 * Generic code to call to know if a channel can be disabled. Return 1 1307 * if channel can be disabled, 0 if not 1308 */ 1309 int 1310 pciide_chan_candisable(cp) 1311 struct pciide_channel *cp; 1312 { 1313 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1314 struct channel_softc *wdc_cp = &cp->wdc_channel; 1315 1316 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1317 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1318 printf("%s: disabling %s channel (no drives)\n", 1319 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1320 cp->hw_ok = 0; 1321 return 1; 1322 } 1323 return 0; 1324 } 1325 1326 /* 1327 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1328 * Set hw_ok=0 on failure 1329 */ 1330 void 1331 pciide_map_compat_intr(pa, cp, compatchan, interface) 1332 struct pci_attach_args *pa; 1333 struct pciide_channel *cp; 1334 int compatchan, interface; 1335 { 1336 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1337 struct channel_softc *wdc_cp = &cp->wdc_channel; 1338 1339 if (cp->hw_ok == 0) 1340 return; 1341 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1342 return; 1343 1344 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1345 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1346 pa, compatchan, pciide_compat_intr, cp); 1347 if (cp->ih == NULL) { 1348 #endif 1349 printf("%s: no compatibility interrupt for use by %s " 1350 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1351 cp->hw_ok = 0; 1352 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1353 } 1354 #endif 1355 } 1356 1357 void 1358 pciide_print_modes(cp) 1359 struct pciide_channel *cp; 1360 { 1361 wdc_print_modes(&cp->wdc_channel); 1362 } 1363 1364 void 1365 default_chip_map(sc, pa) 1366 struct pciide_softc *sc; 1367 struct pci_attach_args *pa; 1368 { 1369 struct pciide_channel *cp; 1370 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1371 pcireg_t csr; 1372 int channel, drive; 1373 struct ata_drive_datas *drvp; 1374 u_int8_t idedma_ctl; 1375 bus_size_t cmdsize, ctlsize; 1376 char *failreason; 1377 1378 if (pciide_chipen(sc, pa) == 0) 1379 return; 1380 1381 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1382 printf("%s: bus-master DMA support present", 1383 sc->sc_wdcdev.sc_dev.dv_xname); 1384 if (sc->sc_pp == &default_product_desc && 1385 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1386 PCIIDE_OPTIONS_DMA) == 0) { 1387 printf(", but unused (no driver support)"); 1388 sc->sc_dma_ok = 0; 1389 } else { 1390 pciide_mapreg_dma(sc, pa); 1391 if (sc->sc_dma_ok != 0) 1392 printf(", used without full driver " 1393 "support"); 1394 } 1395 } else { 1396 printf("%s: hardware does not support DMA", 1397 sc->sc_wdcdev.sc_dev.dv_xname); 1398 sc->sc_dma_ok = 0; 1399 } 1400 printf("\n"); 1401 if (sc->sc_dma_ok) { 1402 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1403 sc->sc_wdcdev.irqack = pciide_irqack; 1404 } 1405 sc->sc_wdcdev.PIO_cap = 0; 1406 sc->sc_wdcdev.DMA_cap = 0; 1407 1408 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1409 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1410 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1411 1412 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1413 cp = &sc->pciide_channels[channel]; 1414 if (pciide_chansetup(sc, channel, interface) == 0) 1415 continue; 1416 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1417 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1418 &ctlsize, pciide_pci_intr); 1419 } else { 1420 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1421 channel, &cmdsize, &ctlsize); 1422 } 1423 if (cp->hw_ok == 0) 1424 continue; 1425 /* 1426 * Check to see if something appears to be there. 1427 */ 1428 failreason = NULL; 1429 if (!wdcprobe(&cp->wdc_channel)) { 1430 failreason = "not responding; disabled or no drives?"; 1431 goto next; 1432 } 1433 /* 1434 * Now, make sure it's actually attributable to this PCI IDE 1435 * channel by trying to access the channel again while the 1436 * PCI IDE controller's I/O space is disabled. (If the 1437 * channel no longer appears to be there, it belongs to 1438 * this controller.) YUCK! 1439 */ 1440 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1441 PCI_COMMAND_STATUS_REG); 1442 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1443 csr & ~PCI_COMMAND_IO_ENABLE); 1444 if (wdcprobe(&cp->wdc_channel)) 1445 failreason = "other hardware responding at addresses"; 1446 pci_conf_write(sc->sc_pc, sc->sc_tag, 1447 PCI_COMMAND_STATUS_REG, csr); 1448 next: 1449 if (failreason) { 1450 printf("%s: %s channel ignored (%s)\n", 1451 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1452 failreason); 1453 cp->hw_ok = 0; 1454 bus_space_unmap(cp->wdc_channel.cmd_iot, 1455 cp->wdc_channel.cmd_ioh, cmdsize); 1456 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1457 bus_space_unmap(cp->wdc_channel.ctl_iot, 1458 cp->ctl_baseioh, ctlsize); 1459 else 1460 bus_space_unmap(cp->wdc_channel.ctl_iot, 1461 cp->wdc_channel.ctl_ioh, ctlsize); 1462 } else { 1463 pciide_map_compat_intr(pa, cp, channel, interface); 1464 } 1465 if (cp->hw_ok) { 1466 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1467 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1468 wdcattach(&cp->wdc_channel); 1469 } 1470 } 1471 1472 if (sc->sc_dma_ok == 0) 1473 return; 1474 1475 /* Allocate DMA maps */ 1476 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1477 idedma_ctl = 0; 1478 cp = &sc->pciide_channels[channel]; 1479 for (drive = 0; drive < 2; drive++) { 1480 drvp = &cp->wdc_channel.ch_drive[drive]; 1481 /* If no drive, skip */ 1482 if ((drvp->drive_flags & DRIVE) == 0) 1483 continue; 1484 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1485 continue; 1486 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1487 /* Abort DMA setup */ 1488 printf("%s:%d:%d: can't allocate DMA maps, " 1489 "using PIO transfers\n", 1490 sc->sc_wdcdev.sc_dev.dv_xname, 1491 channel, drive); 1492 drvp->drive_flags &= ~DRIVE_DMA; 1493 } 1494 printf("%s:%d:%d: using DMA data transfers\n", 1495 sc->sc_wdcdev.sc_dev.dv_xname, 1496 channel, drive); 1497 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1498 } 1499 if (idedma_ctl != 0) { 1500 /* Add software bits in status register */ 1501 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1502 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1503 idedma_ctl); 1504 } 1505 } 1506 } 1507 1508 void 1509 piix_chip_map(sc, pa) 1510 struct pciide_softc *sc; 1511 struct pci_attach_args *pa; 1512 { 1513 struct pciide_channel *cp; 1514 int channel; 1515 u_int32_t idetim; 1516 bus_size_t cmdsize, ctlsize; 1517 1518 if (pciide_chipen(sc, pa) == 0) 1519 return; 1520 1521 printf("%s: bus-master DMA support present", 1522 sc->sc_wdcdev.sc_dev.dv_xname); 1523 pciide_mapreg_dma(sc, pa); 1524 printf("\n"); 1525 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1526 WDC_CAPABILITY_MODE; 1527 if (sc->sc_dma_ok) { 1528 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1529 sc->sc_wdcdev.irqack = pciide_irqack; 1530 switch(sc->sc_pp->ide_product) { 1531 case PCI_PRODUCT_INTEL_82371AB_IDE: 1532 case PCI_PRODUCT_INTEL_82440MX_IDE: 1533 case PCI_PRODUCT_INTEL_82801AA_IDE: 1534 case PCI_PRODUCT_INTEL_82801AB_IDE: 1535 case PCI_PRODUCT_INTEL_82801BA_IDE: 1536 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1537 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1538 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1539 case PCI_PRODUCT_INTEL_82801DB_IDE: 1540 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1541 } 1542 } 1543 sc->sc_wdcdev.PIO_cap = 4; 1544 sc->sc_wdcdev.DMA_cap = 2; 1545 switch(sc->sc_pp->ide_product) { 1546 case PCI_PRODUCT_INTEL_82801AA_IDE: 1547 sc->sc_wdcdev.UDMA_cap = 4; 1548 break; 1549 case PCI_PRODUCT_INTEL_82801BA_IDE: 1550 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1551 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1552 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1553 case PCI_PRODUCT_INTEL_82801DB_IDE: 1554 sc->sc_wdcdev.UDMA_cap = 5; 1555 break; 1556 default: 1557 sc->sc_wdcdev.UDMA_cap = 2; 1558 } 1559 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1560 sc->sc_wdcdev.set_modes = piix_setup_channel; 1561 else 1562 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1563 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1564 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1565 1566 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1567 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1568 DEBUG_PROBE); 1569 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1570 WDCDEBUG_PRINT((", sidetim=0x%x", 1571 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1572 DEBUG_PROBE); 1573 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1574 WDCDEBUG_PRINT((", udamreg 0x%x", 1575 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1576 DEBUG_PROBE); 1577 } 1578 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1580 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1581 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1582 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1583 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1584 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1585 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1586 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1587 DEBUG_PROBE); 1588 } 1589 1590 } 1591 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1592 1593 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1594 cp = &sc->pciide_channels[channel]; 1595 /* PIIX is compat-only */ 1596 if (pciide_chansetup(sc, channel, 0) == 0) 1597 continue; 1598 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1599 if ((PIIX_IDETIM_READ(idetim, channel) & 1600 PIIX_IDETIM_IDE) == 0) { 1601 printf("%s: %s channel ignored (disabled)\n", 1602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1603 continue; 1604 } 1605 /* PIIX are compat-only pciide devices */ 1606 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1607 if (cp->hw_ok == 0) 1608 continue; 1609 if (pciide_chan_candisable(cp)) { 1610 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1611 channel); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1613 idetim); 1614 } 1615 pciide_map_compat_intr(pa, cp, channel, 0); 1616 if (cp->hw_ok == 0) 1617 continue; 1618 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1619 } 1620 1621 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1622 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1623 DEBUG_PROBE); 1624 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1625 WDCDEBUG_PRINT((", sidetim=0x%x", 1626 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1627 DEBUG_PROBE); 1628 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1629 WDCDEBUG_PRINT((", udamreg 0x%x", 1630 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1631 DEBUG_PROBE); 1632 } 1633 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1640 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1641 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1642 DEBUG_PROBE); 1643 } 1644 } 1645 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1646 } 1647 1648 void 1649 piix_setup_channel(chp) 1650 struct channel_softc *chp; 1651 { 1652 u_int8_t mode[2], drive; 1653 u_int32_t oidetim, idetim, idedma_ctl; 1654 struct pciide_channel *cp = (struct pciide_channel*)chp; 1655 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1656 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1657 1658 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1659 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1660 idedma_ctl = 0; 1661 1662 /* set up new idetim: Enable IDE registers decode */ 1663 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1664 chp->channel); 1665 1666 /* setup DMA */ 1667 pciide_channel_dma_setup(cp); 1668 1669 /* 1670 * Here we have to mess up with drives mode: PIIX can't have 1671 * different timings for master and slave drives. 1672 * We need to find the best combination. 1673 */ 1674 1675 /* If both drives supports DMA, take the lower mode */ 1676 if ((drvp[0].drive_flags & DRIVE_DMA) && 1677 (drvp[1].drive_flags & DRIVE_DMA)) { 1678 mode[0] = mode[1] = 1679 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1680 drvp[0].DMA_mode = mode[0]; 1681 drvp[1].DMA_mode = mode[1]; 1682 goto ok; 1683 } 1684 /* 1685 * If only one drive supports DMA, use its mode, and 1686 * put the other one in PIO mode 0 if mode not compatible 1687 */ 1688 if (drvp[0].drive_flags & DRIVE_DMA) { 1689 mode[0] = drvp[0].DMA_mode; 1690 mode[1] = drvp[1].PIO_mode; 1691 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1692 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1693 mode[1] = drvp[1].PIO_mode = 0; 1694 goto ok; 1695 } 1696 if (drvp[1].drive_flags & DRIVE_DMA) { 1697 mode[1] = drvp[1].DMA_mode; 1698 mode[0] = drvp[0].PIO_mode; 1699 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1700 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1701 mode[0] = drvp[0].PIO_mode = 0; 1702 goto ok; 1703 } 1704 /* 1705 * If both drives are not DMA, takes the lower mode, unless 1706 * one of them is PIO mode < 2 1707 */ 1708 if (drvp[0].PIO_mode < 2) { 1709 mode[0] = drvp[0].PIO_mode = 0; 1710 mode[1] = drvp[1].PIO_mode; 1711 } else if (drvp[1].PIO_mode < 2) { 1712 mode[1] = drvp[1].PIO_mode = 0; 1713 mode[0] = drvp[0].PIO_mode; 1714 } else { 1715 mode[0] = mode[1] = 1716 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1717 drvp[0].PIO_mode = mode[0]; 1718 drvp[1].PIO_mode = mode[1]; 1719 } 1720 ok: /* The modes are setup */ 1721 for (drive = 0; drive < 2; drive++) { 1722 if (drvp[drive].drive_flags & DRIVE_DMA) { 1723 idetim |= piix_setup_idetim_timings( 1724 mode[drive], 1, chp->channel); 1725 goto end; 1726 } 1727 } 1728 /* If we are there, none of the drives are DMA */ 1729 if (mode[0] >= 2) 1730 idetim |= piix_setup_idetim_timings( 1731 mode[0], 0, chp->channel); 1732 else 1733 idetim |= piix_setup_idetim_timings( 1734 mode[1], 0, chp->channel); 1735 end: /* 1736 * timing mode is now set up in the controller. Enable 1737 * it per-drive 1738 */ 1739 for (drive = 0; drive < 2; drive++) { 1740 /* If no drive, skip */ 1741 if ((drvp[drive].drive_flags & DRIVE) == 0) 1742 continue; 1743 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1744 if (drvp[drive].drive_flags & DRIVE_DMA) 1745 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1746 } 1747 if (idedma_ctl != 0) { 1748 /* Add software bits in status register */ 1749 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1750 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1751 idedma_ctl); 1752 } 1753 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1754 pciide_print_modes(cp); 1755 } 1756 1757 void 1758 piix3_4_setup_channel(chp) 1759 struct channel_softc *chp; 1760 { 1761 struct ata_drive_datas *drvp; 1762 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1763 struct pciide_channel *cp = (struct pciide_channel*)chp; 1764 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1765 int drive; 1766 int channel = chp->channel; 1767 1768 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1769 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1770 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1771 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1772 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1773 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1774 PIIX_SIDETIM_RTC_MASK(channel)); 1775 1776 idedma_ctl = 0; 1777 /* If channel disabled, no need to go further */ 1778 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1779 return; 1780 /* set up new idetim: Enable IDE registers decode */ 1781 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1782 1783 /* setup DMA if needed */ 1784 pciide_channel_dma_setup(cp); 1785 1786 for (drive = 0; drive < 2; drive++) { 1787 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1788 PIIX_UDMATIM_SET(0x3, channel, drive)); 1789 drvp = &chp->ch_drive[drive]; 1790 /* If no drive, skip */ 1791 if ((drvp->drive_flags & DRIVE) == 0) 1792 continue; 1793 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1794 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1795 goto pio; 1796 1797 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1798 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1799 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1800 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1801 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1802 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1803 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1804 ideconf |= PIIX_CONFIG_PINGPONG; 1805 } 1806 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1807 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1808 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1809 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1810 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1811 /* setup Ultra/100 */ 1812 if (drvp->UDMA_mode > 2 && 1813 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1814 drvp->UDMA_mode = 2; 1815 if (drvp->UDMA_mode > 4) { 1816 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1817 } else { 1818 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1819 if (drvp->UDMA_mode > 2) { 1820 ideconf |= PIIX_CONFIG_UDMA66(channel, 1821 drive); 1822 } else { 1823 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1824 drive); 1825 } 1826 } 1827 } 1828 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1829 /* setup Ultra/66 */ 1830 if (drvp->UDMA_mode > 2 && 1831 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1832 drvp->UDMA_mode = 2; 1833 if (drvp->UDMA_mode > 2) 1834 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1835 else 1836 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1837 } 1838 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1839 (drvp->drive_flags & DRIVE_UDMA)) { 1840 /* use Ultra/DMA */ 1841 drvp->drive_flags &= ~DRIVE_DMA; 1842 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1843 udmareg |= PIIX_UDMATIM_SET( 1844 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1845 } else { 1846 /* use Multiword DMA */ 1847 drvp->drive_flags &= ~DRIVE_UDMA; 1848 if (drive == 0) { 1849 idetim |= piix_setup_idetim_timings( 1850 drvp->DMA_mode, 1, channel); 1851 } else { 1852 sidetim |= piix_setup_sidetim_timings( 1853 drvp->DMA_mode, 1, channel); 1854 idetim =PIIX_IDETIM_SET(idetim, 1855 PIIX_IDETIM_SITRE, channel); 1856 } 1857 } 1858 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1859 1860 pio: /* use PIO mode */ 1861 idetim |= piix_setup_idetim_drvs(drvp); 1862 if (drive == 0) { 1863 idetim |= piix_setup_idetim_timings( 1864 drvp->PIO_mode, 0, channel); 1865 } else { 1866 sidetim |= piix_setup_sidetim_timings( 1867 drvp->PIO_mode, 0, channel); 1868 idetim =PIIX_IDETIM_SET(idetim, 1869 PIIX_IDETIM_SITRE, channel); 1870 } 1871 } 1872 if (idedma_ctl != 0) { 1873 /* Add software bits in status register */ 1874 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1875 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1876 idedma_ctl); 1877 } 1878 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1879 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1880 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1881 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1882 pciide_print_modes(cp); 1883 } 1884 1885 1886 /* setup ISP and RTC fields, based on mode */ 1887 static u_int32_t 1888 piix_setup_idetim_timings(mode, dma, channel) 1889 u_int8_t mode; 1890 u_int8_t dma; 1891 u_int8_t channel; 1892 { 1893 1894 if (dma) 1895 return PIIX_IDETIM_SET(0, 1896 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1897 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1898 channel); 1899 else 1900 return PIIX_IDETIM_SET(0, 1901 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1902 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1903 channel); 1904 } 1905 1906 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1907 static u_int32_t 1908 piix_setup_idetim_drvs(drvp) 1909 struct ata_drive_datas *drvp; 1910 { 1911 u_int32_t ret = 0; 1912 struct channel_softc *chp = drvp->chnl_softc; 1913 u_int8_t channel = chp->channel; 1914 u_int8_t drive = drvp->drive; 1915 1916 /* 1917 * If drive is using UDMA, timings setups are independant 1918 * So just check DMA and PIO here. 1919 */ 1920 if (drvp->drive_flags & DRIVE_DMA) { 1921 /* if mode = DMA mode 0, use compatible timings */ 1922 if ((drvp->drive_flags & DRIVE_DMA) && 1923 drvp->DMA_mode == 0) { 1924 drvp->PIO_mode = 0; 1925 return ret; 1926 } 1927 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1928 /* 1929 * PIO and DMA timings are the same, use fast timings for PIO 1930 * too, else use compat timings. 1931 */ 1932 if ((piix_isp_pio[drvp->PIO_mode] != 1933 piix_isp_dma[drvp->DMA_mode]) || 1934 (piix_rtc_pio[drvp->PIO_mode] != 1935 piix_rtc_dma[drvp->DMA_mode])) 1936 drvp->PIO_mode = 0; 1937 /* if PIO mode <= 2, use compat timings for PIO */ 1938 if (drvp->PIO_mode <= 2) { 1939 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1940 channel); 1941 return ret; 1942 } 1943 } 1944 1945 /* 1946 * Now setup PIO modes. If mode < 2, use compat timings. 1947 * Else enable fast timings. Enable IORDY and prefetch/post 1948 * if PIO mode >= 3. 1949 */ 1950 1951 if (drvp->PIO_mode < 2) 1952 return ret; 1953 1954 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1955 if (drvp->PIO_mode >= 3) { 1956 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1957 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1958 } 1959 return ret; 1960 } 1961 1962 /* setup values in SIDETIM registers, based on mode */ 1963 static u_int32_t 1964 piix_setup_sidetim_timings(mode, dma, channel) 1965 u_int8_t mode; 1966 u_int8_t dma; 1967 u_int8_t channel; 1968 { 1969 if (dma) 1970 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1971 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1972 else 1973 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1974 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1975 } 1976 1977 void 1978 amd7x6_chip_map(sc, pa) 1979 struct pciide_softc *sc; 1980 struct pci_attach_args *pa; 1981 { 1982 struct pciide_channel *cp; 1983 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1984 int channel; 1985 pcireg_t chanenable; 1986 bus_size_t cmdsize, ctlsize; 1987 1988 if (pciide_chipen(sc, pa) == 0) 1989 return; 1990 printf("%s: bus-master DMA support present", 1991 sc->sc_wdcdev.sc_dev.dv_xname); 1992 pciide_mapreg_dma(sc, pa); 1993 printf("\n"); 1994 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1995 WDC_CAPABILITY_MODE; 1996 if (sc->sc_dma_ok) { 1997 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1998 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1999 sc->sc_wdcdev.irqack = pciide_irqack; 2000 } 2001 sc->sc_wdcdev.PIO_cap = 4; 2002 sc->sc_wdcdev.DMA_cap = 2; 2003 2004 switch (sc->sc_pp->ide_product) { 2005 case PCI_PRODUCT_AMD_PBC766_IDE: 2006 case PCI_PRODUCT_AMD_PBC768_IDE: 2007 sc->sc_wdcdev.UDMA_cap = 5; 2008 break; 2009 default: 2010 sc->sc_wdcdev.UDMA_cap = 4; 2011 } 2012 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2013 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2014 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2015 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 2016 2017 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2018 DEBUG_PROBE); 2019 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2020 cp = &sc->pciide_channels[channel]; 2021 if (pciide_chansetup(sc, channel, interface) == 0) 2022 continue; 2023 2024 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2025 printf("%s: %s channel ignored (disabled)\n", 2026 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2027 continue; 2028 } 2029 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2030 pciide_pci_intr); 2031 2032 if (pciide_chan_candisable(cp)) 2033 chanenable &= ~AMD7X6_CHAN_EN(channel); 2034 pciide_map_compat_intr(pa, cp, channel, interface); 2035 if (cp->hw_ok == 0) 2036 continue; 2037 2038 amd7x6_setup_channel(&cp->wdc_channel); 2039 } 2040 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2041 chanenable); 2042 return; 2043 } 2044 2045 void 2046 amd7x6_setup_channel(chp) 2047 struct channel_softc *chp; 2048 { 2049 u_int32_t udmatim_reg, datatim_reg; 2050 u_int8_t idedma_ctl; 2051 int mode, drive; 2052 struct ata_drive_datas *drvp; 2053 struct pciide_channel *cp = (struct pciide_channel*)chp; 2054 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2055 #ifndef PCIIDE_AMD756_ENABLEDMA 2056 int rev = PCI_REVISION( 2057 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2058 #endif 2059 2060 idedma_ctl = 0; 2061 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2062 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2063 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2064 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2065 2066 /* setup DMA if needed */ 2067 pciide_channel_dma_setup(cp); 2068 2069 for (drive = 0; drive < 2; drive++) { 2070 drvp = &chp->ch_drive[drive]; 2071 /* If no drive, skip */ 2072 if ((drvp->drive_flags & DRIVE) == 0) 2073 continue; 2074 /* add timing values, setup DMA if needed */ 2075 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2076 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2077 mode = drvp->PIO_mode; 2078 goto pio; 2079 } 2080 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2081 (drvp->drive_flags & DRIVE_UDMA)) { 2082 /* use Ultra/DMA */ 2083 drvp->drive_flags &= ~DRIVE_DMA; 2084 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2085 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2086 AMD7X6_UDMA_TIME(chp->channel, drive, 2087 amd7x6_udma_tim[drvp->UDMA_mode]); 2088 /* can use PIO timings, MW DMA unused */ 2089 mode = drvp->PIO_mode; 2090 } else { 2091 /* use Multiword DMA, but only if revision is OK */ 2092 drvp->drive_flags &= ~DRIVE_UDMA; 2093 #ifndef PCIIDE_AMD756_ENABLEDMA 2094 /* 2095 * The workaround doesn't seem to be necessary 2096 * with all drives, so it can be disabled by 2097 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2098 * triggered. 2099 */ 2100 if (sc->sc_pp->ide_product == 2101 PCI_PRODUCT_AMD_PBC756_IDE && 2102 AMD756_CHIPREV_DISABLEDMA(rev)) { 2103 printf("%s:%d:%d: multi-word DMA disabled due " 2104 "to chip revision\n", 2105 sc->sc_wdcdev.sc_dev.dv_xname, 2106 chp->channel, drive); 2107 mode = drvp->PIO_mode; 2108 drvp->drive_flags &= ~DRIVE_DMA; 2109 goto pio; 2110 } 2111 #endif 2112 /* mode = min(pio, dma+2) */ 2113 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2114 mode = drvp->PIO_mode; 2115 else 2116 mode = drvp->DMA_mode + 2; 2117 } 2118 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2119 2120 pio: /* setup PIO mode */ 2121 if (mode <= 2) { 2122 drvp->DMA_mode = 0; 2123 drvp->PIO_mode = 0; 2124 mode = 0; 2125 } else { 2126 drvp->PIO_mode = mode; 2127 drvp->DMA_mode = mode - 2; 2128 } 2129 datatim_reg |= 2130 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2131 amd7x6_pio_set[mode]) | 2132 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2133 amd7x6_pio_rec[mode]); 2134 } 2135 if (idedma_ctl != 0) { 2136 /* Add software bits in status register */ 2137 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2138 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2139 idedma_ctl); 2140 } 2141 pciide_print_modes(cp); 2142 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2143 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2144 } 2145 2146 void 2147 apollo_chip_map(sc, pa) 2148 struct pciide_softc *sc; 2149 struct pci_attach_args *pa; 2150 { 2151 struct pciide_channel *cp; 2152 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2153 int channel; 2154 u_int32_t ideconf; 2155 bus_size_t cmdsize, ctlsize; 2156 pcitag_t pcib_tag; 2157 pcireg_t pcib_id, pcib_class; 2158 2159 if (pciide_chipen(sc, pa) == 0) 2160 return; 2161 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2162 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2163 /* and read ID and rev of the ISA bridge */ 2164 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2165 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2166 printf(": VIA Technologies "); 2167 switch (PCI_PRODUCT(pcib_id)) { 2168 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2169 printf("VT82C586 (Apollo VP) "); 2170 if(PCI_REVISION(pcib_class) >= 0x02) { 2171 printf("ATA33 controller\n"); 2172 sc->sc_wdcdev.UDMA_cap = 2; 2173 } else { 2174 printf("controller\n"); 2175 sc->sc_wdcdev.UDMA_cap = 0; 2176 } 2177 break; 2178 case PCI_PRODUCT_VIATECH_VT82C596A: 2179 printf("VT82C596A (Apollo Pro) "); 2180 if (PCI_REVISION(pcib_class) >= 0x12) { 2181 printf("ATA66 controller\n"); 2182 sc->sc_wdcdev.UDMA_cap = 4; 2183 } else { 2184 printf("ATA33 controller\n"); 2185 sc->sc_wdcdev.UDMA_cap = 2; 2186 } 2187 break; 2188 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2189 printf("VT82C686A (Apollo KX133) "); 2190 if (PCI_REVISION(pcib_class) >= 0x40) { 2191 printf("ATA100 controller\n"); 2192 sc->sc_wdcdev.UDMA_cap = 5; 2193 } else { 2194 printf("ATA66 controller\n"); 2195 sc->sc_wdcdev.UDMA_cap = 4; 2196 } 2197 break; 2198 case PCI_PRODUCT_VIATECH_VT8231: 2199 printf("VT8231 ATA100 controller\n"); 2200 sc->sc_wdcdev.UDMA_cap = 5; 2201 break; 2202 case PCI_PRODUCT_VIATECH_VT8233: 2203 printf("VT8233 ATA100 controller\n"); 2204 sc->sc_wdcdev.UDMA_cap = 5; 2205 break; 2206 case PCI_PRODUCT_VIATECH_VT8233A: 2207 printf("VT8233A ATA133 controller\n"); 2208 sc->sc_wdcdev.UDMA_cap = 6; 2209 break; 2210 case PCI_PRODUCT_VIATECH_VT8235: 2211 printf("VT8235 ATA133 controller\n"); 2212 sc->sc_wdcdev.UDMA_cap = 6; 2213 break; 2214 default: 2215 printf("unknown ATA controller\n"); 2216 sc->sc_wdcdev.UDMA_cap = 0; 2217 } 2218 2219 printf("%s: bus-master DMA support present", 2220 sc->sc_wdcdev.sc_dev.dv_xname); 2221 pciide_mapreg_dma(sc, pa); 2222 printf("\n"); 2223 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2224 WDC_CAPABILITY_MODE; 2225 if (sc->sc_dma_ok) { 2226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2227 sc->sc_wdcdev.irqack = pciide_irqack; 2228 if (sc->sc_wdcdev.UDMA_cap > 0) 2229 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2230 } 2231 sc->sc_wdcdev.PIO_cap = 4; 2232 sc->sc_wdcdev.DMA_cap = 2; 2233 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2234 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2235 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2236 2237 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2238 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2239 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2240 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2241 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2242 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2243 DEBUG_PROBE); 2244 2245 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2246 cp = &sc->pciide_channels[channel]; 2247 if (pciide_chansetup(sc, channel, interface) == 0) 2248 continue; 2249 2250 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2251 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2252 printf("%s: %s channel ignored (disabled)\n", 2253 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2254 continue; 2255 } 2256 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2257 pciide_pci_intr); 2258 if (cp->hw_ok == 0) 2259 continue; 2260 if (pciide_chan_candisable(cp)) { 2261 ideconf &= ~APO_IDECONF_EN(channel); 2262 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2263 ideconf); 2264 } 2265 pciide_map_compat_intr(pa, cp, channel, interface); 2266 2267 if (cp->hw_ok == 0) 2268 continue; 2269 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2270 } 2271 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2272 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2273 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2274 } 2275 2276 void 2277 apollo_setup_channel(chp) 2278 struct channel_softc *chp; 2279 { 2280 u_int32_t udmatim_reg, datatim_reg; 2281 u_int8_t idedma_ctl; 2282 int mode, drive; 2283 struct ata_drive_datas *drvp; 2284 struct pciide_channel *cp = (struct pciide_channel*)chp; 2285 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2286 2287 idedma_ctl = 0; 2288 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2289 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2290 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2291 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2292 2293 /* setup DMA if needed */ 2294 pciide_channel_dma_setup(cp); 2295 2296 for (drive = 0; drive < 2; drive++) { 2297 drvp = &chp->ch_drive[drive]; 2298 /* If no drive, skip */ 2299 if ((drvp->drive_flags & DRIVE) == 0) 2300 continue; 2301 /* add timing values, setup DMA if needed */ 2302 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2303 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2304 mode = drvp->PIO_mode; 2305 goto pio; 2306 } 2307 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2308 (drvp->drive_flags & DRIVE_UDMA)) { 2309 /* use Ultra/DMA */ 2310 drvp->drive_flags &= ~DRIVE_DMA; 2311 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2312 APO_UDMA_EN_MTH(chp->channel, drive); 2313 if (sc->sc_wdcdev.UDMA_cap == 6) { 2314 /* 8233a */ 2315 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2316 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2317 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2318 /* 686b */ 2319 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2320 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2321 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2322 /* 596b or 686a */ 2323 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2324 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2325 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2326 } else { 2327 /* 596a or 586b */ 2328 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2329 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2330 } 2331 /* can use PIO timings, MW DMA unused */ 2332 mode = drvp->PIO_mode; 2333 } else { 2334 /* use Multiword DMA */ 2335 drvp->drive_flags &= ~DRIVE_UDMA; 2336 /* mode = min(pio, dma+2) */ 2337 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2338 mode = drvp->PIO_mode; 2339 else 2340 mode = drvp->DMA_mode + 2; 2341 } 2342 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2343 2344 pio: /* setup PIO mode */ 2345 if (mode <= 2) { 2346 drvp->DMA_mode = 0; 2347 drvp->PIO_mode = 0; 2348 mode = 0; 2349 } else { 2350 drvp->PIO_mode = mode; 2351 drvp->DMA_mode = mode - 2; 2352 } 2353 datatim_reg |= 2354 APO_DATATIM_PULSE(chp->channel, drive, 2355 apollo_pio_set[mode]) | 2356 APO_DATATIM_RECOV(chp->channel, drive, 2357 apollo_pio_rec[mode]); 2358 } 2359 if (idedma_ctl != 0) { 2360 /* Add software bits in status register */ 2361 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2362 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2363 idedma_ctl); 2364 } 2365 pciide_print_modes(cp); 2366 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2367 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2368 } 2369 2370 void 2371 cmd_channel_map(pa, sc, channel) 2372 struct pci_attach_args *pa; 2373 struct pciide_softc *sc; 2374 int channel; 2375 { 2376 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2377 bus_size_t cmdsize, ctlsize; 2378 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2379 int interface, one_channel; 2380 2381 /* 2382 * The 0648/0649 can be told to identify as a RAID controller. 2383 * In this case, we have to fake interface 2384 */ 2385 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2386 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2387 PCIIDE_INTERFACE_SETTABLE(1); 2388 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2389 CMD_CONF_DSA1) 2390 interface |= PCIIDE_INTERFACE_PCI(0) | 2391 PCIIDE_INTERFACE_PCI(1); 2392 } else { 2393 interface = PCI_INTERFACE(pa->pa_class); 2394 } 2395 2396 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2397 cp->name = PCIIDE_CHANNEL_NAME(channel); 2398 cp->wdc_channel.channel = channel; 2399 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2400 2401 /* 2402 * Older CMD64X doesn't have independant channels 2403 */ 2404 switch (sc->sc_pp->ide_product) { 2405 case PCI_PRODUCT_CMDTECH_649: 2406 one_channel = 0; 2407 break; 2408 default: 2409 one_channel = 1; 2410 break; 2411 } 2412 2413 if (channel > 0 && one_channel) { 2414 cp->wdc_channel.ch_queue = 2415 sc->pciide_channels[0].wdc_channel.ch_queue; 2416 } else { 2417 cp->wdc_channel.ch_queue = 2418 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2419 } 2420 if (cp->wdc_channel.ch_queue == NULL) { 2421 printf("%s %s channel: " 2422 "can't allocate memory for command queue", 2423 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2424 return; 2425 } 2426 2427 printf("%s: %s channel %s to %s mode\n", 2428 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2429 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2430 "configured" : "wired", 2431 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2432 "native-PCI" : "compatibility"); 2433 2434 /* 2435 * with a CMD PCI64x, if we get here, the first channel is enabled: 2436 * there's no way to disable the first channel without disabling 2437 * the whole device 2438 */ 2439 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2440 printf("%s: %s channel ignored (disabled)\n", 2441 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2442 return; 2443 } 2444 2445 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2446 if (cp->hw_ok == 0) 2447 return; 2448 if (channel == 1) { 2449 if (pciide_chan_candisable(cp)) { 2450 ctrl &= ~CMD_CTRL_2PORT; 2451 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2452 CMD_CTRL, ctrl); 2453 } 2454 } 2455 pciide_map_compat_intr(pa, cp, channel, interface); 2456 } 2457 2458 int 2459 cmd_pci_intr(arg) 2460 void *arg; 2461 { 2462 struct pciide_softc *sc = arg; 2463 struct pciide_channel *cp; 2464 struct channel_softc *wdc_cp; 2465 int i, rv, crv; 2466 u_int32_t priirq, secirq; 2467 2468 rv = 0; 2469 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2470 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2471 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2472 cp = &sc->pciide_channels[i]; 2473 wdc_cp = &cp->wdc_channel; 2474 /* If a compat channel skip. */ 2475 if (cp->compat) 2476 continue; 2477 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2478 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2479 crv = wdcintr(wdc_cp); 2480 if (crv == 0) 2481 printf("%s:%d: bogus intr\n", 2482 sc->sc_wdcdev.sc_dev.dv_xname, i); 2483 else 2484 rv = 1; 2485 } 2486 } 2487 return rv; 2488 } 2489 2490 void 2491 cmd_chip_map(sc, pa) 2492 struct pciide_softc *sc; 2493 struct pci_attach_args *pa; 2494 { 2495 int channel; 2496 2497 /* 2498 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2499 * and base adresses registers can be disabled at 2500 * hardware level. In this case, the device is wired 2501 * in compat mode and its first channel is always enabled, 2502 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2503 * In fact, it seems that the first channel of the CMD PCI0640 2504 * can't be disabled. 2505 */ 2506 2507 #ifdef PCIIDE_CMD064x_DISABLE 2508 if (pciide_chipen(sc, pa) == 0) 2509 return; 2510 #endif 2511 2512 printf("%s: hardware does not support DMA\n", 2513 sc->sc_wdcdev.sc_dev.dv_xname); 2514 sc->sc_dma_ok = 0; 2515 2516 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2517 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2518 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2519 2520 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2521 cmd_channel_map(pa, sc, channel); 2522 } 2523 } 2524 2525 void 2526 cmd0643_9_chip_map(sc, pa) 2527 struct pciide_softc *sc; 2528 struct pci_attach_args *pa; 2529 { 2530 struct pciide_channel *cp; 2531 int channel; 2532 pcireg_t rev = PCI_REVISION(pa->pa_class); 2533 2534 /* 2535 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2536 * and base adresses registers can be disabled at 2537 * hardware level. In this case, the device is wired 2538 * in compat mode and its first channel is always enabled, 2539 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2540 * In fact, it seems that the first channel of the CMD PCI0640 2541 * can't be disabled. 2542 */ 2543 2544 #ifdef PCIIDE_CMD064x_DISABLE 2545 if (pciide_chipen(sc, pa) == 0) 2546 return; 2547 #endif 2548 printf("%s: bus-master DMA support present", 2549 sc->sc_wdcdev.sc_dev.dv_xname); 2550 pciide_mapreg_dma(sc, pa); 2551 printf("\n"); 2552 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2553 WDC_CAPABILITY_MODE; 2554 if (sc->sc_dma_ok) { 2555 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2556 switch (sc->sc_pp->ide_product) { 2557 case PCI_PRODUCT_CMDTECH_649: 2558 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2559 sc->sc_wdcdev.UDMA_cap = 5; 2560 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2561 break; 2562 case PCI_PRODUCT_CMDTECH_648: 2563 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2564 sc->sc_wdcdev.UDMA_cap = 4; 2565 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2566 break; 2567 case PCI_PRODUCT_CMDTECH_646: 2568 if (rev >= CMD0646U2_REV) { 2569 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2570 sc->sc_wdcdev.UDMA_cap = 2; 2571 } else if (rev >= CMD0646U_REV) { 2572 /* 2573 * Linux's driver claims that the 646U is broken 2574 * with UDMA. Only enable it if we know what we're 2575 * doing 2576 */ 2577 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2578 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2579 sc->sc_wdcdev.UDMA_cap = 2; 2580 #endif 2581 /* explicitly disable UDMA */ 2582 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2583 CMD_UDMATIM(0), 0); 2584 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2585 CMD_UDMATIM(1), 0); 2586 } 2587 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2588 break; 2589 default: 2590 sc->sc_wdcdev.irqack = pciide_irqack; 2591 } 2592 } 2593 2594 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2595 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2596 sc->sc_wdcdev.PIO_cap = 4; 2597 sc->sc_wdcdev.DMA_cap = 2; 2598 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2599 2600 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2601 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2602 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2603 DEBUG_PROBE); 2604 2605 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2606 cp = &sc->pciide_channels[channel]; 2607 cmd_channel_map(pa, sc, channel); 2608 if (cp->hw_ok == 0) 2609 continue; 2610 cmd0643_9_setup_channel(&cp->wdc_channel); 2611 } 2612 /* 2613 * note - this also makes sure we clear the irq disable and reset 2614 * bits 2615 */ 2616 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2617 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2618 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2619 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2620 DEBUG_PROBE); 2621 } 2622 2623 void 2624 cmd0643_9_setup_channel(chp) 2625 struct channel_softc *chp; 2626 { 2627 struct ata_drive_datas *drvp; 2628 u_int8_t tim; 2629 u_int32_t idedma_ctl, udma_reg; 2630 int drive; 2631 struct pciide_channel *cp = (struct pciide_channel*)chp; 2632 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2633 2634 idedma_ctl = 0; 2635 /* setup DMA if needed */ 2636 pciide_channel_dma_setup(cp); 2637 2638 for (drive = 0; drive < 2; drive++) { 2639 drvp = &chp->ch_drive[drive]; 2640 /* If no drive, skip */ 2641 if ((drvp->drive_flags & DRIVE) == 0) 2642 continue; 2643 /* add timing values, setup DMA if needed */ 2644 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2645 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2646 if (drvp->drive_flags & DRIVE_UDMA) { 2647 /* UltraDMA on a 646U2, 0648 or 0649 */ 2648 drvp->drive_flags &= ~DRIVE_DMA; 2649 udma_reg = pciide_pci_read(sc->sc_pc, 2650 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2651 if (drvp->UDMA_mode > 2 && 2652 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2653 CMD_BICSR) & 2654 CMD_BICSR_80(chp->channel)) == 0) 2655 drvp->UDMA_mode = 2; 2656 if (drvp->UDMA_mode > 2) 2657 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2658 else if (sc->sc_wdcdev.UDMA_cap > 2) 2659 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2660 udma_reg |= CMD_UDMATIM_UDMA(drive); 2661 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2662 CMD_UDMATIM_TIM_OFF(drive)); 2663 udma_reg |= 2664 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2665 CMD_UDMATIM_TIM_OFF(drive)); 2666 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2667 CMD_UDMATIM(chp->channel), udma_reg); 2668 } else { 2669 /* 2670 * use Multiword DMA. 2671 * Timings will be used for both PIO and DMA, 2672 * so adjust DMA mode if needed 2673 * if we have a 0646U2/8/9, turn off UDMA 2674 */ 2675 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2676 udma_reg = pciide_pci_read(sc->sc_pc, 2677 sc->sc_tag, 2678 CMD_UDMATIM(chp->channel)); 2679 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2680 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2681 CMD_UDMATIM(chp->channel), 2682 udma_reg); 2683 } 2684 if (drvp->PIO_mode >= 3 && 2685 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2686 drvp->DMA_mode = drvp->PIO_mode - 2; 2687 } 2688 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2689 } 2690 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2691 } 2692 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2693 CMD_DATA_TIM(chp->channel, drive), tim); 2694 } 2695 if (idedma_ctl != 0) { 2696 /* Add software bits in status register */ 2697 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2698 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2699 idedma_ctl); 2700 } 2701 pciide_print_modes(cp); 2702 } 2703 2704 void 2705 cmd646_9_irqack(chp) 2706 struct channel_softc *chp; 2707 { 2708 u_int32_t priirq, secirq; 2709 struct pciide_channel *cp = (struct pciide_channel*)chp; 2710 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2711 2712 if (chp->channel == 0) { 2713 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2714 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2715 } else { 2716 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2717 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2718 } 2719 pciide_irqack(chp); 2720 } 2721 2722 void 2723 cy693_chip_map(sc, pa) 2724 struct pciide_softc *sc; 2725 struct pci_attach_args *pa; 2726 { 2727 struct pciide_channel *cp; 2728 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2729 bus_size_t cmdsize, ctlsize; 2730 2731 if (pciide_chipen(sc, pa) == 0) 2732 return; 2733 /* 2734 * this chip has 2 PCI IDE functions, one for primary and one for 2735 * secondary. So we need to call pciide_mapregs_compat() with 2736 * the real channel 2737 */ 2738 if (pa->pa_function == 1) { 2739 sc->sc_cy_compatchan = 0; 2740 } else if (pa->pa_function == 2) { 2741 sc->sc_cy_compatchan = 1; 2742 } else { 2743 printf("%s: unexpected PCI function %d\n", 2744 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2745 return; 2746 } 2747 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2748 printf("%s: bus-master DMA support present", 2749 sc->sc_wdcdev.sc_dev.dv_xname); 2750 pciide_mapreg_dma(sc, pa); 2751 } else { 2752 printf("%s: hardware does not support DMA", 2753 sc->sc_wdcdev.sc_dev.dv_xname); 2754 sc->sc_dma_ok = 0; 2755 } 2756 printf("\n"); 2757 2758 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2759 if (sc->sc_cy_handle == NULL) { 2760 printf("%s: unable to map hyperCache control registers\n", 2761 sc->sc_wdcdev.sc_dev.dv_xname); 2762 sc->sc_dma_ok = 0; 2763 } 2764 2765 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2766 WDC_CAPABILITY_MODE; 2767 if (sc->sc_dma_ok) { 2768 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2769 sc->sc_wdcdev.irqack = pciide_irqack; 2770 } 2771 sc->sc_wdcdev.PIO_cap = 4; 2772 sc->sc_wdcdev.DMA_cap = 2; 2773 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2774 2775 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2776 sc->sc_wdcdev.nchannels = 1; 2777 2778 /* Only one channel for this chip; if we are here it's enabled */ 2779 cp = &sc->pciide_channels[0]; 2780 sc->wdc_chanarray[0] = &cp->wdc_channel; 2781 cp->name = PCIIDE_CHANNEL_NAME(0); 2782 cp->wdc_channel.channel = 0; 2783 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2784 cp->wdc_channel.ch_queue = 2785 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2786 if (cp->wdc_channel.ch_queue == NULL) { 2787 printf("%s primary channel: " 2788 "can't allocate memory for command queue", 2789 sc->sc_wdcdev.sc_dev.dv_xname); 2790 return; 2791 } 2792 printf("%s: primary channel %s to ", 2793 sc->sc_wdcdev.sc_dev.dv_xname, 2794 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2795 "configured" : "wired"); 2796 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2797 printf("native-PCI"); 2798 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2799 pciide_pci_intr); 2800 } else { 2801 printf("compatibility"); 2802 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2803 &cmdsize, &ctlsize); 2804 } 2805 printf(" mode\n"); 2806 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2807 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2808 wdcattach(&cp->wdc_channel); 2809 if (pciide_chan_candisable(cp)) { 2810 pci_conf_write(sc->sc_pc, sc->sc_tag, 2811 PCI_COMMAND_STATUS_REG, 0); 2812 } 2813 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2814 if (cp->hw_ok == 0) 2815 return; 2816 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2817 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2818 cy693_setup_channel(&cp->wdc_channel); 2819 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2820 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2821 } 2822 2823 void 2824 cy693_setup_channel(chp) 2825 struct channel_softc *chp; 2826 { 2827 struct ata_drive_datas *drvp; 2828 int drive; 2829 u_int32_t cy_cmd_ctrl; 2830 u_int32_t idedma_ctl; 2831 struct pciide_channel *cp = (struct pciide_channel*)chp; 2832 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2833 int dma_mode = -1; 2834 2835 cy_cmd_ctrl = idedma_ctl = 0; 2836 2837 /* setup DMA if needed */ 2838 pciide_channel_dma_setup(cp); 2839 2840 for (drive = 0; drive < 2; drive++) { 2841 drvp = &chp->ch_drive[drive]; 2842 /* If no drive, skip */ 2843 if ((drvp->drive_flags & DRIVE) == 0) 2844 continue; 2845 /* add timing values, setup DMA if needed */ 2846 if (drvp->drive_flags & DRIVE_DMA) { 2847 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2848 /* use Multiword DMA */ 2849 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2850 dma_mode = drvp->DMA_mode; 2851 } 2852 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2853 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2854 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2855 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2856 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2857 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2858 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2859 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2860 } 2861 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2862 chp->ch_drive[0].DMA_mode = dma_mode; 2863 chp->ch_drive[1].DMA_mode = dma_mode; 2864 2865 if (dma_mode == -1) 2866 dma_mode = 0; 2867 2868 if (sc->sc_cy_handle != NULL) { 2869 /* Note: `multiple' is implied. */ 2870 cy82c693_write(sc->sc_cy_handle, 2871 (sc->sc_cy_compatchan == 0) ? 2872 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2873 } 2874 2875 pciide_print_modes(cp); 2876 2877 if (idedma_ctl != 0) { 2878 /* Add software bits in status register */ 2879 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2880 IDEDMA_CTL, idedma_ctl); 2881 } 2882 } 2883 2884 static struct sis_hostbr_type { 2885 u_int16_t id; 2886 u_int8_t rev; 2887 u_int8_t udma_mode; 2888 char *name; 2889 u_int8_t type; 2890 #define SIS_TYPE_NOUDMA 0 2891 #define SIS_TYPE_66 1 2892 #define SIS_TYPE_100OLD 2 2893 #define SIS_TYPE_100NEW 3 2894 #define SIS_TYPE_133OLD 4 2895 #define SIS_TYPE_133NEW 5 2896 #define SIS_TYPE_SOUTH 6 2897 } sis_hostbr_type[] = { 2898 /* Most infos here are from sos (at) freebsd.org */ 2899 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 2900 #if 0 2901 /* 2902 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2903 * have problems with UDMA (info provided by Christos) 2904 */ 2905 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 2906 #endif 2907 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 2908 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 2909 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 2910 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 2911 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 2912 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 2913 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 2914 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 2915 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 2916 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 2917 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 2918 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 2919 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 2920 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 2921 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 2922 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 2923 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 2924 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 2925 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 2926 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 2927 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 2928 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 2929 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 2930 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 2931 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 2932 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 2933 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 2934 /* 2935 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 2936 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 2937 */ 2938 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 2939 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 2940 }; 2941 2942 static struct sis_hostbr_type *sis_hostbr_type_match; 2943 2944 static int 2945 sis_hostbr_match(pa) 2946 struct pci_attach_args *pa; 2947 { 2948 int i; 2949 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 2950 return 0; 2951 sis_hostbr_type_match = NULL; 2952 for (i = 0; 2953 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 2954 i++) { 2955 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 2956 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 2957 sis_hostbr_type_match = &sis_hostbr_type[i]; 2958 } 2959 return (sis_hostbr_type_match != NULL); 2960 } 2961 2962 static int sis_south_match(pa) 2963 struct pci_attach_args *pa; 2964 { 2965 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 2966 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 2967 PCI_REVISION(pa->pa_class) >= 0x10); 2968 } 2969 2970 void 2971 sis_chip_map(sc, pa) 2972 struct pciide_softc *sc; 2973 struct pci_attach_args *pa; 2974 { 2975 struct pciide_channel *cp; 2976 int channel; 2977 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2978 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2979 pcireg_t rev = PCI_REVISION(pa->pa_class); 2980 bus_size_t cmdsize, ctlsize; 2981 2982 if (pciide_chipen(sc, pa) == 0) 2983 return; 2984 printf(": Silicon Integrated System "); 2985 pci_find_device(NULL, sis_hostbr_match); 2986 if (sis_hostbr_type_match) { 2987 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 2988 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 2989 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2990 SIS_REG_57) & 0x7f); 2991 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 2992 PCI_ID_REG)) == SIS_PRODUCT_5518) { 2993 printf("96X UDMA%d", 2994 sis_hostbr_type_match->udma_mode); 2995 sc->sis_type = SIS_TYPE_133NEW; 2996 sc->sc_wdcdev.UDMA_cap = 2997 sis_hostbr_type_match->udma_mode; 2998 } else { 2999 if (pci_find_device(NULL, sis_south_match)) { 3000 sc->sis_type = SIS_TYPE_133OLD; 3001 sc->sc_wdcdev.UDMA_cap = 3002 sis_hostbr_type_match->udma_mode; 3003 } else { 3004 sc->sis_type = SIS_TYPE_100NEW; 3005 sc->sc_wdcdev.UDMA_cap = 3006 sis_hostbr_type_match->udma_mode; 3007 } 3008 } 3009 } else { 3010 sc->sis_type = sis_hostbr_type_match->type; 3011 sc->sc_wdcdev.UDMA_cap = 3012 sis_hostbr_type_match->udma_mode; 3013 } 3014 printf(sis_hostbr_type_match->name); 3015 } else { 3016 printf("5597/5598"); 3017 if (rev >= 0xd0) { 3018 sc->sc_wdcdev.UDMA_cap = 2; 3019 sc->sis_type = SIS_TYPE_66; 3020 } else { 3021 sc->sc_wdcdev.UDMA_cap = 0; 3022 sc->sis_type = SIS_TYPE_NOUDMA; 3023 } 3024 } 3025 printf(" IDE controller (rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 3026 printf("%s: bus-master DMA support present", 3027 sc->sc_wdcdev.sc_dev.dv_xname); 3028 pciide_mapreg_dma(sc, pa); 3029 printf("\n"); 3030 3031 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3032 WDC_CAPABILITY_MODE; 3033 if (sc->sc_dma_ok) { 3034 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3035 sc->sc_wdcdev.irqack = pciide_irqack; 3036 if (sc->sis_type >= SIS_TYPE_66) 3037 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3038 } 3039 3040 sc->sc_wdcdev.PIO_cap = 4; 3041 sc->sc_wdcdev.DMA_cap = 2; 3042 3043 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3044 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3045 switch(sc->sis_type) { 3046 case SIS_TYPE_NOUDMA: 3047 case SIS_TYPE_66: 3048 case SIS_TYPE_100OLD: 3049 sc->sc_wdcdev.set_modes = sis_setup_channel; 3050 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3051 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3052 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3053 break; 3054 case SIS_TYPE_100NEW: 3055 case SIS_TYPE_133OLD: 3056 sc->sc_wdcdev.set_modes = sis_setup_channel; 3057 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3058 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3059 break; 3060 case SIS_TYPE_133NEW: 3061 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3062 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3063 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3064 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3065 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3066 break; 3067 } 3068 3069 3070 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3071 cp = &sc->pciide_channels[channel]; 3072 if (pciide_chansetup(sc, channel, interface) == 0) 3073 continue; 3074 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3075 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3076 printf("%s: %s channel ignored (disabled)\n", 3077 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3078 continue; 3079 } 3080 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3081 pciide_pci_intr); 3082 if (cp->hw_ok == 0) 3083 continue; 3084 if (pciide_chan_candisable(cp)) { 3085 if (channel == 0) 3086 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3087 else 3088 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3089 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3090 sis_ctr0); 3091 } 3092 pciide_map_compat_intr(pa, cp, channel, interface); 3093 if (cp->hw_ok == 0) 3094 continue; 3095 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3096 } 3097 } 3098 3099 void 3100 sis96x_setup_channel(chp) 3101 struct channel_softc *chp; 3102 { 3103 struct ata_drive_datas *drvp; 3104 int drive; 3105 u_int32_t sis_tim; 3106 u_int32_t idedma_ctl; 3107 int regtim; 3108 struct pciide_channel *cp = (struct pciide_channel*)chp; 3109 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3110 3111 sis_tim = 0; 3112 idedma_ctl = 0; 3113 /* setup DMA if needed */ 3114 pciide_channel_dma_setup(cp); 3115 3116 for (drive = 0; drive < 2; drive++) { 3117 regtim = SIS_TIM133( 3118 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3119 chp->channel, drive); 3120 drvp = &chp->ch_drive[drive]; 3121 /* If no drive, skip */ 3122 if ((drvp->drive_flags & DRIVE) == 0) 3123 continue; 3124 /* add timing values, setup DMA if needed */ 3125 if (drvp->drive_flags & DRIVE_UDMA) { 3126 /* use Ultra/DMA */ 3127 drvp->drive_flags &= ~DRIVE_DMA; 3128 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3129 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3130 if (drvp->UDMA_mode > 2) 3131 drvp->UDMA_mode = 2; 3132 } 3133 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3134 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3135 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3136 } else if (drvp->drive_flags & DRIVE_DMA) { 3137 /* 3138 * use Multiword DMA 3139 * Timings will be used for both PIO and DMA, 3140 * so adjust DMA mode if needed 3141 */ 3142 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3143 drvp->PIO_mode = drvp->DMA_mode + 2; 3144 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3145 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3146 drvp->PIO_mode - 2 : 0; 3147 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3148 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3149 } else { 3150 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3151 } 3152 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3153 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3154 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3155 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3156 } 3157 if (idedma_ctl != 0) { 3158 /* Add software bits in status register */ 3159 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3160 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3161 idedma_ctl); 3162 } 3163 pciide_print_modes(cp); 3164 } 3165 3166 void 3167 sis_setup_channel(chp) 3168 struct channel_softc *chp; 3169 { 3170 struct ata_drive_datas *drvp; 3171 int drive; 3172 u_int32_t sis_tim; 3173 u_int32_t idedma_ctl; 3174 struct pciide_channel *cp = (struct pciide_channel*)chp; 3175 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3176 3177 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3178 "channel %d 0x%x\n", chp->channel, 3179 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3180 DEBUG_PROBE); 3181 sis_tim = 0; 3182 idedma_ctl = 0; 3183 /* setup DMA if needed */ 3184 pciide_channel_dma_setup(cp); 3185 3186 for (drive = 0; drive < 2; drive++) { 3187 drvp = &chp->ch_drive[drive]; 3188 /* If no drive, skip */ 3189 if ((drvp->drive_flags & DRIVE) == 0) 3190 continue; 3191 /* add timing values, setup DMA if needed */ 3192 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3193 (drvp->drive_flags & DRIVE_UDMA) == 0) 3194 goto pio; 3195 3196 if (drvp->drive_flags & DRIVE_UDMA) { 3197 /* use Ultra/DMA */ 3198 drvp->drive_flags &= ~DRIVE_DMA; 3199 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3200 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3201 if (drvp->UDMA_mode > 2) 3202 drvp->UDMA_mode = 2; 3203 } 3204 switch (sc->sis_type) { 3205 case SIS_TYPE_66: 3206 case SIS_TYPE_100OLD: 3207 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3208 SIS_TIM66_UDMA_TIME_OFF(drive); 3209 break; 3210 case SIS_TYPE_100NEW: 3211 sis_tim |= 3212 sis_udma100new_tim[drvp->UDMA_mode] << 3213 SIS_TIM100_UDMA_TIME_OFF(drive); 3214 case SIS_TYPE_133OLD: 3215 sis_tim |= 3216 sis_udma133old_tim[drvp->UDMA_mode] << 3217 SIS_TIM100_UDMA_TIME_OFF(drive); 3218 break; 3219 default: 3220 printf("unknown SiS IDE type %d\n", 3221 sc->sis_type); 3222 } 3223 } else { 3224 /* 3225 * use Multiword DMA 3226 * Timings will be used for both PIO and DMA, 3227 * so adjust DMA mode if needed 3228 */ 3229 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3230 drvp->PIO_mode = drvp->DMA_mode + 2; 3231 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3232 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3233 drvp->PIO_mode - 2 : 0; 3234 if (drvp->DMA_mode == 0) 3235 drvp->PIO_mode = 0; 3236 } 3237 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3238 pio: switch (sc->sis_type) { 3239 case SIS_TYPE_NOUDMA: 3240 case SIS_TYPE_66: 3241 case SIS_TYPE_100OLD: 3242 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3243 SIS_TIM66_ACT_OFF(drive); 3244 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3245 SIS_TIM66_REC_OFF(drive); 3246 break; 3247 case SIS_TYPE_100NEW: 3248 case SIS_TYPE_133OLD: 3249 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3250 SIS_TIM100_ACT_OFF(drive); 3251 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3252 SIS_TIM100_REC_OFF(drive); 3253 break; 3254 default: 3255 printf("unknown SiS IDE type %d\n", 3256 sc->sis_type); 3257 } 3258 } 3259 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3260 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3261 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3262 if (idedma_ctl != 0) { 3263 /* Add software bits in status register */ 3264 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3265 IDEDMA_CTL, idedma_ctl); 3266 } 3267 pciide_print_modes(cp); 3268 } 3269 3270 void 3271 acer_chip_map(sc, pa) 3272 struct pciide_softc *sc; 3273 struct pci_attach_args *pa; 3274 { 3275 struct pciide_channel *cp; 3276 int channel; 3277 pcireg_t cr, interface; 3278 bus_size_t cmdsize, ctlsize; 3279 pcireg_t rev = PCI_REVISION(pa->pa_class); 3280 3281 if (pciide_chipen(sc, pa) == 0) 3282 return; 3283 printf("%s: bus-master DMA support present", 3284 sc->sc_wdcdev.sc_dev.dv_xname); 3285 pciide_mapreg_dma(sc, pa); 3286 printf("\n"); 3287 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3288 WDC_CAPABILITY_MODE; 3289 if (sc->sc_dma_ok) { 3290 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3291 if (rev >= 0x20) { 3292 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3293 if (rev >= 0xC4) 3294 sc->sc_wdcdev.UDMA_cap = 5; 3295 else if (rev >= 0xC2) 3296 sc->sc_wdcdev.UDMA_cap = 4; 3297 else 3298 sc->sc_wdcdev.UDMA_cap = 2; 3299 } 3300 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3301 sc->sc_wdcdev.irqack = pciide_irqack; 3302 } 3303 3304 sc->sc_wdcdev.PIO_cap = 4; 3305 sc->sc_wdcdev.DMA_cap = 2; 3306 sc->sc_wdcdev.set_modes = acer_setup_channel; 3307 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3308 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3309 3310 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3311 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3312 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3313 3314 /* Enable "microsoft register bits" R/W. */ 3315 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3316 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3317 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3318 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3319 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3320 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3321 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3322 ~ACER_CHANSTATUSREGS_RO); 3323 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3324 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3325 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3326 /* Don't use cr, re-read the real register content instead */ 3327 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3328 PCI_CLASS_REG)); 3329 3330 /* From linux: enable "Cable Detection" */ 3331 if (rev >= 0xC2) { 3332 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3333 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3334 | ACER_0x4B_CDETECT); 3335 } 3336 3337 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3338 cp = &sc->pciide_channels[channel]; 3339 if (pciide_chansetup(sc, channel, interface) == 0) 3340 continue; 3341 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3342 printf("%s: %s channel ignored (disabled)\n", 3343 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3344 continue; 3345 } 3346 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3347 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3348 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3349 if (cp->hw_ok == 0) 3350 continue; 3351 if (pciide_chan_candisable(cp)) { 3352 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3353 pci_conf_write(sc->sc_pc, sc->sc_tag, 3354 PCI_CLASS_REG, cr); 3355 } 3356 pciide_map_compat_intr(pa, cp, channel, interface); 3357 acer_setup_channel(&cp->wdc_channel); 3358 } 3359 } 3360 3361 void 3362 acer_setup_channel(chp) 3363 struct channel_softc *chp; 3364 { 3365 struct ata_drive_datas *drvp; 3366 int drive; 3367 u_int32_t acer_fifo_udma; 3368 u_int32_t idedma_ctl; 3369 struct pciide_channel *cp = (struct pciide_channel*)chp; 3370 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3371 3372 idedma_ctl = 0; 3373 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3374 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3375 acer_fifo_udma), DEBUG_PROBE); 3376 /* setup DMA if needed */ 3377 pciide_channel_dma_setup(cp); 3378 3379 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3380 DRIVE_UDMA) { /* check 80 pins cable */ 3381 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3382 ACER_0x4A_80PIN(chp->channel)) { 3383 if (chp->ch_drive[0].UDMA_mode > 2) 3384 chp->ch_drive[0].UDMA_mode = 2; 3385 if (chp->ch_drive[1].UDMA_mode > 2) 3386 chp->ch_drive[1].UDMA_mode = 2; 3387 } 3388 } 3389 3390 for (drive = 0; drive < 2; drive++) { 3391 drvp = &chp->ch_drive[drive]; 3392 /* If no drive, skip */ 3393 if ((drvp->drive_flags & DRIVE) == 0) 3394 continue; 3395 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3396 "channel %d drive %d 0x%x\n", chp->channel, drive, 3397 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3398 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3399 /* clear FIFO/DMA mode */ 3400 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3401 ACER_UDMA_EN(chp->channel, drive) | 3402 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3403 3404 /* add timing values, setup DMA if needed */ 3405 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3406 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3407 acer_fifo_udma |= 3408 ACER_FTH_OPL(chp->channel, drive, 0x1); 3409 goto pio; 3410 } 3411 3412 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3413 if (drvp->drive_flags & DRIVE_UDMA) { 3414 /* use Ultra/DMA */ 3415 drvp->drive_flags &= ~DRIVE_DMA; 3416 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3417 acer_fifo_udma |= 3418 ACER_UDMA_TIM(chp->channel, drive, 3419 acer_udma[drvp->UDMA_mode]); 3420 /* XXX disable if one drive < UDMA3 ? */ 3421 if (drvp->UDMA_mode >= 3) { 3422 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3423 ACER_0x4B, 3424 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3425 ACER_0x4B) | ACER_0x4B_UDMA66); 3426 } 3427 } else { 3428 /* 3429 * use Multiword DMA 3430 * Timings will be used for both PIO and DMA, 3431 * so adjust DMA mode if needed 3432 */ 3433 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3434 drvp->PIO_mode = drvp->DMA_mode + 2; 3435 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3436 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3437 drvp->PIO_mode - 2 : 0; 3438 if (drvp->DMA_mode == 0) 3439 drvp->PIO_mode = 0; 3440 } 3441 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3442 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3443 ACER_IDETIM(chp->channel, drive), 3444 acer_pio[drvp->PIO_mode]); 3445 } 3446 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3447 acer_fifo_udma), DEBUG_PROBE); 3448 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3449 if (idedma_ctl != 0) { 3450 /* Add software bits in status register */ 3451 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3452 IDEDMA_CTL, idedma_ctl); 3453 } 3454 pciide_print_modes(cp); 3455 } 3456 3457 int 3458 acer_pci_intr(arg) 3459 void *arg; 3460 { 3461 struct pciide_softc *sc = arg; 3462 struct pciide_channel *cp; 3463 struct channel_softc *wdc_cp; 3464 int i, rv, crv; 3465 u_int32_t chids; 3466 3467 rv = 0; 3468 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3469 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3470 cp = &sc->pciide_channels[i]; 3471 wdc_cp = &cp->wdc_channel; 3472 /* If a compat channel skip. */ 3473 if (cp->compat) 3474 continue; 3475 if (chids & ACER_CHIDS_INT(i)) { 3476 crv = wdcintr(wdc_cp); 3477 if (crv == 0) 3478 printf("%s:%d: bogus intr\n", 3479 sc->sc_wdcdev.sc_dev.dv_xname, i); 3480 else 3481 rv = 1; 3482 } 3483 } 3484 return rv; 3485 } 3486 3487 void 3488 hpt_chip_map(sc, pa) 3489 struct pciide_softc *sc; 3490 struct pci_attach_args *pa; 3491 { 3492 struct pciide_channel *cp; 3493 int i, compatchan, revision; 3494 pcireg_t interface; 3495 bus_size_t cmdsize, ctlsize; 3496 3497 if (pciide_chipen(sc, pa) == 0) 3498 return; 3499 revision = PCI_REVISION(pa->pa_class); 3500 printf(": Triones/Highpoint "); 3501 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3502 printf("HPT374 IDE Controller\n"); 3503 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3504 printf("HPT372 IDE Controller\n"); 3505 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3506 if (revision == HPT372_REV) 3507 printf("HPT372 IDE Controller\n"); 3508 else if (revision == HPT370_REV) 3509 printf("HPT370 IDE Controller\n"); 3510 else if (revision == HPT370A_REV) 3511 printf("HPT370A IDE Controller\n"); 3512 else if (revision == HPT366_REV) 3513 printf("HPT366 IDE Controller\n"); 3514 else 3515 printf("unknown HPT IDE controller rev %d\n", revision); 3516 } else 3517 printf("unknown HPT IDE controller 0x%x\n", 3518 sc->sc_pp->ide_product); 3519 3520 /* 3521 * when the chip is in native mode it identifies itself as a 3522 * 'misc mass storage'. Fake interface in this case. 3523 */ 3524 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3525 interface = PCI_INTERFACE(pa->pa_class); 3526 } else { 3527 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3528 PCIIDE_INTERFACE_PCI(0); 3529 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3530 (revision == HPT370_REV || revision == HPT370A_REV || 3531 revision == HPT372_REV)) || 3532 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3533 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3534 interface |= PCIIDE_INTERFACE_PCI(1); 3535 } 3536 3537 printf("%s: bus-master DMA support present", 3538 sc->sc_wdcdev.sc_dev.dv_xname); 3539 pciide_mapreg_dma(sc, pa); 3540 printf("\n"); 3541 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3542 WDC_CAPABILITY_MODE; 3543 if (sc->sc_dma_ok) { 3544 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3545 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3546 sc->sc_wdcdev.irqack = pciide_irqack; 3547 } 3548 sc->sc_wdcdev.PIO_cap = 4; 3549 sc->sc_wdcdev.DMA_cap = 2; 3550 3551 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3552 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3553 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3554 revision == HPT366_REV) { 3555 sc->sc_wdcdev.UDMA_cap = 4; 3556 /* 3557 * The 366 has 2 PCI IDE functions, one for primary and one 3558 * for secondary. So we need to call pciide_mapregs_compat() 3559 * with the real channel 3560 */ 3561 if (pa->pa_function == 0) { 3562 compatchan = 0; 3563 } else if (pa->pa_function == 1) { 3564 compatchan = 1; 3565 } else { 3566 printf("%s: unexpected PCI function %d\n", 3567 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3568 return; 3569 } 3570 sc->sc_wdcdev.nchannels = 1; 3571 } else { 3572 sc->sc_wdcdev.nchannels = 2; 3573 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3574 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3575 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3576 revision == HPT372_REV)) 3577 sc->sc_wdcdev.UDMA_cap = 6; 3578 else 3579 sc->sc_wdcdev.UDMA_cap = 5; 3580 } 3581 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3582 cp = &sc->pciide_channels[i]; 3583 if (sc->sc_wdcdev.nchannels > 1) { 3584 compatchan = i; 3585 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3586 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3587 printf("%s: %s channel ignored (disabled)\n", 3588 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3589 continue; 3590 } 3591 } 3592 if (pciide_chansetup(sc, i, interface) == 0) 3593 continue; 3594 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3595 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3596 &ctlsize, hpt_pci_intr); 3597 } else { 3598 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3599 &cmdsize, &ctlsize); 3600 } 3601 if (cp->hw_ok == 0) 3602 return; 3603 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3604 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3605 wdcattach(&cp->wdc_channel); 3606 hpt_setup_channel(&cp->wdc_channel); 3607 } 3608 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3609 (revision == HPT370_REV || revision == HPT370A_REV || 3610 revision == HPT372_REV)) || 3611 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3612 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3613 /* 3614 * HPT370_REV and highter has a bit to disable interrupts, 3615 * make sure to clear it 3616 */ 3617 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3618 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3619 ~HPT_CSEL_IRQDIS); 3620 } 3621 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 3622 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3623 revision == HPT372_REV ) || 3624 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3625 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3626 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3627 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3628 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3629 return; 3630 } 3631 3632 void 3633 hpt_setup_channel(chp) 3634 struct channel_softc *chp; 3635 { 3636 struct ata_drive_datas *drvp; 3637 int drive; 3638 int cable; 3639 u_int32_t before, after; 3640 u_int32_t idedma_ctl; 3641 struct pciide_channel *cp = (struct pciide_channel*)chp; 3642 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3643 int revision = 3644 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 3645 3646 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3647 3648 /* setup DMA if needed */ 3649 pciide_channel_dma_setup(cp); 3650 3651 idedma_ctl = 0; 3652 3653 /* Per drive settings */ 3654 for (drive = 0; drive < 2; drive++) { 3655 drvp = &chp->ch_drive[drive]; 3656 /* If no drive, skip */ 3657 if ((drvp->drive_flags & DRIVE) == 0) 3658 continue; 3659 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3660 HPT_IDETIM(chp->channel, drive)); 3661 3662 /* add timing values, setup DMA if needed */ 3663 if (drvp->drive_flags & DRIVE_UDMA) { 3664 /* use Ultra/DMA */ 3665 drvp->drive_flags &= ~DRIVE_DMA; 3666 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3667 drvp->UDMA_mode > 2) 3668 drvp->UDMA_mode = 2; 3669 switch (sc->sc_pp->ide_product) { 3670 case PCI_PRODUCT_TRIONES_HPT374: 3671 after = hpt374_udma[drvp->UDMA_mode]; 3672 break; 3673 case PCI_PRODUCT_TRIONES_HPT372: 3674 after = hpt372_udma[drvp->UDMA_mode]; 3675 break; 3676 case PCI_PRODUCT_TRIONES_HPT366: 3677 default: 3678 switch(revision) { 3679 case HPT372_REV: 3680 after = hpt372_udma[drvp->UDMA_mode]; 3681 break; 3682 case HPT370_REV: 3683 case HPT370A_REV: 3684 after = hpt370_udma[drvp->UDMA_mode]; 3685 break; 3686 case HPT366_REV: 3687 default: 3688 after = hpt366_udma[drvp->UDMA_mode]; 3689 break; 3690 } 3691 } 3692 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3693 } else if (drvp->drive_flags & DRIVE_DMA) { 3694 /* 3695 * use Multiword DMA. 3696 * Timings will be used for both PIO and DMA, so adjust 3697 * DMA mode if needed 3698 */ 3699 if (drvp->PIO_mode >= 3 && 3700 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3701 drvp->DMA_mode = drvp->PIO_mode - 2; 3702 } 3703 switch (sc->sc_pp->ide_product) { 3704 case PCI_PRODUCT_TRIONES_HPT374: 3705 after = hpt374_dma[drvp->DMA_mode]; 3706 break; 3707 case PCI_PRODUCT_TRIONES_HPT372: 3708 after = hpt372_dma[drvp->DMA_mode]; 3709 break; 3710 case PCI_PRODUCT_TRIONES_HPT366: 3711 default: 3712 switch(revision) { 3713 case HPT372_REV: 3714 after = hpt372_dma[drvp->DMA_mode]; 3715 break; 3716 case HPT370_REV: 3717 case HPT370A_REV: 3718 after = hpt370_dma[drvp->DMA_mode]; 3719 break; 3720 case HPT366_REV: 3721 default: 3722 after = hpt366_dma[drvp->DMA_mode]; 3723 break; 3724 } 3725 } 3726 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3727 } else { 3728 /* PIO only */ 3729 switch (sc->sc_pp->ide_product) { 3730 case PCI_PRODUCT_TRIONES_HPT374: 3731 after = hpt374_pio[drvp->PIO_mode]; 3732 break; 3733 case PCI_PRODUCT_TRIONES_HPT372: 3734 after = hpt372_pio[drvp->PIO_mode]; 3735 break; 3736 case PCI_PRODUCT_TRIONES_HPT366: 3737 default: 3738 switch(revision) { 3739 case HPT372_REV: 3740 after = hpt372_pio[drvp->PIO_mode]; 3741 break; 3742 case HPT370_REV: 3743 case HPT370A_REV: 3744 after = hpt370_pio[drvp->PIO_mode]; 3745 break; 3746 case HPT366_REV: 3747 default: 3748 after = hpt366_pio[drvp->PIO_mode]; 3749 break; 3750 } 3751 } 3752 } 3753 pci_conf_write(sc->sc_pc, sc->sc_tag, 3754 HPT_IDETIM(chp->channel, drive), after); 3755 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3756 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3757 after, before), DEBUG_PROBE); 3758 } 3759 if (idedma_ctl != 0) { 3760 /* Add software bits in status register */ 3761 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3762 IDEDMA_CTL, idedma_ctl); 3763 } 3764 pciide_print_modes(cp); 3765 } 3766 3767 int 3768 hpt_pci_intr(arg) 3769 void *arg; 3770 { 3771 struct pciide_softc *sc = arg; 3772 struct pciide_channel *cp; 3773 struct channel_softc *wdc_cp; 3774 int rv = 0; 3775 int dmastat, i, crv; 3776 3777 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3778 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3779 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3780 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3781 IDEDMA_CTL_INTR) 3782 continue; 3783 cp = &sc->pciide_channels[i]; 3784 wdc_cp = &cp->wdc_channel; 3785 crv = wdcintr(wdc_cp); 3786 if (crv == 0) { 3787 printf("%s:%d: bogus intr\n", 3788 sc->sc_wdcdev.sc_dev.dv_xname, i); 3789 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3790 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3791 } else 3792 rv = 1; 3793 } 3794 return rv; 3795 } 3796 3797 3798 /* Macros to test product */ 3799 #define PDC_IS_262(sc) \ 3800 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3801 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3802 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3803 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3804 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3805 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3806 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3807 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3808 #define PDC_IS_265(sc) \ 3809 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3810 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3811 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3812 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3813 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3814 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3815 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3816 #define PDC_IS_268(sc) \ 3817 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3818 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3819 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3820 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3821 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3822 #define PDC_IS_276(sc) \ 3823 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3824 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3825 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3826 3827 void 3828 pdc202xx_chip_map(sc, pa) 3829 struct pciide_softc *sc; 3830 struct pci_attach_args *pa; 3831 { 3832 struct pciide_channel *cp; 3833 int channel; 3834 pcireg_t interface, st, mode; 3835 bus_size_t cmdsize, ctlsize; 3836 3837 if (!PDC_IS_268(sc)) { 3838 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3839 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3840 st), DEBUG_PROBE); 3841 } 3842 if (pciide_chipen(sc, pa) == 0) 3843 return; 3844 3845 /* turn off RAID mode */ 3846 if (!PDC_IS_268(sc)) 3847 st &= ~PDC2xx_STATE_IDERAID; 3848 3849 /* 3850 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3851 * mode. We have to fake interface 3852 */ 3853 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3854 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3855 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3856 3857 printf("%s: bus-master DMA support present", 3858 sc->sc_wdcdev.sc_dev.dv_xname); 3859 pciide_mapreg_dma(sc, pa); 3860 printf("\n"); 3861 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3862 WDC_CAPABILITY_MODE; 3863 if (sc->sc_dma_ok) { 3864 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3865 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3866 sc->sc_wdcdev.irqack = pciide_irqack; 3867 } 3868 sc->sc_wdcdev.PIO_cap = 4; 3869 sc->sc_wdcdev.DMA_cap = 2; 3870 if (PDC_IS_276(sc)) 3871 sc->sc_wdcdev.UDMA_cap = 6; 3872 else if (PDC_IS_265(sc)) 3873 sc->sc_wdcdev.UDMA_cap = 5; 3874 else if (PDC_IS_262(sc)) 3875 sc->sc_wdcdev.UDMA_cap = 4; 3876 else 3877 sc->sc_wdcdev.UDMA_cap = 2; 3878 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3879 pdc20268_setup_channel : pdc202xx_setup_channel; 3880 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3881 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3882 3883 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 3884 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 3885 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 3886 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 3887 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 3888 } 3889 3890 if (!PDC_IS_268(sc)) { 3891 /* setup failsafe defaults */ 3892 mode = 0; 3893 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3894 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3895 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3896 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3897 for (channel = 0; 3898 channel < sc->sc_wdcdev.nchannels; 3899 channel++) { 3900 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3901 "drive 0 initial timings 0x%x, now 0x%x\n", 3902 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3903 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3904 DEBUG_PROBE); 3905 pci_conf_write(sc->sc_pc, sc->sc_tag, 3906 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3907 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3908 "drive 1 initial timings 0x%x, now 0x%x\n", 3909 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3910 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3911 pci_conf_write(sc->sc_pc, sc->sc_tag, 3912 PDC2xx_TIM(channel, 1), mode); 3913 } 3914 3915 mode = PDC2xx_SCR_DMA; 3916 if (PDC_IS_262(sc)) { 3917 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3918 } else { 3919 /* the BIOS set it up this way */ 3920 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3921 } 3922 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3923 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3924 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3925 "now 0x%x\n", 3926 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3927 PDC2xx_SCR), 3928 mode), DEBUG_PROBE); 3929 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3930 PDC2xx_SCR, mode); 3931 3932 /* controller initial state register is OK even without BIOS */ 3933 /* Set DMA mode to IDE DMA compatibility */ 3934 mode = 3935 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3936 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3937 DEBUG_PROBE); 3938 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3939 mode | 0x1); 3940 mode = 3941 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3942 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3943 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3944 mode | 0x1); 3945 } 3946 3947 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3948 cp = &sc->pciide_channels[channel]; 3949 if (pciide_chansetup(sc, channel, interface) == 0) 3950 continue; 3951 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3952 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3953 printf("%s: %s channel ignored (disabled)\n", 3954 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3955 continue; 3956 } 3957 if (PDC_IS_265(sc)) 3958 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3959 pdc20265_pci_intr); 3960 else 3961 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3962 pdc202xx_pci_intr); 3963 if (cp->hw_ok == 0) 3964 continue; 3965 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3966 st &= ~(PDC_IS_262(sc) ? 3967 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3968 pciide_map_compat_intr(pa, cp, channel, interface); 3969 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3970 } 3971 if (!PDC_IS_268(sc)) { 3972 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3973 "0x%x\n", st), DEBUG_PROBE); 3974 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3975 } 3976 return; 3977 } 3978 3979 void 3980 pdc202xx_setup_channel(chp) 3981 struct channel_softc *chp; 3982 { 3983 struct ata_drive_datas *drvp; 3984 int drive; 3985 pcireg_t mode, st; 3986 u_int32_t idedma_ctl, scr, atapi; 3987 struct pciide_channel *cp = (struct pciide_channel*)chp; 3988 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3989 int channel = chp->channel; 3990 3991 /* setup DMA if needed */ 3992 pciide_channel_dma_setup(cp); 3993 3994 idedma_ctl = 0; 3995 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3996 sc->sc_wdcdev.sc_dev.dv_xname, 3997 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3998 DEBUG_PROBE); 3999 4000 /* Per channel settings */ 4001 if (PDC_IS_262(sc)) { 4002 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4003 PDC262_U66); 4004 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4005 /* Trim UDMA mode */ 4006 if ((st & PDC262_STATE_80P(channel)) != 0 || 4007 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4008 chp->ch_drive[0].UDMA_mode <= 2) || 4009 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4010 chp->ch_drive[1].UDMA_mode <= 2)) { 4011 if (chp->ch_drive[0].UDMA_mode > 2) 4012 chp->ch_drive[0].UDMA_mode = 2; 4013 if (chp->ch_drive[1].UDMA_mode > 2) 4014 chp->ch_drive[1].UDMA_mode = 2; 4015 } 4016 /* Set U66 if needed */ 4017 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4018 chp->ch_drive[0].UDMA_mode > 2) || 4019 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4020 chp->ch_drive[1].UDMA_mode > 2)) 4021 scr |= PDC262_U66_EN(channel); 4022 else 4023 scr &= ~PDC262_U66_EN(channel); 4024 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4025 PDC262_U66, scr); 4026 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4027 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4028 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4029 PDC262_ATAPI(channel))), DEBUG_PROBE); 4030 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4031 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4032 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4033 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4034 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4035 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4036 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4037 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4038 atapi = 0; 4039 else 4040 atapi = PDC262_ATAPI_UDMA; 4041 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4042 PDC262_ATAPI(channel), atapi); 4043 } 4044 } 4045 for (drive = 0; drive < 2; drive++) { 4046 drvp = &chp->ch_drive[drive]; 4047 /* If no drive, skip */ 4048 if ((drvp->drive_flags & DRIVE) == 0) 4049 continue; 4050 mode = 0; 4051 if (drvp->drive_flags & DRIVE_UDMA) { 4052 /* use Ultra/DMA */ 4053 drvp->drive_flags &= ~DRIVE_DMA; 4054 mode = PDC2xx_TIM_SET_MB(mode, 4055 pdc2xx_udma_mb[drvp->UDMA_mode]); 4056 mode = PDC2xx_TIM_SET_MC(mode, 4057 pdc2xx_udma_mc[drvp->UDMA_mode]); 4058 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4059 } else if (drvp->drive_flags & DRIVE_DMA) { 4060 mode = PDC2xx_TIM_SET_MB(mode, 4061 pdc2xx_dma_mb[drvp->DMA_mode]); 4062 mode = PDC2xx_TIM_SET_MC(mode, 4063 pdc2xx_dma_mc[drvp->DMA_mode]); 4064 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4065 } else { 4066 mode = PDC2xx_TIM_SET_MB(mode, 4067 pdc2xx_dma_mb[0]); 4068 mode = PDC2xx_TIM_SET_MC(mode, 4069 pdc2xx_dma_mc[0]); 4070 } 4071 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4072 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4073 if (drvp->drive_flags & DRIVE_ATA) 4074 mode |= PDC2xx_TIM_PRE; 4075 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4076 if (drvp->PIO_mode >= 3) { 4077 mode |= PDC2xx_TIM_IORDY; 4078 if (drive == 0) 4079 mode |= PDC2xx_TIM_IORDYp; 4080 } 4081 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4082 "timings 0x%x\n", 4083 sc->sc_wdcdev.sc_dev.dv_xname, 4084 chp->channel, drive, mode), DEBUG_PROBE); 4085 pci_conf_write(sc->sc_pc, sc->sc_tag, 4086 PDC2xx_TIM(chp->channel, drive), mode); 4087 } 4088 if (idedma_ctl != 0) { 4089 /* Add software bits in status register */ 4090 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4091 IDEDMA_CTL, idedma_ctl); 4092 } 4093 pciide_print_modes(cp); 4094 } 4095 4096 void 4097 pdc20268_setup_channel(chp) 4098 struct channel_softc *chp; 4099 { 4100 struct ata_drive_datas *drvp; 4101 int drive; 4102 u_int32_t idedma_ctl; 4103 struct pciide_channel *cp = (struct pciide_channel*)chp; 4104 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4105 int u100; 4106 4107 /* setup DMA if needed */ 4108 pciide_channel_dma_setup(cp); 4109 4110 idedma_ctl = 0; 4111 4112 /* I don't know what this is for, FreeBSD does it ... */ 4113 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4114 IDEDMA_CMD + 0x1, 0x0b); 4115 4116 /* 4117 * I don't know what this is for; FreeBSD checks this ... this is not 4118 * cable type detect. 4119 */ 4120 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4121 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 4122 4123 for (drive = 0; drive < 2; drive++) { 4124 drvp = &chp->ch_drive[drive]; 4125 /* If no drive, skip */ 4126 if ((drvp->drive_flags & DRIVE) == 0) 4127 continue; 4128 if (drvp->drive_flags & DRIVE_UDMA) { 4129 /* use Ultra/DMA */ 4130 drvp->drive_flags &= ~DRIVE_DMA; 4131 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4132 if (drvp->UDMA_mode > 2 && u100 == 0) 4133 drvp->UDMA_mode = 2; 4134 } else if (drvp->drive_flags & DRIVE_DMA) { 4135 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4136 } 4137 } 4138 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4139 if (idedma_ctl != 0) { 4140 /* Add software bits in status register */ 4141 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4142 IDEDMA_CTL, idedma_ctl); 4143 } 4144 pciide_print_modes(cp); 4145 } 4146 4147 int 4148 pdc202xx_pci_intr(arg) 4149 void *arg; 4150 { 4151 struct pciide_softc *sc = arg; 4152 struct pciide_channel *cp; 4153 struct channel_softc *wdc_cp; 4154 int i, rv, crv; 4155 u_int32_t scr; 4156 4157 rv = 0; 4158 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4159 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4160 cp = &sc->pciide_channels[i]; 4161 wdc_cp = &cp->wdc_channel; 4162 /* If a compat channel skip. */ 4163 if (cp->compat) 4164 continue; 4165 if (scr & PDC2xx_SCR_INT(i)) { 4166 crv = wdcintr(wdc_cp); 4167 if (crv == 0) 4168 printf("%s:%d: bogus intr (reg 0x%x)\n", 4169 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4170 else 4171 rv = 1; 4172 } 4173 } 4174 return rv; 4175 } 4176 4177 int 4178 pdc20265_pci_intr(arg) 4179 void *arg; 4180 { 4181 struct pciide_softc *sc = arg; 4182 struct pciide_channel *cp; 4183 struct channel_softc *wdc_cp; 4184 int i, rv, crv; 4185 u_int32_t dmastat; 4186 4187 rv = 0; 4188 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4189 cp = &sc->pciide_channels[i]; 4190 wdc_cp = &cp->wdc_channel; 4191 /* If a compat channel skip. */ 4192 if (cp->compat) 4193 continue; 4194 /* 4195 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4196 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4197 * So use it instead (requires 2 reg reads instead of 1, 4198 * but we can't do it another way). 4199 */ 4200 dmastat = bus_space_read_1(sc->sc_dma_iot, 4201 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4202 if((dmastat & IDEDMA_CTL_INTR) == 0) 4203 continue; 4204 crv = wdcintr(wdc_cp); 4205 if (crv == 0) 4206 printf("%s:%d: bogus intr\n", 4207 sc->sc_wdcdev.sc_dev.dv_xname, i); 4208 else 4209 rv = 1; 4210 } 4211 return rv; 4212 } 4213 4214 static void 4215 pdc20262_dma_start(v, channel, drive) 4216 void *v; 4217 int channel, drive; 4218 { 4219 struct pciide_softc *sc = v; 4220 struct pciide_dma_maps *dma_maps = 4221 &sc->pciide_channels[channel].dma_maps[drive]; 4222 int atapi; 4223 4224 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 4225 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 4226 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 4227 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 4228 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4229 PDC262_ATAPI(channel), atapi); 4230 } 4231 4232 pciide_dma_start(v, channel, drive); 4233 } 4234 4235 int 4236 pdc20262_dma_finish(v, channel, drive, force) 4237 void *v; 4238 int channel, drive; 4239 int force; 4240 { 4241 struct pciide_softc *sc = v; 4242 struct pciide_dma_maps *dma_maps = 4243 &sc->pciide_channels[channel].dma_maps[drive]; 4244 struct channel_softc *chp; 4245 int atapi, error; 4246 4247 error = pciide_dma_finish(v, channel, drive, force); 4248 4249 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 4250 chp = sc->wdc_chanarray[channel]; 4251 atapi = 0; 4252 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4253 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4254 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4255 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 4256 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 4257 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 4258 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4259 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4260 atapi = PDC262_ATAPI_UDMA; 4261 } 4262 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4263 PDC262_ATAPI(channel), atapi); 4264 } 4265 4266 return error; 4267 } 4268 4269 void 4270 opti_chip_map(sc, pa) 4271 struct pciide_softc *sc; 4272 struct pci_attach_args *pa; 4273 { 4274 struct pciide_channel *cp; 4275 bus_size_t cmdsize, ctlsize; 4276 pcireg_t interface; 4277 u_int8_t init_ctrl; 4278 int channel; 4279 4280 if (pciide_chipen(sc, pa) == 0) 4281 return; 4282 printf("%s: bus-master DMA support present", 4283 sc->sc_wdcdev.sc_dev.dv_xname); 4284 4285 /* 4286 * XXXSCW: 4287 * There seem to be a couple of buggy revisions/implementations 4288 * of the OPTi pciide chipset. This kludge seems to fix one of 4289 * the reported problems (PR/11644) but still fails for the 4290 * other (PR/13151), although the latter may be due to other 4291 * issues too... 4292 */ 4293 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4294 printf(" but disabled due to chip rev. <= 0x12"); 4295 sc->sc_dma_ok = 0; 4296 } else 4297 pciide_mapreg_dma(sc, pa); 4298 4299 printf("\n"); 4300 4301 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4302 WDC_CAPABILITY_MODE; 4303 sc->sc_wdcdev.PIO_cap = 4; 4304 if (sc->sc_dma_ok) { 4305 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4306 sc->sc_wdcdev.irqack = pciide_irqack; 4307 sc->sc_wdcdev.DMA_cap = 2; 4308 } 4309 sc->sc_wdcdev.set_modes = opti_setup_channel; 4310 4311 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4312 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4313 4314 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4315 OPTI_REG_INIT_CONTROL); 4316 4317 interface = PCI_INTERFACE(pa->pa_class); 4318 4319 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4320 cp = &sc->pciide_channels[channel]; 4321 if (pciide_chansetup(sc, channel, interface) == 0) 4322 continue; 4323 if (channel == 1 && 4324 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4325 printf("%s: %s channel ignored (disabled)\n", 4326 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4327 continue; 4328 } 4329 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4330 pciide_pci_intr); 4331 if (cp->hw_ok == 0) 4332 continue; 4333 pciide_map_compat_intr(pa, cp, channel, interface); 4334 if (cp->hw_ok == 0) 4335 continue; 4336 opti_setup_channel(&cp->wdc_channel); 4337 } 4338 } 4339 4340 void 4341 opti_setup_channel(chp) 4342 struct channel_softc *chp; 4343 { 4344 struct ata_drive_datas *drvp; 4345 struct pciide_channel *cp = (struct pciide_channel*)chp; 4346 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4347 int drive, spd; 4348 int mode[2]; 4349 u_int8_t rv, mr; 4350 4351 /* 4352 * The `Delay' and `Address Setup Time' fields of the 4353 * Miscellaneous Register are always zero initially. 4354 */ 4355 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4356 mr &= ~(OPTI_MISC_DELAY_MASK | 4357 OPTI_MISC_ADDR_SETUP_MASK | 4358 OPTI_MISC_INDEX_MASK); 4359 4360 /* Prime the control register before setting timing values */ 4361 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4362 4363 /* Determine the clockrate of the PCIbus the chip is attached to */ 4364 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4365 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4366 4367 /* setup DMA if needed */ 4368 pciide_channel_dma_setup(cp); 4369 4370 for (drive = 0; drive < 2; drive++) { 4371 drvp = &chp->ch_drive[drive]; 4372 /* If no drive, skip */ 4373 if ((drvp->drive_flags & DRIVE) == 0) { 4374 mode[drive] = -1; 4375 continue; 4376 } 4377 4378 if ((drvp->drive_flags & DRIVE_DMA)) { 4379 /* 4380 * Timings will be used for both PIO and DMA, 4381 * so adjust DMA mode if needed 4382 */ 4383 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4384 drvp->PIO_mode = drvp->DMA_mode + 2; 4385 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4386 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4387 drvp->PIO_mode - 2 : 0; 4388 if (drvp->DMA_mode == 0) 4389 drvp->PIO_mode = 0; 4390 4391 mode[drive] = drvp->DMA_mode + 5; 4392 } else 4393 mode[drive] = drvp->PIO_mode; 4394 4395 if (drive && mode[0] >= 0 && 4396 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4397 /* 4398 * Can't have two drives using different values 4399 * for `Address Setup Time'. 4400 * Slow down the faster drive to compensate. 4401 */ 4402 int d = (opti_tim_as[spd][mode[0]] > 4403 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4404 4405 mode[d] = mode[1-d]; 4406 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4407 chp->ch_drive[d].DMA_mode = 0; 4408 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4409 } 4410 } 4411 4412 for (drive = 0; drive < 2; drive++) { 4413 int m; 4414 if ((m = mode[drive]) < 0) 4415 continue; 4416 4417 /* Set the Address Setup Time and select appropriate index */ 4418 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4419 rv |= OPTI_MISC_INDEX(drive); 4420 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4421 4422 /* Set the pulse width and recovery timing parameters */ 4423 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4424 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4425 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4426 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4427 4428 /* Set the Enhanced Mode register appropriately */ 4429 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4430 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4431 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4432 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4433 } 4434 4435 /* Finally, enable the timings */ 4436 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4437 4438 pciide_print_modes(cp); 4439 } 4440 4441 #define ACARD_IS_850(sc) \ 4442 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4443 4444 void 4445 acard_chip_map(sc, pa) 4446 struct pciide_softc *sc; 4447 struct pci_attach_args *pa; 4448 { 4449 struct pciide_channel *cp; 4450 int i; 4451 pcireg_t interface; 4452 bus_size_t cmdsize, ctlsize; 4453 4454 if (pciide_chipen(sc, pa) == 0) 4455 return; 4456 4457 /* 4458 * when the chip is in native mode it identifies itself as a 4459 * 'misc mass storage'. Fake interface in this case. 4460 */ 4461 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4462 interface = PCI_INTERFACE(pa->pa_class); 4463 } else { 4464 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4465 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4466 } 4467 4468 printf("%s: bus-master DMA support present", 4469 sc->sc_wdcdev.sc_dev.dv_xname); 4470 pciide_mapreg_dma(sc, pa); 4471 printf("\n"); 4472 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4473 WDC_CAPABILITY_MODE; 4474 4475 if (sc->sc_dma_ok) { 4476 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4477 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4478 sc->sc_wdcdev.irqack = pciide_irqack; 4479 } 4480 sc->sc_wdcdev.PIO_cap = 4; 4481 sc->sc_wdcdev.DMA_cap = 2; 4482 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4483 4484 sc->sc_wdcdev.set_modes = acard_setup_channel; 4485 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4486 sc->sc_wdcdev.nchannels = 2; 4487 4488 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4489 cp = &sc->pciide_channels[i]; 4490 if (pciide_chansetup(sc, i, interface) == 0) 4491 continue; 4492 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4493 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4494 &ctlsize, pciide_pci_intr); 4495 } else { 4496 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4497 &cmdsize, &ctlsize); 4498 } 4499 if (cp->hw_ok == 0) 4500 return; 4501 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4502 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4503 wdcattach(&cp->wdc_channel); 4504 acard_setup_channel(&cp->wdc_channel); 4505 } 4506 if (!ACARD_IS_850(sc)) { 4507 u_int32_t reg; 4508 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4509 reg &= ~ATP860_CTRL_INT; 4510 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4511 } 4512 } 4513 4514 void 4515 acard_setup_channel(chp) 4516 struct channel_softc *chp; 4517 { 4518 struct ata_drive_datas *drvp; 4519 struct pciide_channel *cp = (struct pciide_channel*)chp; 4520 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4521 int channel = chp->channel; 4522 int drive; 4523 u_int32_t idetime, udma_mode; 4524 u_int32_t idedma_ctl; 4525 4526 /* setup DMA if needed */ 4527 pciide_channel_dma_setup(cp); 4528 4529 if (ACARD_IS_850(sc)) { 4530 idetime = 0; 4531 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4532 udma_mode &= ~ATP850_UDMA_MASK(channel); 4533 } else { 4534 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4535 idetime &= ~ATP860_SETTIME_MASK(channel); 4536 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4537 udma_mode &= ~ATP860_UDMA_MASK(channel); 4538 4539 /* check 80 pins cable */ 4540 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4541 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4542 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4543 & ATP860_CTRL_80P(chp->channel)) { 4544 if (chp->ch_drive[0].UDMA_mode > 2) 4545 chp->ch_drive[0].UDMA_mode = 2; 4546 if (chp->ch_drive[1].UDMA_mode > 2) 4547 chp->ch_drive[1].UDMA_mode = 2; 4548 } 4549 } 4550 } 4551 4552 idedma_ctl = 0; 4553 4554 /* Per drive settings */ 4555 for (drive = 0; drive < 2; drive++) { 4556 drvp = &chp->ch_drive[drive]; 4557 /* If no drive, skip */ 4558 if ((drvp->drive_flags & DRIVE) == 0) 4559 continue; 4560 /* add timing values, setup DMA if needed */ 4561 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4562 (drvp->drive_flags & DRIVE_UDMA)) { 4563 /* use Ultra/DMA */ 4564 if (ACARD_IS_850(sc)) { 4565 idetime |= ATP850_SETTIME(drive, 4566 acard_act_udma[drvp->UDMA_mode], 4567 acard_rec_udma[drvp->UDMA_mode]); 4568 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4569 acard_udma_conf[drvp->UDMA_mode]); 4570 } else { 4571 idetime |= ATP860_SETTIME(channel, drive, 4572 acard_act_udma[drvp->UDMA_mode], 4573 acard_rec_udma[drvp->UDMA_mode]); 4574 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4575 acard_udma_conf[drvp->UDMA_mode]); 4576 } 4577 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4578 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4579 (drvp->drive_flags & DRIVE_DMA)) { 4580 /* use Multiword DMA */ 4581 drvp->drive_flags &= ~DRIVE_UDMA; 4582 if (ACARD_IS_850(sc)) { 4583 idetime |= ATP850_SETTIME(drive, 4584 acard_act_dma[drvp->DMA_mode], 4585 acard_rec_dma[drvp->DMA_mode]); 4586 } else { 4587 idetime |= ATP860_SETTIME(channel, drive, 4588 acard_act_dma[drvp->DMA_mode], 4589 acard_rec_dma[drvp->DMA_mode]); 4590 } 4591 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4592 } else { 4593 /* PIO only */ 4594 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4595 if (ACARD_IS_850(sc)) { 4596 idetime |= ATP850_SETTIME(drive, 4597 acard_act_pio[drvp->PIO_mode], 4598 acard_rec_pio[drvp->PIO_mode]); 4599 } else { 4600 idetime |= ATP860_SETTIME(channel, drive, 4601 acard_act_pio[drvp->PIO_mode], 4602 acard_rec_pio[drvp->PIO_mode]); 4603 } 4604 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4605 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4606 | ATP8x0_CTRL_EN(channel)); 4607 } 4608 } 4609 4610 if (idedma_ctl != 0) { 4611 /* Add software bits in status register */ 4612 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4613 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4614 } 4615 pciide_print_modes(cp); 4616 4617 if (ACARD_IS_850(sc)) { 4618 pci_conf_write(sc->sc_pc, sc->sc_tag, 4619 ATP850_IDETIME(channel), idetime); 4620 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4621 } else { 4622 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4623 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4624 } 4625 } 4626 4627 int 4628 acard_pci_intr(arg) 4629 void *arg; 4630 { 4631 struct pciide_softc *sc = arg; 4632 struct pciide_channel *cp; 4633 struct channel_softc *wdc_cp; 4634 int rv = 0; 4635 int dmastat, i, crv; 4636 4637 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4638 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4639 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4640 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4641 continue; 4642 cp = &sc->pciide_channels[i]; 4643 wdc_cp = &cp->wdc_channel; 4644 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4645 (void)wdcintr(wdc_cp); 4646 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4647 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4648 continue; 4649 } 4650 crv = wdcintr(wdc_cp); 4651 if (crv == 0) 4652 printf("%s:%d: bogus intr\n", 4653 sc->sc_wdcdev.sc_dev.dv_xname, i); 4654 else if (crv == 1) 4655 rv = 1; 4656 else if (rv == 0) 4657 rv = crv; 4658 } 4659 return rv; 4660 } 4661 4662 static int 4663 sl82c105_bugchk(struct pci_attach_args *pa) 4664 { 4665 4666 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4667 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4668 return (0); 4669 4670 if (PCI_REVISION(pa->pa_class) <= 0x05) 4671 return (1); 4672 4673 return (0); 4674 } 4675 4676 void 4677 sl82c105_chip_map(sc, pa) 4678 struct pciide_softc *sc; 4679 struct pci_attach_args *pa; 4680 { 4681 struct pciide_channel *cp; 4682 bus_size_t cmdsize, ctlsize; 4683 pcireg_t interface, idecr; 4684 int channel; 4685 4686 if (pciide_chipen(sc, pa) == 0) 4687 return; 4688 4689 printf("%s: bus-master DMA support present", 4690 sc->sc_wdcdev.sc_dev.dv_xname); 4691 4692 /* 4693 * Check to see if we're part of the Winbond 83c553 Southbridge. 4694 * If so, we need to disable DMA on rev. <= 5 of that chip. 4695 */ 4696 if (pci_find_device(pa, sl82c105_bugchk)) { 4697 printf(" but disabled due to 83c553 rev. <= 0x05"); 4698 sc->sc_dma_ok = 0; 4699 } else 4700 pciide_mapreg_dma(sc, pa); 4701 printf("\n"); 4702 4703 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4704 WDC_CAPABILITY_MODE; 4705 sc->sc_wdcdev.PIO_cap = 4; 4706 if (sc->sc_dma_ok) { 4707 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4708 sc->sc_wdcdev.irqack = pciide_irqack; 4709 sc->sc_wdcdev.DMA_cap = 2; 4710 } 4711 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4712 4713 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4714 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4715 4716 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4717 4718 interface = PCI_INTERFACE(pa->pa_class); 4719 4720 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4721 cp = &sc->pciide_channels[channel]; 4722 if (pciide_chansetup(sc, channel, interface) == 0) 4723 continue; 4724 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4725 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4726 printf("%s: %s channel ignored (disabled)\n", 4727 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4728 continue; 4729 } 4730 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4731 pciide_pci_intr); 4732 if (cp->hw_ok == 0) 4733 continue; 4734 pciide_map_compat_intr(pa, cp, channel, interface); 4735 if (cp->hw_ok == 0) 4736 continue; 4737 sl82c105_setup_channel(&cp->wdc_channel); 4738 } 4739 } 4740 4741 void 4742 sl82c105_setup_channel(chp) 4743 struct channel_softc *chp; 4744 { 4745 struct ata_drive_datas *drvp; 4746 struct pciide_channel *cp = (struct pciide_channel*)chp; 4747 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4748 int pxdx_reg, drive; 4749 pcireg_t pxdx; 4750 4751 /* Set up DMA if needed. */ 4752 pciide_channel_dma_setup(cp); 4753 4754 for (drive = 0; drive < 2; drive++) { 4755 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4756 : SYMPH_P1D0CR) + (drive * 4); 4757 4758 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4759 4760 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4761 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4762 4763 drvp = &chp->ch_drive[drive]; 4764 /* If no drive, skip. */ 4765 if ((drvp->drive_flags & DRIVE) == 0) { 4766 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4767 continue; 4768 } 4769 4770 if (drvp->drive_flags & DRIVE_DMA) { 4771 /* 4772 * Timings will be used for both PIO and DMA, 4773 * so adjust DMA mode if needed. 4774 */ 4775 if (drvp->PIO_mode >= 3) { 4776 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4777 drvp->DMA_mode = drvp->PIO_mode - 2; 4778 if (drvp->DMA_mode < 1) { 4779 /* 4780 * Can't mix both PIO and DMA. 4781 * Disable DMA. 4782 */ 4783 drvp->drive_flags &= ~DRIVE_DMA; 4784 } 4785 } else { 4786 /* 4787 * Can't mix both PIO and DMA. Disable 4788 * DMA. 4789 */ 4790 drvp->drive_flags &= ~DRIVE_DMA; 4791 } 4792 } 4793 4794 if (drvp->drive_flags & DRIVE_DMA) { 4795 /* Use multi-word DMA. */ 4796 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4797 PxDx_CMD_ON_SHIFT; 4798 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4799 } else { 4800 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4801 PxDx_CMD_ON_SHIFT; 4802 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4803 } 4804 4805 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4806 4807 /* ...and set the mode for this drive. */ 4808 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4809 } 4810 4811 pciide_print_modes(cp); 4812 } 4813 4814 void 4815 serverworks_chip_map(sc, pa) 4816 struct pciide_softc *sc; 4817 struct pci_attach_args *pa; 4818 { 4819 struct pciide_channel *cp; 4820 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4821 pcitag_t pcib_tag; 4822 int channel; 4823 bus_size_t cmdsize, ctlsize; 4824 4825 if (pciide_chipen(sc, pa) == 0) 4826 return; 4827 4828 printf("%s: bus-master DMA support present", 4829 sc->sc_wdcdev.sc_dev.dv_xname); 4830 pciide_mapreg_dma(sc, pa); 4831 printf("\n"); 4832 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4833 WDC_CAPABILITY_MODE; 4834 4835 if (sc->sc_dma_ok) { 4836 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4837 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4838 sc->sc_wdcdev.irqack = pciide_irqack; 4839 } 4840 sc->sc_wdcdev.PIO_cap = 4; 4841 sc->sc_wdcdev.DMA_cap = 2; 4842 switch (sc->sc_pp->ide_product) { 4843 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4844 sc->sc_wdcdev.UDMA_cap = 2; 4845 break; 4846 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4847 if (PCI_REVISION(pa->pa_class) < 0x92) 4848 sc->sc_wdcdev.UDMA_cap = 4; 4849 else 4850 sc->sc_wdcdev.UDMA_cap = 5; 4851 break; 4852 } 4853 4854 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4855 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4856 sc->sc_wdcdev.nchannels = 2; 4857 4858 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4859 cp = &sc->pciide_channels[channel]; 4860 if (pciide_chansetup(sc, channel, interface) == 0) 4861 continue; 4862 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4863 serverworks_pci_intr); 4864 if (cp->hw_ok == 0) 4865 return; 4866 pciide_map_compat_intr(pa, cp, channel, interface); 4867 if (cp->hw_ok == 0) 4868 return; 4869 serverworks_setup_channel(&cp->wdc_channel); 4870 } 4871 4872 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4873 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4874 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4875 } 4876 4877 void 4878 serverworks_setup_channel(chp) 4879 struct channel_softc *chp; 4880 { 4881 struct ata_drive_datas *drvp; 4882 struct pciide_channel *cp = (struct pciide_channel*)chp; 4883 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4884 int channel = chp->channel; 4885 int drive, unit; 4886 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4887 u_int32_t idedma_ctl; 4888 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4889 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4890 4891 /* setup DMA if needed */ 4892 pciide_channel_dma_setup(cp); 4893 4894 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4895 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4896 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4897 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4898 4899 pio_time &= ~(0xffff << (16 * channel)); 4900 dma_time &= ~(0xffff << (16 * channel)); 4901 pio_mode &= ~(0xff << (8 * channel + 16)); 4902 udma_mode &= ~(0xff << (8 * channel + 16)); 4903 udma_mode &= ~(3 << (2 * channel)); 4904 4905 idedma_ctl = 0; 4906 4907 /* Per drive settings */ 4908 for (drive = 0; drive < 2; drive++) { 4909 drvp = &chp->ch_drive[drive]; 4910 /* If no drive, skip */ 4911 if ((drvp->drive_flags & DRIVE) == 0) 4912 continue; 4913 unit = drive + 2 * channel; 4914 /* add timing values, setup DMA if needed */ 4915 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4916 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4917 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4918 (drvp->drive_flags & DRIVE_UDMA)) { 4919 /* use Ultra/DMA, check for 80-pin cable */ 4920 if (drvp->UDMA_mode > 2 && 4921 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4922 drvp->UDMA_mode = 2; 4923 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4924 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4925 udma_mode |= 1 << unit; 4926 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4927 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4928 (drvp->drive_flags & DRIVE_DMA)) { 4929 /* use Multiword DMA */ 4930 drvp->drive_flags &= ~DRIVE_UDMA; 4931 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4932 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4933 } else { 4934 /* PIO only */ 4935 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4936 } 4937 } 4938 4939 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4940 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4941 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4942 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4943 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4944 4945 if (idedma_ctl != 0) { 4946 /* Add software bits in status register */ 4947 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4948 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4949 } 4950 pciide_print_modes(cp); 4951 } 4952 4953 int 4954 serverworks_pci_intr(arg) 4955 void *arg; 4956 { 4957 struct pciide_softc *sc = arg; 4958 struct pciide_channel *cp; 4959 struct channel_softc *wdc_cp; 4960 int rv = 0; 4961 int dmastat, i, crv; 4962 4963 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4964 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4965 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4966 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4967 IDEDMA_CTL_INTR) 4968 continue; 4969 cp = &sc->pciide_channels[i]; 4970 wdc_cp = &cp->wdc_channel; 4971 crv = wdcintr(wdc_cp); 4972 if (crv == 0) { 4973 printf("%s:%d: bogus intr\n", 4974 sc->sc_wdcdev.sc_dev.dv_xname, i); 4975 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4976 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4977 } else 4978 rv = 1; 4979 } 4980 return rv; 4981 } 4982
Indexes created Thu Oct 02 14:10:14 GMT 2025