pciide.c revision 1.153.2.3
1 /* $NetBSD: pciide.c,v 1.153.2.3 2002/06/10 17:08:01 tv Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.153.2.3 2002/06/10 17:08:01 tv Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 192 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void pdc202xx_setup_channel __P((struct channel_softc*)); 194 void pdc20268_setup_channel __P((struct channel_softc*)); 195 int pdc202xx_pci_intr __P((void *)); 196 int pdc20265_pci_intr __P((void *)); 197 198 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void opti_setup_channel __P((struct channel_softc*)); 200 201 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 202 void hpt_setup_channel __P((struct channel_softc*)); 203 int hpt_pci_intr __P((void *)); 204 205 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void acard_setup_channel __P((struct channel_softc*)); 207 int acard_pci_intr __P((void *)); 208 209 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void serverworks_setup_channel __P((struct channel_softc*)); 211 int serverworks_pci_intr __P((void *)); 212 213 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void sl82c105_setup_channel __P((struct channel_softc*)); 215 216 void pciide_channel_dma_setup __P((struct pciide_channel *)); 217 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 218 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 219 void pciide_dma_start __P((void*, int, int)); 220 int pciide_dma_finish __P((void*, int, int, int)); 221 void pciide_irqack __P((struct channel_softc *)); 222 void pciide_print_modes __P((struct pciide_channel *)); 223 224 struct pciide_product_desc { 225 u_int32_t ide_product; 226 int ide_flags; 227 const char *ide_name; 228 /* map and setup chip, probe drives */ 229 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 230 }; 231 232 /* Flags for ide_flags */ 233 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 234 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 235 236 /* Default product description for devices not known from this controller */ 237 const struct pciide_product_desc default_product_desc = { 238 0, 239 0, 240 "Generic PCI IDE controller", 241 default_chip_map, 242 }; 243 244 const struct pciide_product_desc pciide_intel_products[] = { 245 { PCI_PRODUCT_INTEL_82092AA, 246 0, 247 "Intel 82092AA IDE controller", 248 default_chip_map, 249 }, 250 { PCI_PRODUCT_INTEL_82371FB_IDE, 251 0, 252 "Intel 82371FB IDE controller (PIIX)", 253 piix_chip_map, 254 }, 255 { PCI_PRODUCT_INTEL_82371SB_IDE, 256 0, 257 "Intel 82371SB IDE Interface (PIIX3)", 258 piix_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371AB_IDE, 261 0, 262 "Intel 82371AB IDE controller (PIIX4)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82440MX_IDE, 266 0, 267 "Intel 82440MX IDE controller", 268 piix_chip_map 269 }, 270 { PCI_PRODUCT_INTEL_82801AA_IDE, 271 0, 272 "Intel 82801AA IDE Controller (ICH)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82801AB_IDE, 276 0, 277 "Intel 82801AB IDE Controller (ICH0)", 278 piix_chip_map, 279 }, 280 { PCI_PRODUCT_INTEL_82801BA_IDE, 281 0, 282 "Intel 82801BA IDE Controller (ICH2)", 283 piix_chip_map, 284 }, 285 { PCI_PRODUCT_INTEL_82801BAM_IDE, 286 0, 287 "Intel 82801BAM IDE Controller (ICH2)", 288 piix_chip_map, 289 }, 290 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 291 0, 292 "Intel 82201CA IDE Controller", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 296 0, 297 "Intel 82201CA IDE Controller", 298 piix_chip_map, 299 }, 300 { 0, 301 0, 302 NULL, 303 NULL 304 } 305 }; 306 307 const struct pciide_product_desc pciide_amd_products[] = { 308 { PCI_PRODUCT_AMD_PBC756_IDE, 309 0, 310 "Advanced Micro Devices AMD756 IDE Controller", 311 amd7x6_chip_map 312 }, 313 { PCI_PRODUCT_AMD_PBC766_IDE, 314 0, 315 "Advanced Micro Devices AMD766 IDE Controller", 316 amd7x6_chip_map 317 }, 318 { PCI_PRODUCT_AMD_PBC768_IDE, 319 0, 320 "Advanced Micro Devices AMD768 IDE Controller", 321 amd7x6_chip_map 322 }, 323 { 0, 324 0, 325 NULL, 326 NULL 327 } 328 }; 329 330 const struct pciide_product_desc pciide_cmd_products[] = { 331 { PCI_PRODUCT_CMDTECH_640, 332 0, 333 "CMD Technology PCI0640", 334 cmd_chip_map 335 }, 336 { PCI_PRODUCT_CMDTECH_643, 337 0, 338 "CMD Technology PCI0643", 339 cmd0643_9_chip_map, 340 }, 341 { PCI_PRODUCT_CMDTECH_646, 342 0, 343 "CMD Technology PCI0646", 344 cmd0643_9_chip_map, 345 }, 346 { PCI_PRODUCT_CMDTECH_648, 347 IDE_PCI_CLASS_OVERRIDE, 348 "CMD Technology PCI0648", 349 cmd0643_9_chip_map, 350 }, 351 { PCI_PRODUCT_CMDTECH_649, 352 IDE_PCI_CLASS_OVERRIDE, 353 "CMD Technology PCI0649", 354 cmd0643_9_chip_map, 355 }, 356 { 0, 357 0, 358 NULL, 359 NULL 360 } 361 }; 362 363 const struct pciide_product_desc pciide_via_products[] = { 364 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 365 0, 366 NULL, 367 apollo_chip_map, 368 }, 369 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 370 0, 371 NULL, 372 apollo_chip_map, 373 }, 374 { 0, 375 0, 376 NULL, 377 NULL 378 } 379 }; 380 381 const struct pciide_product_desc pciide_cypress_products[] = { 382 { PCI_PRODUCT_CONTAQ_82C693, 383 IDE_16BIT_IOSPACE, 384 "Cypress 82C693 IDE Controller", 385 cy693_chip_map, 386 }, 387 { 0, 388 0, 389 NULL, 390 NULL 391 } 392 }; 393 394 const struct pciide_product_desc pciide_sis_products[] = { 395 { PCI_PRODUCT_SIS_5597_IDE, 396 0, 397 "Silicon Integrated System 5597/5598 IDE controller", 398 sis_chip_map, 399 }, 400 { 0, 401 0, 402 NULL, 403 NULL 404 } 405 }; 406 407 const struct pciide_product_desc pciide_acer_products[] = { 408 { PCI_PRODUCT_ALI_M5229, 409 0, 410 "Acer Labs M5229 UDMA IDE Controller", 411 acer_chip_map, 412 }, 413 { 0, 414 0, 415 NULL, 416 NULL 417 } 418 }; 419 420 const struct pciide_product_desc pciide_promise_products[] = { 421 { PCI_PRODUCT_PROMISE_ULTRA33, 422 IDE_PCI_CLASS_OVERRIDE, 423 "Promise Ultra33/ATA Bus Master IDE Accelerator", 424 pdc202xx_chip_map, 425 }, 426 { PCI_PRODUCT_PROMISE_ULTRA66, 427 IDE_PCI_CLASS_OVERRIDE, 428 "Promise Ultra66/ATA Bus Master IDE Accelerator", 429 pdc202xx_chip_map, 430 }, 431 { PCI_PRODUCT_PROMISE_ULTRA100, 432 IDE_PCI_CLASS_OVERRIDE, 433 "Promise Ultra100/ATA Bus Master IDE Accelerator", 434 pdc202xx_chip_map, 435 }, 436 { PCI_PRODUCT_PROMISE_ULTRA100X, 437 IDE_PCI_CLASS_OVERRIDE, 438 "Promise Ultra100/ATA Bus Master IDE Accelerator", 439 pdc202xx_chip_map, 440 }, 441 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 442 IDE_PCI_CLASS_OVERRIDE, 443 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 444 pdc202xx_chip_map, 445 }, 446 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 447 IDE_PCI_CLASS_OVERRIDE, 448 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 449 pdc202xx_chip_map, 450 }, 451 { PCI_PRODUCT_PROMISE_ULTRA133, 452 IDE_PCI_CLASS_OVERRIDE, 453 "Promise Ultra133/ATA Bus Master IDE Accelerator", 454 pdc202xx_chip_map, 455 }, 456 { 0, 457 0, 458 NULL, 459 NULL 460 } 461 }; 462 463 const struct pciide_product_desc pciide_opti_products[] = { 464 { PCI_PRODUCT_OPTI_82C621, 465 0, 466 "OPTi 82c621 PCI IDE controller", 467 opti_chip_map, 468 }, 469 { PCI_PRODUCT_OPTI_82C568, 470 0, 471 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 472 opti_chip_map, 473 }, 474 { PCI_PRODUCT_OPTI_82D568, 475 0, 476 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 477 opti_chip_map, 478 }, 479 { 0, 480 0, 481 NULL, 482 NULL 483 } 484 }; 485 486 const struct pciide_product_desc pciide_triones_products[] = { 487 { PCI_PRODUCT_TRIONES_HPT366, 488 IDE_PCI_CLASS_OVERRIDE, 489 NULL, 490 hpt_chip_map, 491 }, 492 { PCI_PRODUCT_TRIONES_HPT374, 493 IDE_PCI_CLASS_OVERRIDE, 494 NULL, 495 hpt_chip_map 496 }, 497 { 0, 498 0, 499 NULL, 500 NULL 501 } 502 }; 503 504 const struct pciide_product_desc pciide_acard_products[] = { 505 { PCI_PRODUCT_ACARD_ATP850U, 506 IDE_PCI_CLASS_OVERRIDE, 507 "Acard ATP850U Ultra33 IDE Controller", 508 acard_chip_map, 509 }, 510 { PCI_PRODUCT_ACARD_ATP860, 511 IDE_PCI_CLASS_OVERRIDE, 512 "Acard ATP860 Ultra66 IDE Controller", 513 acard_chip_map, 514 }, 515 { PCI_PRODUCT_ACARD_ATP860A, 516 IDE_PCI_CLASS_OVERRIDE, 517 "Acard ATP860-A Ultra66 IDE Controller", 518 acard_chip_map, 519 }, 520 { 0, 521 0, 522 NULL, 523 NULL 524 } 525 }; 526 527 const struct pciide_product_desc pciide_serverworks_products[] = { 528 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 529 0, 530 "ServerWorks OSB4 IDE Controller", 531 serverworks_chip_map, 532 }, 533 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 534 0, 535 "ServerWorks CSB5 IDE Controller", 536 serverworks_chip_map, 537 }, 538 { 0, 539 0, 540 NULL, 541 } 542 }; 543 544 const struct pciide_product_desc pciide_symphony_products[] = { 545 { PCI_PRODUCT_SYMPHONY_82C105, 546 0, 547 "Symphony Labs 82C105 IDE controller", 548 sl82c105_chip_map, 549 }, 550 { 0, 551 0, 552 NULL, 553 } 554 }; 555 556 const struct pciide_product_desc pciide_winbond_products[] = { 557 { PCI_PRODUCT_WINBOND_W83C553F_1, 558 0, 559 "Winbond W83C553F IDE controller", 560 sl82c105_chip_map, 561 }, 562 { 0, 563 0, 564 NULL, 565 } 566 }; 567 568 struct pciide_vendor_desc { 569 u_int32_t ide_vendor; 570 const struct pciide_product_desc *ide_products; 571 }; 572 573 const struct pciide_vendor_desc pciide_vendors[] = { 574 { PCI_VENDOR_INTEL, pciide_intel_products }, 575 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 576 { PCI_VENDOR_VIATECH, pciide_via_products }, 577 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 578 { PCI_VENDOR_SIS, pciide_sis_products }, 579 { PCI_VENDOR_ALI, pciide_acer_products }, 580 { PCI_VENDOR_PROMISE, pciide_promise_products }, 581 { PCI_VENDOR_AMD, pciide_amd_products }, 582 { PCI_VENDOR_OPTI, pciide_opti_products }, 583 { PCI_VENDOR_TRIONES, pciide_triones_products }, 584 { PCI_VENDOR_ACARD, pciide_acard_products }, 585 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 586 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 587 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 588 { 0, NULL } 589 }; 590 591 /* options passed via the 'flags' config keyword */ 592 #define PCIIDE_OPTIONS_DMA 0x01 593 #define PCIIDE_OPTIONS_NODMA 0x02 594 595 int pciide_match __P((struct device *, struct cfdata *, void *)); 596 void pciide_attach __P((struct device *, struct device *, void *)); 597 598 struct cfattach pciide_ca = { 599 sizeof(struct pciide_softc), pciide_match, pciide_attach 600 }; 601 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 602 int pciide_mapregs_compat __P(( struct pci_attach_args *, 603 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 604 int pciide_mapregs_native __P((struct pci_attach_args *, 605 struct pciide_channel *, bus_size_t *, bus_size_t *, 606 int (*pci_intr) __P((void *)))); 607 void pciide_mapreg_dma __P((struct pciide_softc *, 608 struct pci_attach_args *)); 609 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 610 void pciide_mapchan __P((struct pci_attach_args *, 611 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 612 int (*pci_intr) __P((void *)))); 613 int pciide_chan_candisable __P((struct pciide_channel *)); 614 void pciide_map_compat_intr __P(( struct pci_attach_args *, 615 struct pciide_channel *, int, int)); 616 int pciide_compat_intr __P((void *)); 617 int pciide_pci_intr __P((void *)); 618 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 619 620 const struct pciide_product_desc * 621 pciide_lookup_product(id) 622 u_int32_t id; 623 { 624 const struct pciide_product_desc *pp; 625 const struct pciide_vendor_desc *vp; 626 627 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 628 if (PCI_VENDOR(id) == vp->ide_vendor) 629 break; 630 631 if ((pp = vp->ide_products) == NULL) 632 return NULL; 633 634 for (; pp->chip_map != NULL; pp++) 635 if (PCI_PRODUCT(id) == pp->ide_product) 636 break; 637 638 if (pp->chip_map == NULL) 639 return NULL; 640 return pp; 641 } 642 643 int 644 pciide_match(parent, match, aux) 645 struct device *parent; 646 struct cfdata *match; 647 void *aux; 648 { 649 struct pci_attach_args *pa = aux; 650 const struct pciide_product_desc *pp; 651 652 /* 653 * Check the ID register to see that it's a PCI IDE controller. 654 * If it is, we assume that we can deal with it; it _should_ 655 * work in a standardized way... 656 */ 657 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 658 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 659 return (1); 660 } 661 662 /* 663 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 664 * controllers. Let see if we can deal with it anyway. 665 */ 666 pp = pciide_lookup_product(pa->pa_id); 667 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 668 return (1); 669 } 670 671 return (0); 672 } 673 674 void 675 pciide_attach(parent, self, aux) 676 struct device *parent, *self; 677 void *aux; 678 { 679 struct pci_attach_args *pa = aux; 680 pci_chipset_tag_t pc = pa->pa_pc; 681 pcitag_t tag = pa->pa_tag; 682 struct pciide_softc *sc = (struct pciide_softc *)self; 683 pcireg_t csr; 684 char devinfo[256]; 685 const char *displaydev; 686 687 sc->sc_pp = pciide_lookup_product(pa->pa_id); 688 if (sc->sc_pp == NULL) { 689 sc->sc_pp = &default_product_desc; 690 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 691 displaydev = devinfo; 692 } else 693 displaydev = sc->sc_pp->ide_name; 694 695 /* if displaydev == NULL, printf is done in chip-specific map */ 696 if (displaydev) 697 printf(": %s (rev. 0x%02x)\n", displaydev, 698 PCI_REVISION(pa->pa_class)); 699 700 sc->sc_pc = pa->pa_pc; 701 sc->sc_tag = pa->pa_tag; 702 #ifdef WDCDEBUG 703 if (wdcdebug_pciide_mask & DEBUG_PROBE) 704 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 705 #endif 706 sc->sc_pp->chip_map(sc, pa); 707 708 if (sc->sc_dma_ok) { 709 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 710 csr |= PCI_COMMAND_MASTER_ENABLE; 711 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 712 } 713 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 714 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 715 } 716 717 /* tell wether the chip is enabled or not */ 718 int 719 pciide_chipen(sc, pa) 720 struct pciide_softc *sc; 721 struct pci_attach_args *pa; 722 { 723 pcireg_t csr; 724 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 725 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 726 PCI_COMMAND_STATUS_REG); 727 printf("%s: device disabled (at %s)\n", 728 sc->sc_wdcdev.sc_dev.dv_xname, 729 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 730 "device" : "bridge"); 731 return 0; 732 } 733 return 1; 734 } 735 736 int 737 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 738 struct pci_attach_args *pa; 739 struct pciide_channel *cp; 740 int compatchan; 741 bus_size_t *cmdsizep, *ctlsizep; 742 { 743 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 744 struct channel_softc *wdc_cp = &cp->wdc_channel; 745 746 cp->compat = 1; 747 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 748 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 749 750 wdc_cp->cmd_iot = pa->pa_iot; 751 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 752 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 753 printf("%s: couldn't map %s channel cmd regs\n", 754 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 755 return (0); 756 } 757 758 wdc_cp->ctl_iot = pa->pa_iot; 759 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 760 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 761 printf("%s: couldn't map %s channel ctl regs\n", 762 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 763 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 764 PCIIDE_COMPAT_CMD_SIZE); 765 return (0); 766 } 767 768 return (1); 769 } 770 771 int 772 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 773 struct pci_attach_args * pa; 774 struct pciide_channel *cp; 775 bus_size_t *cmdsizep, *ctlsizep; 776 int (*pci_intr) __P((void *)); 777 { 778 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 779 struct channel_softc *wdc_cp = &cp->wdc_channel; 780 const char *intrstr; 781 pci_intr_handle_t intrhandle; 782 783 cp->compat = 0; 784 785 if (sc->sc_pci_ih == NULL) { 786 if (pci_intr_map(pa, &intrhandle) != 0) { 787 printf("%s: couldn't map native-PCI interrupt\n", 788 sc->sc_wdcdev.sc_dev.dv_xname); 789 return 0; 790 } 791 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 792 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 793 intrhandle, IPL_BIO, pci_intr, sc); 794 if (sc->sc_pci_ih != NULL) { 795 printf("%s: using %s for native-PCI interrupt\n", 796 sc->sc_wdcdev.sc_dev.dv_xname, 797 intrstr ? intrstr : "unknown interrupt"); 798 } else { 799 printf("%s: couldn't establish native-PCI interrupt", 800 sc->sc_wdcdev.sc_dev.dv_xname); 801 if (intrstr != NULL) 802 printf(" at %s", intrstr); 803 printf("\n"); 804 return 0; 805 } 806 } 807 cp->ih = sc->sc_pci_ih; 808 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 809 PCI_MAPREG_TYPE_IO, 0, 810 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 811 printf("%s: couldn't map %s channel cmd regs\n", 812 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 813 return 0; 814 } 815 816 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 817 PCI_MAPREG_TYPE_IO, 0, 818 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 819 printf("%s: couldn't map %s channel ctl regs\n", 820 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 821 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 822 return 0; 823 } 824 /* 825 * In native mode, 4 bytes of I/O space are mapped for the control 826 * register, the control register is at offset 2. Pass the generic 827 * code a handle for only one byte at the rigth offset. 828 */ 829 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 830 &wdc_cp->ctl_ioh) != 0) { 831 printf("%s: unable to subregion %s channel ctl regs\n", 832 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 833 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 834 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 835 return 0; 836 } 837 return (1); 838 } 839 840 void 841 pciide_mapreg_dma(sc, pa) 842 struct pciide_softc *sc; 843 struct pci_attach_args *pa; 844 { 845 pcireg_t maptype; 846 bus_addr_t addr; 847 848 /* 849 * Map DMA registers 850 * 851 * Note that sc_dma_ok is the right variable to test to see if 852 * DMA can be done. If the interface doesn't support DMA, 853 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 854 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 855 * non-zero if the interface supports DMA and the registers 856 * could be mapped. 857 * 858 * XXX Note that despite the fact that the Bus Master IDE specs 859 * XXX say that "The bus master IDE function uses 16 bytes of IO 860 * XXX space," some controllers (at least the United 861 * XXX Microelectronics UM8886BF) place it in memory space. 862 */ 863 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 864 PCIIDE_REG_BUS_MASTER_DMA); 865 866 switch (maptype) { 867 case PCI_MAPREG_TYPE_IO: 868 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 869 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 870 &addr, NULL, NULL) == 0); 871 if (sc->sc_dma_ok == 0) { 872 printf(", but unused (couldn't query registers)"); 873 break; 874 } 875 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 876 && addr >= 0x10000) { 877 sc->sc_dma_ok = 0; 878 printf(", but unused (registers at unsafe address " 879 "%#lx)", (unsigned long)addr); 880 break; 881 } 882 /* FALLTHROUGH */ 883 884 case PCI_MAPREG_MEM_TYPE_32BIT: 885 sc->sc_dma_ok = (pci_mapreg_map(pa, 886 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 887 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 888 sc->sc_dmat = pa->pa_dmat; 889 if (sc->sc_dma_ok == 0) { 890 printf(", but unused (couldn't map registers)"); 891 } else { 892 sc->sc_wdcdev.dma_arg = sc; 893 sc->sc_wdcdev.dma_init = pciide_dma_init; 894 sc->sc_wdcdev.dma_start = pciide_dma_start; 895 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 896 } 897 898 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 899 PCIIDE_OPTIONS_NODMA) { 900 printf(", but unused (forced off by config file)"); 901 sc->sc_dma_ok = 0; 902 } 903 break; 904 905 default: 906 sc->sc_dma_ok = 0; 907 printf(", but unsupported register maptype (0x%x)", maptype); 908 } 909 } 910 911 int 912 pciide_compat_intr(arg) 913 void *arg; 914 { 915 struct pciide_channel *cp = arg; 916 917 #ifdef DIAGNOSTIC 918 /* should only be called for a compat channel */ 919 if (cp->compat == 0) 920 panic("pciide compat intr called for non-compat chan %p\n", cp); 921 #endif 922 return (wdcintr(&cp->wdc_channel)); 923 } 924 925 int 926 pciide_pci_intr(arg) 927 void *arg; 928 { 929 struct pciide_softc *sc = arg; 930 struct pciide_channel *cp; 931 struct channel_softc *wdc_cp; 932 int i, rv, crv; 933 934 rv = 0; 935 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 936 cp = &sc->pciide_channels[i]; 937 wdc_cp = &cp->wdc_channel; 938 939 /* If a compat channel skip. */ 940 if (cp->compat) 941 continue; 942 /* if this channel not waiting for intr, skip */ 943 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 944 continue; 945 946 crv = wdcintr(wdc_cp); 947 if (crv == 0) 948 ; /* leave rv alone */ 949 else if (crv == 1) 950 rv = 1; /* claim the intr */ 951 else if (rv == 0) /* crv should be -1 in this case */ 952 rv = crv; /* if we've done no better, take it */ 953 } 954 return (rv); 955 } 956 957 void 958 pciide_channel_dma_setup(cp) 959 struct pciide_channel *cp; 960 { 961 int drive; 962 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 963 struct ata_drive_datas *drvp; 964 965 for (drive = 0; drive < 2; drive++) { 966 drvp = &cp->wdc_channel.ch_drive[drive]; 967 /* If no drive, skip */ 968 if ((drvp->drive_flags & DRIVE) == 0) 969 continue; 970 /* setup DMA if needed */ 971 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 972 (drvp->drive_flags & DRIVE_UDMA) == 0) || 973 sc->sc_dma_ok == 0) { 974 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 975 continue; 976 } 977 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 978 != 0) { 979 /* Abort DMA setup */ 980 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 981 continue; 982 } 983 } 984 } 985 986 int 987 pciide_dma_table_setup(sc, channel, drive) 988 struct pciide_softc *sc; 989 int channel, drive; 990 { 991 bus_dma_segment_t seg; 992 int error, rseg; 993 const bus_size_t dma_table_size = 994 sizeof(struct idedma_table) * NIDEDMA_TABLES; 995 struct pciide_dma_maps *dma_maps = 996 &sc->pciide_channels[channel].dma_maps[drive]; 997 998 /* If table was already allocated, just return */ 999 if (dma_maps->dma_table) 1000 return 0; 1001 1002 /* Allocate memory for the DMA tables and map it */ 1003 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1004 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1005 BUS_DMA_NOWAIT)) != 0) { 1006 printf("%s:%d: unable to allocate table DMA for " 1007 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1008 channel, drive, error); 1009 return error; 1010 } 1011 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1012 dma_table_size, 1013 (caddr_t *)&dma_maps->dma_table, 1014 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1015 printf("%s:%d: unable to map table DMA for" 1016 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1017 channel, drive, error); 1018 return error; 1019 } 1020 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1021 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1022 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1023 1024 /* Create and load table DMA map for this disk */ 1025 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1026 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1027 &dma_maps->dmamap_table)) != 0) { 1028 printf("%s:%d: unable to create table DMA map for " 1029 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1030 channel, drive, error); 1031 return error; 1032 } 1033 if ((error = bus_dmamap_load(sc->sc_dmat, 1034 dma_maps->dmamap_table, 1035 dma_maps->dma_table, 1036 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1037 printf("%s:%d: unable to load table DMA map for " 1038 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1039 channel, drive, error); 1040 return error; 1041 } 1042 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1043 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1044 DEBUG_PROBE); 1045 /* Create a xfer DMA map for this drive */ 1046 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1047 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1048 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1049 &dma_maps->dmamap_xfer)) != 0) { 1050 printf("%s:%d: unable to create xfer DMA map for " 1051 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1052 channel, drive, error); 1053 return error; 1054 } 1055 return 0; 1056 } 1057 1058 int 1059 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1060 void *v; 1061 int channel, drive; 1062 void *databuf; 1063 size_t datalen; 1064 int flags; 1065 { 1066 struct pciide_softc *sc = v; 1067 int error, seg; 1068 struct pciide_dma_maps *dma_maps = 1069 &sc->pciide_channels[channel].dma_maps[drive]; 1070 1071 error = bus_dmamap_load(sc->sc_dmat, 1072 dma_maps->dmamap_xfer, 1073 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1074 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1075 if (error) { 1076 printf("%s:%d: unable to load xfer DMA map for" 1077 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1078 channel, drive, error); 1079 return error; 1080 } 1081 1082 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1083 dma_maps->dmamap_xfer->dm_mapsize, 1084 (flags & WDC_DMA_READ) ? 1085 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1086 1087 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1088 #ifdef DIAGNOSTIC 1089 /* A segment must not cross a 64k boundary */ 1090 { 1091 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1092 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1093 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1094 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1095 printf("pciide_dma: segment %d physical addr 0x%lx" 1096 " len 0x%lx not properly aligned\n", 1097 seg, phys, len); 1098 panic("pciide_dma: buf align"); 1099 } 1100 } 1101 #endif 1102 dma_maps->dma_table[seg].base_addr = 1103 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1104 dma_maps->dma_table[seg].byte_count = 1105 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1106 IDEDMA_BYTE_COUNT_MASK); 1107 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1108 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1109 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1110 1111 } 1112 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1113 htole32(IDEDMA_BYTE_COUNT_EOT); 1114 1115 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1116 dma_maps->dmamap_table->dm_mapsize, 1117 BUS_DMASYNC_PREWRITE); 1118 1119 /* Maps are ready. Start DMA function */ 1120 #ifdef DIAGNOSTIC 1121 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1122 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1123 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1124 panic("pciide_dma_init: table align"); 1125 } 1126 #endif 1127 1128 /* Clear status bits */ 1129 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1130 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1131 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1132 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1133 /* Write table addr */ 1134 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1135 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1136 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1137 /* set read/write */ 1138 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1139 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1140 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1141 /* remember flags */ 1142 dma_maps->dma_flags = flags; 1143 return 0; 1144 } 1145 1146 void 1147 pciide_dma_start(v, channel, drive) 1148 void *v; 1149 int channel, drive; 1150 { 1151 struct pciide_softc *sc = v; 1152 1153 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1154 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1155 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1156 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1157 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1158 } 1159 1160 int 1161 pciide_dma_finish(v, channel, drive, force) 1162 void *v; 1163 int channel, drive; 1164 int force; 1165 { 1166 struct pciide_softc *sc = v; 1167 u_int8_t status; 1168 int error = 0; 1169 struct pciide_dma_maps *dma_maps = 1170 &sc->pciide_channels[channel].dma_maps[drive]; 1171 1172 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1173 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1174 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1175 DEBUG_XFERS); 1176 1177 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1178 return WDC_DMAST_NOIRQ; 1179 1180 /* stop DMA channel */ 1181 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1182 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1183 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1184 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1185 1186 /* Unload the map of the data buffer */ 1187 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1188 dma_maps->dmamap_xfer->dm_mapsize, 1189 (dma_maps->dma_flags & WDC_DMA_READ) ? 1190 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1191 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1192 1193 if ((status & IDEDMA_CTL_ERR) != 0) { 1194 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1195 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1196 error |= WDC_DMAST_ERR; 1197 } 1198 1199 if ((status & IDEDMA_CTL_INTR) == 0) { 1200 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1201 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1202 drive, status); 1203 error |= WDC_DMAST_NOIRQ; 1204 } 1205 1206 if ((status & IDEDMA_CTL_ACT) != 0) { 1207 /* data underrun, may be a valid condition for ATAPI */ 1208 error |= WDC_DMAST_UNDER; 1209 } 1210 return error; 1211 } 1212 1213 void 1214 pciide_irqack(chp) 1215 struct channel_softc *chp; 1216 { 1217 struct pciide_channel *cp = (struct pciide_channel*)chp; 1218 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1219 1220 /* clear status bits in IDE DMA registers */ 1221 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1222 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1223 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1224 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1225 } 1226 1227 /* some common code used by several chip_map */ 1228 int 1229 pciide_chansetup(sc, channel, interface) 1230 struct pciide_softc *sc; 1231 int channel; 1232 pcireg_t interface; 1233 { 1234 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1235 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1236 cp->name = PCIIDE_CHANNEL_NAME(channel); 1237 cp->wdc_channel.channel = channel; 1238 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1239 cp->wdc_channel.ch_queue = 1240 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1241 if (cp->wdc_channel.ch_queue == NULL) { 1242 printf("%s %s channel: " 1243 "can't allocate memory for command queue", 1244 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1245 return 0; 1246 } 1247 printf("%s: %s channel %s to %s mode\n", 1248 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1249 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1250 "configured" : "wired", 1251 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1252 "native-PCI" : "compatibility"); 1253 return 1; 1254 } 1255 1256 /* some common code used by several chip channel_map */ 1257 void 1258 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1259 struct pci_attach_args *pa; 1260 struct pciide_channel *cp; 1261 pcireg_t interface; 1262 bus_size_t *cmdsizep, *ctlsizep; 1263 int (*pci_intr) __P((void *)); 1264 { 1265 struct channel_softc *wdc_cp = &cp->wdc_channel; 1266 1267 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1268 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1269 pci_intr); 1270 else 1271 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1272 wdc_cp->channel, cmdsizep, ctlsizep); 1273 1274 if (cp->hw_ok == 0) 1275 return; 1276 wdc_cp->data32iot = wdc_cp->cmd_iot; 1277 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1278 wdcattach(wdc_cp); 1279 } 1280 1281 /* 1282 * Generic code to call to know if a channel can be disabled. Return 1 1283 * if channel can be disabled, 0 if not 1284 */ 1285 int 1286 pciide_chan_candisable(cp) 1287 struct pciide_channel *cp; 1288 { 1289 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1290 struct channel_softc *wdc_cp = &cp->wdc_channel; 1291 1292 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1293 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1294 printf("%s: disabling %s channel (no drives)\n", 1295 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1296 cp->hw_ok = 0; 1297 return 1; 1298 } 1299 return 0; 1300 } 1301 1302 /* 1303 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1304 * Set hw_ok=0 on failure 1305 */ 1306 void 1307 pciide_map_compat_intr(pa, cp, compatchan, interface) 1308 struct pci_attach_args *pa; 1309 struct pciide_channel *cp; 1310 int compatchan, interface; 1311 { 1312 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1313 struct channel_softc *wdc_cp = &cp->wdc_channel; 1314 1315 if (cp->hw_ok == 0) 1316 return; 1317 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1318 return; 1319 1320 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1321 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1322 pa, compatchan, pciide_compat_intr, cp); 1323 if (cp->ih == NULL) { 1324 #endif 1325 printf("%s: no compatibility interrupt for use by %s " 1326 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1327 cp->hw_ok = 0; 1328 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1329 } 1330 #endif 1331 } 1332 1333 void 1334 pciide_print_modes(cp) 1335 struct pciide_channel *cp; 1336 { 1337 wdc_print_modes(&cp->wdc_channel); 1338 } 1339 1340 void 1341 default_chip_map(sc, pa) 1342 struct pciide_softc *sc; 1343 struct pci_attach_args *pa; 1344 { 1345 struct pciide_channel *cp; 1346 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1347 pcireg_t csr; 1348 int channel, drive; 1349 struct ata_drive_datas *drvp; 1350 u_int8_t idedma_ctl; 1351 bus_size_t cmdsize, ctlsize; 1352 char *failreason; 1353 1354 if (pciide_chipen(sc, pa) == 0) 1355 return; 1356 1357 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1358 printf("%s: bus-master DMA support present", 1359 sc->sc_wdcdev.sc_dev.dv_xname); 1360 if (sc->sc_pp == &default_product_desc && 1361 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1362 PCIIDE_OPTIONS_DMA) == 0) { 1363 printf(", but unused (no driver support)"); 1364 sc->sc_dma_ok = 0; 1365 } else { 1366 pciide_mapreg_dma(sc, pa); 1367 if (sc->sc_dma_ok != 0) 1368 printf(", used without full driver " 1369 "support"); 1370 } 1371 } else { 1372 printf("%s: hardware does not support DMA", 1373 sc->sc_wdcdev.sc_dev.dv_xname); 1374 sc->sc_dma_ok = 0; 1375 } 1376 printf("\n"); 1377 if (sc->sc_dma_ok) { 1378 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1379 sc->sc_wdcdev.irqack = pciide_irqack; 1380 } 1381 sc->sc_wdcdev.PIO_cap = 0; 1382 sc->sc_wdcdev.DMA_cap = 0; 1383 1384 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1385 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1386 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1387 1388 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1389 cp = &sc->pciide_channels[channel]; 1390 if (pciide_chansetup(sc, channel, interface) == 0) 1391 continue; 1392 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1393 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1394 &ctlsize, pciide_pci_intr); 1395 } else { 1396 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1397 channel, &cmdsize, &ctlsize); 1398 } 1399 if (cp->hw_ok == 0) 1400 continue; 1401 /* 1402 * Check to see if something appears to be there. 1403 */ 1404 failreason = NULL; 1405 if (!wdcprobe(&cp->wdc_channel)) { 1406 failreason = "not responding; disabled or no drives?"; 1407 goto next; 1408 } 1409 /* 1410 * Now, make sure it's actually attributable to this PCI IDE 1411 * channel by trying to access the channel again while the 1412 * PCI IDE controller's I/O space is disabled. (If the 1413 * channel no longer appears to be there, it belongs to 1414 * this controller.) YUCK! 1415 */ 1416 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1417 PCI_COMMAND_STATUS_REG); 1418 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1419 csr & ~PCI_COMMAND_IO_ENABLE); 1420 if (wdcprobe(&cp->wdc_channel)) 1421 failreason = "other hardware responding at addresses"; 1422 pci_conf_write(sc->sc_pc, sc->sc_tag, 1423 PCI_COMMAND_STATUS_REG, csr); 1424 next: 1425 if (failreason) { 1426 printf("%s: %s channel ignored (%s)\n", 1427 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1428 failreason); 1429 cp->hw_ok = 0; 1430 bus_space_unmap(cp->wdc_channel.cmd_iot, 1431 cp->wdc_channel.cmd_ioh, cmdsize); 1432 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1433 bus_space_unmap(cp->wdc_channel.ctl_iot, 1434 cp->ctl_baseioh, ctlsize); 1435 else 1436 bus_space_unmap(cp->wdc_channel.ctl_iot, 1437 cp->wdc_channel.ctl_ioh, ctlsize); 1438 } else { 1439 pciide_map_compat_intr(pa, cp, channel, interface); 1440 } 1441 if (cp->hw_ok) { 1442 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1443 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1444 wdcattach(&cp->wdc_channel); 1445 } 1446 } 1447 1448 if (sc->sc_dma_ok == 0) 1449 return; 1450 1451 /* Allocate DMA maps */ 1452 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1453 idedma_ctl = 0; 1454 cp = &sc->pciide_channels[channel]; 1455 for (drive = 0; drive < 2; drive++) { 1456 drvp = &cp->wdc_channel.ch_drive[drive]; 1457 /* If no drive, skip */ 1458 if ((drvp->drive_flags & DRIVE) == 0) 1459 continue; 1460 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1461 continue; 1462 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1463 /* Abort DMA setup */ 1464 printf("%s:%d:%d: can't allocate DMA maps, " 1465 "using PIO transfers\n", 1466 sc->sc_wdcdev.sc_dev.dv_xname, 1467 channel, drive); 1468 drvp->drive_flags &= ~DRIVE_DMA; 1469 } 1470 printf("%s:%d:%d: using DMA data transfers\n", 1471 sc->sc_wdcdev.sc_dev.dv_xname, 1472 channel, drive); 1473 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1474 } 1475 if (idedma_ctl != 0) { 1476 /* Add software bits in status register */ 1477 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1478 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1479 idedma_ctl); 1480 } 1481 } 1482 } 1483 1484 void 1485 piix_chip_map(sc, pa) 1486 struct pciide_softc *sc; 1487 struct pci_attach_args *pa; 1488 { 1489 struct pciide_channel *cp; 1490 int channel; 1491 u_int32_t idetim; 1492 bus_size_t cmdsize, ctlsize; 1493 1494 if (pciide_chipen(sc, pa) == 0) 1495 return; 1496 1497 printf("%s: bus-master DMA support present", 1498 sc->sc_wdcdev.sc_dev.dv_xname); 1499 pciide_mapreg_dma(sc, pa); 1500 printf("\n"); 1501 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1502 WDC_CAPABILITY_MODE; 1503 if (sc->sc_dma_ok) { 1504 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1505 sc->sc_wdcdev.irqack = pciide_irqack; 1506 switch(sc->sc_pp->ide_product) { 1507 case PCI_PRODUCT_INTEL_82371AB_IDE: 1508 case PCI_PRODUCT_INTEL_82440MX_IDE: 1509 case PCI_PRODUCT_INTEL_82801AA_IDE: 1510 case PCI_PRODUCT_INTEL_82801AB_IDE: 1511 case PCI_PRODUCT_INTEL_82801BA_IDE: 1512 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1513 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1514 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1515 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1516 } 1517 } 1518 sc->sc_wdcdev.PIO_cap = 4; 1519 sc->sc_wdcdev.DMA_cap = 2; 1520 switch(sc->sc_pp->ide_product) { 1521 case PCI_PRODUCT_INTEL_82801AA_IDE: 1522 sc->sc_wdcdev.UDMA_cap = 4; 1523 break; 1524 case PCI_PRODUCT_INTEL_82801BA_IDE: 1525 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1526 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1527 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1528 sc->sc_wdcdev.UDMA_cap = 5; 1529 break; 1530 default: 1531 sc->sc_wdcdev.UDMA_cap = 2; 1532 } 1533 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1534 sc->sc_wdcdev.set_modes = piix_setup_channel; 1535 else 1536 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1537 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1538 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1539 1540 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1541 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1542 DEBUG_PROBE); 1543 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1544 WDCDEBUG_PRINT((", sidetim=0x%x", 1545 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1546 DEBUG_PROBE); 1547 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1548 WDCDEBUG_PRINT((", udamreg 0x%x", 1549 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1550 DEBUG_PROBE); 1551 } 1552 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1555 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1556 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1557 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1558 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1559 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1560 DEBUG_PROBE); 1561 } 1562 1563 } 1564 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1565 1566 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1567 cp = &sc->pciide_channels[channel]; 1568 /* PIIX is compat-only */ 1569 if (pciide_chansetup(sc, channel, 0) == 0) 1570 continue; 1571 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1572 if ((PIIX_IDETIM_READ(idetim, channel) & 1573 PIIX_IDETIM_IDE) == 0) { 1574 printf("%s: %s channel ignored (disabled)\n", 1575 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1576 continue; 1577 } 1578 /* PIIX are compat-only pciide devices */ 1579 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1580 if (cp->hw_ok == 0) 1581 continue; 1582 if (pciide_chan_candisable(cp)) { 1583 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1584 channel); 1585 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1586 idetim); 1587 } 1588 pciide_map_compat_intr(pa, cp, channel, 0); 1589 if (cp->hw_ok == 0) 1590 continue; 1591 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1592 } 1593 1594 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1595 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1596 DEBUG_PROBE); 1597 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1598 WDCDEBUG_PRINT((", sidetim=0x%x", 1599 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1600 DEBUG_PROBE); 1601 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1602 WDCDEBUG_PRINT((", udamreg 0x%x", 1603 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1604 DEBUG_PROBE); 1605 } 1606 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1609 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1610 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1611 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1612 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1613 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1614 DEBUG_PROBE); 1615 } 1616 } 1617 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1618 } 1619 1620 void 1621 piix_setup_channel(chp) 1622 struct channel_softc *chp; 1623 { 1624 u_int8_t mode[2], drive; 1625 u_int32_t oidetim, idetim, idedma_ctl; 1626 struct pciide_channel *cp = (struct pciide_channel*)chp; 1627 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1628 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1629 1630 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1631 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1632 idedma_ctl = 0; 1633 1634 /* set up new idetim: Enable IDE registers decode */ 1635 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1636 chp->channel); 1637 1638 /* setup DMA */ 1639 pciide_channel_dma_setup(cp); 1640 1641 /* 1642 * Here we have to mess up with drives mode: PIIX can't have 1643 * different timings for master and slave drives. 1644 * We need to find the best combination. 1645 */ 1646 1647 /* If both drives supports DMA, take the lower mode */ 1648 if ((drvp[0].drive_flags & DRIVE_DMA) && 1649 (drvp[1].drive_flags & DRIVE_DMA)) { 1650 mode[0] = mode[1] = 1651 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1652 drvp[0].DMA_mode = mode[0]; 1653 drvp[1].DMA_mode = mode[1]; 1654 goto ok; 1655 } 1656 /* 1657 * If only one drive supports DMA, use its mode, and 1658 * put the other one in PIO mode 0 if mode not compatible 1659 */ 1660 if (drvp[0].drive_flags & DRIVE_DMA) { 1661 mode[0] = drvp[0].DMA_mode; 1662 mode[1] = drvp[1].PIO_mode; 1663 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1664 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1665 mode[1] = drvp[1].PIO_mode = 0; 1666 goto ok; 1667 } 1668 if (drvp[1].drive_flags & DRIVE_DMA) { 1669 mode[1] = drvp[1].DMA_mode; 1670 mode[0] = drvp[0].PIO_mode; 1671 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1672 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1673 mode[0] = drvp[0].PIO_mode = 0; 1674 goto ok; 1675 } 1676 /* 1677 * If both drives are not DMA, takes the lower mode, unless 1678 * one of them is PIO mode < 2 1679 */ 1680 if (drvp[0].PIO_mode < 2) { 1681 mode[0] = drvp[0].PIO_mode = 0; 1682 mode[1] = drvp[1].PIO_mode; 1683 } else if (drvp[1].PIO_mode < 2) { 1684 mode[1] = drvp[1].PIO_mode = 0; 1685 mode[0] = drvp[0].PIO_mode; 1686 } else { 1687 mode[0] = mode[1] = 1688 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1689 drvp[0].PIO_mode = mode[0]; 1690 drvp[1].PIO_mode = mode[1]; 1691 } 1692 ok: /* The modes are setup */ 1693 for (drive = 0; drive < 2; drive++) { 1694 if (drvp[drive].drive_flags & DRIVE_DMA) { 1695 idetim |= piix_setup_idetim_timings( 1696 mode[drive], 1, chp->channel); 1697 goto end; 1698 } 1699 } 1700 /* If we are there, none of the drives are DMA */ 1701 if (mode[0] >= 2) 1702 idetim |= piix_setup_idetim_timings( 1703 mode[0], 0, chp->channel); 1704 else 1705 idetim |= piix_setup_idetim_timings( 1706 mode[1], 0, chp->channel); 1707 end: /* 1708 * timing mode is now set up in the controller. Enable 1709 * it per-drive 1710 */ 1711 for (drive = 0; drive < 2; drive++) { 1712 /* If no drive, skip */ 1713 if ((drvp[drive].drive_flags & DRIVE) == 0) 1714 continue; 1715 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1716 if (drvp[drive].drive_flags & DRIVE_DMA) 1717 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1718 } 1719 if (idedma_ctl != 0) { 1720 /* Add software bits in status register */ 1721 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1722 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1723 idedma_ctl); 1724 } 1725 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1726 pciide_print_modes(cp); 1727 } 1728 1729 void 1730 piix3_4_setup_channel(chp) 1731 struct channel_softc *chp; 1732 { 1733 struct ata_drive_datas *drvp; 1734 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1735 struct pciide_channel *cp = (struct pciide_channel*)chp; 1736 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1737 int drive; 1738 int channel = chp->channel; 1739 1740 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1741 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1742 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1743 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1744 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1745 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1746 PIIX_SIDETIM_RTC_MASK(channel)); 1747 1748 idedma_ctl = 0; 1749 /* If channel disabled, no need to go further */ 1750 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1751 return; 1752 /* set up new idetim: Enable IDE registers decode */ 1753 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1754 1755 /* setup DMA if needed */ 1756 pciide_channel_dma_setup(cp); 1757 1758 for (drive = 0; drive < 2; drive++) { 1759 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1760 PIIX_UDMATIM_SET(0x3, channel, drive)); 1761 drvp = &chp->ch_drive[drive]; 1762 /* If no drive, skip */ 1763 if ((drvp->drive_flags & DRIVE) == 0) 1764 continue; 1765 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1766 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1767 goto pio; 1768 1769 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1770 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1771 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1772 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1773 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1774 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1775 ideconf |= PIIX_CONFIG_PINGPONG; 1776 } 1777 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1778 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1779 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1780 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1781 /* setup Ultra/100 */ 1782 if (drvp->UDMA_mode > 2 && 1783 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1784 drvp->UDMA_mode = 2; 1785 if (drvp->UDMA_mode > 4) { 1786 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1787 } else { 1788 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1789 if (drvp->UDMA_mode > 2) { 1790 ideconf |= PIIX_CONFIG_UDMA66(channel, 1791 drive); 1792 } else { 1793 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1794 drive); 1795 } 1796 } 1797 } 1798 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1799 /* setup Ultra/66 */ 1800 if (drvp->UDMA_mode > 2 && 1801 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1802 drvp->UDMA_mode = 2; 1803 if (drvp->UDMA_mode > 2) 1804 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1805 else 1806 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1807 } 1808 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1809 (drvp->drive_flags & DRIVE_UDMA)) { 1810 /* use Ultra/DMA */ 1811 drvp->drive_flags &= ~DRIVE_DMA; 1812 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1813 udmareg |= PIIX_UDMATIM_SET( 1814 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1815 } else { 1816 /* use Multiword DMA */ 1817 drvp->drive_flags &= ~DRIVE_UDMA; 1818 if (drive == 0) { 1819 idetim |= piix_setup_idetim_timings( 1820 drvp->DMA_mode, 1, channel); 1821 } else { 1822 sidetim |= piix_setup_sidetim_timings( 1823 drvp->DMA_mode, 1, channel); 1824 idetim =PIIX_IDETIM_SET(idetim, 1825 PIIX_IDETIM_SITRE, channel); 1826 } 1827 } 1828 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1829 1830 pio: /* use PIO mode */ 1831 idetim |= piix_setup_idetim_drvs(drvp); 1832 if (drive == 0) { 1833 idetim |= piix_setup_idetim_timings( 1834 drvp->PIO_mode, 0, channel); 1835 } else { 1836 sidetim |= piix_setup_sidetim_timings( 1837 drvp->PIO_mode, 0, channel); 1838 idetim =PIIX_IDETIM_SET(idetim, 1839 PIIX_IDETIM_SITRE, channel); 1840 } 1841 } 1842 if (idedma_ctl != 0) { 1843 /* Add software bits in status register */ 1844 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1845 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1846 idedma_ctl); 1847 } 1848 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1849 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1850 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1851 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1852 pciide_print_modes(cp); 1853 } 1854 1855 1856 /* setup ISP and RTC fields, based on mode */ 1857 static u_int32_t 1858 piix_setup_idetim_timings(mode, dma, channel) 1859 u_int8_t mode; 1860 u_int8_t dma; 1861 u_int8_t channel; 1862 { 1863 1864 if (dma) 1865 return PIIX_IDETIM_SET(0, 1866 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1867 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1868 channel); 1869 else 1870 return PIIX_IDETIM_SET(0, 1871 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1872 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1873 channel); 1874 } 1875 1876 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1877 static u_int32_t 1878 piix_setup_idetim_drvs(drvp) 1879 struct ata_drive_datas *drvp; 1880 { 1881 u_int32_t ret = 0; 1882 struct channel_softc *chp = drvp->chnl_softc; 1883 u_int8_t channel = chp->channel; 1884 u_int8_t drive = drvp->drive; 1885 1886 /* 1887 * If drive is using UDMA, timings setups are independant 1888 * So just check DMA and PIO here. 1889 */ 1890 if (drvp->drive_flags & DRIVE_DMA) { 1891 /* if mode = DMA mode 0, use compatible timings */ 1892 if ((drvp->drive_flags & DRIVE_DMA) && 1893 drvp->DMA_mode == 0) { 1894 drvp->PIO_mode = 0; 1895 return ret; 1896 } 1897 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1898 /* 1899 * PIO and DMA timings are the same, use fast timings for PIO 1900 * too, else use compat timings. 1901 */ 1902 if ((piix_isp_pio[drvp->PIO_mode] != 1903 piix_isp_dma[drvp->DMA_mode]) || 1904 (piix_rtc_pio[drvp->PIO_mode] != 1905 piix_rtc_dma[drvp->DMA_mode])) 1906 drvp->PIO_mode = 0; 1907 /* if PIO mode <= 2, use compat timings for PIO */ 1908 if (drvp->PIO_mode <= 2) { 1909 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1910 channel); 1911 return ret; 1912 } 1913 } 1914 1915 /* 1916 * Now setup PIO modes. If mode < 2, use compat timings. 1917 * Else enable fast timings. Enable IORDY and prefetch/post 1918 * if PIO mode >= 3. 1919 */ 1920 1921 if (drvp->PIO_mode < 2) 1922 return ret; 1923 1924 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1925 if (drvp->PIO_mode >= 3) { 1926 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1927 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1928 } 1929 return ret; 1930 } 1931 1932 /* setup values in SIDETIM registers, based on mode */ 1933 static u_int32_t 1934 piix_setup_sidetim_timings(mode, dma, channel) 1935 u_int8_t mode; 1936 u_int8_t dma; 1937 u_int8_t channel; 1938 { 1939 if (dma) 1940 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1941 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1942 else 1943 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1944 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1945 } 1946 1947 void 1948 amd7x6_chip_map(sc, pa) 1949 struct pciide_softc *sc; 1950 struct pci_attach_args *pa; 1951 { 1952 struct pciide_channel *cp; 1953 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1954 int channel; 1955 pcireg_t chanenable; 1956 bus_size_t cmdsize, ctlsize; 1957 1958 if (pciide_chipen(sc, pa) == 0) 1959 return; 1960 printf("%s: bus-master DMA support present", 1961 sc->sc_wdcdev.sc_dev.dv_xname); 1962 pciide_mapreg_dma(sc, pa); 1963 printf("\n"); 1964 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1965 WDC_CAPABILITY_MODE; 1966 if (sc->sc_dma_ok) { 1967 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1968 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1969 sc->sc_wdcdev.irqack = pciide_irqack; 1970 } 1971 sc->sc_wdcdev.PIO_cap = 4; 1972 sc->sc_wdcdev.DMA_cap = 2; 1973 1974 switch (sc->sc_pp->ide_product) { 1975 case PCI_PRODUCT_AMD_PBC766_IDE: 1976 case PCI_PRODUCT_AMD_PBC768_IDE: 1977 sc->sc_wdcdev.UDMA_cap = 5; 1978 break; 1979 default: 1980 sc->sc_wdcdev.UDMA_cap = 4; 1981 } 1982 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1983 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1984 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1985 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1986 1987 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1988 DEBUG_PROBE); 1989 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1990 cp = &sc->pciide_channels[channel]; 1991 if (pciide_chansetup(sc, channel, interface) == 0) 1992 continue; 1993 1994 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1995 printf("%s: %s channel ignored (disabled)\n", 1996 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1997 continue; 1998 } 1999 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2000 pciide_pci_intr); 2001 2002 if (pciide_chan_candisable(cp)) 2003 chanenable &= ~AMD7X6_CHAN_EN(channel); 2004 pciide_map_compat_intr(pa, cp, channel, interface); 2005 if (cp->hw_ok == 0) 2006 continue; 2007 2008 amd7x6_setup_channel(&cp->wdc_channel); 2009 } 2010 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2011 chanenable); 2012 return; 2013 } 2014 2015 void 2016 amd7x6_setup_channel(chp) 2017 struct channel_softc *chp; 2018 { 2019 u_int32_t udmatim_reg, datatim_reg; 2020 u_int8_t idedma_ctl; 2021 int mode, drive; 2022 struct ata_drive_datas *drvp; 2023 struct pciide_channel *cp = (struct pciide_channel*)chp; 2024 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2025 #ifndef PCIIDE_AMD756_ENABLEDMA 2026 int rev = PCI_REVISION( 2027 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2028 #endif 2029 2030 idedma_ctl = 0; 2031 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2032 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2033 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2034 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2035 2036 /* setup DMA if needed */ 2037 pciide_channel_dma_setup(cp); 2038 2039 for (drive = 0; drive < 2; drive++) { 2040 drvp = &chp->ch_drive[drive]; 2041 /* If no drive, skip */ 2042 if ((drvp->drive_flags & DRIVE) == 0) 2043 continue; 2044 /* add timing values, setup DMA if needed */ 2045 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2046 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2047 mode = drvp->PIO_mode; 2048 goto pio; 2049 } 2050 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2051 (drvp->drive_flags & DRIVE_UDMA)) { 2052 /* use Ultra/DMA */ 2053 drvp->drive_flags &= ~DRIVE_DMA; 2054 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2055 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2056 AMD7X6_UDMA_TIME(chp->channel, drive, 2057 amd7x6_udma_tim[drvp->UDMA_mode]); 2058 /* can use PIO timings, MW DMA unused */ 2059 mode = drvp->PIO_mode; 2060 } else { 2061 /* use Multiword DMA, but only if revision is OK */ 2062 drvp->drive_flags &= ~DRIVE_UDMA; 2063 #ifndef PCIIDE_AMD756_ENABLEDMA 2064 /* 2065 * The workaround doesn't seem to be necessary 2066 * with all drives, so it can be disabled by 2067 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2068 * triggered. 2069 */ 2070 if (sc->sc_pp->ide_product == 2071 PCI_PRODUCT_AMD_PBC756_IDE && 2072 AMD756_CHIPREV_DISABLEDMA(rev)) { 2073 printf("%s:%d:%d: multi-word DMA disabled due " 2074 "to chip revision\n", 2075 sc->sc_wdcdev.sc_dev.dv_xname, 2076 chp->channel, drive); 2077 mode = drvp->PIO_mode; 2078 drvp->drive_flags &= ~DRIVE_DMA; 2079 goto pio; 2080 } 2081 #endif 2082 /* mode = min(pio, dma+2) */ 2083 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2084 mode = drvp->PIO_mode; 2085 else 2086 mode = drvp->DMA_mode + 2; 2087 } 2088 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2089 2090 pio: /* setup PIO mode */ 2091 if (mode <= 2) { 2092 drvp->DMA_mode = 0; 2093 drvp->PIO_mode = 0; 2094 mode = 0; 2095 } else { 2096 drvp->PIO_mode = mode; 2097 drvp->DMA_mode = mode - 2; 2098 } 2099 datatim_reg |= 2100 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2101 amd7x6_pio_set[mode]) | 2102 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2103 amd7x6_pio_rec[mode]); 2104 } 2105 if (idedma_ctl != 0) { 2106 /* Add software bits in status register */ 2107 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2108 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2109 idedma_ctl); 2110 } 2111 pciide_print_modes(cp); 2112 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2113 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2114 } 2115 2116 void 2117 apollo_chip_map(sc, pa) 2118 struct pciide_softc *sc; 2119 struct pci_attach_args *pa; 2120 { 2121 struct pciide_channel *cp; 2122 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2123 int channel; 2124 u_int32_t ideconf; 2125 bus_size_t cmdsize, ctlsize; 2126 pcitag_t pcib_tag; 2127 pcireg_t pcib_id, pcib_class; 2128 2129 if (pciide_chipen(sc, pa) == 0) 2130 return; 2131 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2132 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2133 /* and read ID and rev of the ISA bridge */ 2134 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2135 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2136 printf(": VIA Technologies "); 2137 switch (PCI_PRODUCT(pcib_id)) { 2138 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2139 printf("VT82C586 (Apollo VP) "); 2140 if(PCI_REVISION(pcib_class) >= 0x02) { 2141 printf("ATA33 controller\n"); 2142 sc->sc_wdcdev.UDMA_cap = 2; 2143 } else { 2144 printf("controller\n"); 2145 sc->sc_wdcdev.UDMA_cap = 0; 2146 } 2147 break; 2148 case PCI_PRODUCT_VIATECH_VT82C596A: 2149 printf("VT82C596A (Apollo Pro) "); 2150 if (PCI_REVISION(pcib_class) >= 0x12) { 2151 printf("ATA66 controller\n"); 2152 sc->sc_wdcdev.UDMA_cap = 4; 2153 } else { 2154 printf("ATA33 controller\n"); 2155 sc->sc_wdcdev.UDMA_cap = 2; 2156 } 2157 break; 2158 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2159 printf("VT82C686A (Apollo KX133) "); 2160 if (PCI_REVISION(pcib_class) >= 0x40) { 2161 printf("ATA100 controller\n"); 2162 sc->sc_wdcdev.UDMA_cap = 5; 2163 } else { 2164 printf("ATA66 controller\n"); 2165 sc->sc_wdcdev.UDMA_cap = 4; 2166 } 2167 break; 2168 case PCI_PRODUCT_VIATECH_VT8231: 2169 printf("VT8231 ATA100 controller\n"); 2170 sc->sc_wdcdev.UDMA_cap = 5; 2171 break; 2172 case PCI_PRODUCT_VIATECH_VT8233: 2173 printf("VT8233 ATA100 controller\n"); 2174 sc->sc_wdcdev.UDMA_cap = 5; 2175 break; 2176 default: 2177 printf("unknown ATA controller\n"); 2178 sc->sc_wdcdev.UDMA_cap = 0; 2179 } 2180 2181 printf("%s: bus-master DMA support present", 2182 sc->sc_wdcdev.sc_dev.dv_xname); 2183 pciide_mapreg_dma(sc, pa); 2184 printf("\n"); 2185 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2186 WDC_CAPABILITY_MODE; 2187 if (sc->sc_dma_ok) { 2188 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2189 sc->sc_wdcdev.irqack = pciide_irqack; 2190 if (sc->sc_wdcdev.UDMA_cap > 0) 2191 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2192 } 2193 sc->sc_wdcdev.PIO_cap = 4; 2194 sc->sc_wdcdev.DMA_cap = 2; 2195 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2196 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2197 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2198 2199 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2200 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2201 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2202 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2203 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2204 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2205 DEBUG_PROBE); 2206 2207 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2208 cp = &sc->pciide_channels[channel]; 2209 if (pciide_chansetup(sc, channel, interface) == 0) 2210 continue; 2211 2212 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2213 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2214 printf("%s: %s channel ignored (disabled)\n", 2215 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2216 continue; 2217 } 2218 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2219 pciide_pci_intr); 2220 if (cp->hw_ok == 0) 2221 continue; 2222 if (pciide_chan_candisable(cp)) { 2223 ideconf &= ~APO_IDECONF_EN(channel); 2224 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2225 ideconf); 2226 } 2227 pciide_map_compat_intr(pa, cp, channel, interface); 2228 2229 if (cp->hw_ok == 0) 2230 continue; 2231 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2232 } 2233 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2234 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2235 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2236 } 2237 2238 void 2239 apollo_setup_channel(chp) 2240 struct channel_softc *chp; 2241 { 2242 u_int32_t udmatim_reg, datatim_reg; 2243 u_int8_t idedma_ctl; 2244 int mode, drive; 2245 struct ata_drive_datas *drvp; 2246 struct pciide_channel *cp = (struct pciide_channel*)chp; 2247 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2248 2249 idedma_ctl = 0; 2250 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2251 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2252 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2253 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2254 2255 /* setup DMA if needed */ 2256 pciide_channel_dma_setup(cp); 2257 2258 for (drive = 0; drive < 2; drive++) { 2259 drvp = &chp->ch_drive[drive]; 2260 /* If no drive, skip */ 2261 if ((drvp->drive_flags & DRIVE) == 0) 2262 continue; 2263 /* add timing values, setup DMA if needed */ 2264 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2265 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2266 mode = drvp->PIO_mode; 2267 goto pio; 2268 } 2269 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2270 (drvp->drive_flags & DRIVE_UDMA)) { 2271 /* use Ultra/DMA */ 2272 drvp->drive_flags &= ~DRIVE_DMA; 2273 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2274 APO_UDMA_EN_MTH(chp->channel, drive); 2275 if (sc->sc_wdcdev.UDMA_cap == 5) { 2276 /* 686b */ 2277 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2278 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2279 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2280 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2281 /* 596b or 686a */ 2282 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2283 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2284 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2285 } else { 2286 /* 596a or 586b */ 2287 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2288 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2289 } 2290 /* can use PIO timings, MW DMA unused */ 2291 mode = drvp->PIO_mode; 2292 } else { 2293 /* use Multiword DMA */ 2294 drvp->drive_flags &= ~DRIVE_UDMA; 2295 /* mode = min(pio, dma+2) */ 2296 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2297 mode = drvp->PIO_mode; 2298 else 2299 mode = drvp->DMA_mode + 2; 2300 } 2301 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2302 2303 pio: /* setup PIO mode */ 2304 if (mode <= 2) { 2305 drvp->DMA_mode = 0; 2306 drvp->PIO_mode = 0; 2307 mode = 0; 2308 } else { 2309 drvp->PIO_mode = mode; 2310 drvp->DMA_mode = mode - 2; 2311 } 2312 datatim_reg |= 2313 APO_DATATIM_PULSE(chp->channel, drive, 2314 apollo_pio_set[mode]) | 2315 APO_DATATIM_RECOV(chp->channel, drive, 2316 apollo_pio_rec[mode]); 2317 } 2318 if (idedma_ctl != 0) { 2319 /* Add software bits in status register */ 2320 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2321 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2322 idedma_ctl); 2323 } 2324 pciide_print_modes(cp); 2325 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2326 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2327 } 2328 2329 void 2330 cmd_channel_map(pa, sc, channel) 2331 struct pci_attach_args *pa; 2332 struct pciide_softc *sc; 2333 int channel; 2334 { 2335 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2336 bus_size_t cmdsize, ctlsize; 2337 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2338 int interface, one_channel; 2339 2340 /* 2341 * The 0648/0649 can be told to identify as a RAID controller. 2342 * In this case, we have to fake interface 2343 */ 2344 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2345 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2346 PCIIDE_INTERFACE_SETTABLE(1); 2347 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2348 CMD_CONF_DSA1) 2349 interface |= PCIIDE_INTERFACE_PCI(0) | 2350 PCIIDE_INTERFACE_PCI(1); 2351 } else { 2352 interface = PCI_INTERFACE(pa->pa_class); 2353 } 2354 2355 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2356 cp->name = PCIIDE_CHANNEL_NAME(channel); 2357 cp->wdc_channel.channel = channel; 2358 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2359 2360 /* 2361 * Older CMD64X doesn't have independant channels 2362 */ 2363 switch (sc->sc_pp->ide_product) { 2364 case PCI_PRODUCT_CMDTECH_649: 2365 one_channel = 0; 2366 break; 2367 default: 2368 one_channel = 1; 2369 break; 2370 } 2371 2372 if (channel > 0 && one_channel) { 2373 cp->wdc_channel.ch_queue = 2374 sc->pciide_channels[0].wdc_channel.ch_queue; 2375 } else { 2376 cp->wdc_channel.ch_queue = 2377 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2378 } 2379 if (cp->wdc_channel.ch_queue == NULL) { 2380 printf("%s %s channel: " 2381 "can't allocate memory for command queue", 2382 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2383 return; 2384 } 2385 2386 printf("%s: %s channel %s to %s mode\n", 2387 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2388 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2389 "configured" : "wired", 2390 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2391 "native-PCI" : "compatibility"); 2392 2393 /* 2394 * with a CMD PCI64x, if we get here, the first channel is enabled: 2395 * there's no way to disable the first channel without disabling 2396 * the whole device 2397 */ 2398 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2399 printf("%s: %s channel ignored (disabled)\n", 2400 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2401 return; 2402 } 2403 2404 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2405 if (cp->hw_ok == 0) 2406 return; 2407 if (channel == 1) { 2408 if (pciide_chan_candisable(cp)) { 2409 ctrl &= ~CMD_CTRL_2PORT; 2410 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2411 CMD_CTRL, ctrl); 2412 } 2413 } 2414 pciide_map_compat_intr(pa, cp, channel, interface); 2415 } 2416 2417 int 2418 cmd_pci_intr(arg) 2419 void *arg; 2420 { 2421 struct pciide_softc *sc = arg; 2422 struct pciide_channel *cp; 2423 struct channel_softc *wdc_cp; 2424 int i, rv, crv; 2425 u_int32_t priirq, secirq; 2426 2427 rv = 0; 2428 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2429 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2430 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2431 cp = &sc->pciide_channels[i]; 2432 wdc_cp = &cp->wdc_channel; 2433 /* If a compat channel skip. */ 2434 if (cp->compat) 2435 continue; 2436 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2437 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2438 crv = wdcintr(wdc_cp); 2439 if (crv == 0) 2440 printf("%s:%d: bogus intr\n", 2441 sc->sc_wdcdev.sc_dev.dv_xname, i); 2442 else 2443 rv = 1; 2444 } 2445 } 2446 return rv; 2447 } 2448 2449 void 2450 cmd_chip_map(sc, pa) 2451 struct pciide_softc *sc; 2452 struct pci_attach_args *pa; 2453 { 2454 int channel; 2455 2456 /* 2457 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2458 * and base adresses registers can be disabled at 2459 * hardware level. In this case, the device is wired 2460 * in compat mode and its first channel is always enabled, 2461 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2462 * In fact, it seems that the first channel of the CMD PCI0640 2463 * can't be disabled. 2464 */ 2465 2466 #ifdef PCIIDE_CMD064x_DISABLE 2467 if (pciide_chipen(sc, pa) == 0) 2468 return; 2469 #endif 2470 2471 printf("%s: hardware does not support DMA\n", 2472 sc->sc_wdcdev.sc_dev.dv_xname); 2473 sc->sc_dma_ok = 0; 2474 2475 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2476 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2477 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2478 2479 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2480 cmd_channel_map(pa, sc, channel); 2481 } 2482 } 2483 2484 void 2485 cmd0643_9_chip_map(sc, pa) 2486 struct pciide_softc *sc; 2487 struct pci_attach_args *pa; 2488 { 2489 struct pciide_channel *cp; 2490 int channel; 2491 pcireg_t rev = PCI_REVISION(pa->pa_class); 2492 2493 /* 2494 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2495 * and base adresses registers can be disabled at 2496 * hardware level. In this case, the device is wired 2497 * in compat mode and its first channel is always enabled, 2498 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2499 * In fact, it seems that the first channel of the CMD PCI0640 2500 * can't be disabled. 2501 */ 2502 2503 #ifdef PCIIDE_CMD064x_DISABLE 2504 if (pciide_chipen(sc, pa) == 0) 2505 return; 2506 #endif 2507 printf("%s: bus-master DMA support present", 2508 sc->sc_wdcdev.sc_dev.dv_xname); 2509 pciide_mapreg_dma(sc, pa); 2510 printf("\n"); 2511 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2512 WDC_CAPABILITY_MODE; 2513 if (sc->sc_dma_ok) { 2514 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2515 switch (sc->sc_pp->ide_product) { 2516 case PCI_PRODUCT_CMDTECH_649: 2517 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2518 sc->sc_wdcdev.UDMA_cap = 5; 2519 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2520 break; 2521 case PCI_PRODUCT_CMDTECH_648: 2522 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2523 sc->sc_wdcdev.UDMA_cap = 4; 2524 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2525 break; 2526 case PCI_PRODUCT_CMDTECH_646: 2527 if (rev >= CMD0646U2_REV) { 2528 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2529 sc->sc_wdcdev.UDMA_cap = 2; 2530 } else if (rev >= CMD0646U_REV) { 2531 /* 2532 * Linux's driver claims that the 646U is broken 2533 * with UDMA. Only enable it if we know what we're 2534 * doing 2535 */ 2536 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2537 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2538 sc->sc_wdcdev.UDMA_cap = 2; 2539 #endif 2540 /* explicitly disable UDMA */ 2541 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2542 CMD_UDMATIM(0), 0); 2543 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2544 CMD_UDMATIM(1), 0); 2545 } 2546 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2547 break; 2548 default: 2549 sc->sc_wdcdev.irqack = pciide_irqack; 2550 } 2551 } 2552 2553 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2554 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2555 sc->sc_wdcdev.PIO_cap = 4; 2556 sc->sc_wdcdev.DMA_cap = 2; 2557 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2558 2559 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2560 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2561 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2562 DEBUG_PROBE); 2563 2564 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2565 cp = &sc->pciide_channels[channel]; 2566 cmd_channel_map(pa, sc, channel); 2567 if (cp->hw_ok == 0) 2568 continue; 2569 cmd0643_9_setup_channel(&cp->wdc_channel); 2570 } 2571 /* 2572 * note - this also makes sure we clear the irq disable and reset 2573 * bits 2574 */ 2575 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2576 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2577 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2578 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2579 DEBUG_PROBE); 2580 } 2581 2582 void 2583 cmd0643_9_setup_channel(chp) 2584 struct channel_softc *chp; 2585 { 2586 struct ata_drive_datas *drvp; 2587 u_int8_t tim; 2588 u_int32_t idedma_ctl, udma_reg; 2589 int drive; 2590 struct pciide_channel *cp = (struct pciide_channel*)chp; 2591 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2592 2593 idedma_ctl = 0; 2594 /* setup DMA if needed */ 2595 pciide_channel_dma_setup(cp); 2596 2597 for (drive = 0; drive < 2; drive++) { 2598 drvp = &chp->ch_drive[drive]; 2599 /* If no drive, skip */ 2600 if ((drvp->drive_flags & DRIVE) == 0) 2601 continue; 2602 /* add timing values, setup DMA if needed */ 2603 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2604 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2605 if (drvp->drive_flags & DRIVE_UDMA) { 2606 /* UltraDMA on a 646U2, 0648 or 0649 */ 2607 drvp->drive_flags &= ~DRIVE_DMA; 2608 udma_reg = pciide_pci_read(sc->sc_pc, 2609 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2610 if (drvp->UDMA_mode > 2 && 2611 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2612 CMD_BICSR) & 2613 CMD_BICSR_80(chp->channel)) == 0) 2614 drvp->UDMA_mode = 2; 2615 if (drvp->UDMA_mode > 2) 2616 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2617 else if (sc->sc_wdcdev.UDMA_cap > 2) 2618 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2619 udma_reg |= CMD_UDMATIM_UDMA(drive); 2620 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2621 CMD_UDMATIM_TIM_OFF(drive)); 2622 udma_reg |= 2623 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2624 CMD_UDMATIM_TIM_OFF(drive)); 2625 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2626 CMD_UDMATIM(chp->channel), udma_reg); 2627 } else { 2628 /* 2629 * use Multiword DMA. 2630 * Timings will be used for both PIO and DMA, 2631 * so adjust DMA mode if needed 2632 * if we have a 0646U2/8/9, turn off UDMA 2633 */ 2634 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2635 udma_reg = pciide_pci_read(sc->sc_pc, 2636 sc->sc_tag, 2637 CMD_UDMATIM(chp->channel)); 2638 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2639 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2640 CMD_UDMATIM(chp->channel), 2641 udma_reg); 2642 } 2643 if (drvp->PIO_mode >= 3 && 2644 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2645 drvp->DMA_mode = drvp->PIO_mode - 2; 2646 } 2647 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2648 } 2649 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2650 } 2651 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2652 CMD_DATA_TIM(chp->channel, drive), tim); 2653 } 2654 if (idedma_ctl != 0) { 2655 /* Add software bits in status register */ 2656 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2657 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2658 idedma_ctl); 2659 } 2660 pciide_print_modes(cp); 2661 } 2662 2663 void 2664 cmd646_9_irqack(chp) 2665 struct channel_softc *chp; 2666 { 2667 u_int32_t priirq, secirq; 2668 struct pciide_channel *cp = (struct pciide_channel*)chp; 2669 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2670 2671 if (chp->channel == 0) { 2672 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2673 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2674 } else { 2675 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2676 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2677 } 2678 pciide_irqack(chp); 2679 } 2680 2681 void 2682 cy693_chip_map(sc, pa) 2683 struct pciide_softc *sc; 2684 struct pci_attach_args *pa; 2685 { 2686 struct pciide_channel *cp; 2687 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2688 bus_size_t cmdsize, ctlsize; 2689 2690 if (pciide_chipen(sc, pa) == 0) 2691 return; 2692 /* 2693 * this chip has 2 PCI IDE functions, one for primary and one for 2694 * secondary. So we need to call pciide_mapregs_compat() with 2695 * the real channel 2696 */ 2697 if (pa->pa_function == 1) { 2698 sc->sc_cy_compatchan = 0; 2699 } else if (pa->pa_function == 2) { 2700 sc->sc_cy_compatchan = 1; 2701 } else { 2702 printf("%s: unexpected PCI function %d\n", 2703 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2704 return; 2705 } 2706 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2707 printf("%s: bus-master DMA support present", 2708 sc->sc_wdcdev.sc_dev.dv_xname); 2709 pciide_mapreg_dma(sc, pa); 2710 } else { 2711 printf("%s: hardware does not support DMA", 2712 sc->sc_wdcdev.sc_dev.dv_xname); 2713 sc->sc_dma_ok = 0; 2714 } 2715 printf("\n"); 2716 2717 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2718 if (sc->sc_cy_handle == NULL) { 2719 printf("%s: unable to map hyperCache control registers\n", 2720 sc->sc_wdcdev.sc_dev.dv_xname); 2721 sc->sc_dma_ok = 0; 2722 } 2723 2724 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2725 WDC_CAPABILITY_MODE; 2726 if (sc->sc_dma_ok) { 2727 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2728 sc->sc_wdcdev.irqack = pciide_irqack; 2729 } 2730 sc->sc_wdcdev.PIO_cap = 4; 2731 sc->sc_wdcdev.DMA_cap = 2; 2732 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2733 2734 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2735 sc->sc_wdcdev.nchannels = 1; 2736 2737 /* Only one channel for this chip; if we are here it's enabled */ 2738 cp = &sc->pciide_channels[0]; 2739 sc->wdc_chanarray[0] = &cp->wdc_channel; 2740 cp->name = PCIIDE_CHANNEL_NAME(0); 2741 cp->wdc_channel.channel = 0; 2742 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2743 cp->wdc_channel.ch_queue = 2744 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2745 if (cp->wdc_channel.ch_queue == NULL) { 2746 printf("%s primary channel: " 2747 "can't allocate memory for command queue", 2748 sc->sc_wdcdev.sc_dev.dv_xname); 2749 return; 2750 } 2751 printf("%s: primary channel %s to ", 2752 sc->sc_wdcdev.sc_dev.dv_xname, 2753 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2754 "configured" : "wired"); 2755 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2756 printf("native-PCI"); 2757 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2758 pciide_pci_intr); 2759 } else { 2760 printf("compatibility"); 2761 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2762 &cmdsize, &ctlsize); 2763 } 2764 printf(" mode\n"); 2765 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2766 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2767 wdcattach(&cp->wdc_channel); 2768 if (pciide_chan_candisable(cp)) { 2769 pci_conf_write(sc->sc_pc, sc->sc_tag, 2770 PCI_COMMAND_STATUS_REG, 0); 2771 } 2772 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2773 if (cp->hw_ok == 0) 2774 return; 2775 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2776 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2777 cy693_setup_channel(&cp->wdc_channel); 2778 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2779 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2780 } 2781 2782 void 2783 cy693_setup_channel(chp) 2784 struct channel_softc *chp; 2785 { 2786 struct ata_drive_datas *drvp; 2787 int drive; 2788 u_int32_t cy_cmd_ctrl; 2789 u_int32_t idedma_ctl; 2790 struct pciide_channel *cp = (struct pciide_channel*)chp; 2791 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2792 int dma_mode = -1; 2793 2794 cy_cmd_ctrl = idedma_ctl = 0; 2795 2796 /* setup DMA if needed */ 2797 pciide_channel_dma_setup(cp); 2798 2799 for (drive = 0; drive < 2; drive++) { 2800 drvp = &chp->ch_drive[drive]; 2801 /* If no drive, skip */ 2802 if ((drvp->drive_flags & DRIVE) == 0) 2803 continue; 2804 /* add timing values, setup DMA if needed */ 2805 if (drvp->drive_flags & DRIVE_DMA) { 2806 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2807 /* use Multiword DMA */ 2808 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2809 dma_mode = drvp->DMA_mode; 2810 } 2811 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2812 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2813 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2814 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2815 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2816 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2817 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2818 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2819 } 2820 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2821 chp->ch_drive[0].DMA_mode = dma_mode; 2822 chp->ch_drive[1].DMA_mode = dma_mode; 2823 2824 if (dma_mode == -1) 2825 dma_mode = 0; 2826 2827 if (sc->sc_cy_handle != NULL) { 2828 /* Note: `multiple' is implied. */ 2829 cy82c693_write(sc->sc_cy_handle, 2830 (sc->sc_cy_compatchan == 0) ? 2831 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2832 } 2833 2834 pciide_print_modes(cp); 2835 2836 if (idedma_ctl != 0) { 2837 /* Add software bits in status register */ 2838 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2839 IDEDMA_CTL, idedma_ctl); 2840 } 2841 } 2842 2843 static int 2844 sis_hostbr_match(pa) 2845 struct pci_attach_args *pa; 2846 { 2847 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2848 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2849 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2850 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2851 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2852 } 2853 2854 void 2855 sis_chip_map(sc, pa) 2856 struct pciide_softc *sc; 2857 struct pci_attach_args *pa; 2858 { 2859 struct pciide_channel *cp; 2860 int channel; 2861 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2862 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2863 pcireg_t rev = PCI_REVISION(pa->pa_class); 2864 bus_size_t cmdsize, ctlsize; 2865 pcitag_t pchb_tag; 2866 pcireg_t pchb_id, pchb_class; 2867 2868 if (pciide_chipen(sc, pa) == 0) 2869 return; 2870 printf("%s: bus-master DMA support present", 2871 sc->sc_wdcdev.sc_dev.dv_xname); 2872 pciide_mapreg_dma(sc, pa); 2873 printf("\n"); 2874 2875 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2876 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2877 /* and read ID and rev of the ISA bridge */ 2878 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2879 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2880 2881 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2882 WDC_CAPABILITY_MODE; 2883 if (sc->sc_dma_ok) { 2884 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2885 sc->sc_wdcdev.irqack = pciide_irqack; 2886 /* 2887 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2888 * have problems with UDMA (info provided by Christos) 2889 */ 2890 if (rev >= 0xd0 && 2891 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2892 PCI_REVISION(pchb_class) >= 0x03)) 2893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2894 } 2895 2896 sc->sc_wdcdev.PIO_cap = 4; 2897 sc->sc_wdcdev.DMA_cap = 2; 2898 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2899 /* 2900 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2901 * chipsets. 2902 */ 2903 sc->sc_wdcdev.UDMA_cap = 2904 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2905 sc->sc_wdcdev.set_modes = sis_setup_channel; 2906 2907 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2908 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2909 2910 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2911 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2912 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2913 2914 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2915 cp = &sc->pciide_channels[channel]; 2916 if (pciide_chansetup(sc, channel, interface) == 0) 2917 continue; 2918 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2919 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2920 printf("%s: %s channel ignored (disabled)\n", 2921 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2922 continue; 2923 } 2924 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2925 pciide_pci_intr); 2926 if (cp->hw_ok == 0) 2927 continue; 2928 if (pciide_chan_candisable(cp)) { 2929 if (channel == 0) 2930 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2931 else 2932 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2933 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2934 sis_ctr0); 2935 } 2936 pciide_map_compat_intr(pa, cp, channel, interface); 2937 if (cp->hw_ok == 0) 2938 continue; 2939 sis_setup_channel(&cp->wdc_channel); 2940 } 2941 } 2942 2943 void 2944 sis_setup_channel(chp) 2945 struct channel_softc *chp; 2946 { 2947 struct ata_drive_datas *drvp; 2948 int drive; 2949 u_int32_t sis_tim; 2950 u_int32_t idedma_ctl; 2951 struct pciide_channel *cp = (struct pciide_channel*)chp; 2952 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2953 2954 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2955 "channel %d 0x%x\n", chp->channel, 2956 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2957 DEBUG_PROBE); 2958 sis_tim = 0; 2959 idedma_ctl = 0; 2960 /* setup DMA if needed */ 2961 pciide_channel_dma_setup(cp); 2962 2963 for (drive = 0; drive < 2; drive++) { 2964 drvp = &chp->ch_drive[drive]; 2965 /* If no drive, skip */ 2966 if ((drvp->drive_flags & DRIVE) == 0) 2967 continue; 2968 /* add timing values, setup DMA if needed */ 2969 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2970 (drvp->drive_flags & DRIVE_UDMA) == 0) 2971 goto pio; 2972 2973 if (drvp->drive_flags & DRIVE_UDMA) { 2974 /* use Ultra/DMA */ 2975 drvp->drive_flags &= ~DRIVE_DMA; 2976 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2977 SIS_TIM_UDMA_TIME_OFF(drive); 2978 sis_tim |= SIS_TIM_UDMA_EN(drive); 2979 } else { 2980 /* 2981 * use Multiword DMA 2982 * Timings will be used for both PIO and DMA, 2983 * so adjust DMA mode if needed 2984 */ 2985 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2986 drvp->PIO_mode = drvp->DMA_mode + 2; 2987 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2988 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2989 drvp->PIO_mode - 2 : 0; 2990 if (drvp->DMA_mode == 0) 2991 drvp->PIO_mode = 0; 2992 } 2993 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2994 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2995 SIS_TIM_ACT_OFF(drive); 2996 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2997 SIS_TIM_REC_OFF(drive); 2998 } 2999 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3000 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3001 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3002 if (idedma_ctl != 0) { 3003 /* Add software bits in status register */ 3004 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3005 IDEDMA_CTL, idedma_ctl); 3006 } 3007 pciide_print_modes(cp); 3008 } 3009 3010 void 3011 acer_chip_map(sc, pa) 3012 struct pciide_softc *sc; 3013 struct pci_attach_args *pa; 3014 { 3015 struct pciide_channel *cp; 3016 int channel; 3017 pcireg_t cr, interface; 3018 bus_size_t cmdsize, ctlsize; 3019 pcireg_t rev = PCI_REVISION(pa->pa_class); 3020 3021 if (pciide_chipen(sc, pa) == 0) 3022 return; 3023 printf("%s: bus-master DMA support present", 3024 sc->sc_wdcdev.sc_dev.dv_xname); 3025 pciide_mapreg_dma(sc, pa); 3026 printf("\n"); 3027 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3028 WDC_CAPABILITY_MODE; 3029 if (sc->sc_dma_ok) { 3030 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3031 if (rev >= 0x20) { 3032 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3033 if (rev >= 0xC4) 3034 sc->sc_wdcdev.UDMA_cap = 5; 3035 else if (rev >= 0xC2) 3036 sc->sc_wdcdev.UDMA_cap = 4; 3037 else 3038 sc->sc_wdcdev.UDMA_cap = 2; 3039 } 3040 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3041 sc->sc_wdcdev.irqack = pciide_irqack; 3042 } 3043 3044 sc->sc_wdcdev.PIO_cap = 4; 3045 sc->sc_wdcdev.DMA_cap = 2; 3046 sc->sc_wdcdev.set_modes = acer_setup_channel; 3047 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3048 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3049 3050 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3051 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3052 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3053 3054 /* Enable "microsoft register bits" R/W. */ 3055 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3056 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3057 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3058 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3059 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3060 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3061 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3062 ~ACER_CHANSTATUSREGS_RO); 3063 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3064 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3065 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3066 /* Don't use cr, re-read the real register content instead */ 3067 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3068 PCI_CLASS_REG)); 3069 3070 /* From linux: enable "Cable Detection" */ 3071 if (rev >= 0xC2) { 3072 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3073 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3074 | ACER_0x4B_CDETECT); 3075 } 3076 3077 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3078 cp = &sc->pciide_channels[channel]; 3079 if (pciide_chansetup(sc, channel, interface) == 0) 3080 continue; 3081 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3082 printf("%s: %s channel ignored (disabled)\n", 3083 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3084 continue; 3085 } 3086 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3087 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3088 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3089 if (cp->hw_ok == 0) 3090 continue; 3091 if (pciide_chan_candisable(cp)) { 3092 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3093 pci_conf_write(sc->sc_pc, sc->sc_tag, 3094 PCI_CLASS_REG, cr); 3095 } 3096 pciide_map_compat_intr(pa, cp, channel, interface); 3097 acer_setup_channel(&cp->wdc_channel); 3098 } 3099 } 3100 3101 void 3102 acer_setup_channel(chp) 3103 struct channel_softc *chp; 3104 { 3105 struct ata_drive_datas *drvp; 3106 int drive; 3107 u_int32_t acer_fifo_udma; 3108 u_int32_t idedma_ctl; 3109 struct pciide_channel *cp = (struct pciide_channel*)chp; 3110 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3111 3112 idedma_ctl = 0; 3113 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3114 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3115 acer_fifo_udma), DEBUG_PROBE); 3116 /* setup DMA if needed */ 3117 pciide_channel_dma_setup(cp); 3118 3119 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3120 DRIVE_UDMA) { /* check 80 pins cable */ 3121 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3122 ACER_0x4A_80PIN(chp->channel)) { 3123 if (chp->ch_drive[0].UDMA_mode > 2) 3124 chp->ch_drive[0].UDMA_mode = 2; 3125 if (chp->ch_drive[1].UDMA_mode > 2) 3126 chp->ch_drive[1].UDMA_mode = 2; 3127 } 3128 } 3129 3130 for (drive = 0; drive < 2; drive++) { 3131 drvp = &chp->ch_drive[drive]; 3132 /* If no drive, skip */ 3133 if ((drvp->drive_flags & DRIVE) == 0) 3134 continue; 3135 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3136 "channel %d drive %d 0x%x\n", chp->channel, drive, 3137 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3138 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3139 /* clear FIFO/DMA mode */ 3140 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3141 ACER_UDMA_EN(chp->channel, drive) | 3142 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3143 3144 /* add timing values, setup DMA if needed */ 3145 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3146 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3147 acer_fifo_udma |= 3148 ACER_FTH_OPL(chp->channel, drive, 0x1); 3149 goto pio; 3150 } 3151 3152 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3153 if (drvp->drive_flags & DRIVE_UDMA) { 3154 /* use Ultra/DMA */ 3155 drvp->drive_flags &= ~DRIVE_DMA; 3156 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3157 acer_fifo_udma |= 3158 ACER_UDMA_TIM(chp->channel, drive, 3159 acer_udma[drvp->UDMA_mode]); 3160 /* XXX disable if one drive < UDMA3 ? */ 3161 if (drvp->UDMA_mode >= 3) { 3162 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3163 ACER_0x4B, 3164 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3165 ACER_0x4B) | ACER_0x4B_UDMA66); 3166 } 3167 } else { 3168 /* 3169 * use Multiword DMA 3170 * Timings will be used for both PIO and DMA, 3171 * so adjust DMA mode if needed 3172 */ 3173 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3174 drvp->PIO_mode = drvp->DMA_mode + 2; 3175 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3176 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3177 drvp->PIO_mode - 2 : 0; 3178 if (drvp->DMA_mode == 0) 3179 drvp->PIO_mode = 0; 3180 } 3181 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3182 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3183 ACER_IDETIM(chp->channel, drive), 3184 acer_pio[drvp->PIO_mode]); 3185 } 3186 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3187 acer_fifo_udma), DEBUG_PROBE); 3188 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3189 if (idedma_ctl != 0) { 3190 /* Add software bits in status register */ 3191 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3192 IDEDMA_CTL, idedma_ctl); 3193 } 3194 pciide_print_modes(cp); 3195 } 3196 3197 int 3198 acer_pci_intr(arg) 3199 void *arg; 3200 { 3201 struct pciide_softc *sc = arg; 3202 struct pciide_channel *cp; 3203 struct channel_softc *wdc_cp; 3204 int i, rv, crv; 3205 u_int32_t chids; 3206 3207 rv = 0; 3208 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3209 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3210 cp = &sc->pciide_channels[i]; 3211 wdc_cp = &cp->wdc_channel; 3212 /* If a compat channel skip. */ 3213 if (cp->compat) 3214 continue; 3215 if (chids & ACER_CHIDS_INT(i)) { 3216 crv = wdcintr(wdc_cp); 3217 if (crv == 0) 3218 printf("%s:%d: bogus intr\n", 3219 sc->sc_wdcdev.sc_dev.dv_xname, i); 3220 else 3221 rv = 1; 3222 } 3223 } 3224 return rv; 3225 } 3226 3227 void 3228 hpt_chip_map(sc, pa) 3229 struct pciide_softc *sc; 3230 struct pci_attach_args *pa; 3231 { 3232 struct pciide_channel *cp; 3233 int i, compatchan, revision; 3234 pcireg_t interface; 3235 bus_size_t cmdsize, ctlsize; 3236 3237 if (pciide_chipen(sc, pa) == 0) 3238 return; 3239 revision = PCI_REVISION(pa->pa_class); 3240 printf(": Triones/Highpoint "); 3241 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3242 printf("HPT374 IDE Controller\n"); 3243 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3244 if (revision == HPT370_REV) 3245 printf("HPT370 IDE Controller\n"); 3246 else if (revision == HPT370A_REV) 3247 printf("HPT370A IDE Controller\n"); 3248 else if (revision == HPT366_REV) 3249 printf("HPT366 IDE Controller\n"); 3250 else 3251 printf("unknown HPT IDE controller rev %d\n", revision); 3252 } else 3253 printf("unknown HPT IDE controller 0x%x\n", 3254 sc->sc_pp->ide_product); 3255 3256 /* 3257 * when the chip is in native mode it identifies itself as a 3258 * 'misc mass storage'. Fake interface in this case. 3259 */ 3260 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3261 interface = PCI_INTERFACE(pa->pa_class); 3262 } else { 3263 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3264 PCIIDE_INTERFACE_PCI(0); 3265 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3266 (revision == HPT370_REV || revision == HPT370A_REV)) || 3267 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3268 interface |= PCIIDE_INTERFACE_PCI(1); 3269 } 3270 3271 printf("%s: bus-master DMA support present", 3272 sc->sc_wdcdev.sc_dev.dv_xname); 3273 pciide_mapreg_dma(sc, pa); 3274 printf("\n"); 3275 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3276 WDC_CAPABILITY_MODE; 3277 if (sc->sc_dma_ok) { 3278 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3279 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3280 sc->sc_wdcdev.irqack = pciide_irqack; 3281 } 3282 sc->sc_wdcdev.PIO_cap = 4; 3283 sc->sc_wdcdev.DMA_cap = 2; 3284 3285 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3286 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3287 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3288 revision == HPT366_REV) { 3289 sc->sc_wdcdev.UDMA_cap = 4; 3290 /* 3291 * The 366 has 2 PCI IDE functions, one for primary and one 3292 * for secondary. So we need to call pciide_mapregs_compat() 3293 * with the real channel 3294 */ 3295 if (pa->pa_function == 0) { 3296 compatchan = 0; 3297 } else if (pa->pa_function == 1) { 3298 compatchan = 1; 3299 } else { 3300 printf("%s: unexpected PCI function %d\n", 3301 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3302 return; 3303 } 3304 sc->sc_wdcdev.nchannels = 1; 3305 } else { 3306 sc->sc_wdcdev.nchannels = 2; 3307 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3308 sc->sc_wdcdev.UDMA_cap = 6; 3309 else 3310 sc->sc_wdcdev.UDMA_cap = 5; 3311 } 3312 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3313 cp = &sc->pciide_channels[i]; 3314 if (sc->sc_wdcdev.nchannels > 1) { 3315 compatchan = i; 3316 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3317 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3318 printf("%s: %s channel ignored (disabled)\n", 3319 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3320 continue; 3321 } 3322 } 3323 if (pciide_chansetup(sc, i, interface) == 0) 3324 continue; 3325 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3326 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3327 &ctlsize, hpt_pci_intr); 3328 } else { 3329 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3330 &cmdsize, &ctlsize); 3331 } 3332 if (cp->hw_ok == 0) 3333 return; 3334 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3335 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3336 wdcattach(&cp->wdc_channel); 3337 hpt_setup_channel(&cp->wdc_channel); 3338 } 3339 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3340 (revision == HPT370_REV || revision == HPT370A_REV)) || 3341 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3342 /* 3343 * HPT370_REV and highter has a bit to disable interrupts, 3344 * make sure to clear it 3345 */ 3346 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3347 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3348 ~HPT_CSEL_IRQDIS); 3349 } 3350 /* set clocks, etc (mandatory on 374, optional otherwise) */ 3351 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3352 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3353 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3354 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3355 return; 3356 } 3357 3358 void 3359 hpt_setup_channel(chp) 3360 struct channel_softc *chp; 3361 { 3362 struct ata_drive_datas *drvp; 3363 int drive; 3364 int cable; 3365 u_int32_t before, after; 3366 u_int32_t idedma_ctl; 3367 struct pciide_channel *cp = (struct pciide_channel*)chp; 3368 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3369 3370 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3371 3372 /* setup DMA if needed */ 3373 pciide_channel_dma_setup(cp); 3374 3375 idedma_ctl = 0; 3376 3377 /* Per drive settings */ 3378 for (drive = 0; drive < 2; drive++) { 3379 drvp = &chp->ch_drive[drive]; 3380 /* If no drive, skip */ 3381 if ((drvp->drive_flags & DRIVE) == 0) 3382 continue; 3383 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3384 HPT_IDETIM(chp->channel, drive)); 3385 3386 /* add timing values, setup DMA if needed */ 3387 if (drvp->drive_flags & DRIVE_UDMA) { 3388 /* use Ultra/DMA */ 3389 drvp->drive_flags &= ~DRIVE_DMA; 3390 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3391 drvp->UDMA_mode > 2) 3392 drvp->UDMA_mode = 2; 3393 after = (sc->sc_wdcdev.nchannels == 2) ? 3394 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3395 hpt374_udma[drvp->UDMA_mode] : 3396 hpt370_udma[drvp->UDMA_mode]) : 3397 hpt366_udma[drvp->UDMA_mode]; 3398 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3399 } else if (drvp->drive_flags & DRIVE_DMA) { 3400 /* 3401 * use Multiword DMA. 3402 * Timings will be used for both PIO and DMA, so adjust 3403 * DMA mode if needed 3404 */ 3405 if (drvp->PIO_mode >= 3 && 3406 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3407 drvp->DMA_mode = drvp->PIO_mode - 2; 3408 } 3409 after = (sc->sc_wdcdev.nchannels == 2) ? 3410 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3411 hpt374_dma[drvp->DMA_mode] : 3412 hpt370_dma[drvp->DMA_mode]) : 3413 hpt366_dma[drvp->DMA_mode]; 3414 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3415 } else { 3416 /* PIO only */ 3417 after = (sc->sc_wdcdev.nchannels == 2) ? 3418 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3419 hpt374_pio[drvp->PIO_mode] : 3420 hpt370_pio[drvp->PIO_mode]) : 3421 hpt366_pio[drvp->PIO_mode]; 3422 } 3423 pci_conf_write(sc->sc_pc, sc->sc_tag, 3424 HPT_IDETIM(chp->channel, drive), after); 3425 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3426 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3427 after, before), DEBUG_PROBE); 3428 } 3429 if (idedma_ctl != 0) { 3430 /* Add software bits in status register */ 3431 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3432 IDEDMA_CTL, idedma_ctl); 3433 } 3434 pciide_print_modes(cp); 3435 } 3436 3437 int 3438 hpt_pci_intr(arg) 3439 void *arg; 3440 { 3441 struct pciide_softc *sc = arg; 3442 struct pciide_channel *cp; 3443 struct channel_softc *wdc_cp; 3444 int rv = 0; 3445 int dmastat, i, crv; 3446 3447 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3448 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3449 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3450 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3451 IDEDMA_CTL_INTR) 3452 continue; 3453 cp = &sc->pciide_channels[i]; 3454 wdc_cp = &cp->wdc_channel; 3455 crv = wdcintr(wdc_cp); 3456 if (crv == 0) { 3457 printf("%s:%d: bogus intr\n", 3458 sc->sc_wdcdev.sc_dev.dv_xname, i); 3459 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3460 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3461 } else 3462 rv = 1; 3463 } 3464 return rv; 3465 } 3466 3467 3468 /* Macros to test product */ 3469 #define PDC_IS_262(sc) \ 3470 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3471 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3472 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3473 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3474 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3475 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3476 #define PDC_IS_265(sc) \ 3477 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3478 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3479 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3480 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3481 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3482 #define PDC_IS_268(sc) \ 3483 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3484 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3485 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3486 3487 void 3488 pdc202xx_chip_map(sc, pa) 3489 struct pciide_softc *sc; 3490 struct pci_attach_args *pa; 3491 { 3492 struct pciide_channel *cp; 3493 int channel; 3494 pcireg_t interface, st, mode; 3495 bus_size_t cmdsize, ctlsize; 3496 3497 if (!PDC_IS_268(sc)) { 3498 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3499 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3500 st), DEBUG_PROBE); 3501 } 3502 if (pciide_chipen(sc, pa) == 0) 3503 return; 3504 3505 /* turn off RAID mode */ 3506 if (!PDC_IS_268(sc)) 3507 st &= ~PDC2xx_STATE_IDERAID; 3508 3509 /* 3510 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3511 * mode. We have to fake interface 3512 */ 3513 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3514 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3515 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3516 3517 printf("%s: bus-master DMA support present", 3518 sc->sc_wdcdev.sc_dev.dv_xname); 3519 pciide_mapreg_dma(sc, pa); 3520 printf("\n"); 3521 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3522 WDC_CAPABILITY_MODE; 3523 if (sc->sc_dma_ok) { 3524 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3525 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3526 sc->sc_wdcdev.irqack = pciide_irqack; 3527 } 3528 sc->sc_wdcdev.PIO_cap = 4; 3529 sc->sc_wdcdev.DMA_cap = 2; 3530 if (PDC_IS_265(sc)) 3531 sc->sc_wdcdev.UDMA_cap = 5; 3532 else if (PDC_IS_262(sc)) 3533 sc->sc_wdcdev.UDMA_cap = 4; 3534 else 3535 sc->sc_wdcdev.UDMA_cap = 2; 3536 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3537 pdc20268_setup_channel : pdc202xx_setup_channel; 3538 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3539 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3540 3541 if (!PDC_IS_268(sc)) { 3542 /* setup failsafe defaults */ 3543 mode = 0; 3544 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3545 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3546 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3547 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3548 for (channel = 0; 3549 channel < sc->sc_wdcdev.nchannels; 3550 channel++) { 3551 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3552 "drive 0 initial timings 0x%x, now 0x%x\n", 3553 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3554 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3555 DEBUG_PROBE); 3556 pci_conf_write(sc->sc_pc, sc->sc_tag, 3557 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3558 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3559 "drive 1 initial timings 0x%x, now 0x%x\n", 3560 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3561 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3562 pci_conf_write(sc->sc_pc, sc->sc_tag, 3563 PDC2xx_TIM(channel, 1), mode); 3564 } 3565 3566 mode = PDC2xx_SCR_DMA; 3567 if (PDC_IS_262(sc)) { 3568 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3569 } else { 3570 /* the BIOS set it up this way */ 3571 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3572 } 3573 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3574 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3575 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3576 "now 0x%x\n", 3577 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3578 PDC2xx_SCR), 3579 mode), DEBUG_PROBE); 3580 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3581 PDC2xx_SCR, mode); 3582 3583 /* controller initial state register is OK even without BIOS */ 3584 /* Set DMA mode to IDE DMA compatibility */ 3585 mode = 3586 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3587 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3588 DEBUG_PROBE); 3589 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3590 mode | 0x1); 3591 mode = 3592 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3593 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3594 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3595 mode | 0x1); 3596 } 3597 3598 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3599 cp = &sc->pciide_channels[channel]; 3600 if (pciide_chansetup(sc, channel, interface) == 0) 3601 continue; 3602 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3603 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3604 printf("%s: %s channel ignored (disabled)\n", 3605 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3606 continue; 3607 } 3608 if (PDC_IS_265(sc)) 3609 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3610 pdc20265_pci_intr); 3611 else 3612 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3613 pdc202xx_pci_intr); 3614 if (cp->hw_ok == 0) 3615 continue; 3616 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3617 st &= ~(PDC_IS_262(sc) ? 3618 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3619 pciide_map_compat_intr(pa, cp, channel, interface); 3620 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3621 } 3622 if (!PDC_IS_268(sc)) { 3623 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3624 "0x%x\n", st), DEBUG_PROBE); 3625 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3626 } 3627 return; 3628 } 3629 3630 void 3631 pdc202xx_setup_channel(chp) 3632 struct channel_softc *chp; 3633 { 3634 struct ata_drive_datas *drvp; 3635 int drive; 3636 pcireg_t mode, st; 3637 u_int32_t idedma_ctl, scr, atapi; 3638 struct pciide_channel *cp = (struct pciide_channel*)chp; 3639 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3640 int channel = chp->channel; 3641 3642 /* setup DMA if needed */ 3643 pciide_channel_dma_setup(cp); 3644 3645 idedma_ctl = 0; 3646 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3647 sc->sc_wdcdev.sc_dev.dv_xname, 3648 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3649 DEBUG_PROBE); 3650 3651 /* Per channel settings */ 3652 if (PDC_IS_262(sc)) { 3653 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3654 PDC262_U66); 3655 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3656 /* Trim UDMA mode */ 3657 if ((st & PDC262_STATE_80P(channel)) != 0 || 3658 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3659 chp->ch_drive[0].UDMA_mode <= 2) || 3660 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3661 chp->ch_drive[1].UDMA_mode <= 2)) { 3662 if (chp->ch_drive[0].UDMA_mode > 2) 3663 chp->ch_drive[0].UDMA_mode = 2; 3664 if (chp->ch_drive[1].UDMA_mode > 2) 3665 chp->ch_drive[1].UDMA_mode = 2; 3666 } 3667 /* Set U66 if needed */ 3668 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3669 chp->ch_drive[0].UDMA_mode > 2) || 3670 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3671 chp->ch_drive[1].UDMA_mode > 2)) 3672 scr |= PDC262_U66_EN(channel); 3673 else 3674 scr &= ~PDC262_U66_EN(channel); 3675 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3676 PDC262_U66, scr); 3677 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3678 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3679 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3680 PDC262_ATAPI(channel))), DEBUG_PROBE); 3681 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3682 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3683 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3684 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3685 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3686 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3687 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3688 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3689 atapi = 0; 3690 else 3691 atapi = PDC262_ATAPI_UDMA; 3692 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3693 PDC262_ATAPI(channel), atapi); 3694 } 3695 } 3696 for (drive = 0; drive < 2; drive++) { 3697 drvp = &chp->ch_drive[drive]; 3698 /* If no drive, skip */ 3699 if ((drvp->drive_flags & DRIVE) == 0) 3700 continue; 3701 mode = 0; 3702 if (drvp->drive_flags & DRIVE_UDMA) { 3703 /* use Ultra/DMA */ 3704 drvp->drive_flags &= ~DRIVE_DMA; 3705 mode = PDC2xx_TIM_SET_MB(mode, 3706 pdc2xx_udma_mb[drvp->UDMA_mode]); 3707 mode = PDC2xx_TIM_SET_MC(mode, 3708 pdc2xx_udma_mc[drvp->UDMA_mode]); 3709 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3710 } else if (drvp->drive_flags & DRIVE_DMA) { 3711 mode = PDC2xx_TIM_SET_MB(mode, 3712 pdc2xx_dma_mb[drvp->DMA_mode]); 3713 mode = PDC2xx_TIM_SET_MC(mode, 3714 pdc2xx_dma_mc[drvp->DMA_mode]); 3715 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3716 } else { 3717 mode = PDC2xx_TIM_SET_MB(mode, 3718 pdc2xx_dma_mb[0]); 3719 mode = PDC2xx_TIM_SET_MC(mode, 3720 pdc2xx_dma_mc[0]); 3721 } 3722 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3723 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3724 if (drvp->drive_flags & DRIVE_ATA) 3725 mode |= PDC2xx_TIM_PRE; 3726 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3727 if (drvp->PIO_mode >= 3) { 3728 mode |= PDC2xx_TIM_IORDY; 3729 if (drive == 0) 3730 mode |= PDC2xx_TIM_IORDYp; 3731 } 3732 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3733 "timings 0x%x\n", 3734 sc->sc_wdcdev.sc_dev.dv_xname, 3735 chp->channel, drive, mode), DEBUG_PROBE); 3736 pci_conf_write(sc->sc_pc, sc->sc_tag, 3737 PDC2xx_TIM(chp->channel, drive), mode); 3738 } 3739 if (idedma_ctl != 0) { 3740 /* Add software bits in status register */ 3741 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3742 IDEDMA_CTL, idedma_ctl); 3743 } 3744 pciide_print_modes(cp); 3745 } 3746 3747 void 3748 pdc20268_setup_channel(chp) 3749 struct channel_softc *chp; 3750 { 3751 struct ata_drive_datas *drvp; 3752 int drive; 3753 u_int32_t idedma_ctl; 3754 struct pciide_channel *cp = (struct pciide_channel*)chp; 3755 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3756 int u100; 3757 3758 /* setup DMA if needed */ 3759 pciide_channel_dma_setup(cp); 3760 3761 idedma_ctl = 0; 3762 3763 /* I don't know what this is for, FreeBSD does it ... */ 3764 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3765 IDEDMA_CMD + 0x1, 0x0b); 3766 3767 /* 3768 * I don't know what this is for; FreeBSD checks this ... this is not 3769 * cable type detect. 3770 */ 3771 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3772 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3773 3774 for (drive = 0; drive < 2; drive++) { 3775 drvp = &chp->ch_drive[drive]; 3776 /* If no drive, skip */ 3777 if ((drvp->drive_flags & DRIVE) == 0) 3778 continue; 3779 if (drvp->drive_flags & DRIVE_UDMA) { 3780 /* use Ultra/DMA */ 3781 drvp->drive_flags &= ~DRIVE_DMA; 3782 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3783 if (drvp->UDMA_mode > 2 && u100 == 0) 3784 drvp->UDMA_mode = 2; 3785 } else if (drvp->drive_flags & DRIVE_DMA) { 3786 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3787 } 3788 } 3789 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3790 if (idedma_ctl != 0) { 3791 /* Add software bits in status register */ 3792 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3793 IDEDMA_CTL, idedma_ctl); 3794 } 3795 pciide_print_modes(cp); 3796 } 3797 3798 int 3799 pdc202xx_pci_intr(arg) 3800 void *arg; 3801 { 3802 struct pciide_softc *sc = arg; 3803 struct pciide_channel *cp; 3804 struct channel_softc *wdc_cp; 3805 int i, rv, crv; 3806 u_int32_t scr; 3807 3808 rv = 0; 3809 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3810 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3811 cp = &sc->pciide_channels[i]; 3812 wdc_cp = &cp->wdc_channel; 3813 /* If a compat channel skip. */ 3814 if (cp->compat) 3815 continue; 3816 if (scr & PDC2xx_SCR_INT(i)) { 3817 crv = wdcintr(wdc_cp); 3818 if (crv == 0) 3819 printf("%s:%d: bogus intr (reg 0x%x)\n", 3820 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3821 else 3822 rv = 1; 3823 } 3824 } 3825 return rv; 3826 } 3827 3828 int 3829 pdc20265_pci_intr(arg) 3830 void *arg; 3831 { 3832 struct pciide_softc *sc = arg; 3833 struct pciide_channel *cp; 3834 struct channel_softc *wdc_cp; 3835 int i, rv, crv; 3836 u_int32_t dmastat; 3837 3838 rv = 0; 3839 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3840 cp = &sc->pciide_channels[i]; 3841 wdc_cp = &cp->wdc_channel; 3842 /* If a compat channel skip. */ 3843 if (cp->compat) 3844 continue; 3845 /* 3846 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3847 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3848 * So use it instead (requires 2 reg reads instead of 1, 3849 * but we can't do it another way). 3850 */ 3851 dmastat = bus_space_read_1(sc->sc_dma_iot, 3852 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3853 if((dmastat & IDEDMA_CTL_INTR) == 0) 3854 continue; 3855 crv = wdcintr(wdc_cp); 3856 if (crv == 0) 3857 printf("%s:%d: bogus intr\n", 3858 sc->sc_wdcdev.sc_dev.dv_xname, i); 3859 else 3860 rv = 1; 3861 } 3862 return rv; 3863 } 3864 3865 void 3866 opti_chip_map(sc, pa) 3867 struct pciide_softc *sc; 3868 struct pci_attach_args *pa; 3869 { 3870 struct pciide_channel *cp; 3871 bus_size_t cmdsize, ctlsize; 3872 pcireg_t interface; 3873 u_int8_t init_ctrl; 3874 int channel; 3875 3876 if (pciide_chipen(sc, pa) == 0) 3877 return; 3878 printf("%s: bus-master DMA support present", 3879 sc->sc_wdcdev.sc_dev.dv_xname); 3880 3881 /* 3882 * XXXSCW: 3883 * There seem to be a couple of buggy revisions/implementations 3884 * of the OPTi pciide chipset. This kludge seems to fix one of 3885 * the reported problems (PR/11644) but still fails for the 3886 * other (PR/13151), although the latter may be due to other 3887 * issues too... 3888 */ 3889 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3890 printf(" but disabled due to chip rev. <= 0x12"); 3891 sc->sc_dma_ok = 0; 3892 } else 3893 pciide_mapreg_dma(sc, pa); 3894 3895 printf("\n"); 3896 3897 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 3898 WDC_CAPABILITY_MODE; 3899 sc->sc_wdcdev.PIO_cap = 4; 3900 if (sc->sc_dma_ok) { 3901 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3902 sc->sc_wdcdev.irqack = pciide_irqack; 3903 sc->sc_wdcdev.DMA_cap = 2; 3904 } 3905 sc->sc_wdcdev.set_modes = opti_setup_channel; 3906 3907 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3908 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3909 3910 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3911 OPTI_REG_INIT_CONTROL); 3912 3913 interface = PCI_INTERFACE(pa->pa_class); 3914 3915 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3916 cp = &sc->pciide_channels[channel]; 3917 if (pciide_chansetup(sc, channel, interface) == 0) 3918 continue; 3919 if (channel == 1 && 3920 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3921 printf("%s: %s channel ignored (disabled)\n", 3922 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3923 continue; 3924 } 3925 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3926 pciide_pci_intr); 3927 if (cp->hw_ok == 0) 3928 continue; 3929 pciide_map_compat_intr(pa, cp, channel, interface); 3930 if (cp->hw_ok == 0) 3931 continue; 3932 opti_setup_channel(&cp->wdc_channel); 3933 } 3934 } 3935 3936 void 3937 opti_setup_channel(chp) 3938 struct channel_softc *chp; 3939 { 3940 struct ata_drive_datas *drvp; 3941 struct pciide_channel *cp = (struct pciide_channel*)chp; 3942 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3943 int drive, spd; 3944 int mode[2]; 3945 u_int8_t rv, mr; 3946 3947 /* 3948 * The `Delay' and `Address Setup Time' fields of the 3949 * Miscellaneous Register are always zero initially. 3950 */ 3951 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3952 mr &= ~(OPTI_MISC_DELAY_MASK | 3953 OPTI_MISC_ADDR_SETUP_MASK | 3954 OPTI_MISC_INDEX_MASK); 3955 3956 /* Prime the control register before setting timing values */ 3957 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3958 3959 /* Determine the clockrate of the PCIbus the chip is attached to */ 3960 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3961 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3962 3963 /* setup DMA if needed */ 3964 pciide_channel_dma_setup(cp); 3965 3966 for (drive = 0; drive < 2; drive++) { 3967 drvp = &chp->ch_drive[drive]; 3968 /* If no drive, skip */ 3969 if ((drvp->drive_flags & DRIVE) == 0) { 3970 mode[drive] = -1; 3971 continue; 3972 } 3973 3974 if ((drvp->drive_flags & DRIVE_DMA)) { 3975 /* 3976 * Timings will be used for both PIO and DMA, 3977 * so adjust DMA mode if needed 3978 */ 3979 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3980 drvp->PIO_mode = drvp->DMA_mode + 2; 3981 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3982 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3983 drvp->PIO_mode - 2 : 0; 3984 if (drvp->DMA_mode == 0) 3985 drvp->PIO_mode = 0; 3986 3987 mode[drive] = drvp->DMA_mode + 5; 3988 } else 3989 mode[drive] = drvp->PIO_mode; 3990 3991 if (drive && mode[0] >= 0 && 3992 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3993 /* 3994 * Can't have two drives using different values 3995 * for `Address Setup Time'. 3996 * Slow down the faster drive to compensate. 3997 */ 3998 int d = (opti_tim_as[spd][mode[0]] > 3999 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4000 4001 mode[d] = mode[1-d]; 4002 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4003 chp->ch_drive[d].DMA_mode = 0; 4004 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4005 } 4006 } 4007 4008 for (drive = 0; drive < 2; drive++) { 4009 int m; 4010 if ((m = mode[drive]) < 0) 4011 continue; 4012 4013 /* Set the Address Setup Time and select appropriate index */ 4014 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4015 rv |= OPTI_MISC_INDEX(drive); 4016 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4017 4018 /* Set the pulse width and recovery timing parameters */ 4019 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4020 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4021 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4022 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4023 4024 /* Set the Enhanced Mode register appropriately */ 4025 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4026 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4027 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4028 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4029 } 4030 4031 /* Finally, enable the timings */ 4032 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4033 4034 pciide_print_modes(cp); 4035 } 4036 4037 #define ACARD_IS_850(sc) \ 4038 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4039 4040 void 4041 acard_chip_map(sc, pa) 4042 struct pciide_softc *sc; 4043 struct pci_attach_args *pa; 4044 { 4045 struct pciide_channel *cp; 4046 int i; 4047 pcireg_t interface; 4048 bus_size_t cmdsize, ctlsize; 4049 4050 if (pciide_chipen(sc, pa) == 0) 4051 return; 4052 4053 /* 4054 * when the chip is in native mode it identifies itself as a 4055 * 'misc mass storage'. Fake interface in this case. 4056 */ 4057 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4058 interface = PCI_INTERFACE(pa->pa_class); 4059 } else { 4060 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4061 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4062 } 4063 4064 printf("%s: bus-master DMA support present", 4065 sc->sc_wdcdev.sc_dev.dv_xname); 4066 pciide_mapreg_dma(sc, pa); 4067 printf("\n"); 4068 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4069 WDC_CAPABILITY_MODE; 4070 4071 if (sc->sc_dma_ok) { 4072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4073 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4074 sc->sc_wdcdev.irqack = pciide_irqack; 4075 } 4076 sc->sc_wdcdev.PIO_cap = 4; 4077 sc->sc_wdcdev.DMA_cap = 2; 4078 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4079 4080 sc->sc_wdcdev.set_modes = acard_setup_channel; 4081 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4082 sc->sc_wdcdev.nchannels = 2; 4083 4084 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4085 cp = &sc->pciide_channels[i]; 4086 if (pciide_chansetup(sc, i, interface) == 0) 4087 continue; 4088 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4089 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4090 &ctlsize, pciide_pci_intr); 4091 } else { 4092 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4093 &cmdsize, &ctlsize); 4094 } 4095 if (cp->hw_ok == 0) 4096 return; 4097 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4098 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4099 wdcattach(&cp->wdc_channel); 4100 acard_setup_channel(&cp->wdc_channel); 4101 } 4102 if (!ACARD_IS_850(sc)) { 4103 u_int32_t reg; 4104 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4105 reg &= ~ATP860_CTRL_INT; 4106 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4107 } 4108 } 4109 4110 void 4111 acard_setup_channel(chp) 4112 struct channel_softc *chp; 4113 { 4114 struct ata_drive_datas *drvp; 4115 struct pciide_channel *cp = (struct pciide_channel*)chp; 4116 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4117 int channel = chp->channel; 4118 int drive; 4119 u_int32_t idetime, udma_mode; 4120 u_int32_t idedma_ctl; 4121 4122 /* setup DMA if needed */ 4123 pciide_channel_dma_setup(cp); 4124 4125 if (ACARD_IS_850(sc)) { 4126 idetime = 0; 4127 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4128 udma_mode &= ~ATP850_UDMA_MASK(channel); 4129 } else { 4130 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4131 idetime &= ~ATP860_SETTIME_MASK(channel); 4132 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4133 udma_mode &= ~ATP860_UDMA_MASK(channel); 4134 4135 /* check 80 pins cable */ 4136 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4137 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4138 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4139 & ATP860_CTRL_80P(chp->channel)) { 4140 if (chp->ch_drive[0].UDMA_mode > 2) 4141 chp->ch_drive[0].UDMA_mode = 2; 4142 if (chp->ch_drive[1].UDMA_mode > 2) 4143 chp->ch_drive[1].UDMA_mode = 2; 4144 } 4145 } 4146 } 4147 4148 idedma_ctl = 0; 4149 4150 /* Per drive settings */ 4151 for (drive = 0; drive < 2; drive++) { 4152 drvp = &chp->ch_drive[drive]; 4153 /* If no drive, skip */ 4154 if ((drvp->drive_flags & DRIVE) == 0) 4155 continue; 4156 /* add timing values, setup DMA if needed */ 4157 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4158 (drvp->drive_flags & DRIVE_UDMA)) { 4159 /* use Ultra/DMA */ 4160 if (ACARD_IS_850(sc)) { 4161 idetime |= ATP850_SETTIME(drive, 4162 acard_act_udma[drvp->UDMA_mode], 4163 acard_rec_udma[drvp->UDMA_mode]); 4164 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4165 acard_udma_conf[drvp->UDMA_mode]); 4166 } else { 4167 idetime |= ATP860_SETTIME(channel, drive, 4168 acard_act_udma[drvp->UDMA_mode], 4169 acard_rec_udma[drvp->UDMA_mode]); 4170 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4171 acard_udma_conf[drvp->UDMA_mode]); 4172 } 4173 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4174 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4175 (drvp->drive_flags & DRIVE_DMA)) { 4176 /* use Multiword DMA */ 4177 drvp->drive_flags &= ~DRIVE_UDMA; 4178 if (ACARD_IS_850(sc)) { 4179 idetime |= ATP850_SETTIME(drive, 4180 acard_act_dma[drvp->DMA_mode], 4181 acard_rec_dma[drvp->DMA_mode]); 4182 } else { 4183 idetime |= ATP860_SETTIME(channel, drive, 4184 acard_act_dma[drvp->DMA_mode], 4185 acard_rec_dma[drvp->DMA_mode]); 4186 } 4187 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4188 } else { 4189 /* PIO only */ 4190 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4191 if (ACARD_IS_850(sc)) { 4192 idetime |= ATP850_SETTIME(drive, 4193 acard_act_pio[drvp->PIO_mode], 4194 acard_rec_pio[drvp->PIO_mode]); 4195 } else { 4196 idetime |= ATP860_SETTIME(channel, drive, 4197 acard_act_pio[drvp->PIO_mode], 4198 acard_rec_pio[drvp->PIO_mode]); 4199 } 4200 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4201 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4202 | ATP8x0_CTRL_EN(channel)); 4203 } 4204 } 4205 4206 if (idedma_ctl != 0) { 4207 /* Add software bits in status register */ 4208 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4209 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4210 } 4211 pciide_print_modes(cp); 4212 4213 if (ACARD_IS_850(sc)) { 4214 pci_conf_write(sc->sc_pc, sc->sc_tag, 4215 ATP850_IDETIME(channel), idetime); 4216 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4217 } else { 4218 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4219 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4220 } 4221 } 4222 4223 int 4224 acard_pci_intr(arg) 4225 void *arg; 4226 { 4227 struct pciide_softc *sc = arg; 4228 struct pciide_channel *cp; 4229 struct channel_softc *wdc_cp; 4230 int rv = 0; 4231 int dmastat, i, crv; 4232 4233 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4234 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4235 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4236 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4237 continue; 4238 cp = &sc->pciide_channels[i]; 4239 wdc_cp = &cp->wdc_channel; 4240 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4241 (void)wdcintr(wdc_cp); 4242 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4243 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4244 continue; 4245 } 4246 crv = wdcintr(wdc_cp); 4247 if (crv == 0) 4248 printf("%s:%d: bogus intr\n", 4249 sc->sc_wdcdev.sc_dev.dv_xname, i); 4250 else if (crv == 1) 4251 rv = 1; 4252 else if (rv == 0) 4253 rv = crv; 4254 } 4255 return rv; 4256 } 4257 4258 static int 4259 sl82c105_bugchk(struct pci_attach_args *pa) 4260 { 4261 4262 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4263 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4264 return (0); 4265 4266 if (PCI_REVISION(pa->pa_class) <= 0x05) 4267 return (1); 4268 4269 return (0); 4270 } 4271 4272 void 4273 sl82c105_chip_map(sc, pa) 4274 struct pciide_softc *sc; 4275 struct pci_attach_args *pa; 4276 { 4277 struct pciide_channel *cp; 4278 bus_size_t cmdsize, ctlsize; 4279 pcireg_t interface, idecr; 4280 int channel; 4281 4282 if (pciide_chipen(sc, pa) == 0) 4283 return; 4284 4285 printf("%s: bus-master DMA support present", 4286 sc->sc_wdcdev.sc_dev.dv_xname); 4287 4288 /* 4289 * Check to see if we're part of the Winbond 83c553 Southbridge. 4290 * If so, we need to disable DMA on rev. <= 5 of that chip. 4291 */ 4292 if (pci_find_device(pa, sl82c105_bugchk)) { 4293 printf(" but disabled due to 83c553 rev. <= 0x05"); 4294 sc->sc_dma_ok = 0; 4295 } else 4296 pciide_mapreg_dma(sc, pa); 4297 printf("\n"); 4298 4299 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4300 WDC_CAPABILITY_MODE; 4301 sc->sc_wdcdev.PIO_cap = 4; 4302 if (sc->sc_dma_ok) { 4303 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4304 sc->sc_wdcdev.irqack = pciide_irqack; 4305 sc->sc_wdcdev.DMA_cap = 2; 4306 } 4307 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4308 4309 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4310 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4311 4312 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4313 4314 interface = PCI_INTERFACE(pa->pa_class); 4315 4316 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4317 cp = &sc->pciide_channels[channel]; 4318 if (pciide_chansetup(sc, channel, interface) == 0) 4319 continue; 4320 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4321 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4322 printf("%s: %s channel ignored (disabled)\n", 4323 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4324 continue; 4325 } 4326 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4327 pciide_pci_intr); 4328 if (cp->hw_ok == 0) 4329 continue; 4330 pciide_map_compat_intr(pa, cp, channel, interface); 4331 if (cp->hw_ok == 0) 4332 continue; 4333 sl82c105_setup_channel(&cp->wdc_channel); 4334 } 4335 } 4336 4337 void 4338 sl82c105_setup_channel(chp) 4339 struct channel_softc *chp; 4340 { 4341 struct ata_drive_datas *drvp; 4342 struct pciide_channel *cp = (struct pciide_channel*)chp; 4343 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4344 int pxdx_reg, drive; 4345 pcireg_t pxdx; 4346 4347 /* Set up DMA if needed. */ 4348 pciide_channel_dma_setup(cp); 4349 4350 for (drive = 0; drive < 2; drive++) { 4351 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4352 : SYMPH_P1D0CR) + (drive * 4); 4353 4354 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4355 4356 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4357 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4358 4359 drvp = &chp->ch_drive[drive]; 4360 /* If no drive, skip. */ 4361 if ((drvp->drive_flags & DRIVE) == 0) { 4362 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4363 continue; 4364 } 4365 4366 if (drvp->drive_flags & DRIVE_DMA) { 4367 /* 4368 * Timings will be used for both PIO and DMA, 4369 * so adjust DMA mode if needed. 4370 */ 4371 if (drvp->PIO_mode >= 3) { 4372 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4373 drvp->DMA_mode = drvp->PIO_mode - 2; 4374 if (drvp->DMA_mode < 1) { 4375 /* 4376 * Can't mix both PIO and DMA. 4377 * Disable DMA. 4378 */ 4379 drvp->drive_flags &= ~DRIVE_DMA; 4380 } 4381 } else { 4382 /* 4383 * Can't mix both PIO and DMA. Disable 4384 * DMA. 4385 */ 4386 drvp->drive_flags &= ~DRIVE_DMA; 4387 } 4388 } 4389 4390 if (drvp->drive_flags & DRIVE_DMA) { 4391 /* Use multi-word DMA. */ 4392 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4393 PxDx_CMD_ON_SHIFT; 4394 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4395 } else { 4396 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4397 PxDx_CMD_ON_SHIFT; 4398 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4399 } 4400 4401 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4402 4403 /* ...and set the mode for this drive. */ 4404 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4405 } 4406 4407 pciide_print_modes(cp); 4408 } 4409 4410 void 4411 serverworks_chip_map(sc, pa) 4412 struct pciide_softc *sc; 4413 struct pci_attach_args *pa; 4414 { 4415 struct pciide_channel *cp; 4416 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4417 pcitag_t pcib_tag; 4418 int channel; 4419 bus_size_t cmdsize, ctlsize; 4420 4421 if (pciide_chipen(sc, pa) == 0) 4422 return; 4423 4424 printf("%s: bus-master DMA support present", 4425 sc->sc_wdcdev.sc_dev.dv_xname); 4426 pciide_mapreg_dma(sc, pa); 4427 printf("\n"); 4428 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4429 WDC_CAPABILITY_MODE; 4430 4431 if (sc->sc_dma_ok) { 4432 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4433 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4434 sc->sc_wdcdev.irqack = pciide_irqack; 4435 } 4436 sc->sc_wdcdev.PIO_cap = 4; 4437 sc->sc_wdcdev.DMA_cap = 2; 4438 switch (sc->sc_pp->ide_product) { 4439 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4440 sc->sc_wdcdev.UDMA_cap = 2; 4441 break; 4442 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4443 if (PCI_REVISION(pa->pa_class) < 0x92) 4444 sc->sc_wdcdev.UDMA_cap = 4; 4445 else 4446 sc->sc_wdcdev.UDMA_cap = 5; 4447 break; 4448 } 4449 4450 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4451 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4452 sc->sc_wdcdev.nchannels = 2; 4453 4454 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4455 cp = &sc->pciide_channels[channel]; 4456 if (pciide_chansetup(sc, channel, interface) == 0) 4457 continue; 4458 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4459 serverworks_pci_intr); 4460 if (cp->hw_ok == 0) 4461 return; 4462 pciide_map_compat_intr(pa, cp, channel, interface); 4463 if (cp->hw_ok == 0) 4464 return; 4465 serverworks_setup_channel(&cp->wdc_channel); 4466 } 4467 4468 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4469 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4470 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4471 } 4472 4473 void 4474 serverworks_setup_channel(chp) 4475 struct channel_softc *chp; 4476 { 4477 struct ata_drive_datas *drvp; 4478 struct pciide_channel *cp = (struct pciide_channel*)chp; 4479 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4480 int channel = chp->channel; 4481 int drive, unit; 4482 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4483 u_int32_t idedma_ctl; 4484 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4485 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4486 4487 /* setup DMA if needed */ 4488 pciide_channel_dma_setup(cp); 4489 4490 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4491 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4492 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4493 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4494 4495 pio_time &= ~(0xffff << (16 * channel)); 4496 dma_time &= ~(0xffff << (16 * channel)); 4497 pio_mode &= ~(0xff << (8 * channel + 16)); 4498 udma_mode &= ~(0xff << (8 * channel + 16)); 4499 udma_mode &= ~(3 << (2 * channel)); 4500 4501 idedma_ctl = 0; 4502 4503 /* Per drive settings */ 4504 for (drive = 0; drive < 2; drive++) { 4505 drvp = &chp->ch_drive[drive]; 4506 /* If no drive, skip */ 4507 if ((drvp->drive_flags & DRIVE) == 0) 4508 continue; 4509 unit = drive + 2 * channel; 4510 /* add timing values, setup DMA if needed */ 4511 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4512 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4513 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4514 (drvp->drive_flags & DRIVE_UDMA)) { 4515 /* use Ultra/DMA, check for 80-pin cable */ 4516 if (drvp->UDMA_mode > 2 && 4517 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4518 drvp->UDMA_mode = 2; 4519 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4520 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4521 udma_mode |= 1 << unit; 4522 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4523 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4524 (drvp->drive_flags & DRIVE_DMA)) { 4525 /* use Multiword DMA */ 4526 drvp->drive_flags &= ~DRIVE_UDMA; 4527 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4528 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4529 } else { 4530 /* PIO only */ 4531 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4532 } 4533 } 4534 4535 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4536 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4537 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4538 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4539 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4540 4541 if (idedma_ctl != 0) { 4542 /* Add software bits in status register */ 4543 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4544 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4545 } 4546 pciide_print_modes(cp); 4547 } 4548 4549 int 4550 serverworks_pci_intr(arg) 4551 void *arg; 4552 { 4553 struct pciide_softc *sc = arg; 4554 struct pciide_channel *cp; 4555 struct channel_softc *wdc_cp; 4556 int rv = 0; 4557 int dmastat, i, crv; 4558 4559 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4560 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4561 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4562 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4563 IDEDMA_CTL_INTR) 4564 continue; 4565 cp = &sc->pciide_channels[i]; 4566 wdc_cp = &cp->wdc_channel; 4567 crv = wdcintr(wdc_cp); 4568 if (crv == 0) { 4569 printf("%s:%d: bogus intr\n", 4570 sc->sc_wdcdev.sc_dev.dv_xname, i); 4571 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4572 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4573 } else 4574 rv = 1; 4575 } 4576 return rv; 4577 } 4578
Indexes created Thu Oct 02 10:09:58 GMT 2025