pciide.c revision 1.153.2.5
1 /* $NetBSD: pciide.c,v 1.153.2.5 2002/08/02 05:55:43 lukem Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.153.2.5 2002/08/02 05:55:43 lukem Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 192 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void pdc202xx_setup_channel __P((struct channel_softc*)); 194 void pdc20268_setup_channel __P((struct channel_softc*)); 195 int pdc202xx_pci_intr __P((void *)); 196 int pdc20265_pci_intr __P((void *)); 197 198 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void opti_setup_channel __P((struct channel_softc*)); 200 201 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 202 void hpt_setup_channel __P((struct channel_softc*)); 203 int hpt_pci_intr __P((void *)); 204 205 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void acard_setup_channel __P((struct channel_softc*)); 207 int acard_pci_intr __P((void *)); 208 209 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void serverworks_setup_channel __P((struct channel_softc*)); 211 int serverworks_pci_intr __P((void *)); 212 213 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void sl82c105_setup_channel __P((struct channel_softc*)); 215 216 void pciide_channel_dma_setup __P((struct pciide_channel *)); 217 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 218 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 219 void pciide_dma_start __P((void*, int, int)); 220 int pciide_dma_finish __P((void*, int, int, int)); 221 void pciide_irqack __P((struct channel_softc *)); 222 void pciide_print_modes __P((struct pciide_channel *)); 223 224 struct pciide_product_desc { 225 u_int32_t ide_product; 226 int ide_flags; 227 const char *ide_name; 228 /* map and setup chip, probe drives */ 229 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 230 }; 231 232 /* Flags for ide_flags */ 233 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 234 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 235 236 /* Default product description for devices not known from this controller */ 237 const struct pciide_product_desc default_product_desc = { 238 0, 239 0, 240 "Generic PCI IDE controller", 241 default_chip_map, 242 }; 243 244 const struct pciide_product_desc pciide_intel_products[] = { 245 { PCI_PRODUCT_INTEL_82092AA, 246 0, 247 "Intel 82092AA IDE controller", 248 default_chip_map, 249 }, 250 { PCI_PRODUCT_INTEL_82371FB_IDE, 251 0, 252 "Intel 82371FB IDE controller (PIIX)", 253 piix_chip_map, 254 }, 255 { PCI_PRODUCT_INTEL_82371SB_IDE, 256 0, 257 "Intel 82371SB IDE Interface (PIIX3)", 258 piix_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371AB_IDE, 261 0, 262 "Intel 82371AB IDE controller (PIIX4)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82440MX_IDE, 266 0, 267 "Intel 82440MX IDE controller", 268 piix_chip_map 269 }, 270 { PCI_PRODUCT_INTEL_82801AA_IDE, 271 0, 272 "Intel 82801AA IDE Controller (ICH)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82801AB_IDE, 276 0, 277 "Intel 82801AB IDE Controller (ICH0)", 278 piix_chip_map, 279 }, 280 { PCI_PRODUCT_INTEL_82801BA_IDE, 281 0, 282 "Intel 82801BA IDE Controller (ICH2)", 283 piix_chip_map, 284 }, 285 { PCI_PRODUCT_INTEL_82801BAM_IDE, 286 0, 287 "Intel 82801BAM IDE Controller (ICH2)", 288 piix_chip_map, 289 }, 290 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 291 0, 292 "Intel 82801CA IDE Controller", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 296 0, 297 "Intel 82801CA IDE Controller", 298 piix_chip_map, 299 }, 300 { PCI_PRODUCT_INTEL_82801DB_IDE, 301 0, 302 "Intel 82801DB IDE Controller (ICH4)", 303 piix_chip_map, 304 }, 305 { 0, 306 0, 307 NULL, 308 NULL 309 } 310 }; 311 312 const struct pciide_product_desc pciide_amd_products[] = { 313 { PCI_PRODUCT_AMD_PBC756_IDE, 314 0, 315 "Advanced Micro Devices AMD756 IDE Controller", 316 amd7x6_chip_map 317 }, 318 { PCI_PRODUCT_AMD_PBC766_IDE, 319 0, 320 "Advanced Micro Devices AMD766 IDE Controller", 321 amd7x6_chip_map 322 }, 323 { PCI_PRODUCT_AMD_PBC768_IDE, 324 0, 325 "Advanced Micro Devices AMD768 IDE Controller", 326 amd7x6_chip_map 327 }, 328 { 0, 329 0, 330 NULL, 331 NULL 332 } 333 }; 334 335 const struct pciide_product_desc pciide_cmd_products[] = { 336 { PCI_PRODUCT_CMDTECH_640, 337 0, 338 "CMD Technology PCI0640", 339 cmd_chip_map 340 }, 341 { PCI_PRODUCT_CMDTECH_643, 342 0, 343 "CMD Technology PCI0643", 344 cmd0643_9_chip_map, 345 }, 346 { PCI_PRODUCT_CMDTECH_646, 347 0, 348 "CMD Technology PCI0646", 349 cmd0643_9_chip_map, 350 }, 351 { PCI_PRODUCT_CMDTECH_648, 352 IDE_PCI_CLASS_OVERRIDE, 353 "CMD Technology PCI0648", 354 cmd0643_9_chip_map, 355 }, 356 { PCI_PRODUCT_CMDTECH_649, 357 IDE_PCI_CLASS_OVERRIDE, 358 "CMD Technology PCI0649", 359 cmd0643_9_chip_map, 360 }, 361 { 0, 362 0, 363 NULL, 364 NULL 365 } 366 }; 367 368 const struct pciide_product_desc pciide_via_products[] = { 369 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 370 0, 371 NULL, 372 apollo_chip_map, 373 }, 374 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 375 0, 376 NULL, 377 apollo_chip_map, 378 }, 379 { 0, 380 0, 381 NULL, 382 NULL 383 } 384 }; 385 386 const struct pciide_product_desc pciide_cypress_products[] = { 387 { PCI_PRODUCT_CONTAQ_82C693, 388 IDE_16BIT_IOSPACE, 389 "Cypress 82C693 IDE Controller", 390 cy693_chip_map, 391 }, 392 { 0, 393 0, 394 NULL, 395 NULL 396 } 397 }; 398 399 const struct pciide_product_desc pciide_sis_products[] = { 400 { PCI_PRODUCT_SIS_5597_IDE, 401 0, 402 "Silicon Integrated System 5597/5598 IDE controller", 403 sis_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 NULL 409 } 410 }; 411 412 const struct pciide_product_desc pciide_acer_products[] = { 413 { PCI_PRODUCT_ALI_M5229, 414 0, 415 "Acer Labs M5229 UDMA IDE Controller", 416 acer_chip_map, 417 }, 418 { 0, 419 0, 420 NULL, 421 NULL 422 } 423 }; 424 425 const struct pciide_product_desc pciide_promise_products[] = { 426 { PCI_PRODUCT_PROMISE_ULTRA33, 427 IDE_PCI_CLASS_OVERRIDE, 428 "Promise Ultra33/ATA Bus Master IDE Accelerator", 429 pdc202xx_chip_map, 430 }, 431 { PCI_PRODUCT_PROMISE_ULTRA66, 432 IDE_PCI_CLASS_OVERRIDE, 433 "Promise Ultra66/ATA Bus Master IDE Accelerator", 434 pdc202xx_chip_map, 435 }, 436 { PCI_PRODUCT_PROMISE_ULTRA100, 437 IDE_PCI_CLASS_OVERRIDE, 438 "Promise Ultra100/ATA Bus Master IDE Accelerator", 439 pdc202xx_chip_map, 440 }, 441 { PCI_PRODUCT_PROMISE_ULTRA100X, 442 IDE_PCI_CLASS_OVERRIDE, 443 "Promise Ultra100/ATA Bus Master IDE Accelerator", 444 pdc202xx_chip_map, 445 }, 446 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 447 IDE_PCI_CLASS_OVERRIDE, 448 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 449 pdc202xx_chip_map, 450 }, 451 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 452 IDE_PCI_CLASS_OVERRIDE, 453 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 454 pdc202xx_chip_map, 455 }, 456 { PCI_PRODUCT_PROMISE_ULTRA133, 457 IDE_PCI_CLASS_OVERRIDE, 458 "Promise Ultra133/ATA Bus Master IDE Accelerator", 459 pdc202xx_chip_map, 460 }, 461 { 0, 462 0, 463 NULL, 464 NULL 465 } 466 }; 467 468 const struct pciide_product_desc pciide_opti_products[] = { 469 { PCI_PRODUCT_OPTI_82C621, 470 0, 471 "OPTi 82c621 PCI IDE controller", 472 opti_chip_map, 473 }, 474 { PCI_PRODUCT_OPTI_82C568, 475 0, 476 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 477 opti_chip_map, 478 }, 479 { PCI_PRODUCT_OPTI_82D568, 480 0, 481 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 482 opti_chip_map, 483 }, 484 { 0, 485 0, 486 NULL, 487 NULL 488 } 489 }; 490 491 const struct pciide_product_desc pciide_triones_products[] = { 492 { PCI_PRODUCT_TRIONES_HPT366, 493 IDE_PCI_CLASS_OVERRIDE, 494 NULL, 495 hpt_chip_map, 496 }, 497 { PCI_PRODUCT_TRIONES_HPT374, 498 IDE_PCI_CLASS_OVERRIDE, 499 NULL, 500 hpt_chip_map 501 }, 502 { 0, 503 0, 504 NULL, 505 NULL 506 } 507 }; 508 509 const struct pciide_product_desc pciide_acard_products[] = { 510 { PCI_PRODUCT_ACARD_ATP850U, 511 IDE_PCI_CLASS_OVERRIDE, 512 "Acard ATP850U Ultra33 IDE Controller", 513 acard_chip_map, 514 }, 515 { PCI_PRODUCT_ACARD_ATP860, 516 IDE_PCI_CLASS_OVERRIDE, 517 "Acard ATP860 Ultra66 IDE Controller", 518 acard_chip_map, 519 }, 520 { PCI_PRODUCT_ACARD_ATP860A, 521 IDE_PCI_CLASS_OVERRIDE, 522 "Acard ATP860-A Ultra66 IDE Controller", 523 acard_chip_map, 524 }, 525 { 0, 526 0, 527 NULL, 528 NULL 529 } 530 }; 531 532 const struct pciide_product_desc pciide_serverworks_products[] = { 533 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 534 0, 535 "ServerWorks OSB4 IDE Controller", 536 serverworks_chip_map, 537 }, 538 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 539 0, 540 "ServerWorks CSB5 IDE Controller", 541 serverworks_chip_map, 542 }, 543 { 0, 544 0, 545 NULL, 546 } 547 }; 548 549 const struct pciide_product_desc pciide_symphony_products[] = { 550 { PCI_PRODUCT_SYMPHONY_82C105, 551 0, 552 "Symphony Labs 82C105 IDE controller", 553 sl82c105_chip_map, 554 }, 555 { 0, 556 0, 557 NULL, 558 } 559 }; 560 561 const struct pciide_product_desc pciide_winbond_products[] = { 562 { PCI_PRODUCT_WINBOND_W83C553F_1, 563 0, 564 "Winbond W83C553F IDE controller", 565 sl82c105_chip_map, 566 }, 567 { 0, 568 0, 569 NULL, 570 } 571 }; 572 573 struct pciide_vendor_desc { 574 u_int32_t ide_vendor; 575 const struct pciide_product_desc *ide_products; 576 }; 577 578 const struct pciide_vendor_desc pciide_vendors[] = { 579 { PCI_VENDOR_INTEL, pciide_intel_products }, 580 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 581 { PCI_VENDOR_VIATECH, pciide_via_products }, 582 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 583 { PCI_VENDOR_SIS, pciide_sis_products }, 584 { PCI_VENDOR_ALI, pciide_acer_products }, 585 { PCI_VENDOR_PROMISE, pciide_promise_products }, 586 { PCI_VENDOR_AMD, pciide_amd_products }, 587 { PCI_VENDOR_OPTI, pciide_opti_products }, 588 { PCI_VENDOR_TRIONES, pciide_triones_products }, 589 { PCI_VENDOR_ACARD, pciide_acard_products }, 590 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 591 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 592 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 593 { 0, NULL } 594 }; 595 596 /* options passed via the 'flags' config keyword */ 597 #define PCIIDE_OPTIONS_DMA 0x01 598 #define PCIIDE_OPTIONS_NODMA 0x02 599 600 int pciide_match __P((struct device *, struct cfdata *, void *)); 601 void pciide_attach __P((struct device *, struct device *, void *)); 602 603 struct cfattach pciide_ca = { 604 sizeof(struct pciide_softc), pciide_match, pciide_attach 605 }; 606 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 607 int pciide_mapregs_compat __P(( struct pci_attach_args *, 608 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 609 int pciide_mapregs_native __P((struct pci_attach_args *, 610 struct pciide_channel *, bus_size_t *, bus_size_t *, 611 int (*pci_intr) __P((void *)))); 612 void pciide_mapreg_dma __P((struct pciide_softc *, 613 struct pci_attach_args *)); 614 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 615 void pciide_mapchan __P((struct pci_attach_args *, 616 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 617 int (*pci_intr) __P((void *)))); 618 int pciide_chan_candisable __P((struct pciide_channel *)); 619 void pciide_map_compat_intr __P(( struct pci_attach_args *, 620 struct pciide_channel *, int, int)); 621 int pciide_compat_intr __P((void *)); 622 int pciide_pci_intr __P((void *)); 623 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 624 625 const struct pciide_product_desc * 626 pciide_lookup_product(id) 627 u_int32_t id; 628 { 629 const struct pciide_product_desc *pp; 630 const struct pciide_vendor_desc *vp; 631 632 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 633 if (PCI_VENDOR(id) == vp->ide_vendor) 634 break; 635 636 if ((pp = vp->ide_products) == NULL) 637 return NULL; 638 639 for (; pp->chip_map != NULL; pp++) 640 if (PCI_PRODUCT(id) == pp->ide_product) 641 break; 642 643 if (pp->chip_map == NULL) 644 return NULL; 645 return pp; 646 } 647 648 int 649 pciide_match(parent, match, aux) 650 struct device *parent; 651 struct cfdata *match; 652 void *aux; 653 { 654 struct pci_attach_args *pa = aux; 655 const struct pciide_product_desc *pp; 656 657 /* 658 * Check the ID register to see that it's a PCI IDE controller. 659 * If it is, we assume that we can deal with it; it _should_ 660 * work in a standardized way... 661 */ 662 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 663 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 664 return (1); 665 } 666 667 /* 668 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 669 * controllers. Let see if we can deal with it anyway. 670 */ 671 pp = pciide_lookup_product(pa->pa_id); 672 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 673 return (1); 674 } 675 676 return (0); 677 } 678 679 void 680 pciide_attach(parent, self, aux) 681 struct device *parent, *self; 682 void *aux; 683 { 684 struct pci_attach_args *pa = aux; 685 pci_chipset_tag_t pc = pa->pa_pc; 686 pcitag_t tag = pa->pa_tag; 687 struct pciide_softc *sc = (struct pciide_softc *)self; 688 pcireg_t csr; 689 char devinfo[256]; 690 const char *displaydev; 691 692 sc->sc_pp = pciide_lookup_product(pa->pa_id); 693 if (sc->sc_pp == NULL) { 694 sc->sc_pp = &default_product_desc; 695 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 696 displaydev = devinfo; 697 } else 698 displaydev = sc->sc_pp->ide_name; 699 700 /* if displaydev == NULL, printf is done in chip-specific map */ 701 if (displaydev) 702 printf(": %s (rev. 0x%02x)\n", displaydev, 703 PCI_REVISION(pa->pa_class)); 704 705 sc->sc_pc = pa->pa_pc; 706 sc->sc_tag = pa->pa_tag; 707 #ifdef WDCDEBUG 708 if (wdcdebug_pciide_mask & DEBUG_PROBE) 709 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 710 #endif 711 sc->sc_pp->chip_map(sc, pa); 712 713 if (sc->sc_dma_ok) { 714 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 715 csr |= PCI_COMMAND_MASTER_ENABLE; 716 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 717 } 718 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 719 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 720 } 721 722 /* tell wether the chip is enabled or not */ 723 int 724 pciide_chipen(sc, pa) 725 struct pciide_softc *sc; 726 struct pci_attach_args *pa; 727 { 728 pcireg_t csr; 729 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 730 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 731 PCI_COMMAND_STATUS_REG); 732 printf("%s: device disabled (at %s)\n", 733 sc->sc_wdcdev.sc_dev.dv_xname, 734 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 735 "device" : "bridge"); 736 return 0; 737 } 738 return 1; 739 } 740 741 int 742 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 743 struct pci_attach_args *pa; 744 struct pciide_channel *cp; 745 int compatchan; 746 bus_size_t *cmdsizep, *ctlsizep; 747 { 748 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 749 struct channel_softc *wdc_cp = &cp->wdc_channel; 750 751 cp->compat = 1; 752 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 753 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 754 755 wdc_cp->cmd_iot = pa->pa_iot; 756 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 757 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 758 printf("%s: couldn't map %s channel cmd regs\n", 759 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 760 return (0); 761 } 762 763 wdc_cp->ctl_iot = pa->pa_iot; 764 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 765 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 766 printf("%s: couldn't map %s channel ctl regs\n", 767 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 768 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 769 PCIIDE_COMPAT_CMD_SIZE); 770 return (0); 771 } 772 773 return (1); 774 } 775 776 int 777 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 778 struct pci_attach_args * pa; 779 struct pciide_channel *cp; 780 bus_size_t *cmdsizep, *ctlsizep; 781 int (*pci_intr) __P((void *)); 782 { 783 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 784 struct channel_softc *wdc_cp = &cp->wdc_channel; 785 const char *intrstr; 786 pci_intr_handle_t intrhandle; 787 788 cp->compat = 0; 789 790 if (sc->sc_pci_ih == NULL) { 791 if (pci_intr_map(pa, &intrhandle) != 0) { 792 printf("%s: couldn't map native-PCI interrupt\n", 793 sc->sc_wdcdev.sc_dev.dv_xname); 794 return 0; 795 } 796 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 797 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 798 intrhandle, IPL_BIO, pci_intr, sc); 799 if (sc->sc_pci_ih != NULL) { 800 printf("%s: using %s for native-PCI interrupt\n", 801 sc->sc_wdcdev.sc_dev.dv_xname, 802 intrstr ? intrstr : "unknown interrupt"); 803 } else { 804 printf("%s: couldn't establish native-PCI interrupt", 805 sc->sc_wdcdev.sc_dev.dv_xname); 806 if (intrstr != NULL) 807 printf(" at %s", intrstr); 808 printf("\n"); 809 return 0; 810 } 811 } 812 cp->ih = sc->sc_pci_ih; 813 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 814 PCI_MAPREG_TYPE_IO, 0, 815 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 816 printf("%s: couldn't map %s channel cmd regs\n", 817 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 818 return 0; 819 } 820 821 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 822 PCI_MAPREG_TYPE_IO, 0, 823 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 824 printf("%s: couldn't map %s channel ctl regs\n", 825 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 826 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 827 return 0; 828 } 829 /* 830 * In native mode, 4 bytes of I/O space are mapped for the control 831 * register, the control register is at offset 2. Pass the generic 832 * code a handle for only one byte at the rigth offset. 833 */ 834 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 835 &wdc_cp->ctl_ioh) != 0) { 836 printf("%s: unable to subregion %s channel ctl regs\n", 837 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 838 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 839 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 840 return 0; 841 } 842 return (1); 843 } 844 845 void 846 pciide_mapreg_dma(sc, pa) 847 struct pciide_softc *sc; 848 struct pci_attach_args *pa; 849 { 850 pcireg_t maptype; 851 bus_addr_t addr; 852 853 /* 854 * Map DMA registers 855 * 856 * Note that sc_dma_ok is the right variable to test to see if 857 * DMA can be done. If the interface doesn't support DMA, 858 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 859 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 860 * non-zero if the interface supports DMA and the registers 861 * could be mapped. 862 * 863 * XXX Note that despite the fact that the Bus Master IDE specs 864 * XXX say that "The bus master IDE function uses 16 bytes of IO 865 * XXX space," some controllers (at least the United 866 * XXX Microelectronics UM8886BF) place it in memory space. 867 */ 868 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 869 PCIIDE_REG_BUS_MASTER_DMA); 870 871 switch (maptype) { 872 case PCI_MAPREG_TYPE_IO: 873 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 874 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 875 &addr, NULL, NULL) == 0); 876 if (sc->sc_dma_ok == 0) { 877 printf(", but unused (couldn't query registers)"); 878 break; 879 } 880 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 881 && addr >= 0x10000) { 882 sc->sc_dma_ok = 0; 883 printf(", but unused (registers at unsafe address " 884 "%#lx)", (unsigned long)addr); 885 break; 886 } 887 /* FALLTHROUGH */ 888 889 case PCI_MAPREG_MEM_TYPE_32BIT: 890 sc->sc_dma_ok = (pci_mapreg_map(pa, 891 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 892 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 893 sc->sc_dmat = pa->pa_dmat; 894 if (sc->sc_dma_ok == 0) { 895 printf(", but unused (couldn't map registers)"); 896 } else { 897 sc->sc_wdcdev.dma_arg = sc; 898 sc->sc_wdcdev.dma_init = pciide_dma_init; 899 sc->sc_wdcdev.dma_start = pciide_dma_start; 900 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 901 } 902 903 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 904 PCIIDE_OPTIONS_NODMA) { 905 printf(", but unused (forced off by config file)"); 906 sc->sc_dma_ok = 0; 907 } 908 break; 909 910 default: 911 sc->sc_dma_ok = 0; 912 printf(", but unsupported register maptype (0x%x)", maptype); 913 } 914 } 915 916 int 917 pciide_compat_intr(arg) 918 void *arg; 919 { 920 struct pciide_channel *cp = arg; 921 922 #ifdef DIAGNOSTIC 923 /* should only be called for a compat channel */ 924 if (cp->compat == 0) 925 panic("pciide compat intr called for non-compat chan %p\n", cp); 926 #endif 927 return (wdcintr(&cp->wdc_channel)); 928 } 929 930 int 931 pciide_pci_intr(arg) 932 void *arg; 933 { 934 struct pciide_softc *sc = arg; 935 struct pciide_channel *cp; 936 struct channel_softc *wdc_cp; 937 int i, rv, crv; 938 939 rv = 0; 940 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 941 cp = &sc->pciide_channels[i]; 942 wdc_cp = &cp->wdc_channel; 943 944 /* If a compat channel skip. */ 945 if (cp->compat) 946 continue; 947 /* if this channel not waiting for intr, skip */ 948 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 949 continue; 950 951 crv = wdcintr(wdc_cp); 952 if (crv == 0) 953 ; /* leave rv alone */ 954 else if (crv == 1) 955 rv = 1; /* claim the intr */ 956 else if (rv == 0) /* crv should be -1 in this case */ 957 rv = crv; /* if we've done no better, take it */ 958 } 959 return (rv); 960 } 961 962 void 963 pciide_channel_dma_setup(cp) 964 struct pciide_channel *cp; 965 { 966 int drive; 967 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 968 struct ata_drive_datas *drvp; 969 970 for (drive = 0; drive < 2; drive++) { 971 drvp = &cp->wdc_channel.ch_drive[drive]; 972 /* If no drive, skip */ 973 if ((drvp->drive_flags & DRIVE) == 0) 974 continue; 975 /* setup DMA if needed */ 976 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 977 (drvp->drive_flags & DRIVE_UDMA) == 0) || 978 sc->sc_dma_ok == 0) { 979 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 980 continue; 981 } 982 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 983 != 0) { 984 /* Abort DMA setup */ 985 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 986 continue; 987 } 988 } 989 } 990 991 int 992 pciide_dma_table_setup(sc, channel, drive) 993 struct pciide_softc *sc; 994 int channel, drive; 995 { 996 bus_dma_segment_t seg; 997 int error, rseg; 998 const bus_size_t dma_table_size = 999 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1000 struct pciide_dma_maps *dma_maps = 1001 &sc->pciide_channels[channel].dma_maps[drive]; 1002 1003 /* If table was already allocated, just return */ 1004 if (dma_maps->dma_table) 1005 return 0; 1006 1007 /* Allocate memory for the DMA tables and map it */ 1008 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1009 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1010 BUS_DMA_NOWAIT)) != 0) { 1011 printf("%s:%d: unable to allocate table DMA for " 1012 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1013 channel, drive, error); 1014 return error; 1015 } 1016 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1017 dma_table_size, 1018 (caddr_t *)&dma_maps->dma_table, 1019 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1020 printf("%s:%d: unable to map table DMA for" 1021 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1022 channel, drive, error); 1023 return error; 1024 } 1025 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1026 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1027 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1028 1029 /* Create and load table DMA map for this disk */ 1030 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1031 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1032 &dma_maps->dmamap_table)) != 0) { 1033 printf("%s:%d: unable to create table DMA map for " 1034 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1035 channel, drive, error); 1036 return error; 1037 } 1038 if ((error = bus_dmamap_load(sc->sc_dmat, 1039 dma_maps->dmamap_table, 1040 dma_maps->dma_table, 1041 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1042 printf("%s:%d: unable to load table DMA map for " 1043 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1044 channel, drive, error); 1045 return error; 1046 } 1047 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1048 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1049 DEBUG_PROBE); 1050 /* Create a xfer DMA map for this drive */ 1051 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1052 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1053 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1054 &dma_maps->dmamap_xfer)) != 0) { 1055 printf("%s:%d: unable to create xfer DMA map for " 1056 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1057 channel, drive, error); 1058 return error; 1059 } 1060 return 0; 1061 } 1062 1063 int 1064 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1065 void *v; 1066 int channel, drive; 1067 void *databuf; 1068 size_t datalen; 1069 int flags; 1070 { 1071 struct pciide_softc *sc = v; 1072 int error, seg; 1073 struct pciide_dma_maps *dma_maps = 1074 &sc->pciide_channels[channel].dma_maps[drive]; 1075 1076 error = bus_dmamap_load(sc->sc_dmat, 1077 dma_maps->dmamap_xfer, 1078 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1079 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1080 if (error) { 1081 printf("%s:%d: unable to load xfer DMA map for" 1082 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1083 channel, drive, error); 1084 return error; 1085 } 1086 1087 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1088 dma_maps->dmamap_xfer->dm_mapsize, 1089 (flags & WDC_DMA_READ) ? 1090 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1091 1092 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1093 #ifdef DIAGNOSTIC 1094 /* A segment must not cross a 64k boundary */ 1095 { 1096 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1097 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1098 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1099 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1100 printf("pciide_dma: segment %d physical addr 0x%lx" 1101 " len 0x%lx not properly aligned\n", 1102 seg, phys, len); 1103 panic("pciide_dma: buf align"); 1104 } 1105 } 1106 #endif 1107 dma_maps->dma_table[seg].base_addr = 1108 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1109 dma_maps->dma_table[seg].byte_count = 1110 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1111 IDEDMA_BYTE_COUNT_MASK); 1112 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1113 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1114 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1115 1116 } 1117 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1118 htole32(IDEDMA_BYTE_COUNT_EOT); 1119 1120 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1121 dma_maps->dmamap_table->dm_mapsize, 1122 BUS_DMASYNC_PREWRITE); 1123 1124 /* Maps are ready. Start DMA function */ 1125 #ifdef DIAGNOSTIC 1126 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1127 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1128 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1129 panic("pciide_dma_init: table align"); 1130 } 1131 #endif 1132 1133 /* Clear status bits */ 1134 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1135 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1136 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1137 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1138 /* Write table addr */ 1139 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1140 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1141 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1142 /* set read/write */ 1143 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1144 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1145 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1146 /* remember flags */ 1147 dma_maps->dma_flags = flags; 1148 return 0; 1149 } 1150 1151 void 1152 pciide_dma_start(v, channel, drive) 1153 void *v; 1154 int channel, drive; 1155 { 1156 struct pciide_softc *sc = v; 1157 1158 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1159 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1160 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1161 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1162 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1163 } 1164 1165 int 1166 pciide_dma_finish(v, channel, drive, force) 1167 void *v; 1168 int channel, drive; 1169 int force; 1170 { 1171 struct pciide_softc *sc = v; 1172 u_int8_t status; 1173 int error = 0; 1174 struct pciide_dma_maps *dma_maps = 1175 &sc->pciide_channels[channel].dma_maps[drive]; 1176 1177 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1178 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1179 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1180 DEBUG_XFERS); 1181 1182 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1183 return WDC_DMAST_NOIRQ; 1184 1185 /* stop DMA channel */ 1186 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1187 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1188 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1189 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1190 1191 /* Unload the map of the data buffer */ 1192 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1193 dma_maps->dmamap_xfer->dm_mapsize, 1194 (dma_maps->dma_flags & WDC_DMA_READ) ? 1195 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1196 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1197 1198 if ((status & IDEDMA_CTL_ERR) != 0) { 1199 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1200 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1201 error |= WDC_DMAST_ERR; 1202 } 1203 1204 if ((status & IDEDMA_CTL_INTR) == 0) { 1205 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1206 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1207 drive, status); 1208 error |= WDC_DMAST_NOIRQ; 1209 } 1210 1211 if ((status & IDEDMA_CTL_ACT) != 0) { 1212 /* data underrun, may be a valid condition for ATAPI */ 1213 error |= WDC_DMAST_UNDER; 1214 } 1215 return error; 1216 } 1217 1218 void 1219 pciide_irqack(chp) 1220 struct channel_softc *chp; 1221 { 1222 struct pciide_channel *cp = (struct pciide_channel*)chp; 1223 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1224 1225 /* clear status bits in IDE DMA registers */ 1226 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1227 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1228 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1229 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1230 } 1231 1232 /* some common code used by several chip_map */ 1233 int 1234 pciide_chansetup(sc, channel, interface) 1235 struct pciide_softc *sc; 1236 int channel; 1237 pcireg_t interface; 1238 { 1239 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1240 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1241 cp->name = PCIIDE_CHANNEL_NAME(channel); 1242 cp->wdc_channel.channel = channel; 1243 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1244 cp->wdc_channel.ch_queue = 1245 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1246 if (cp->wdc_channel.ch_queue == NULL) { 1247 printf("%s %s channel: " 1248 "can't allocate memory for command queue", 1249 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1250 return 0; 1251 } 1252 printf("%s: %s channel %s to %s mode\n", 1253 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1254 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1255 "configured" : "wired", 1256 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1257 "native-PCI" : "compatibility"); 1258 return 1; 1259 } 1260 1261 /* some common code used by several chip channel_map */ 1262 void 1263 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1264 struct pci_attach_args *pa; 1265 struct pciide_channel *cp; 1266 pcireg_t interface; 1267 bus_size_t *cmdsizep, *ctlsizep; 1268 int (*pci_intr) __P((void *)); 1269 { 1270 struct channel_softc *wdc_cp = &cp->wdc_channel; 1271 1272 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1273 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1274 pci_intr); 1275 else 1276 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1277 wdc_cp->channel, cmdsizep, ctlsizep); 1278 1279 if (cp->hw_ok == 0) 1280 return; 1281 wdc_cp->data32iot = wdc_cp->cmd_iot; 1282 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1283 wdcattach(wdc_cp); 1284 } 1285 1286 /* 1287 * Generic code to call to know if a channel can be disabled. Return 1 1288 * if channel can be disabled, 0 if not 1289 */ 1290 int 1291 pciide_chan_candisable(cp) 1292 struct pciide_channel *cp; 1293 { 1294 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1295 struct channel_softc *wdc_cp = &cp->wdc_channel; 1296 1297 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1298 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1299 printf("%s: disabling %s channel (no drives)\n", 1300 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1301 cp->hw_ok = 0; 1302 return 1; 1303 } 1304 return 0; 1305 } 1306 1307 /* 1308 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1309 * Set hw_ok=0 on failure 1310 */ 1311 void 1312 pciide_map_compat_intr(pa, cp, compatchan, interface) 1313 struct pci_attach_args *pa; 1314 struct pciide_channel *cp; 1315 int compatchan, interface; 1316 { 1317 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1318 struct channel_softc *wdc_cp = &cp->wdc_channel; 1319 1320 if (cp->hw_ok == 0) 1321 return; 1322 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1323 return; 1324 1325 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1326 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1327 pa, compatchan, pciide_compat_intr, cp); 1328 if (cp->ih == NULL) { 1329 #endif 1330 printf("%s: no compatibility interrupt for use by %s " 1331 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1332 cp->hw_ok = 0; 1333 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1334 } 1335 #endif 1336 } 1337 1338 void 1339 pciide_print_modes(cp) 1340 struct pciide_channel *cp; 1341 { 1342 wdc_print_modes(&cp->wdc_channel); 1343 } 1344 1345 void 1346 default_chip_map(sc, pa) 1347 struct pciide_softc *sc; 1348 struct pci_attach_args *pa; 1349 { 1350 struct pciide_channel *cp; 1351 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1352 pcireg_t csr; 1353 int channel, drive; 1354 struct ata_drive_datas *drvp; 1355 u_int8_t idedma_ctl; 1356 bus_size_t cmdsize, ctlsize; 1357 char *failreason; 1358 1359 if (pciide_chipen(sc, pa) == 0) 1360 return; 1361 1362 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1363 printf("%s: bus-master DMA support present", 1364 sc->sc_wdcdev.sc_dev.dv_xname); 1365 if (sc->sc_pp == &default_product_desc && 1366 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1367 PCIIDE_OPTIONS_DMA) == 0) { 1368 printf(", but unused (no driver support)"); 1369 sc->sc_dma_ok = 0; 1370 } else { 1371 pciide_mapreg_dma(sc, pa); 1372 if (sc->sc_dma_ok != 0) 1373 printf(", used without full driver " 1374 "support"); 1375 } 1376 } else { 1377 printf("%s: hardware does not support DMA", 1378 sc->sc_wdcdev.sc_dev.dv_xname); 1379 sc->sc_dma_ok = 0; 1380 } 1381 printf("\n"); 1382 if (sc->sc_dma_ok) { 1383 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1384 sc->sc_wdcdev.irqack = pciide_irqack; 1385 } 1386 sc->sc_wdcdev.PIO_cap = 0; 1387 sc->sc_wdcdev.DMA_cap = 0; 1388 1389 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1390 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1391 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1392 1393 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1394 cp = &sc->pciide_channels[channel]; 1395 if (pciide_chansetup(sc, channel, interface) == 0) 1396 continue; 1397 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1398 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1399 &ctlsize, pciide_pci_intr); 1400 } else { 1401 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1402 channel, &cmdsize, &ctlsize); 1403 } 1404 if (cp->hw_ok == 0) 1405 continue; 1406 /* 1407 * Check to see if something appears to be there. 1408 */ 1409 failreason = NULL; 1410 if (!wdcprobe(&cp->wdc_channel)) { 1411 failreason = "not responding; disabled or no drives?"; 1412 goto next; 1413 } 1414 /* 1415 * Now, make sure it's actually attributable to this PCI IDE 1416 * channel by trying to access the channel again while the 1417 * PCI IDE controller's I/O space is disabled. (If the 1418 * channel no longer appears to be there, it belongs to 1419 * this controller.) YUCK! 1420 */ 1421 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1422 PCI_COMMAND_STATUS_REG); 1423 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1424 csr & ~PCI_COMMAND_IO_ENABLE); 1425 if (wdcprobe(&cp->wdc_channel)) 1426 failreason = "other hardware responding at addresses"; 1427 pci_conf_write(sc->sc_pc, sc->sc_tag, 1428 PCI_COMMAND_STATUS_REG, csr); 1429 next: 1430 if (failreason) { 1431 printf("%s: %s channel ignored (%s)\n", 1432 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1433 failreason); 1434 cp->hw_ok = 0; 1435 bus_space_unmap(cp->wdc_channel.cmd_iot, 1436 cp->wdc_channel.cmd_ioh, cmdsize); 1437 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1438 bus_space_unmap(cp->wdc_channel.ctl_iot, 1439 cp->ctl_baseioh, ctlsize); 1440 else 1441 bus_space_unmap(cp->wdc_channel.ctl_iot, 1442 cp->wdc_channel.ctl_ioh, ctlsize); 1443 } else { 1444 pciide_map_compat_intr(pa, cp, channel, interface); 1445 } 1446 if (cp->hw_ok) { 1447 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1448 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1449 wdcattach(&cp->wdc_channel); 1450 } 1451 } 1452 1453 if (sc->sc_dma_ok == 0) 1454 return; 1455 1456 /* Allocate DMA maps */ 1457 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1458 idedma_ctl = 0; 1459 cp = &sc->pciide_channels[channel]; 1460 for (drive = 0; drive < 2; drive++) { 1461 drvp = &cp->wdc_channel.ch_drive[drive]; 1462 /* If no drive, skip */ 1463 if ((drvp->drive_flags & DRIVE) == 0) 1464 continue; 1465 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1466 continue; 1467 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1468 /* Abort DMA setup */ 1469 printf("%s:%d:%d: can't allocate DMA maps, " 1470 "using PIO transfers\n", 1471 sc->sc_wdcdev.sc_dev.dv_xname, 1472 channel, drive); 1473 drvp->drive_flags &= ~DRIVE_DMA; 1474 } 1475 printf("%s:%d:%d: using DMA data transfers\n", 1476 sc->sc_wdcdev.sc_dev.dv_xname, 1477 channel, drive); 1478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1479 } 1480 if (idedma_ctl != 0) { 1481 /* Add software bits in status register */ 1482 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1483 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1484 idedma_ctl); 1485 } 1486 } 1487 } 1488 1489 void 1490 piix_chip_map(sc, pa) 1491 struct pciide_softc *sc; 1492 struct pci_attach_args *pa; 1493 { 1494 struct pciide_channel *cp; 1495 int channel; 1496 u_int32_t idetim; 1497 bus_size_t cmdsize, ctlsize; 1498 1499 if (pciide_chipen(sc, pa) == 0) 1500 return; 1501 1502 printf("%s: bus-master DMA support present", 1503 sc->sc_wdcdev.sc_dev.dv_xname); 1504 pciide_mapreg_dma(sc, pa); 1505 printf("\n"); 1506 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1507 WDC_CAPABILITY_MODE; 1508 if (sc->sc_dma_ok) { 1509 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1510 sc->sc_wdcdev.irqack = pciide_irqack; 1511 switch(sc->sc_pp->ide_product) { 1512 case PCI_PRODUCT_INTEL_82371AB_IDE: 1513 case PCI_PRODUCT_INTEL_82440MX_IDE: 1514 case PCI_PRODUCT_INTEL_82801AA_IDE: 1515 case PCI_PRODUCT_INTEL_82801AB_IDE: 1516 case PCI_PRODUCT_INTEL_82801BA_IDE: 1517 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1518 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1519 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1520 case PCI_PRODUCT_INTEL_82801DB_IDE: 1521 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1522 } 1523 } 1524 sc->sc_wdcdev.PIO_cap = 4; 1525 sc->sc_wdcdev.DMA_cap = 2; 1526 switch(sc->sc_pp->ide_product) { 1527 case PCI_PRODUCT_INTEL_82801AA_IDE: 1528 sc->sc_wdcdev.UDMA_cap = 4; 1529 break; 1530 case PCI_PRODUCT_INTEL_82801BA_IDE: 1531 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1532 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1533 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1534 case PCI_PRODUCT_INTEL_82801DB_IDE: 1535 sc->sc_wdcdev.UDMA_cap = 5; 1536 break; 1537 default: 1538 sc->sc_wdcdev.UDMA_cap = 2; 1539 } 1540 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1541 sc->sc_wdcdev.set_modes = piix_setup_channel; 1542 else 1543 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1544 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1545 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1546 1547 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1548 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1549 DEBUG_PROBE); 1550 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1551 WDCDEBUG_PRINT((", sidetim=0x%x", 1552 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1553 DEBUG_PROBE); 1554 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1555 WDCDEBUG_PRINT((", udamreg 0x%x", 1556 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1557 DEBUG_PROBE); 1558 } 1559 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1560 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1561 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1563 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1564 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1565 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1566 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1567 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1568 DEBUG_PROBE); 1569 } 1570 1571 } 1572 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1573 1574 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1575 cp = &sc->pciide_channels[channel]; 1576 /* PIIX is compat-only */ 1577 if (pciide_chansetup(sc, channel, 0) == 0) 1578 continue; 1579 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1580 if ((PIIX_IDETIM_READ(idetim, channel) & 1581 PIIX_IDETIM_IDE) == 0) { 1582 printf("%s: %s channel ignored (disabled)\n", 1583 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1584 continue; 1585 } 1586 /* PIIX are compat-only pciide devices */ 1587 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1588 if (cp->hw_ok == 0) 1589 continue; 1590 if (pciide_chan_candisable(cp)) { 1591 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1592 channel); 1593 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1594 idetim); 1595 } 1596 pciide_map_compat_intr(pa, cp, channel, 0); 1597 if (cp->hw_ok == 0) 1598 continue; 1599 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1600 } 1601 1602 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1603 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1604 DEBUG_PROBE); 1605 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1606 WDCDEBUG_PRINT((", sidetim=0x%x", 1607 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1608 DEBUG_PROBE); 1609 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1610 WDCDEBUG_PRINT((", udamreg 0x%x", 1611 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1612 DEBUG_PROBE); 1613 } 1614 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1617 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1618 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1619 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1620 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1621 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1622 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1623 DEBUG_PROBE); 1624 } 1625 } 1626 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1627 } 1628 1629 void 1630 piix_setup_channel(chp) 1631 struct channel_softc *chp; 1632 { 1633 u_int8_t mode[2], drive; 1634 u_int32_t oidetim, idetim, idedma_ctl; 1635 struct pciide_channel *cp = (struct pciide_channel*)chp; 1636 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1637 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1638 1639 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1640 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1641 idedma_ctl = 0; 1642 1643 /* set up new idetim: Enable IDE registers decode */ 1644 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1645 chp->channel); 1646 1647 /* setup DMA */ 1648 pciide_channel_dma_setup(cp); 1649 1650 /* 1651 * Here we have to mess up with drives mode: PIIX can't have 1652 * different timings for master and slave drives. 1653 * We need to find the best combination. 1654 */ 1655 1656 /* If both drives supports DMA, take the lower mode */ 1657 if ((drvp[0].drive_flags & DRIVE_DMA) && 1658 (drvp[1].drive_flags & DRIVE_DMA)) { 1659 mode[0] = mode[1] = 1660 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1661 drvp[0].DMA_mode = mode[0]; 1662 drvp[1].DMA_mode = mode[1]; 1663 goto ok; 1664 } 1665 /* 1666 * If only one drive supports DMA, use its mode, and 1667 * put the other one in PIO mode 0 if mode not compatible 1668 */ 1669 if (drvp[0].drive_flags & DRIVE_DMA) { 1670 mode[0] = drvp[0].DMA_mode; 1671 mode[1] = drvp[1].PIO_mode; 1672 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1673 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1674 mode[1] = drvp[1].PIO_mode = 0; 1675 goto ok; 1676 } 1677 if (drvp[1].drive_flags & DRIVE_DMA) { 1678 mode[1] = drvp[1].DMA_mode; 1679 mode[0] = drvp[0].PIO_mode; 1680 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1681 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1682 mode[0] = drvp[0].PIO_mode = 0; 1683 goto ok; 1684 } 1685 /* 1686 * If both drives are not DMA, takes the lower mode, unless 1687 * one of them is PIO mode < 2 1688 */ 1689 if (drvp[0].PIO_mode < 2) { 1690 mode[0] = drvp[0].PIO_mode = 0; 1691 mode[1] = drvp[1].PIO_mode; 1692 } else if (drvp[1].PIO_mode < 2) { 1693 mode[1] = drvp[1].PIO_mode = 0; 1694 mode[0] = drvp[0].PIO_mode; 1695 } else { 1696 mode[0] = mode[1] = 1697 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1698 drvp[0].PIO_mode = mode[0]; 1699 drvp[1].PIO_mode = mode[1]; 1700 } 1701 ok: /* The modes are setup */ 1702 for (drive = 0; drive < 2; drive++) { 1703 if (drvp[drive].drive_flags & DRIVE_DMA) { 1704 idetim |= piix_setup_idetim_timings( 1705 mode[drive], 1, chp->channel); 1706 goto end; 1707 } 1708 } 1709 /* If we are there, none of the drives are DMA */ 1710 if (mode[0] >= 2) 1711 idetim |= piix_setup_idetim_timings( 1712 mode[0], 0, chp->channel); 1713 else 1714 idetim |= piix_setup_idetim_timings( 1715 mode[1], 0, chp->channel); 1716 end: /* 1717 * timing mode is now set up in the controller. Enable 1718 * it per-drive 1719 */ 1720 for (drive = 0; drive < 2; drive++) { 1721 /* If no drive, skip */ 1722 if ((drvp[drive].drive_flags & DRIVE) == 0) 1723 continue; 1724 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1725 if (drvp[drive].drive_flags & DRIVE_DMA) 1726 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1727 } 1728 if (idedma_ctl != 0) { 1729 /* Add software bits in status register */ 1730 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1731 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1732 idedma_ctl); 1733 } 1734 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1735 pciide_print_modes(cp); 1736 } 1737 1738 void 1739 piix3_4_setup_channel(chp) 1740 struct channel_softc *chp; 1741 { 1742 struct ata_drive_datas *drvp; 1743 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1744 struct pciide_channel *cp = (struct pciide_channel*)chp; 1745 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1746 int drive; 1747 int channel = chp->channel; 1748 1749 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1750 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1751 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1752 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1753 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1754 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1755 PIIX_SIDETIM_RTC_MASK(channel)); 1756 1757 idedma_ctl = 0; 1758 /* If channel disabled, no need to go further */ 1759 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1760 return; 1761 /* set up new idetim: Enable IDE registers decode */ 1762 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1763 1764 /* setup DMA if needed */ 1765 pciide_channel_dma_setup(cp); 1766 1767 for (drive = 0; drive < 2; drive++) { 1768 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1769 PIIX_UDMATIM_SET(0x3, channel, drive)); 1770 drvp = &chp->ch_drive[drive]; 1771 /* If no drive, skip */ 1772 if ((drvp->drive_flags & DRIVE) == 0) 1773 continue; 1774 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1775 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1776 goto pio; 1777 1778 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1779 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1780 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1781 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1782 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1783 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1784 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1785 ideconf |= PIIX_CONFIG_PINGPONG; 1786 } 1787 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1788 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1789 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1790 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1791 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1792 /* setup Ultra/100 */ 1793 if (drvp->UDMA_mode > 2 && 1794 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1795 drvp->UDMA_mode = 2; 1796 if (drvp->UDMA_mode > 4) { 1797 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1798 } else { 1799 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1800 if (drvp->UDMA_mode > 2) { 1801 ideconf |= PIIX_CONFIG_UDMA66(channel, 1802 drive); 1803 } else { 1804 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1805 drive); 1806 } 1807 } 1808 } 1809 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1810 /* setup Ultra/66 */ 1811 if (drvp->UDMA_mode > 2 && 1812 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1813 drvp->UDMA_mode = 2; 1814 if (drvp->UDMA_mode > 2) 1815 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1816 else 1817 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1818 } 1819 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1820 (drvp->drive_flags & DRIVE_UDMA)) { 1821 /* use Ultra/DMA */ 1822 drvp->drive_flags &= ~DRIVE_DMA; 1823 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1824 udmareg |= PIIX_UDMATIM_SET( 1825 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1826 } else { 1827 /* use Multiword DMA */ 1828 drvp->drive_flags &= ~DRIVE_UDMA; 1829 if (drive == 0) { 1830 idetim |= piix_setup_idetim_timings( 1831 drvp->DMA_mode, 1, channel); 1832 } else { 1833 sidetim |= piix_setup_sidetim_timings( 1834 drvp->DMA_mode, 1, channel); 1835 idetim =PIIX_IDETIM_SET(idetim, 1836 PIIX_IDETIM_SITRE, channel); 1837 } 1838 } 1839 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1840 1841 pio: /* use PIO mode */ 1842 idetim |= piix_setup_idetim_drvs(drvp); 1843 if (drive == 0) { 1844 idetim |= piix_setup_idetim_timings( 1845 drvp->PIO_mode, 0, channel); 1846 } else { 1847 sidetim |= piix_setup_sidetim_timings( 1848 drvp->PIO_mode, 0, channel); 1849 idetim =PIIX_IDETIM_SET(idetim, 1850 PIIX_IDETIM_SITRE, channel); 1851 } 1852 } 1853 if (idedma_ctl != 0) { 1854 /* Add software bits in status register */ 1855 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1856 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1857 idedma_ctl); 1858 } 1859 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1860 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1861 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1862 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1863 pciide_print_modes(cp); 1864 } 1865 1866 1867 /* setup ISP and RTC fields, based on mode */ 1868 static u_int32_t 1869 piix_setup_idetim_timings(mode, dma, channel) 1870 u_int8_t mode; 1871 u_int8_t dma; 1872 u_int8_t channel; 1873 { 1874 1875 if (dma) 1876 return PIIX_IDETIM_SET(0, 1877 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1878 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1879 channel); 1880 else 1881 return PIIX_IDETIM_SET(0, 1882 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1883 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1884 channel); 1885 } 1886 1887 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1888 static u_int32_t 1889 piix_setup_idetim_drvs(drvp) 1890 struct ata_drive_datas *drvp; 1891 { 1892 u_int32_t ret = 0; 1893 struct channel_softc *chp = drvp->chnl_softc; 1894 u_int8_t channel = chp->channel; 1895 u_int8_t drive = drvp->drive; 1896 1897 /* 1898 * If drive is using UDMA, timings setups are independant 1899 * So just check DMA and PIO here. 1900 */ 1901 if (drvp->drive_flags & DRIVE_DMA) { 1902 /* if mode = DMA mode 0, use compatible timings */ 1903 if ((drvp->drive_flags & DRIVE_DMA) && 1904 drvp->DMA_mode == 0) { 1905 drvp->PIO_mode = 0; 1906 return ret; 1907 } 1908 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1909 /* 1910 * PIO and DMA timings are the same, use fast timings for PIO 1911 * too, else use compat timings. 1912 */ 1913 if ((piix_isp_pio[drvp->PIO_mode] != 1914 piix_isp_dma[drvp->DMA_mode]) || 1915 (piix_rtc_pio[drvp->PIO_mode] != 1916 piix_rtc_dma[drvp->DMA_mode])) 1917 drvp->PIO_mode = 0; 1918 /* if PIO mode <= 2, use compat timings for PIO */ 1919 if (drvp->PIO_mode <= 2) { 1920 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1921 channel); 1922 return ret; 1923 } 1924 } 1925 1926 /* 1927 * Now setup PIO modes. If mode < 2, use compat timings. 1928 * Else enable fast timings. Enable IORDY and prefetch/post 1929 * if PIO mode >= 3. 1930 */ 1931 1932 if (drvp->PIO_mode < 2) 1933 return ret; 1934 1935 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1936 if (drvp->PIO_mode >= 3) { 1937 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1938 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1939 } 1940 return ret; 1941 } 1942 1943 /* setup values in SIDETIM registers, based on mode */ 1944 static u_int32_t 1945 piix_setup_sidetim_timings(mode, dma, channel) 1946 u_int8_t mode; 1947 u_int8_t dma; 1948 u_int8_t channel; 1949 { 1950 if (dma) 1951 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1952 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1953 else 1954 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1955 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1956 } 1957 1958 void 1959 amd7x6_chip_map(sc, pa) 1960 struct pciide_softc *sc; 1961 struct pci_attach_args *pa; 1962 { 1963 struct pciide_channel *cp; 1964 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1965 int channel; 1966 pcireg_t chanenable; 1967 bus_size_t cmdsize, ctlsize; 1968 1969 if (pciide_chipen(sc, pa) == 0) 1970 return; 1971 printf("%s: bus-master DMA support present", 1972 sc->sc_wdcdev.sc_dev.dv_xname); 1973 pciide_mapreg_dma(sc, pa); 1974 printf("\n"); 1975 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1976 WDC_CAPABILITY_MODE; 1977 if (sc->sc_dma_ok) { 1978 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1979 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1980 sc->sc_wdcdev.irqack = pciide_irqack; 1981 } 1982 sc->sc_wdcdev.PIO_cap = 4; 1983 sc->sc_wdcdev.DMA_cap = 2; 1984 1985 switch (sc->sc_pp->ide_product) { 1986 case PCI_PRODUCT_AMD_PBC766_IDE: 1987 case PCI_PRODUCT_AMD_PBC768_IDE: 1988 sc->sc_wdcdev.UDMA_cap = 5; 1989 break; 1990 default: 1991 sc->sc_wdcdev.UDMA_cap = 4; 1992 } 1993 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1994 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1995 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1996 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1997 1998 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1999 DEBUG_PROBE); 2000 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2001 cp = &sc->pciide_channels[channel]; 2002 if (pciide_chansetup(sc, channel, interface) == 0) 2003 continue; 2004 2005 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2006 printf("%s: %s channel ignored (disabled)\n", 2007 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2008 continue; 2009 } 2010 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2011 pciide_pci_intr); 2012 2013 if (pciide_chan_candisable(cp)) 2014 chanenable &= ~AMD7X6_CHAN_EN(channel); 2015 pciide_map_compat_intr(pa, cp, channel, interface); 2016 if (cp->hw_ok == 0) 2017 continue; 2018 2019 amd7x6_setup_channel(&cp->wdc_channel); 2020 } 2021 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2022 chanenable); 2023 return; 2024 } 2025 2026 void 2027 amd7x6_setup_channel(chp) 2028 struct channel_softc *chp; 2029 { 2030 u_int32_t udmatim_reg, datatim_reg; 2031 u_int8_t idedma_ctl; 2032 int mode, drive; 2033 struct ata_drive_datas *drvp; 2034 struct pciide_channel *cp = (struct pciide_channel*)chp; 2035 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2036 #ifndef PCIIDE_AMD756_ENABLEDMA 2037 int rev = PCI_REVISION( 2038 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2039 #endif 2040 2041 idedma_ctl = 0; 2042 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2043 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2044 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2045 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2046 2047 /* setup DMA if needed */ 2048 pciide_channel_dma_setup(cp); 2049 2050 for (drive = 0; drive < 2; drive++) { 2051 drvp = &chp->ch_drive[drive]; 2052 /* If no drive, skip */ 2053 if ((drvp->drive_flags & DRIVE) == 0) 2054 continue; 2055 /* add timing values, setup DMA if needed */ 2056 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2057 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2058 mode = drvp->PIO_mode; 2059 goto pio; 2060 } 2061 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2062 (drvp->drive_flags & DRIVE_UDMA)) { 2063 /* use Ultra/DMA */ 2064 drvp->drive_flags &= ~DRIVE_DMA; 2065 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2066 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2067 AMD7X6_UDMA_TIME(chp->channel, drive, 2068 amd7x6_udma_tim[drvp->UDMA_mode]); 2069 /* can use PIO timings, MW DMA unused */ 2070 mode = drvp->PIO_mode; 2071 } else { 2072 /* use Multiword DMA, but only if revision is OK */ 2073 drvp->drive_flags &= ~DRIVE_UDMA; 2074 #ifndef PCIIDE_AMD756_ENABLEDMA 2075 /* 2076 * The workaround doesn't seem to be necessary 2077 * with all drives, so it can be disabled by 2078 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2079 * triggered. 2080 */ 2081 if (sc->sc_pp->ide_product == 2082 PCI_PRODUCT_AMD_PBC756_IDE && 2083 AMD756_CHIPREV_DISABLEDMA(rev)) { 2084 printf("%s:%d:%d: multi-word DMA disabled due " 2085 "to chip revision\n", 2086 sc->sc_wdcdev.sc_dev.dv_xname, 2087 chp->channel, drive); 2088 mode = drvp->PIO_mode; 2089 drvp->drive_flags &= ~DRIVE_DMA; 2090 goto pio; 2091 } 2092 #endif 2093 /* mode = min(pio, dma+2) */ 2094 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2095 mode = drvp->PIO_mode; 2096 else 2097 mode = drvp->DMA_mode + 2; 2098 } 2099 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2100 2101 pio: /* setup PIO mode */ 2102 if (mode <= 2) { 2103 drvp->DMA_mode = 0; 2104 drvp->PIO_mode = 0; 2105 mode = 0; 2106 } else { 2107 drvp->PIO_mode = mode; 2108 drvp->DMA_mode = mode - 2; 2109 } 2110 datatim_reg |= 2111 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2112 amd7x6_pio_set[mode]) | 2113 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2114 amd7x6_pio_rec[mode]); 2115 } 2116 if (idedma_ctl != 0) { 2117 /* Add software bits in status register */ 2118 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2119 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2120 idedma_ctl); 2121 } 2122 pciide_print_modes(cp); 2123 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2124 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2125 } 2126 2127 void 2128 apollo_chip_map(sc, pa) 2129 struct pciide_softc *sc; 2130 struct pci_attach_args *pa; 2131 { 2132 struct pciide_channel *cp; 2133 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2134 int channel; 2135 u_int32_t ideconf; 2136 bus_size_t cmdsize, ctlsize; 2137 pcitag_t pcib_tag; 2138 pcireg_t pcib_id, pcib_class; 2139 2140 if (pciide_chipen(sc, pa) == 0) 2141 return; 2142 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2143 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2144 /* and read ID and rev of the ISA bridge */ 2145 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2146 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2147 printf(": VIA Technologies "); 2148 switch (PCI_PRODUCT(pcib_id)) { 2149 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2150 printf("VT82C586 (Apollo VP) "); 2151 if(PCI_REVISION(pcib_class) >= 0x02) { 2152 printf("ATA33 controller\n"); 2153 sc->sc_wdcdev.UDMA_cap = 2; 2154 } else { 2155 printf("controller\n"); 2156 sc->sc_wdcdev.UDMA_cap = 0; 2157 } 2158 break; 2159 case PCI_PRODUCT_VIATECH_VT82C596A: 2160 printf("VT82C596A (Apollo Pro) "); 2161 if (PCI_REVISION(pcib_class) >= 0x12) { 2162 printf("ATA66 controller\n"); 2163 sc->sc_wdcdev.UDMA_cap = 4; 2164 } else { 2165 printf("ATA33 controller\n"); 2166 sc->sc_wdcdev.UDMA_cap = 2; 2167 } 2168 break; 2169 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2170 printf("VT82C686A (Apollo KX133) "); 2171 if (PCI_REVISION(pcib_class) >= 0x40) { 2172 printf("ATA100 controller\n"); 2173 sc->sc_wdcdev.UDMA_cap = 5; 2174 } else { 2175 printf("ATA66 controller\n"); 2176 sc->sc_wdcdev.UDMA_cap = 4; 2177 } 2178 break; 2179 case PCI_PRODUCT_VIATECH_VT8231: 2180 printf("VT8231 ATA100 controller\n"); 2181 sc->sc_wdcdev.UDMA_cap = 5; 2182 break; 2183 case PCI_PRODUCT_VIATECH_VT8233: 2184 printf("VT8233 ATA100 controller\n"); 2185 sc->sc_wdcdev.UDMA_cap = 5; 2186 break; 2187 case PCI_PRODUCT_VIATECH_VT8233A: 2188 printf("VT8233A ATA133 controller\n"); 2189 /* XXX use ATA100 untill ATA133 is supported */ 2190 sc->sc_wdcdev.UDMA_cap = 5; 2191 break; 2192 default: 2193 printf("unknown ATA controller\n"); 2194 sc->sc_wdcdev.UDMA_cap = 0; 2195 } 2196 2197 printf("%s: bus-master DMA support present", 2198 sc->sc_wdcdev.sc_dev.dv_xname); 2199 pciide_mapreg_dma(sc, pa); 2200 printf("\n"); 2201 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2202 WDC_CAPABILITY_MODE; 2203 if (sc->sc_dma_ok) { 2204 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2205 sc->sc_wdcdev.irqack = pciide_irqack; 2206 if (sc->sc_wdcdev.UDMA_cap > 0) 2207 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2208 } 2209 sc->sc_wdcdev.PIO_cap = 4; 2210 sc->sc_wdcdev.DMA_cap = 2; 2211 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2212 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2213 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2214 2215 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2216 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2217 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2218 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2219 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2220 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2221 DEBUG_PROBE); 2222 2223 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2224 cp = &sc->pciide_channels[channel]; 2225 if (pciide_chansetup(sc, channel, interface) == 0) 2226 continue; 2227 2228 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2229 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2230 printf("%s: %s channel ignored (disabled)\n", 2231 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2232 continue; 2233 } 2234 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2235 pciide_pci_intr); 2236 if (cp->hw_ok == 0) 2237 continue; 2238 if (pciide_chan_candisable(cp)) { 2239 ideconf &= ~APO_IDECONF_EN(channel); 2240 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2241 ideconf); 2242 } 2243 pciide_map_compat_intr(pa, cp, channel, interface); 2244 2245 if (cp->hw_ok == 0) 2246 continue; 2247 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2248 } 2249 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2250 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2251 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2252 } 2253 2254 void 2255 apollo_setup_channel(chp) 2256 struct channel_softc *chp; 2257 { 2258 u_int32_t udmatim_reg, datatim_reg; 2259 u_int8_t idedma_ctl; 2260 int mode, drive; 2261 struct ata_drive_datas *drvp; 2262 struct pciide_channel *cp = (struct pciide_channel*)chp; 2263 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2264 2265 idedma_ctl = 0; 2266 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2267 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2268 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2269 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2270 2271 /* setup DMA if needed */ 2272 pciide_channel_dma_setup(cp); 2273 2274 for (drive = 0; drive < 2; drive++) { 2275 drvp = &chp->ch_drive[drive]; 2276 /* If no drive, skip */ 2277 if ((drvp->drive_flags & DRIVE) == 0) 2278 continue; 2279 /* add timing values, setup DMA if needed */ 2280 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2281 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2282 mode = drvp->PIO_mode; 2283 goto pio; 2284 } 2285 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2286 (drvp->drive_flags & DRIVE_UDMA)) { 2287 /* use Ultra/DMA */ 2288 drvp->drive_flags &= ~DRIVE_DMA; 2289 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2290 APO_UDMA_EN_MTH(chp->channel, drive); 2291 if (sc->sc_wdcdev.UDMA_cap == 5) { 2292 /* 686b */ 2293 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2294 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2295 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2296 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2297 /* 596b or 686a */ 2298 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2299 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2300 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2301 } else { 2302 /* 596a or 586b */ 2303 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2304 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2305 } 2306 /* can use PIO timings, MW DMA unused */ 2307 mode = drvp->PIO_mode; 2308 } else { 2309 /* use Multiword DMA */ 2310 drvp->drive_flags &= ~DRIVE_UDMA; 2311 /* mode = min(pio, dma+2) */ 2312 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2313 mode = drvp->PIO_mode; 2314 else 2315 mode = drvp->DMA_mode + 2; 2316 } 2317 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2318 2319 pio: /* setup PIO mode */ 2320 if (mode <= 2) { 2321 drvp->DMA_mode = 0; 2322 drvp->PIO_mode = 0; 2323 mode = 0; 2324 } else { 2325 drvp->PIO_mode = mode; 2326 drvp->DMA_mode = mode - 2; 2327 } 2328 datatim_reg |= 2329 APO_DATATIM_PULSE(chp->channel, drive, 2330 apollo_pio_set[mode]) | 2331 APO_DATATIM_RECOV(chp->channel, drive, 2332 apollo_pio_rec[mode]); 2333 } 2334 if (idedma_ctl != 0) { 2335 /* Add software bits in status register */ 2336 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2337 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2338 idedma_ctl); 2339 } 2340 pciide_print_modes(cp); 2341 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2342 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2343 } 2344 2345 void 2346 cmd_channel_map(pa, sc, channel) 2347 struct pci_attach_args *pa; 2348 struct pciide_softc *sc; 2349 int channel; 2350 { 2351 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2352 bus_size_t cmdsize, ctlsize; 2353 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2354 int interface, one_channel; 2355 2356 /* 2357 * The 0648/0649 can be told to identify as a RAID controller. 2358 * In this case, we have to fake interface 2359 */ 2360 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2361 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2362 PCIIDE_INTERFACE_SETTABLE(1); 2363 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2364 CMD_CONF_DSA1) 2365 interface |= PCIIDE_INTERFACE_PCI(0) | 2366 PCIIDE_INTERFACE_PCI(1); 2367 } else { 2368 interface = PCI_INTERFACE(pa->pa_class); 2369 } 2370 2371 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2372 cp->name = PCIIDE_CHANNEL_NAME(channel); 2373 cp->wdc_channel.channel = channel; 2374 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2375 2376 /* 2377 * Older CMD64X doesn't have independant channels 2378 */ 2379 switch (sc->sc_pp->ide_product) { 2380 case PCI_PRODUCT_CMDTECH_649: 2381 one_channel = 0; 2382 break; 2383 default: 2384 one_channel = 1; 2385 break; 2386 } 2387 2388 if (channel > 0 && one_channel) { 2389 cp->wdc_channel.ch_queue = 2390 sc->pciide_channels[0].wdc_channel.ch_queue; 2391 } else { 2392 cp->wdc_channel.ch_queue = 2393 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2394 } 2395 if (cp->wdc_channel.ch_queue == NULL) { 2396 printf("%s %s channel: " 2397 "can't allocate memory for command queue", 2398 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2399 return; 2400 } 2401 2402 printf("%s: %s channel %s to %s mode\n", 2403 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2404 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2405 "configured" : "wired", 2406 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2407 "native-PCI" : "compatibility"); 2408 2409 /* 2410 * with a CMD PCI64x, if we get here, the first channel is enabled: 2411 * there's no way to disable the first channel without disabling 2412 * the whole device 2413 */ 2414 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2415 printf("%s: %s channel ignored (disabled)\n", 2416 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2417 return; 2418 } 2419 2420 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2421 if (cp->hw_ok == 0) 2422 return; 2423 if (channel == 1) { 2424 if (pciide_chan_candisable(cp)) { 2425 ctrl &= ~CMD_CTRL_2PORT; 2426 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2427 CMD_CTRL, ctrl); 2428 } 2429 } 2430 pciide_map_compat_intr(pa, cp, channel, interface); 2431 } 2432 2433 int 2434 cmd_pci_intr(arg) 2435 void *arg; 2436 { 2437 struct pciide_softc *sc = arg; 2438 struct pciide_channel *cp; 2439 struct channel_softc *wdc_cp; 2440 int i, rv, crv; 2441 u_int32_t priirq, secirq; 2442 2443 rv = 0; 2444 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2445 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2446 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2447 cp = &sc->pciide_channels[i]; 2448 wdc_cp = &cp->wdc_channel; 2449 /* If a compat channel skip. */ 2450 if (cp->compat) 2451 continue; 2452 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2453 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2454 crv = wdcintr(wdc_cp); 2455 if (crv == 0) 2456 printf("%s:%d: bogus intr\n", 2457 sc->sc_wdcdev.sc_dev.dv_xname, i); 2458 else 2459 rv = 1; 2460 } 2461 } 2462 return rv; 2463 } 2464 2465 void 2466 cmd_chip_map(sc, pa) 2467 struct pciide_softc *sc; 2468 struct pci_attach_args *pa; 2469 { 2470 int channel; 2471 2472 /* 2473 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2474 * and base adresses registers can be disabled at 2475 * hardware level. In this case, the device is wired 2476 * in compat mode and its first channel is always enabled, 2477 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2478 * In fact, it seems that the first channel of the CMD PCI0640 2479 * can't be disabled. 2480 */ 2481 2482 #ifdef PCIIDE_CMD064x_DISABLE 2483 if (pciide_chipen(sc, pa) == 0) 2484 return; 2485 #endif 2486 2487 printf("%s: hardware does not support DMA\n", 2488 sc->sc_wdcdev.sc_dev.dv_xname); 2489 sc->sc_dma_ok = 0; 2490 2491 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2492 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2493 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2494 2495 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2496 cmd_channel_map(pa, sc, channel); 2497 } 2498 } 2499 2500 void 2501 cmd0643_9_chip_map(sc, pa) 2502 struct pciide_softc *sc; 2503 struct pci_attach_args *pa; 2504 { 2505 struct pciide_channel *cp; 2506 int channel; 2507 pcireg_t rev = PCI_REVISION(pa->pa_class); 2508 2509 /* 2510 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2511 * and base adresses registers can be disabled at 2512 * hardware level. In this case, the device is wired 2513 * in compat mode and its first channel is always enabled, 2514 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2515 * In fact, it seems that the first channel of the CMD PCI0640 2516 * can't be disabled. 2517 */ 2518 2519 #ifdef PCIIDE_CMD064x_DISABLE 2520 if (pciide_chipen(sc, pa) == 0) 2521 return; 2522 #endif 2523 printf("%s: bus-master DMA support present", 2524 sc->sc_wdcdev.sc_dev.dv_xname); 2525 pciide_mapreg_dma(sc, pa); 2526 printf("\n"); 2527 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2528 WDC_CAPABILITY_MODE; 2529 if (sc->sc_dma_ok) { 2530 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2531 switch (sc->sc_pp->ide_product) { 2532 case PCI_PRODUCT_CMDTECH_649: 2533 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2534 sc->sc_wdcdev.UDMA_cap = 5; 2535 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2536 break; 2537 case PCI_PRODUCT_CMDTECH_648: 2538 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2539 sc->sc_wdcdev.UDMA_cap = 4; 2540 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2541 break; 2542 case PCI_PRODUCT_CMDTECH_646: 2543 if (rev >= CMD0646U2_REV) { 2544 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2545 sc->sc_wdcdev.UDMA_cap = 2; 2546 } else if (rev >= CMD0646U_REV) { 2547 /* 2548 * Linux's driver claims that the 646U is broken 2549 * with UDMA. Only enable it if we know what we're 2550 * doing 2551 */ 2552 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2553 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2554 sc->sc_wdcdev.UDMA_cap = 2; 2555 #endif 2556 /* explicitly disable UDMA */ 2557 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2558 CMD_UDMATIM(0), 0); 2559 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2560 CMD_UDMATIM(1), 0); 2561 } 2562 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2563 break; 2564 default: 2565 sc->sc_wdcdev.irqack = pciide_irqack; 2566 } 2567 } 2568 2569 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2570 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2571 sc->sc_wdcdev.PIO_cap = 4; 2572 sc->sc_wdcdev.DMA_cap = 2; 2573 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2574 2575 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2576 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2577 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2578 DEBUG_PROBE); 2579 2580 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2581 cp = &sc->pciide_channels[channel]; 2582 cmd_channel_map(pa, sc, channel); 2583 if (cp->hw_ok == 0) 2584 continue; 2585 cmd0643_9_setup_channel(&cp->wdc_channel); 2586 } 2587 /* 2588 * note - this also makes sure we clear the irq disable and reset 2589 * bits 2590 */ 2591 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2592 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2593 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2594 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2595 DEBUG_PROBE); 2596 } 2597 2598 void 2599 cmd0643_9_setup_channel(chp) 2600 struct channel_softc *chp; 2601 { 2602 struct ata_drive_datas *drvp; 2603 u_int8_t tim; 2604 u_int32_t idedma_ctl, udma_reg; 2605 int drive; 2606 struct pciide_channel *cp = (struct pciide_channel*)chp; 2607 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2608 2609 idedma_ctl = 0; 2610 /* setup DMA if needed */ 2611 pciide_channel_dma_setup(cp); 2612 2613 for (drive = 0; drive < 2; drive++) { 2614 drvp = &chp->ch_drive[drive]; 2615 /* If no drive, skip */ 2616 if ((drvp->drive_flags & DRIVE) == 0) 2617 continue; 2618 /* add timing values, setup DMA if needed */ 2619 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2620 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2621 if (drvp->drive_flags & DRIVE_UDMA) { 2622 /* UltraDMA on a 646U2, 0648 or 0649 */ 2623 drvp->drive_flags &= ~DRIVE_DMA; 2624 udma_reg = pciide_pci_read(sc->sc_pc, 2625 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2626 if (drvp->UDMA_mode > 2 && 2627 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2628 CMD_BICSR) & 2629 CMD_BICSR_80(chp->channel)) == 0) 2630 drvp->UDMA_mode = 2; 2631 if (drvp->UDMA_mode > 2) 2632 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2633 else if (sc->sc_wdcdev.UDMA_cap > 2) 2634 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2635 udma_reg |= CMD_UDMATIM_UDMA(drive); 2636 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2637 CMD_UDMATIM_TIM_OFF(drive)); 2638 udma_reg |= 2639 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2640 CMD_UDMATIM_TIM_OFF(drive)); 2641 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2642 CMD_UDMATIM(chp->channel), udma_reg); 2643 } else { 2644 /* 2645 * use Multiword DMA. 2646 * Timings will be used for both PIO and DMA, 2647 * so adjust DMA mode if needed 2648 * if we have a 0646U2/8/9, turn off UDMA 2649 */ 2650 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2651 udma_reg = pciide_pci_read(sc->sc_pc, 2652 sc->sc_tag, 2653 CMD_UDMATIM(chp->channel)); 2654 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2655 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2656 CMD_UDMATIM(chp->channel), 2657 udma_reg); 2658 } 2659 if (drvp->PIO_mode >= 3 && 2660 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2661 drvp->DMA_mode = drvp->PIO_mode - 2; 2662 } 2663 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2664 } 2665 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2666 } 2667 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2668 CMD_DATA_TIM(chp->channel, drive), tim); 2669 } 2670 if (idedma_ctl != 0) { 2671 /* Add software bits in status register */ 2672 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2673 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2674 idedma_ctl); 2675 } 2676 pciide_print_modes(cp); 2677 } 2678 2679 void 2680 cmd646_9_irqack(chp) 2681 struct channel_softc *chp; 2682 { 2683 u_int32_t priirq, secirq; 2684 struct pciide_channel *cp = (struct pciide_channel*)chp; 2685 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2686 2687 if (chp->channel == 0) { 2688 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2689 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2690 } else { 2691 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2692 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2693 } 2694 pciide_irqack(chp); 2695 } 2696 2697 void 2698 cy693_chip_map(sc, pa) 2699 struct pciide_softc *sc; 2700 struct pci_attach_args *pa; 2701 { 2702 struct pciide_channel *cp; 2703 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2704 bus_size_t cmdsize, ctlsize; 2705 2706 if (pciide_chipen(sc, pa) == 0) 2707 return; 2708 /* 2709 * this chip has 2 PCI IDE functions, one for primary and one for 2710 * secondary. So we need to call pciide_mapregs_compat() with 2711 * the real channel 2712 */ 2713 if (pa->pa_function == 1) { 2714 sc->sc_cy_compatchan = 0; 2715 } else if (pa->pa_function == 2) { 2716 sc->sc_cy_compatchan = 1; 2717 } else { 2718 printf("%s: unexpected PCI function %d\n", 2719 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2720 return; 2721 } 2722 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2723 printf("%s: bus-master DMA support present", 2724 sc->sc_wdcdev.sc_dev.dv_xname); 2725 pciide_mapreg_dma(sc, pa); 2726 } else { 2727 printf("%s: hardware does not support DMA", 2728 sc->sc_wdcdev.sc_dev.dv_xname); 2729 sc->sc_dma_ok = 0; 2730 } 2731 printf("\n"); 2732 2733 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2734 if (sc->sc_cy_handle == NULL) { 2735 printf("%s: unable to map hyperCache control registers\n", 2736 sc->sc_wdcdev.sc_dev.dv_xname); 2737 sc->sc_dma_ok = 0; 2738 } 2739 2740 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2741 WDC_CAPABILITY_MODE; 2742 if (sc->sc_dma_ok) { 2743 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2744 sc->sc_wdcdev.irqack = pciide_irqack; 2745 } 2746 sc->sc_wdcdev.PIO_cap = 4; 2747 sc->sc_wdcdev.DMA_cap = 2; 2748 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2749 2750 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2751 sc->sc_wdcdev.nchannels = 1; 2752 2753 /* Only one channel for this chip; if we are here it's enabled */ 2754 cp = &sc->pciide_channels[0]; 2755 sc->wdc_chanarray[0] = &cp->wdc_channel; 2756 cp->name = PCIIDE_CHANNEL_NAME(0); 2757 cp->wdc_channel.channel = 0; 2758 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2759 cp->wdc_channel.ch_queue = 2760 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2761 if (cp->wdc_channel.ch_queue == NULL) { 2762 printf("%s primary channel: " 2763 "can't allocate memory for command queue", 2764 sc->sc_wdcdev.sc_dev.dv_xname); 2765 return; 2766 } 2767 printf("%s: primary channel %s to ", 2768 sc->sc_wdcdev.sc_dev.dv_xname, 2769 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2770 "configured" : "wired"); 2771 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2772 printf("native-PCI"); 2773 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2774 pciide_pci_intr); 2775 } else { 2776 printf("compatibility"); 2777 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2778 &cmdsize, &ctlsize); 2779 } 2780 printf(" mode\n"); 2781 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2782 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2783 wdcattach(&cp->wdc_channel); 2784 if (pciide_chan_candisable(cp)) { 2785 pci_conf_write(sc->sc_pc, sc->sc_tag, 2786 PCI_COMMAND_STATUS_REG, 0); 2787 } 2788 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2789 if (cp->hw_ok == 0) 2790 return; 2791 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2792 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2793 cy693_setup_channel(&cp->wdc_channel); 2794 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2795 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2796 } 2797 2798 void 2799 cy693_setup_channel(chp) 2800 struct channel_softc *chp; 2801 { 2802 struct ata_drive_datas *drvp; 2803 int drive; 2804 u_int32_t cy_cmd_ctrl; 2805 u_int32_t idedma_ctl; 2806 struct pciide_channel *cp = (struct pciide_channel*)chp; 2807 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2808 int dma_mode = -1; 2809 2810 cy_cmd_ctrl = idedma_ctl = 0; 2811 2812 /* setup DMA if needed */ 2813 pciide_channel_dma_setup(cp); 2814 2815 for (drive = 0; drive < 2; drive++) { 2816 drvp = &chp->ch_drive[drive]; 2817 /* If no drive, skip */ 2818 if ((drvp->drive_flags & DRIVE) == 0) 2819 continue; 2820 /* add timing values, setup DMA if needed */ 2821 if (drvp->drive_flags & DRIVE_DMA) { 2822 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2823 /* use Multiword DMA */ 2824 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2825 dma_mode = drvp->DMA_mode; 2826 } 2827 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2828 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2829 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2830 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2831 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2832 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2833 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2834 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2835 } 2836 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2837 chp->ch_drive[0].DMA_mode = dma_mode; 2838 chp->ch_drive[1].DMA_mode = dma_mode; 2839 2840 if (dma_mode == -1) 2841 dma_mode = 0; 2842 2843 if (sc->sc_cy_handle != NULL) { 2844 /* Note: `multiple' is implied. */ 2845 cy82c693_write(sc->sc_cy_handle, 2846 (sc->sc_cy_compatchan == 0) ? 2847 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2848 } 2849 2850 pciide_print_modes(cp); 2851 2852 if (idedma_ctl != 0) { 2853 /* Add software bits in status register */ 2854 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2855 IDEDMA_CTL, idedma_ctl); 2856 } 2857 } 2858 2859 static int 2860 sis_hostbr_match(pa) 2861 struct pci_attach_args *pa; 2862 { 2863 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2864 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2865 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2866 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2867 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2868 } 2869 2870 void 2871 sis_chip_map(sc, pa) 2872 struct pciide_softc *sc; 2873 struct pci_attach_args *pa; 2874 { 2875 struct pciide_channel *cp; 2876 int channel; 2877 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2878 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2879 pcireg_t rev = PCI_REVISION(pa->pa_class); 2880 bus_size_t cmdsize, ctlsize; 2881 pcitag_t pchb_tag; 2882 pcireg_t pchb_id, pchb_class; 2883 2884 if (pciide_chipen(sc, pa) == 0) 2885 return; 2886 printf("%s: bus-master DMA support present", 2887 sc->sc_wdcdev.sc_dev.dv_xname); 2888 pciide_mapreg_dma(sc, pa); 2889 printf("\n"); 2890 2891 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2892 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2893 /* and read ID and rev of the ISA bridge */ 2894 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2895 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2896 2897 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2898 WDC_CAPABILITY_MODE; 2899 if (sc->sc_dma_ok) { 2900 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2901 sc->sc_wdcdev.irqack = pciide_irqack; 2902 /* 2903 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2904 * have problems with UDMA (info provided by Christos) 2905 */ 2906 if (rev >= 0xd0 && 2907 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2908 PCI_REVISION(pchb_class) >= 0x03)) 2909 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2910 } 2911 2912 sc->sc_wdcdev.PIO_cap = 4; 2913 sc->sc_wdcdev.DMA_cap = 2; 2914 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2915 /* 2916 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2917 * chipsets. 2918 */ 2919 sc->sc_wdcdev.UDMA_cap = 2920 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2921 sc->sc_wdcdev.set_modes = sis_setup_channel; 2922 2923 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2924 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2925 2926 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2927 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2928 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2929 2930 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2931 cp = &sc->pciide_channels[channel]; 2932 if (pciide_chansetup(sc, channel, interface) == 0) 2933 continue; 2934 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2935 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2936 printf("%s: %s channel ignored (disabled)\n", 2937 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2938 continue; 2939 } 2940 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2941 pciide_pci_intr); 2942 if (cp->hw_ok == 0) 2943 continue; 2944 if (pciide_chan_candisable(cp)) { 2945 if (channel == 0) 2946 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2947 else 2948 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2949 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2950 sis_ctr0); 2951 } 2952 pciide_map_compat_intr(pa, cp, channel, interface); 2953 if (cp->hw_ok == 0) 2954 continue; 2955 sis_setup_channel(&cp->wdc_channel); 2956 } 2957 } 2958 2959 void 2960 sis_setup_channel(chp) 2961 struct channel_softc *chp; 2962 { 2963 struct ata_drive_datas *drvp; 2964 int drive; 2965 u_int32_t sis_tim; 2966 u_int32_t idedma_ctl; 2967 struct pciide_channel *cp = (struct pciide_channel*)chp; 2968 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2969 2970 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2971 "channel %d 0x%x\n", chp->channel, 2972 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2973 DEBUG_PROBE); 2974 sis_tim = 0; 2975 idedma_ctl = 0; 2976 /* setup DMA if needed */ 2977 pciide_channel_dma_setup(cp); 2978 2979 for (drive = 0; drive < 2; drive++) { 2980 drvp = &chp->ch_drive[drive]; 2981 /* If no drive, skip */ 2982 if ((drvp->drive_flags & DRIVE) == 0) 2983 continue; 2984 /* add timing values, setup DMA if needed */ 2985 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2986 (drvp->drive_flags & DRIVE_UDMA) == 0) 2987 goto pio; 2988 2989 if (drvp->drive_flags & DRIVE_UDMA) { 2990 /* use Ultra/DMA */ 2991 drvp->drive_flags &= ~DRIVE_DMA; 2992 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2993 SIS_TIM_UDMA_TIME_OFF(drive); 2994 sis_tim |= SIS_TIM_UDMA_EN(drive); 2995 } else { 2996 /* 2997 * use Multiword DMA 2998 * Timings will be used for both PIO and DMA, 2999 * so adjust DMA mode if needed 3000 */ 3001 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3002 drvp->PIO_mode = drvp->DMA_mode + 2; 3003 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3004 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3005 drvp->PIO_mode - 2 : 0; 3006 if (drvp->DMA_mode == 0) 3007 drvp->PIO_mode = 0; 3008 } 3009 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3010 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 3011 SIS_TIM_ACT_OFF(drive); 3012 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3013 SIS_TIM_REC_OFF(drive); 3014 } 3015 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3016 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3017 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3018 if (idedma_ctl != 0) { 3019 /* Add software bits in status register */ 3020 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3021 IDEDMA_CTL, idedma_ctl); 3022 } 3023 pciide_print_modes(cp); 3024 } 3025 3026 void 3027 acer_chip_map(sc, pa) 3028 struct pciide_softc *sc; 3029 struct pci_attach_args *pa; 3030 { 3031 struct pciide_channel *cp; 3032 int channel; 3033 pcireg_t cr, interface; 3034 bus_size_t cmdsize, ctlsize; 3035 pcireg_t rev = PCI_REVISION(pa->pa_class); 3036 3037 if (pciide_chipen(sc, pa) == 0) 3038 return; 3039 printf("%s: bus-master DMA support present", 3040 sc->sc_wdcdev.sc_dev.dv_xname); 3041 pciide_mapreg_dma(sc, pa); 3042 printf("\n"); 3043 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3044 WDC_CAPABILITY_MODE; 3045 if (sc->sc_dma_ok) { 3046 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3047 if (rev >= 0x20) { 3048 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3049 if (rev >= 0xC4) 3050 sc->sc_wdcdev.UDMA_cap = 5; 3051 else if (rev >= 0xC2) 3052 sc->sc_wdcdev.UDMA_cap = 4; 3053 else 3054 sc->sc_wdcdev.UDMA_cap = 2; 3055 } 3056 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3057 sc->sc_wdcdev.irqack = pciide_irqack; 3058 } 3059 3060 sc->sc_wdcdev.PIO_cap = 4; 3061 sc->sc_wdcdev.DMA_cap = 2; 3062 sc->sc_wdcdev.set_modes = acer_setup_channel; 3063 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3064 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3065 3066 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3067 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3068 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3069 3070 /* Enable "microsoft register bits" R/W. */ 3071 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3072 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3073 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3074 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3075 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3076 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3077 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3078 ~ACER_CHANSTATUSREGS_RO); 3079 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3080 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3081 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3082 /* Don't use cr, re-read the real register content instead */ 3083 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3084 PCI_CLASS_REG)); 3085 3086 /* From linux: enable "Cable Detection" */ 3087 if (rev >= 0xC2) { 3088 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3089 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3090 | ACER_0x4B_CDETECT); 3091 } 3092 3093 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3094 cp = &sc->pciide_channels[channel]; 3095 if (pciide_chansetup(sc, channel, interface) == 0) 3096 continue; 3097 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3098 printf("%s: %s channel ignored (disabled)\n", 3099 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3100 continue; 3101 } 3102 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3103 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3104 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3105 if (cp->hw_ok == 0) 3106 continue; 3107 if (pciide_chan_candisable(cp)) { 3108 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3109 pci_conf_write(sc->sc_pc, sc->sc_tag, 3110 PCI_CLASS_REG, cr); 3111 } 3112 pciide_map_compat_intr(pa, cp, channel, interface); 3113 acer_setup_channel(&cp->wdc_channel); 3114 } 3115 } 3116 3117 void 3118 acer_setup_channel(chp) 3119 struct channel_softc *chp; 3120 { 3121 struct ata_drive_datas *drvp; 3122 int drive; 3123 u_int32_t acer_fifo_udma; 3124 u_int32_t idedma_ctl; 3125 struct pciide_channel *cp = (struct pciide_channel*)chp; 3126 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3127 3128 idedma_ctl = 0; 3129 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3130 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3131 acer_fifo_udma), DEBUG_PROBE); 3132 /* setup DMA if needed */ 3133 pciide_channel_dma_setup(cp); 3134 3135 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3136 DRIVE_UDMA) { /* check 80 pins cable */ 3137 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3138 ACER_0x4A_80PIN(chp->channel)) { 3139 if (chp->ch_drive[0].UDMA_mode > 2) 3140 chp->ch_drive[0].UDMA_mode = 2; 3141 if (chp->ch_drive[1].UDMA_mode > 2) 3142 chp->ch_drive[1].UDMA_mode = 2; 3143 } 3144 } 3145 3146 for (drive = 0; drive < 2; drive++) { 3147 drvp = &chp->ch_drive[drive]; 3148 /* If no drive, skip */ 3149 if ((drvp->drive_flags & DRIVE) == 0) 3150 continue; 3151 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3152 "channel %d drive %d 0x%x\n", chp->channel, drive, 3153 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3154 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3155 /* clear FIFO/DMA mode */ 3156 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3157 ACER_UDMA_EN(chp->channel, drive) | 3158 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3159 3160 /* add timing values, setup DMA if needed */ 3161 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3162 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3163 acer_fifo_udma |= 3164 ACER_FTH_OPL(chp->channel, drive, 0x1); 3165 goto pio; 3166 } 3167 3168 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3169 if (drvp->drive_flags & DRIVE_UDMA) { 3170 /* use Ultra/DMA */ 3171 drvp->drive_flags &= ~DRIVE_DMA; 3172 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3173 acer_fifo_udma |= 3174 ACER_UDMA_TIM(chp->channel, drive, 3175 acer_udma[drvp->UDMA_mode]); 3176 /* XXX disable if one drive < UDMA3 ? */ 3177 if (drvp->UDMA_mode >= 3) { 3178 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3179 ACER_0x4B, 3180 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3181 ACER_0x4B) | ACER_0x4B_UDMA66); 3182 } 3183 } else { 3184 /* 3185 * use Multiword DMA 3186 * Timings will be used for both PIO and DMA, 3187 * so adjust DMA mode if needed 3188 */ 3189 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3190 drvp->PIO_mode = drvp->DMA_mode + 2; 3191 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3192 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3193 drvp->PIO_mode - 2 : 0; 3194 if (drvp->DMA_mode == 0) 3195 drvp->PIO_mode = 0; 3196 } 3197 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3198 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3199 ACER_IDETIM(chp->channel, drive), 3200 acer_pio[drvp->PIO_mode]); 3201 } 3202 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3203 acer_fifo_udma), DEBUG_PROBE); 3204 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3205 if (idedma_ctl != 0) { 3206 /* Add software bits in status register */ 3207 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3208 IDEDMA_CTL, idedma_ctl); 3209 } 3210 pciide_print_modes(cp); 3211 } 3212 3213 int 3214 acer_pci_intr(arg) 3215 void *arg; 3216 { 3217 struct pciide_softc *sc = arg; 3218 struct pciide_channel *cp; 3219 struct channel_softc *wdc_cp; 3220 int i, rv, crv; 3221 u_int32_t chids; 3222 3223 rv = 0; 3224 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3225 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3226 cp = &sc->pciide_channels[i]; 3227 wdc_cp = &cp->wdc_channel; 3228 /* If a compat channel skip. */ 3229 if (cp->compat) 3230 continue; 3231 if (chids & ACER_CHIDS_INT(i)) { 3232 crv = wdcintr(wdc_cp); 3233 if (crv == 0) 3234 printf("%s:%d: bogus intr\n", 3235 sc->sc_wdcdev.sc_dev.dv_xname, i); 3236 else 3237 rv = 1; 3238 } 3239 } 3240 return rv; 3241 } 3242 3243 void 3244 hpt_chip_map(sc, pa) 3245 struct pciide_softc *sc; 3246 struct pci_attach_args *pa; 3247 { 3248 struct pciide_channel *cp; 3249 int i, compatchan, revision; 3250 pcireg_t interface; 3251 bus_size_t cmdsize, ctlsize; 3252 3253 if (pciide_chipen(sc, pa) == 0) 3254 return; 3255 revision = PCI_REVISION(pa->pa_class); 3256 printf(": Triones/Highpoint "); 3257 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3258 printf("HPT374 IDE Controller\n"); 3259 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3260 if (revision == HPT370_REV) 3261 printf("HPT370 IDE Controller\n"); 3262 else if (revision == HPT370A_REV) 3263 printf("HPT370A IDE Controller\n"); 3264 else if (revision == HPT366_REV) 3265 printf("HPT366 IDE Controller\n"); 3266 else 3267 printf("unknown HPT IDE controller rev %d\n", revision); 3268 } else 3269 printf("unknown HPT IDE controller 0x%x\n", 3270 sc->sc_pp->ide_product); 3271 3272 /* 3273 * when the chip is in native mode it identifies itself as a 3274 * 'misc mass storage'. Fake interface in this case. 3275 */ 3276 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3277 interface = PCI_INTERFACE(pa->pa_class); 3278 } else { 3279 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3280 PCIIDE_INTERFACE_PCI(0); 3281 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3282 (revision == HPT370_REV || revision == HPT370A_REV)) || 3283 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3284 interface |= PCIIDE_INTERFACE_PCI(1); 3285 } 3286 3287 printf("%s: bus-master DMA support present", 3288 sc->sc_wdcdev.sc_dev.dv_xname); 3289 pciide_mapreg_dma(sc, pa); 3290 printf("\n"); 3291 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3292 WDC_CAPABILITY_MODE; 3293 if (sc->sc_dma_ok) { 3294 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3295 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3296 sc->sc_wdcdev.irqack = pciide_irqack; 3297 } 3298 sc->sc_wdcdev.PIO_cap = 4; 3299 sc->sc_wdcdev.DMA_cap = 2; 3300 3301 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3302 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3303 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3304 revision == HPT366_REV) { 3305 sc->sc_wdcdev.UDMA_cap = 4; 3306 /* 3307 * The 366 has 2 PCI IDE functions, one for primary and one 3308 * for secondary. So we need to call pciide_mapregs_compat() 3309 * with the real channel 3310 */ 3311 if (pa->pa_function == 0) { 3312 compatchan = 0; 3313 } else if (pa->pa_function == 1) { 3314 compatchan = 1; 3315 } else { 3316 printf("%s: unexpected PCI function %d\n", 3317 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3318 return; 3319 } 3320 sc->sc_wdcdev.nchannels = 1; 3321 } else { 3322 sc->sc_wdcdev.nchannels = 2; 3323 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3324 sc->sc_wdcdev.UDMA_cap = 6; 3325 else 3326 sc->sc_wdcdev.UDMA_cap = 5; 3327 } 3328 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3329 cp = &sc->pciide_channels[i]; 3330 if (sc->sc_wdcdev.nchannels > 1) { 3331 compatchan = i; 3332 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3333 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3334 printf("%s: %s channel ignored (disabled)\n", 3335 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3336 continue; 3337 } 3338 } 3339 if (pciide_chansetup(sc, i, interface) == 0) 3340 continue; 3341 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3342 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3343 &ctlsize, hpt_pci_intr); 3344 } else { 3345 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3346 &cmdsize, &ctlsize); 3347 } 3348 if (cp->hw_ok == 0) 3349 return; 3350 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3351 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3352 wdcattach(&cp->wdc_channel); 3353 hpt_setup_channel(&cp->wdc_channel); 3354 } 3355 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3356 (revision == HPT370_REV || revision == HPT370A_REV)) || 3357 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3358 /* 3359 * HPT370_REV and highter has a bit to disable interrupts, 3360 * make sure to clear it 3361 */ 3362 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3363 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3364 ~HPT_CSEL_IRQDIS); 3365 } 3366 /* set clocks, etc (mandatory on 374, optional otherwise) */ 3367 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3368 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3369 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3370 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3371 return; 3372 } 3373 3374 void 3375 hpt_setup_channel(chp) 3376 struct channel_softc *chp; 3377 { 3378 struct ata_drive_datas *drvp; 3379 int drive; 3380 int cable; 3381 u_int32_t before, after; 3382 u_int32_t idedma_ctl; 3383 struct pciide_channel *cp = (struct pciide_channel*)chp; 3384 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3385 3386 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3387 3388 /* setup DMA if needed */ 3389 pciide_channel_dma_setup(cp); 3390 3391 idedma_ctl = 0; 3392 3393 /* Per drive settings */ 3394 for (drive = 0; drive < 2; drive++) { 3395 drvp = &chp->ch_drive[drive]; 3396 /* If no drive, skip */ 3397 if ((drvp->drive_flags & DRIVE) == 0) 3398 continue; 3399 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3400 HPT_IDETIM(chp->channel, drive)); 3401 3402 /* add timing values, setup DMA if needed */ 3403 if (drvp->drive_flags & DRIVE_UDMA) { 3404 /* use Ultra/DMA */ 3405 drvp->drive_flags &= ~DRIVE_DMA; 3406 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3407 drvp->UDMA_mode > 2) 3408 drvp->UDMA_mode = 2; 3409 after = (sc->sc_wdcdev.nchannels == 2) ? 3410 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3411 hpt374_udma[drvp->UDMA_mode] : 3412 hpt370_udma[drvp->UDMA_mode]) : 3413 hpt366_udma[drvp->UDMA_mode]; 3414 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3415 } else if (drvp->drive_flags & DRIVE_DMA) { 3416 /* 3417 * use Multiword DMA. 3418 * Timings will be used for both PIO and DMA, so adjust 3419 * DMA mode if needed 3420 */ 3421 if (drvp->PIO_mode >= 3 && 3422 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3423 drvp->DMA_mode = drvp->PIO_mode - 2; 3424 } 3425 after = (sc->sc_wdcdev.nchannels == 2) ? 3426 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3427 hpt374_dma[drvp->DMA_mode] : 3428 hpt370_dma[drvp->DMA_mode]) : 3429 hpt366_dma[drvp->DMA_mode]; 3430 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3431 } else { 3432 /* PIO only */ 3433 after = (sc->sc_wdcdev.nchannels == 2) ? 3434 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3435 hpt374_pio[drvp->PIO_mode] : 3436 hpt370_pio[drvp->PIO_mode]) : 3437 hpt366_pio[drvp->PIO_mode]; 3438 } 3439 pci_conf_write(sc->sc_pc, sc->sc_tag, 3440 HPT_IDETIM(chp->channel, drive), after); 3441 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3442 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3443 after, before), DEBUG_PROBE); 3444 } 3445 if (idedma_ctl != 0) { 3446 /* Add software bits in status register */ 3447 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3448 IDEDMA_CTL, idedma_ctl); 3449 } 3450 pciide_print_modes(cp); 3451 } 3452 3453 int 3454 hpt_pci_intr(arg) 3455 void *arg; 3456 { 3457 struct pciide_softc *sc = arg; 3458 struct pciide_channel *cp; 3459 struct channel_softc *wdc_cp; 3460 int rv = 0; 3461 int dmastat, i, crv; 3462 3463 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3464 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3465 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3466 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3467 IDEDMA_CTL_INTR) 3468 continue; 3469 cp = &sc->pciide_channels[i]; 3470 wdc_cp = &cp->wdc_channel; 3471 crv = wdcintr(wdc_cp); 3472 if (crv == 0) { 3473 printf("%s:%d: bogus intr\n", 3474 sc->sc_wdcdev.sc_dev.dv_xname, i); 3475 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3476 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3477 } else 3478 rv = 1; 3479 } 3480 return rv; 3481 } 3482 3483 3484 /* Macros to test product */ 3485 #define PDC_IS_262(sc) \ 3486 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3487 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3488 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3489 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3490 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3491 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3492 #define PDC_IS_265(sc) \ 3493 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3494 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3495 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3496 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3497 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3498 #define PDC_IS_268(sc) \ 3499 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3500 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3501 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3502 3503 void 3504 pdc202xx_chip_map(sc, pa) 3505 struct pciide_softc *sc; 3506 struct pci_attach_args *pa; 3507 { 3508 struct pciide_channel *cp; 3509 int channel; 3510 pcireg_t interface, st, mode; 3511 bus_size_t cmdsize, ctlsize; 3512 3513 if (!PDC_IS_268(sc)) { 3514 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3515 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3516 st), DEBUG_PROBE); 3517 } 3518 if (pciide_chipen(sc, pa) == 0) 3519 return; 3520 3521 /* turn off RAID mode */ 3522 if (!PDC_IS_268(sc)) 3523 st &= ~PDC2xx_STATE_IDERAID; 3524 3525 /* 3526 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3527 * mode. We have to fake interface 3528 */ 3529 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3530 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3531 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3532 3533 printf("%s: bus-master DMA support present", 3534 sc->sc_wdcdev.sc_dev.dv_xname); 3535 pciide_mapreg_dma(sc, pa); 3536 printf("\n"); 3537 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3538 WDC_CAPABILITY_MODE; 3539 if (sc->sc_dma_ok) { 3540 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3541 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3542 sc->sc_wdcdev.irqack = pciide_irqack; 3543 } 3544 sc->sc_wdcdev.PIO_cap = 4; 3545 sc->sc_wdcdev.DMA_cap = 2; 3546 if (PDC_IS_265(sc)) 3547 sc->sc_wdcdev.UDMA_cap = 5; 3548 else if (PDC_IS_262(sc)) 3549 sc->sc_wdcdev.UDMA_cap = 4; 3550 else 3551 sc->sc_wdcdev.UDMA_cap = 2; 3552 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3553 pdc20268_setup_channel : pdc202xx_setup_channel; 3554 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3555 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3556 3557 if (!PDC_IS_268(sc)) { 3558 /* setup failsafe defaults */ 3559 mode = 0; 3560 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3561 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3562 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3563 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3564 for (channel = 0; 3565 channel < sc->sc_wdcdev.nchannels; 3566 channel++) { 3567 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3568 "drive 0 initial timings 0x%x, now 0x%x\n", 3569 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3570 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3571 DEBUG_PROBE); 3572 pci_conf_write(sc->sc_pc, sc->sc_tag, 3573 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3574 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3575 "drive 1 initial timings 0x%x, now 0x%x\n", 3576 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3577 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3578 pci_conf_write(sc->sc_pc, sc->sc_tag, 3579 PDC2xx_TIM(channel, 1), mode); 3580 } 3581 3582 mode = PDC2xx_SCR_DMA; 3583 if (PDC_IS_262(sc)) { 3584 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3585 } else { 3586 /* the BIOS set it up this way */ 3587 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3588 } 3589 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3590 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3591 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3592 "now 0x%x\n", 3593 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3594 PDC2xx_SCR), 3595 mode), DEBUG_PROBE); 3596 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3597 PDC2xx_SCR, mode); 3598 3599 /* controller initial state register is OK even without BIOS */ 3600 /* Set DMA mode to IDE DMA compatibility */ 3601 mode = 3602 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3603 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3604 DEBUG_PROBE); 3605 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3606 mode | 0x1); 3607 mode = 3608 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3609 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3610 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3611 mode | 0x1); 3612 } 3613 3614 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3615 cp = &sc->pciide_channels[channel]; 3616 if (pciide_chansetup(sc, channel, interface) == 0) 3617 continue; 3618 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3619 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3620 printf("%s: %s channel ignored (disabled)\n", 3621 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3622 continue; 3623 } 3624 if (PDC_IS_265(sc)) 3625 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3626 pdc20265_pci_intr); 3627 else 3628 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3629 pdc202xx_pci_intr); 3630 if (cp->hw_ok == 0) 3631 continue; 3632 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3633 st &= ~(PDC_IS_262(sc) ? 3634 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3635 pciide_map_compat_intr(pa, cp, channel, interface); 3636 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3637 } 3638 if (!PDC_IS_268(sc)) { 3639 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3640 "0x%x\n", st), DEBUG_PROBE); 3641 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3642 } 3643 return; 3644 } 3645 3646 void 3647 pdc202xx_setup_channel(chp) 3648 struct channel_softc *chp; 3649 { 3650 struct ata_drive_datas *drvp; 3651 int drive; 3652 pcireg_t mode, st; 3653 u_int32_t idedma_ctl, scr, atapi; 3654 struct pciide_channel *cp = (struct pciide_channel*)chp; 3655 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3656 int channel = chp->channel; 3657 3658 /* setup DMA if needed */ 3659 pciide_channel_dma_setup(cp); 3660 3661 idedma_ctl = 0; 3662 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3663 sc->sc_wdcdev.sc_dev.dv_xname, 3664 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3665 DEBUG_PROBE); 3666 3667 /* Per channel settings */ 3668 if (PDC_IS_262(sc)) { 3669 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3670 PDC262_U66); 3671 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3672 /* Trim UDMA mode */ 3673 if ((st & PDC262_STATE_80P(channel)) != 0 || 3674 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3675 chp->ch_drive[0].UDMA_mode <= 2) || 3676 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3677 chp->ch_drive[1].UDMA_mode <= 2)) { 3678 if (chp->ch_drive[0].UDMA_mode > 2) 3679 chp->ch_drive[0].UDMA_mode = 2; 3680 if (chp->ch_drive[1].UDMA_mode > 2) 3681 chp->ch_drive[1].UDMA_mode = 2; 3682 } 3683 /* Set U66 if needed */ 3684 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3685 chp->ch_drive[0].UDMA_mode > 2) || 3686 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3687 chp->ch_drive[1].UDMA_mode > 2)) 3688 scr |= PDC262_U66_EN(channel); 3689 else 3690 scr &= ~PDC262_U66_EN(channel); 3691 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3692 PDC262_U66, scr); 3693 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3694 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3695 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3696 PDC262_ATAPI(channel))), DEBUG_PROBE); 3697 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3698 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3699 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3700 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3701 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3702 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3703 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3704 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3705 atapi = 0; 3706 else 3707 atapi = PDC262_ATAPI_UDMA; 3708 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3709 PDC262_ATAPI(channel), atapi); 3710 } 3711 } 3712 for (drive = 0; drive < 2; drive++) { 3713 drvp = &chp->ch_drive[drive]; 3714 /* If no drive, skip */ 3715 if ((drvp->drive_flags & DRIVE) == 0) 3716 continue; 3717 mode = 0; 3718 if (drvp->drive_flags & DRIVE_UDMA) { 3719 /* use Ultra/DMA */ 3720 drvp->drive_flags &= ~DRIVE_DMA; 3721 mode = PDC2xx_TIM_SET_MB(mode, 3722 pdc2xx_udma_mb[drvp->UDMA_mode]); 3723 mode = PDC2xx_TIM_SET_MC(mode, 3724 pdc2xx_udma_mc[drvp->UDMA_mode]); 3725 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3726 } else if (drvp->drive_flags & DRIVE_DMA) { 3727 mode = PDC2xx_TIM_SET_MB(mode, 3728 pdc2xx_dma_mb[drvp->DMA_mode]); 3729 mode = PDC2xx_TIM_SET_MC(mode, 3730 pdc2xx_dma_mc[drvp->DMA_mode]); 3731 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3732 } else { 3733 mode = PDC2xx_TIM_SET_MB(mode, 3734 pdc2xx_dma_mb[0]); 3735 mode = PDC2xx_TIM_SET_MC(mode, 3736 pdc2xx_dma_mc[0]); 3737 } 3738 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3739 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3740 if (drvp->drive_flags & DRIVE_ATA) 3741 mode |= PDC2xx_TIM_PRE; 3742 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3743 if (drvp->PIO_mode >= 3) { 3744 mode |= PDC2xx_TIM_IORDY; 3745 if (drive == 0) 3746 mode |= PDC2xx_TIM_IORDYp; 3747 } 3748 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3749 "timings 0x%x\n", 3750 sc->sc_wdcdev.sc_dev.dv_xname, 3751 chp->channel, drive, mode), DEBUG_PROBE); 3752 pci_conf_write(sc->sc_pc, sc->sc_tag, 3753 PDC2xx_TIM(chp->channel, drive), mode); 3754 } 3755 if (idedma_ctl != 0) { 3756 /* Add software bits in status register */ 3757 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3758 IDEDMA_CTL, idedma_ctl); 3759 } 3760 pciide_print_modes(cp); 3761 } 3762 3763 void 3764 pdc20268_setup_channel(chp) 3765 struct channel_softc *chp; 3766 { 3767 struct ata_drive_datas *drvp; 3768 int drive; 3769 u_int32_t idedma_ctl; 3770 struct pciide_channel *cp = (struct pciide_channel*)chp; 3771 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3772 int u100; 3773 3774 /* setup DMA if needed */ 3775 pciide_channel_dma_setup(cp); 3776 3777 idedma_ctl = 0; 3778 3779 /* I don't know what this is for, FreeBSD does it ... */ 3780 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3781 IDEDMA_CMD + 0x1, 0x0b); 3782 3783 /* 3784 * I don't know what this is for; FreeBSD checks this ... this is not 3785 * cable type detect. 3786 */ 3787 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3788 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3789 3790 for (drive = 0; drive < 2; drive++) { 3791 drvp = &chp->ch_drive[drive]; 3792 /* If no drive, skip */ 3793 if ((drvp->drive_flags & DRIVE) == 0) 3794 continue; 3795 if (drvp->drive_flags & DRIVE_UDMA) { 3796 /* use Ultra/DMA */ 3797 drvp->drive_flags &= ~DRIVE_DMA; 3798 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3799 if (drvp->UDMA_mode > 2 && u100 == 0) 3800 drvp->UDMA_mode = 2; 3801 } else if (drvp->drive_flags & DRIVE_DMA) { 3802 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3803 } 3804 } 3805 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3806 if (idedma_ctl != 0) { 3807 /* Add software bits in status register */ 3808 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3809 IDEDMA_CTL, idedma_ctl); 3810 } 3811 pciide_print_modes(cp); 3812 } 3813 3814 int 3815 pdc202xx_pci_intr(arg) 3816 void *arg; 3817 { 3818 struct pciide_softc *sc = arg; 3819 struct pciide_channel *cp; 3820 struct channel_softc *wdc_cp; 3821 int i, rv, crv; 3822 u_int32_t scr; 3823 3824 rv = 0; 3825 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3826 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3827 cp = &sc->pciide_channels[i]; 3828 wdc_cp = &cp->wdc_channel; 3829 /* If a compat channel skip. */ 3830 if (cp->compat) 3831 continue; 3832 if (scr & PDC2xx_SCR_INT(i)) { 3833 crv = wdcintr(wdc_cp); 3834 if (crv == 0) 3835 printf("%s:%d: bogus intr (reg 0x%x)\n", 3836 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3837 else 3838 rv = 1; 3839 } 3840 } 3841 return rv; 3842 } 3843 3844 int 3845 pdc20265_pci_intr(arg) 3846 void *arg; 3847 { 3848 struct pciide_softc *sc = arg; 3849 struct pciide_channel *cp; 3850 struct channel_softc *wdc_cp; 3851 int i, rv, crv; 3852 u_int32_t dmastat; 3853 3854 rv = 0; 3855 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3856 cp = &sc->pciide_channels[i]; 3857 wdc_cp = &cp->wdc_channel; 3858 /* If a compat channel skip. */ 3859 if (cp->compat) 3860 continue; 3861 /* 3862 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3863 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3864 * So use it instead (requires 2 reg reads instead of 1, 3865 * but we can't do it another way). 3866 */ 3867 dmastat = bus_space_read_1(sc->sc_dma_iot, 3868 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3869 if((dmastat & IDEDMA_CTL_INTR) == 0) 3870 continue; 3871 crv = wdcintr(wdc_cp); 3872 if (crv == 0) 3873 printf("%s:%d: bogus intr\n", 3874 sc->sc_wdcdev.sc_dev.dv_xname, i); 3875 else 3876 rv = 1; 3877 } 3878 return rv; 3879 } 3880 3881 void 3882 opti_chip_map(sc, pa) 3883 struct pciide_softc *sc; 3884 struct pci_attach_args *pa; 3885 { 3886 struct pciide_channel *cp; 3887 bus_size_t cmdsize, ctlsize; 3888 pcireg_t interface; 3889 u_int8_t init_ctrl; 3890 int channel; 3891 3892 if (pciide_chipen(sc, pa) == 0) 3893 return; 3894 printf("%s: bus-master DMA support present", 3895 sc->sc_wdcdev.sc_dev.dv_xname); 3896 3897 /* 3898 * XXXSCW: 3899 * There seem to be a couple of buggy revisions/implementations 3900 * of the OPTi pciide chipset. This kludge seems to fix one of 3901 * the reported problems (PR/11644) but still fails for the 3902 * other (PR/13151), although the latter may be due to other 3903 * issues too... 3904 */ 3905 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3906 printf(" but disabled due to chip rev. <= 0x12"); 3907 sc->sc_dma_ok = 0; 3908 } else 3909 pciide_mapreg_dma(sc, pa); 3910 3911 printf("\n"); 3912 3913 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 3914 WDC_CAPABILITY_MODE; 3915 sc->sc_wdcdev.PIO_cap = 4; 3916 if (sc->sc_dma_ok) { 3917 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3918 sc->sc_wdcdev.irqack = pciide_irqack; 3919 sc->sc_wdcdev.DMA_cap = 2; 3920 } 3921 sc->sc_wdcdev.set_modes = opti_setup_channel; 3922 3923 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3924 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3925 3926 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3927 OPTI_REG_INIT_CONTROL); 3928 3929 interface = PCI_INTERFACE(pa->pa_class); 3930 3931 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3932 cp = &sc->pciide_channels[channel]; 3933 if (pciide_chansetup(sc, channel, interface) == 0) 3934 continue; 3935 if (channel == 1 && 3936 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3937 printf("%s: %s channel ignored (disabled)\n", 3938 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3939 continue; 3940 } 3941 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3942 pciide_pci_intr); 3943 if (cp->hw_ok == 0) 3944 continue; 3945 pciide_map_compat_intr(pa, cp, channel, interface); 3946 if (cp->hw_ok == 0) 3947 continue; 3948 opti_setup_channel(&cp->wdc_channel); 3949 } 3950 } 3951 3952 void 3953 opti_setup_channel(chp) 3954 struct channel_softc *chp; 3955 { 3956 struct ata_drive_datas *drvp; 3957 struct pciide_channel *cp = (struct pciide_channel*)chp; 3958 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3959 int drive, spd; 3960 int mode[2]; 3961 u_int8_t rv, mr; 3962 3963 /* 3964 * The `Delay' and `Address Setup Time' fields of the 3965 * Miscellaneous Register are always zero initially. 3966 */ 3967 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3968 mr &= ~(OPTI_MISC_DELAY_MASK | 3969 OPTI_MISC_ADDR_SETUP_MASK | 3970 OPTI_MISC_INDEX_MASK); 3971 3972 /* Prime the control register before setting timing values */ 3973 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3974 3975 /* Determine the clockrate of the PCIbus the chip is attached to */ 3976 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3977 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3978 3979 /* setup DMA if needed */ 3980 pciide_channel_dma_setup(cp); 3981 3982 for (drive = 0; drive < 2; drive++) { 3983 drvp = &chp->ch_drive[drive]; 3984 /* If no drive, skip */ 3985 if ((drvp->drive_flags & DRIVE) == 0) { 3986 mode[drive] = -1; 3987 continue; 3988 } 3989 3990 if ((drvp->drive_flags & DRIVE_DMA)) { 3991 /* 3992 * Timings will be used for both PIO and DMA, 3993 * so adjust DMA mode if needed 3994 */ 3995 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3996 drvp->PIO_mode = drvp->DMA_mode + 2; 3997 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3998 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3999 drvp->PIO_mode - 2 : 0; 4000 if (drvp->DMA_mode == 0) 4001 drvp->PIO_mode = 0; 4002 4003 mode[drive] = drvp->DMA_mode + 5; 4004 } else 4005 mode[drive] = drvp->PIO_mode; 4006 4007 if (drive && mode[0] >= 0 && 4008 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4009 /* 4010 * Can't have two drives using different values 4011 * for `Address Setup Time'. 4012 * Slow down the faster drive to compensate. 4013 */ 4014 int d = (opti_tim_as[spd][mode[0]] > 4015 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4016 4017 mode[d] = mode[1-d]; 4018 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4019 chp->ch_drive[d].DMA_mode = 0; 4020 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4021 } 4022 } 4023 4024 for (drive = 0; drive < 2; drive++) { 4025 int m; 4026 if ((m = mode[drive]) < 0) 4027 continue; 4028 4029 /* Set the Address Setup Time and select appropriate index */ 4030 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4031 rv |= OPTI_MISC_INDEX(drive); 4032 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4033 4034 /* Set the pulse width and recovery timing parameters */ 4035 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4036 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4037 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4038 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4039 4040 /* Set the Enhanced Mode register appropriately */ 4041 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4042 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4043 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4044 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4045 } 4046 4047 /* Finally, enable the timings */ 4048 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4049 4050 pciide_print_modes(cp); 4051 } 4052 4053 #define ACARD_IS_850(sc) \ 4054 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4055 4056 void 4057 acard_chip_map(sc, pa) 4058 struct pciide_softc *sc; 4059 struct pci_attach_args *pa; 4060 { 4061 struct pciide_channel *cp; 4062 int i; 4063 pcireg_t interface; 4064 bus_size_t cmdsize, ctlsize; 4065 4066 if (pciide_chipen(sc, pa) == 0) 4067 return; 4068 4069 /* 4070 * when the chip is in native mode it identifies itself as a 4071 * 'misc mass storage'. Fake interface in this case. 4072 */ 4073 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4074 interface = PCI_INTERFACE(pa->pa_class); 4075 } else { 4076 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4077 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4078 } 4079 4080 printf("%s: bus-master DMA support present", 4081 sc->sc_wdcdev.sc_dev.dv_xname); 4082 pciide_mapreg_dma(sc, pa); 4083 printf("\n"); 4084 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4085 WDC_CAPABILITY_MODE; 4086 4087 if (sc->sc_dma_ok) { 4088 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4089 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4090 sc->sc_wdcdev.irqack = pciide_irqack; 4091 } 4092 sc->sc_wdcdev.PIO_cap = 4; 4093 sc->sc_wdcdev.DMA_cap = 2; 4094 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4095 4096 sc->sc_wdcdev.set_modes = acard_setup_channel; 4097 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4098 sc->sc_wdcdev.nchannels = 2; 4099 4100 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4101 cp = &sc->pciide_channels[i]; 4102 if (pciide_chansetup(sc, i, interface) == 0) 4103 continue; 4104 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4105 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4106 &ctlsize, pciide_pci_intr); 4107 } else { 4108 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4109 &cmdsize, &ctlsize); 4110 } 4111 if (cp->hw_ok == 0) 4112 return; 4113 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4114 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4115 wdcattach(&cp->wdc_channel); 4116 acard_setup_channel(&cp->wdc_channel); 4117 } 4118 if (!ACARD_IS_850(sc)) { 4119 u_int32_t reg; 4120 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4121 reg &= ~ATP860_CTRL_INT; 4122 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4123 } 4124 } 4125 4126 void 4127 acard_setup_channel(chp) 4128 struct channel_softc *chp; 4129 { 4130 struct ata_drive_datas *drvp; 4131 struct pciide_channel *cp = (struct pciide_channel*)chp; 4132 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4133 int channel = chp->channel; 4134 int drive; 4135 u_int32_t idetime, udma_mode; 4136 u_int32_t idedma_ctl; 4137 4138 /* setup DMA if needed */ 4139 pciide_channel_dma_setup(cp); 4140 4141 if (ACARD_IS_850(sc)) { 4142 idetime = 0; 4143 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4144 udma_mode &= ~ATP850_UDMA_MASK(channel); 4145 } else { 4146 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4147 idetime &= ~ATP860_SETTIME_MASK(channel); 4148 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4149 udma_mode &= ~ATP860_UDMA_MASK(channel); 4150 4151 /* check 80 pins cable */ 4152 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4153 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4154 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4155 & ATP860_CTRL_80P(chp->channel)) { 4156 if (chp->ch_drive[0].UDMA_mode > 2) 4157 chp->ch_drive[0].UDMA_mode = 2; 4158 if (chp->ch_drive[1].UDMA_mode > 2) 4159 chp->ch_drive[1].UDMA_mode = 2; 4160 } 4161 } 4162 } 4163 4164 idedma_ctl = 0; 4165 4166 /* Per drive settings */ 4167 for (drive = 0; drive < 2; drive++) { 4168 drvp = &chp->ch_drive[drive]; 4169 /* If no drive, skip */ 4170 if ((drvp->drive_flags & DRIVE) == 0) 4171 continue; 4172 /* add timing values, setup DMA if needed */ 4173 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4174 (drvp->drive_flags & DRIVE_UDMA)) { 4175 /* use Ultra/DMA */ 4176 if (ACARD_IS_850(sc)) { 4177 idetime |= ATP850_SETTIME(drive, 4178 acard_act_udma[drvp->UDMA_mode], 4179 acard_rec_udma[drvp->UDMA_mode]); 4180 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4181 acard_udma_conf[drvp->UDMA_mode]); 4182 } else { 4183 idetime |= ATP860_SETTIME(channel, drive, 4184 acard_act_udma[drvp->UDMA_mode], 4185 acard_rec_udma[drvp->UDMA_mode]); 4186 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4187 acard_udma_conf[drvp->UDMA_mode]); 4188 } 4189 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4190 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4191 (drvp->drive_flags & DRIVE_DMA)) { 4192 /* use Multiword DMA */ 4193 drvp->drive_flags &= ~DRIVE_UDMA; 4194 if (ACARD_IS_850(sc)) { 4195 idetime |= ATP850_SETTIME(drive, 4196 acard_act_dma[drvp->DMA_mode], 4197 acard_rec_dma[drvp->DMA_mode]); 4198 } else { 4199 idetime |= ATP860_SETTIME(channel, drive, 4200 acard_act_dma[drvp->DMA_mode], 4201 acard_rec_dma[drvp->DMA_mode]); 4202 } 4203 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4204 } else { 4205 /* PIO only */ 4206 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4207 if (ACARD_IS_850(sc)) { 4208 idetime |= ATP850_SETTIME(drive, 4209 acard_act_pio[drvp->PIO_mode], 4210 acard_rec_pio[drvp->PIO_mode]); 4211 } else { 4212 idetime |= ATP860_SETTIME(channel, drive, 4213 acard_act_pio[drvp->PIO_mode], 4214 acard_rec_pio[drvp->PIO_mode]); 4215 } 4216 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4217 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4218 | ATP8x0_CTRL_EN(channel)); 4219 } 4220 } 4221 4222 if (idedma_ctl != 0) { 4223 /* Add software bits in status register */ 4224 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4225 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4226 } 4227 pciide_print_modes(cp); 4228 4229 if (ACARD_IS_850(sc)) { 4230 pci_conf_write(sc->sc_pc, sc->sc_tag, 4231 ATP850_IDETIME(channel), idetime); 4232 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4233 } else { 4234 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4235 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4236 } 4237 } 4238 4239 int 4240 acard_pci_intr(arg) 4241 void *arg; 4242 { 4243 struct pciide_softc *sc = arg; 4244 struct pciide_channel *cp; 4245 struct channel_softc *wdc_cp; 4246 int rv = 0; 4247 int dmastat, i, crv; 4248 4249 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4250 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4251 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4252 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4253 continue; 4254 cp = &sc->pciide_channels[i]; 4255 wdc_cp = &cp->wdc_channel; 4256 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4257 (void)wdcintr(wdc_cp); 4258 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4259 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4260 continue; 4261 } 4262 crv = wdcintr(wdc_cp); 4263 if (crv == 0) 4264 printf("%s:%d: bogus intr\n", 4265 sc->sc_wdcdev.sc_dev.dv_xname, i); 4266 else if (crv == 1) 4267 rv = 1; 4268 else if (rv == 0) 4269 rv = crv; 4270 } 4271 return rv; 4272 } 4273 4274 static int 4275 sl82c105_bugchk(struct pci_attach_args *pa) 4276 { 4277 4278 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4279 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4280 return (0); 4281 4282 if (PCI_REVISION(pa->pa_class) <= 0x05) 4283 return (1); 4284 4285 return (0); 4286 } 4287 4288 void 4289 sl82c105_chip_map(sc, pa) 4290 struct pciide_softc *sc; 4291 struct pci_attach_args *pa; 4292 { 4293 struct pciide_channel *cp; 4294 bus_size_t cmdsize, ctlsize; 4295 pcireg_t interface, idecr; 4296 int channel; 4297 4298 if (pciide_chipen(sc, pa) == 0) 4299 return; 4300 4301 printf("%s: bus-master DMA support present", 4302 sc->sc_wdcdev.sc_dev.dv_xname); 4303 4304 /* 4305 * Check to see if we're part of the Winbond 83c553 Southbridge. 4306 * If so, we need to disable DMA on rev. <= 5 of that chip. 4307 */ 4308 if (pci_find_device(pa, sl82c105_bugchk)) { 4309 printf(" but disabled due to 83c553 rev. <= 0x05"); 4310 sc->sc_dma_ok = 0; 4311 } else 4312 pciide_mapreg_dma(sc, pa); 4313 printf("\n"); 4314 4315 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4316 WDC_CAPABILITY_MODE; 4317 sc->sc_wdcdev.PIO_cap = 4; 4318 if (sc->sc_dma_ok) { 4319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4320 sc->sc_wdcdev.irqack = pciide_irqack; 4321 sc->sc_wdcdev.DMA_cap = 2; 4322 } 4323 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4324 4325 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4326 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4327 4328 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4329 4330 interface = PCI_INTERFACE(pa->pa_class); 4331 4332 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4333 cp = &sc->pciide_channels[channel]; 4334 if (pciide_chansetup(sc, channel, interface) == 0) 4335 continue; 4336 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4337 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4338 printf("%s: %s channel ignored (disabled)\n", 4339 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4340 continue; 4341 } 4342 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4343 pciide_pci_intr); 4344 if (cp->hw_ok == 0) 4345 continue; 4346 pciide_map_compat_intr(pa, cp, channel, interface); 4347 if (cp->hw_ok == 0) 4348 continue; 4349 sl82c105_setup_channel(&cp->wdc_channel); 4350 } 4351 } 4352 4353 void 4354 sl82c105_setup_channel(chp) 4355 struct channel_softc *chp; 4356 { 4357 struct ata_drive_datas *drvp; 4358 struct pciide_channel *cp = (struct pciide_channel*)chp; 4359 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4360 int pxdx_reg, drive; 4361 pcireg_t pxdx; 4362 4363 /* Set up DMA if needed. */ 4364 pciide_channel_dma_setup(cp); 4365 4366 for (drive = 0; drive < 2; drive++) { 4367 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4368 : SYMPH_P1D0CR) + (drive * 4); 4369 4370 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4371 4372 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4373 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4374 4375 drvp = &chp->ch_drive[drive]; 4376 /* If no drive, skip. */ 4377 if ((drvp->drive_flags & DRIVE) == 0) { 4378 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4379 continue; 4380 } 4381 4382 if (drvp->drive_flags & DRIVE_DMA) { 4383 /* 4384 * Timings will be used for both PIO and DMA, 4385 * so adjust DMA mode if needed. 4386 */ 4387 if (drvp->PIO_mode >= 3) { 4388 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4389 drvp->DMA_mode = drvp->PIO_mode - 2; 4390 if (drvp->DMA_mode < 1) { 4391 /* 4392 * Can't mix both PIO and DMA. 4393 * Disable DMA. 4394 */ 4395 drvp->drive_flags &= ~DRIVE_DMA; 4396 } 4397 } else { 4398 /* 4399 * Can't mix both PIO and DMA. Disable 4400 * DMA. 4401 */ 4402 drvp->drive_flags &= ~DRIVE_DMA; 4403 } 4404 } 4405 4406 if (drvp->drive_flags & DRIVE_DMA) { 4407 /* Use multi-word DMA. */ 4408 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4409 PxDx_CMD_ON_SHIFT; 4410 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4411 } else { 4412 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4413 PxDx_CMD_ON_SHIFT; 4414 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4415 } 4416 4417 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4418 4419 /* ...and set the mode for this drive. */ 4420 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4421 } 4422 4423 pciide_print_modes(cp); 4424 } 4425 4426 void 4427 serverworks_chip_map(sc, pa) 4428 struct pciide_softc *sc; 4429 struct pci_attach_args *pa; 4430 { 4431 struct pciide_channel *cp; 4432 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4433 pcitag_t pcib_tag; 4434 int channel; 4435 bus_size_t cmdsize, ctlsize; 4436 4437 if (pciide_chipen(sc, pa) == 0) 4438 return; 4439 4440 printf("%s: bus-master DMA support present", 4441 sc->sc_wdcdev.sc_dev.dv_xname); 4442 pciide_mapreg_dma(sc, pa); 4443 printf("\n"); 4444 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4445 WDC_CAPABILITY_MODE; 4446 4447 if (sc->sc_dma_ok) { 4448 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4449 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4450 sc->sc_wdcdev.irqack = pciide_irqack; 4451 } 4452 sc->sc_wdcdev.PIO_cap = 4; 4453 sc->sc_wdcdev.DMA_cap = 2; 4454 switch (sc->sc_pp->ide_product) { 4455 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4456 sc->sc_wdcdev.UDMA_cap = 2; 4457 break; 4458 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4459 if (PCI_REVISION(pa->pa_class) < 0x92) 4460 sc->sc_wdcdev.UDMA_cap = 4; 4461 else 4462 sc->sc_wdcdev.UDMA_cap = 5; 4463 break; 4464 } 4465 4466 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4467 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4468 sc->sc_wdcdev.nchannels = 2; 4469 4470 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4471 cp = &sc->pciide_channels[channel]; 4472 if (pciide_chansetup(sc, channel, interface) == 0) 4473 continue; 4474 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4475 serverworks_pci_intr); 4476 if (cp->hw_ok == 0) 4477 return; 4478 pciide_map_compat_intr(pa, cp, channel, interface); 4479 if (cp->hw_ok == 0) 4480 return; 4481 serverworks_setup_channel(&cp->wdc_channel); 4482 } 4483 4484 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4485 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4486 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4487 } 4488 4489 void 4490 serverworks_setup_channel(chp) 4491 struct channel_softc *chp; 4492 { 4493 struct ata_drive_datas *drvp; 4494 struct pciide_channel *cp = (struct pciide_channel*)chp; 4495 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4496 int channel = chp->channel; 4497 int drive, unit; 4498 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4499 u_int32_t idedma_ctl; 4500 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4501 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4502 4503 /* setup DMA if needed */ 4504 pciide_channel_dma_setup(cp); 4505 4506 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4507 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4508 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4509 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4510 4511 pio_time &= ~(0xffff << (16 * channel)); 4512 dma_time &= ~(0xffff << (16 * channel)); 4513 pio_mode &= ~(0xff << (8 * channel + 16)); 4514 udma_mode &= ~(0xff << (8 * channel + 16)); 4515 udma_mode &= ~(3 << (2 * channel)); 4516 4517 idedma_ctl = 0; 4518 4519 /* Per drive settings */ 4520 for (drive = 0; drive < 2; drive++) { 4521 drvp = &chp->ch_drive[drive]; 4522 /* If no drive, skip */ 4523 if ((drvp->drive_flags & DRIVE) == 0) 4524 continue; 4525 unit = drive + 2 * channel; 4526 /* add timing values, setup DMA if needed */ 4527 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4528 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4529 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4530 (drvp->drive_flags & DRIVE_UDMA)) { 4531 /* use Ultra/DMA, check for 80-pin cable */ 4532 if (drvp->UDMA_mode > 2 && 4533 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4534 drvp->UDMA_mode = 2; 4535 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4536 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4537 udma_mode |= 1 << unit; 4538 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4539 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4540 (drvp->drive_flags & DRIVE_DMA)) { 4541 /* use Multiword DMA */ 4542 drvp->drive_flags &= ~DRIVE_UDMA; 4543 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4544 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4545 } else { 4546 /* PIO only */ 4547 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4548 } 4549 } 4550 4551 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4552 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4553 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4554 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4555 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4556 4557 if (idedma_ctl != 0) { 4558 /* Add software bits in status register */ 4559 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4560 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4561 } 4562 pciide_print_modes(cp); 4563 } 4564 4565 int 4566 serverworks_pci_intr(arg) 4567 void *arg; 4568 { 4569 struct pciide_softc *sc = arg; 4570 struct pciide_channel *cp; 4571 struct channel_softc *wdc_cp; 4572 int rv = 0; 4573 int dmastat, i, crv; 4574 4575 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4576 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4577 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4578 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4579 IDEDMA_CTL_INTR) 4580 continue; 4581 cp = &sc->pciide_channels[i]; 4582 wdc_cp = &cp->wdc_channel; 4583 crv = wdcintr(wdc_cp); 4584 if (crv == 0) { 4585 printf("%s:%d: bogus intr\n", 4586 sc->sc_wdcdev.sc_dev.dv_xname, i); 4587 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4588 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4589 } else 4590 rv = 1; 4591 } 4592 return rv; 4593 } 4594
Indexes created Thu Oct 02 10:09:58 GMT 2025