pciide.c revision 1.153.2.9
1 /* $NetBSD: pciide.c,v 1.153.2.9 2002/11/01 16:37:42 tron Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.153.2.9 2002/11/01 16:37:42 tron Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 192 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void pdc202xx_setup_channel __P((struct channel_softc*)); 194 void pdc20268_setup_channel __P((struct channel_softc*)); 195 int pdc202xx_pci_intr __P((void *)); 196 int pdc20265_pci_intr __P((void *)); 197 198 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void opti_setup_channel __P((struct channel_softc*)); 200 201 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 202 void hpt_setup_channel __P((struct channel_softc*)); 203 int hpt_pci_intr __P((void *)); 204 205 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void acard_setup_channel __P((struct channel_softc*)); 207 int acard_pci_intr __P((void *)); 208 209 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void serverworks_setup_channel __P((struct channel_softc*)); 211 int serverworks_pci_intr __P((void *)); 212 213 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void sl82c105_setup_channel __P((struct channel_softc*)); 215 216 void pciide_channel_dma_setup __P((struct pciide_channel *)); 217 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 218 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 219 void pciide_dma_start __P((void*, int, int)); 220 int pciide_dma_finish __P((void*, int, int, int)); 221 void pciide_irqack __P((struct channel_softc *)); 222 void pciide_print_modes __P((struct pciide_channel *)); 223 224 struct pciide_product_desc { 225 u_int32_t ide_product; 226 int ide_flags; 227 const char *ide_name; 228 /* map and setup chip, probe drives */ 229 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 230 }; 231 232 /* Flags for ide_flags */ 233 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 234 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 235 236 /* Default product description for devices not known from this controller */ 237 const struct pciide_product_desc default_product_desc = { 238 0, 239 0, 240 "Generic PCI IDE controller", 241 default_chip_map, 242 }; 243 244 const struct pciide_product_desc pciide_intel_products[] = { 245 { PCI_PRODUCT_INTEL_82092AA, 246 0, 247 "Intel 82092AA IDE controller", 248 default_chip_map, 249 }, 250 { PCI_PRODUCT_INTEL_82371FB_IDE, 251 0, 252 "Intel 82371FB IDE controller (PIIX)", 253 piix_chip_map, 254 }, 255 { PCI_PRODUCT_INTEL_82371SB_IDE, 256 0, 257 "Intel 82371SB IDE Interface (PIIX3)", 258 piix_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371AB_IDE, 261 0, 262 "Intel 82371AB IDE controller (PIIX4)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82440MX_IDE, 266 0, 267 "Intel 82440MX IDE controller", 268 piix_chip_map 269 }, 270 { PCI_PRODUCT_INTEL_82801AA_IDE, 271 0, 272 "Intel 82801AA IDE Controller (ICH)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82801AB_IDE, 276 0, 277 "Intel 82801AB IDE Controller (ICH0)", 278 piix_chip_map, 279 }, 280 { PCI_PRODUCT_INTEL_82801BA_IDE, 281 0, 282 "Intel 82801BA IDE Controller (ICH2)", 283 piix_chip_map, 284 }, 285 { PCI_PRODUCT_INTEL_82801BAM_IDE, 286 0, 287 "Intel 82801BAM IDE Controller (ICH2)", 288 piix_chip_map, 289 }, 290 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 291 0, 292 "Intel 82801CA IDE Controller", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 296 0, 297 "Intel 82801CA IDE Controller", 298 piix_chip_map, 299 }, 300 { PCI_PRODUCT_INTEL_82801DB_IDE, 301 0, 302 "Intel 82801DB IDE Controller (ICH4)", 303 piix_chip_map, 304 }, 305 { 0, 306 0, 307 NULL, 308 NULL 309 } 310 }; 311 312 const struct pciide_product_desc pciide_amd_products[] = { 313 { PCI_PRODUCT_AMD_PBC756_IDE, 314 0, 315 "Advanced Micro Devices AMD756 IDE Controller", 316 amd7x6_chip_map 317 }, 318 { PCI_PRODUCT_AMD_PBC766_IDE, 319 0, 320 "Advanced Micro Devices AMD766 IDE Controller", 321 amd7x6_chip_map 322 }, 323 { PCI_PRODUCT_AMD_PBC768_IDE, 324 0, 325 "Advanced Micro Devices AMD768 IDE Controller", 326 amd7x6_chip_map 327 }, 328 { 0, 329 0, 330 NULL, 331 NULL 332 } 333 }; 334 335 const struct pciide_product_desc pciide_cmd_products[] = { 336 { PCI_PRODUCT_CMDTECH_640, 337 0, 338 "CMD Technology PCI0640", 339 cmd_chip_map 340 }, 341 { PCI_PRODUCT_CMDTECH_643, 342 0, 343 "CMD Technology PCI0643", 344 cmd0643_9_chip_map, 345 }, 346 { PCI_PRODUCT_CMDTECH_646, 347 0, 348 "CMD Technology PCI0646", 349 cmd0643_9_chip_map, 350 }, 351 { PCI_PRODUCT_CMDTECH_648, 352 IDE_PCI_CLASS_OVERRIDE, 353 "CMD Technology PCI0648", 354 cmd0643_9_chip_map, 355 }, 356 { PCI_PRODUCT_CMDTECH_649, 357 IDE_PCI_CLASS_OVERRIDE, 358 "CMD Technology PCI0649", 359 cmd0643_9_chip_map, 360 }, 361 { 0, 362 0, 363 NULL, 364 NULL 365 } 366 }; 367 368 const struct pciide_product_desc pciide_via_products[] = { 369 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 370 0, 371 NULL, 372 apollo_chip_map, 373 }, 374 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 375 0, 376 NULL, 377 apollo_chip_map, 378 }, 379 { 0, 380 0, 381 NULL, 382 NULL 383 } 384 }; 385 386 const struct pciide_product_desc pciide_cypress_products[] = { 387 { PCI_PRODUCT_CONTAQ_82C693, 388 IDE_16BIT_IOSPACE, 389 "Cypress 82C693 IDE Controller", 390 cy693_chip_map, 391 }, 392 { 0, 393 0, 394 NULL, 395 NULL 396 } 397 }; 398 399 const struct pciide_product_desc pciide_sis_products[] = { 400 { PCI_PRODUCT_SIS_5597_IDE, 401 0, 402 "Silicon Integrated System 5597/5598 IDE controller", 403 sis_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 NULL 409 } 410 }; 411 412 const struct pciide_product_desc pciide_acer_products[] = { 413 { PCI_PRODUCT_ALI_M5229, 414 0, 415 "Acer Labs M5229 UDMA IDE Controller", 416 acer_chip_map, 417 }, 418 { 0, 419 0, 420 NULL, 421 NULL 422 } 423 }; 424 425 const struct pciide_product_desc pciide_promise_products[] = { 426 { PCI_PRODUCT_PROMISE_ULTRA33, 427 IDE_PCI_CLASS_OVERRIDE, 428 "Promise Ultra33/ATA Bus Master IDE Accelerator", 429 pdc202xx_chip_map, 430 }, 431 { PCI_PRODUCT_PROMISE_ULTRA66, 432 IDE_PCI_CLASS_OVERRIDE, 433 "Promise Ultra66/ATA Bus Master IDE Accelerator", 434 pdc202xx_chip_map, 435 }, 436 { PCI_PRODUCT_PROMISE_ULTRA100, 437 IDE_PCI_CLASS_OVERRIDE, 438 "Promise Ultra100/ATA Bus Master IDE Accelerator", 439 pdc202xx_chip_map, 440 }, 441 { PCI_PRODUCT_PROMISE_ULTRA100X, 442 IDE_PCI_CLASS_OVERRIDE, 443 "Promise Ultra100/ATA Bus Master IDE Accelerator", 444 pdc202xx_chip_map, 445 }, 446 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 447 IDE_PCI_CLASS_OVERRIDE, 448 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 449 pdc202xx_chip_map, 450 }, 451 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 452 IDE_PCI_CLASS_OVERRIDE, 453 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 454 pdc202xx_chip_map, 455 }, 456 { PCI_PRODUCT_PROMISE_ULTRA133, 457 IDE_PCI_CLASS_OVERRIDE, 458 "Promise Ultra133/ATA Bus Master IDE Accelerator", 459 pdc202xx_chip_map, 460 }, 461 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 462 IDE_PCI_CLASS_OVERRIDE, 463 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 464 pdc202xx_chip_map, 465 }, 466 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 467 IDE_PCI_CLASS_OVERRIDE, 468 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 469 pdc202xx_chip_map, 470 }, 471 { 0, 472 0, 473 NULL, 474 NULL 475 } 476 }; 477 478 const struct pciide_product_desc pciide_opti_products[] = { 479 { PCI_PRODUCT_OPTI_82C621, 480 0, 481 "OPTi 82c621 PCI IDE controller", 482 opti_chip_map, 483 }, 484 { PCI_PRODUCT_OPTI_82C568, 485 0, 486 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 487 opti_chip_map, 488 }, 489 { PCI_PRODUCT_OPTI_82D568, 490 0, 491 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 492 opti_chip_map, 493 }, 494 { 0, 495 0, 496 NULL, 497 NULL 498 } 499 }; 500 501 const struct pciide_product_desc pciide_triones_products[] = { 502 { PCI_PRODUCT_TRIONES_HPT366, 503 IDE_PCI_CLASS_OVERRIDE, 504 NULL, 505 hpt_chip_map, 506 }, 507 { PCI_PRODUCT_TRIONES_HPT372, 508 IDE_PCI_CLASS_OVERRIDE, 509 NULL, 510 hpt_chip_map 511 }, 512 { PCI_PRODUCT_TRIONES_HPT374, 513 IDE_PCI_CLASS_OVERRIDE, 514 NULL, 515 hpt_chip_map 516 }, 517 { 0, 518 0, 519 NULL, 520 NULL 521 } 522 }; 523 524 const struct pciide_product_desc pciide_acard_products[] = { 525 { PCI_PRODUCT_ACARD_ATP850U, 526 IDE_PCI_CLASS_OVERRIDE, 527 "Acard ATP850U Ultra33 IDE Controller", 528 acard_chip_map, 529 }, 530 { PCI_PRODUCT_ACARD_ATP860, 531 IDE_PCI_CLASS_OVERRIDE, 532 "Acard ATP860 Ultra66 IDE Controller", 533 acard_chip_map, 534 }, 535 { PCI_PRODUCT_ACARD_ATP860A, 536 IDE_PCI_CLASS_OVERRIDE, 537 "Acard ATP860-A Ultra66 IDE Controller", 538 acard_chip_map, 539 }, 540 { 0, 541 0, 542 NULL, 543 NULL 544 } 545 }; 546 547 const struct pciide_product_desc pciide_serverworks_products[] = { 548 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 549 0, 550 "ServerWorks OSB4 IDE Controller", 551 serverworks_chip_map, 552 }, 553 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 554 0, 555 "ServerWorks CSB5 IDE Controller", 556 serverworks_chip_map, 557 }, 558 { 0, 559 0, 560 NULL, 561 } 562 }; 563 564 const struct pciide_product_desc pciide_symphony_products[] = { 565 { PCI_PRODUCT_SYMPHONY_82C105, 566 0, 567 "Symphony Labs 82C105 IDE controller", 568 sl82c105_chip_map, 569 }, 570 { 0, 571 0, 572 NULL, 573 } 574 }; 575 576 const struct pciide_product_desc pciide_winbond_products[] = { 577 { PCI_PRODUCT_WINBOND_W83C553F_1, 578 0, 579 "Winbond W83C553F IDE controller", 580 sl82c105_chip_map, 581 }, 582 { 0, 583 0, 584 NULL, 585 } 586 }; 587 588 struct pciide_vendor_desc { 589 u_int32_t ide_vendor; 590 const struct pciide_product_desc *ide_products; 591 }; 592 593 const struct pciide_vendor_desc pciide_vendors[] = { 594 { PCI_VENDOR_INTEL, pciide_intel_products }, 595 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 596 { PCI_VENDOR_VIATECH, pciide_via_products }, 597 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 598 { PCI_VENDOR_SIS, pciide_sis_products }, 599 { PCI_VENDOR_ALI, pciide_acer_products }, 600 { PCI_VENDOR_PROMISE, pciide_promise_products }, 601 { PCI_VENDOR_AMD, pciide_amd_products }, 602 { PCI_VENDOR_OPTI, pciide_opti_products }, 603 { PCI_VENDOR_TRIONES, pciide_triones_products }, 604 { PCI_VENDOR_ACARD, pciide_acard_products }, 605 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 606 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 607 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 608 { 0, NULL } 609 }; 610 611 /* options passed via the 'flags' config keyword */ 612 #define PCIIDE_OPTIONS_DMA 0x01 613 #define PCIIDE_OPTIONS_NODMA 0x02 614 615 int pciide_match __P((struct device *, struct cfdata *, void *)); 616 void pciide_attach __P((struct device *, struct device *, void *)); 617 618 struct cfattach pciide_ca = { 619 sizeof(struct pciide_softc), pciide_match, pciide_attach 620 }; 621 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 622 int pciide_mapregs_compat __P(( struct pci_attach_args *, 623 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 624 int pciide_mapregs_native __P((struct pci_attach_args *, 625 struct pciide_channel *, bus_size_t *, bus_size_t *, 626 int (*pci_intr) __P((void *)))); 627 void pciide_mapreg_dma __P((struct pciide_softc *, 628 struct pci_attach_args *)); 629 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 630 void pciide_mapchan __P((struct pci_attach_args *, 631 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 632 int (*pci_intr) __P((void *)))); 633 int pciide_chan_candisable __P((struct pciide_channel *)); 634 void pciide_map_compat_intr __P(( struct pci_attach_args *, 635 struct pciide_channel *, int, int)); 636 int pciide_compat_intr __P((void *)); 637 int pciide_pci_intr __P((void *)); 638 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 639 640 const struct pciide_product_desc * 641 pciide_lookup_product(id) 642 u_int32_t id; 643 { 644 const struct pciide_product_desc *pp; 645 const struct pciide_vendor_desc *vp; 646 647 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 648 if (PCI_VENDOR(id) == vp->ide_vendor) 649 break; 650 651 if ((pp = vp->ide_products) == NULL) 652 return NULL; 653 654 for (; pp->chip_map != NULL; pp++) 655 if (PCI_PRODUCT(id) == pp->ide_product) 656 break; 657 658 if (pp->chip_map == NULL) 659 return NULL; 660 return pp; 661 } 662 663 int 664 pciide_match(parent, match, aux) 665 struct device *parent; 666 struct cfdata *match; 667 void *aux; 668 { 669 struct pci_attach_args *pa = aux; 670 const struct pciide_product_desc *pp; 671 672 /* 673 * Check the ID register to see that it's a PCI IDE controller. 674 * If it is, we assume that we can deal with it; it _should_ 675 * work in a standardized way... 676 */ 677 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 678 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 679 return (1); 680 } 681 682 /* 683 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 684 * controllers. Let see if we can deal with it anyway. 685 */ 686 pp = pciide_lookup_product(pa->pa_id); 687 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 688 return (1); 689 } 690 691 return (0); 692 } 693 694 void 695 pciide_attach(parent, self, aux) 696 struct device *parent, *self; 697 void *aux; 698 { 699 struct pci_attach_args *pa = aux; 700 pci_chipset_tag_t pc = pa->pa_pc; 701 pcitag_t tag = pa->pa_tag; 702 struct pciide_softc *sc = (struct pciide_softc *)self; 703 pcireg_t csr; 704 char devinfo[256]; 705 const char *displaydev; 706 707 sc->sc_pp = pciide_lookup_product(pa->pa_id); 708 if (sc->sc_pp == NULL) { 709 sc->sc_pp = &default_product_desc; 710 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 711 displaydev = devinfo; 712 } else 713 displaydev = sc->sc_pp->ide_name; 714 715 /* if displaydev == NULL, printf is done in chip-specific map */ 716 if (displaydev) 717 printf(": %s (rev. 0x%02x)\n", displaydev, 718 PCI_REVISION(pa->pa_class)); 719 720 sc->sc_pc = pa->pa_pc; 721 sc->sc_tag = pa->pa_tag; 722 #ifdef WDCDEBUG 723 if (wdcdebug_pciide_mask & DEBUG_PROBE) 724 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 725 #endif 726 sc->sc_pp->chip_map(sc, pa); 727 728 if (sc->sc_dma_ok) { 729 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 730 csr |= PCI_COMMAND_MASTER_ENABLE; 731 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 732 } 733 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 734 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 735 } 736 737 /* tell wether the chip is enabled or not */ 738 int 739 pciide_chipen(sc, pa) 740 struct pciide_softc *sc; 741 struct pci_attach_args *pa; 742 { 743 pcireg_t csr; 744 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 745 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 746 PCI_COMMAND_STATUS_REG); 747 printf("%s: device disabled (at %s)\n", 748 sc->sc_wdcdev.sc_dev.dv_xname, 749 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 750 "device" : "bridge"); 751 return 0; 752 } 753 return 1; 754 } 755 756 int 757 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 758 struct pci_attach_args *pa; 759 struct pciide_channel *cp; 760 int compatchan; 761 bus_size_t *cmdsizep, *ctlsizep; 762 { 763 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 764 struct channel_softc *wdc_cp = &cp->wdc_channel; 765 766 cp->compat = 1; 767 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 768 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 769 770 wdc_cp->cmd_iot = pa->pa_iot; 771 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 772 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 773 printf("%s: couldn't map %s channel cmd regs\n", 774 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 775 return (0); 776 } 777 778 wdc_cp->ctl_iot = pa->pa_iot; 779 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 780 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 781 printf("%s: couldn't map %s channel ctl regs\n", 782 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 783 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 784 PCIIDE_COMPAT_CMD_SIZE); 785 return (0); 786 } 787 788 return (1); 789 } 790 791 int 792 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 793 struct pci_attach_args * pa; 794 struct pciide_channel *cp; 795 bus_size_t *cmdsizep, *ctlsizep; 796 int (*pci_intr) __P((void *)); 797 { 798 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 799 struct channel_softc *wdc_cp = &cp->wdc_channel; 800 const char *intrstr; 801 pci_intr_handle_t intrhandle; 802 803 cp->compat = 0; 804 805 if (sc->sc_pci_ih == NULL) { 806 if (pci_intr_map(pa, &intrhandle) != 0) { 807 printf("%s: couldn't map native-PCI interrupt\n", 808 sc->sc_wdcdev.sc_dev.dv_xname); 809 return 0; 810 } 811 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 812 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 813 intrhandle, IPL_BIO, pci_intr, sc); 814 if (sc->sc_pci_ih != NULL) { 815 printf("%s: using %s for native-PCI interrupt\n", 816 sc->sc_wdcdev.sc_dev.dv_xname, 817 intrstr ? intrstr : "unknown interrupt"); 818 } else { 819 printf("%s: couldn't establish native-PCI interrupt", 820 sc->sc_wdcdev.sc_dev.dv_xname); 821 if (intrstr != NULL) 822 printf(" at %s", intrstr); 823 printf("\n"); 824 return 0; 825 } 826 } 827 cp->ih = sc->sc_pci_ih; 828 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 829 PCI_MAPREG_TYPE_IO, 0, 830 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 831 printf("%s: couldn't map %s channel cmd regs\n", 832 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 833 return 0; 834 } 835 836 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 837 PCI_MAPREG_TYPE_IO, 0, 838 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 839 printf("%s: couldn't map %s channel ctl regs\n", 840 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 841 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 842 return 0; 843 } 844 /* 845 * In native mode, 4 bytes of I/O space are mapped for the control 846 * register, the control register is at offset 2. Pass the generic 847 * code a handle for only one byte at the rigth offset. 848 */ 849 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 850 &wdc_cp->ctl_ioh) != 0) { 851 printf("%s: unable to subregion %s channel ctl regs\n", 852 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 853 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 854 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 855 return 0; 856 } 857 return (1); 858 } 859 860 void 861 pciide_mapreg_dma(sc, pa) 862 struct pciide_softc *sc; 863 struct pci_attach_args *pa; 864 { 865 pcireg_t maptype; 866 bus_addr_t addr; 867 868 /* 869 * Map DMA registers 870 * 871 * Note that sc_dma_ok is the right variable to test to see if 872 * DMA can be done. If the interface doesn't support DMA, 873 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 874 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 875 * non-zero if the interface supports DMA and the registers 876 * could be mapped. 877 * 878 * XXX Note that despite the fact that the Bus Master IDE specs 879 * XXX say that "The bus master IDE function uses 16 bytes of IO 880 * XXX space," some controllers (at least the United 881 * XXX Microelectronics UM8886BF) place it in memory space. 882 */ 883 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 884 PCIIDE_REG_BUS_MASTER_DMA); 885 886 switch (maptype) { 887 case PCI_MAPREG_TYPE_IO: 888 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 889 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 890 &addr, NULL, NULL) == 0); 891 if (sc->sc_dma_ok == 0) { 892 printf(", but unused (couldn't query registers)"); 893 break; 894 } 895 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 896 && addr >= 0x10000) { 897 sc->sc_dma_ok = 0; 898 printf(", but unused (registers at unsafe address " 899 "%#lx)", (unsigned long)addr); 900 break; 901 } 902 /* FALLTHROUGH */ 903 904 case PCI_MAPREG_MEM_TYPE_32BIT: 905 sc->sc_dma_ok = (pci_mapreg_map(pa, 906 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 907 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 908 sc->sc_dmat = pa->pa_dmat; 909 if (sc->sc_dma_ok == 0) { 910 printf(", but unused (couldn't map registers)"); 911 } else { 912 sc->sc_wdcdev.dma_arg = sc; 913 sc->sc_wdcdev.dma_init = pciide_dma_init; 914 sc->sc_wdcdev.dma_start = pciide_dma_start; 915 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 916 } 917 918 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 919 PCIIDE_OPTIONS_NODMA) { 920 printf(", but unused (forced off by config file)"); 921 sc->sc_dma_ok = 0; 922 } 923 break; 924 925 default: 926 sc->sc_dma_ok = 0; 927 printf(", but unsupported register maptype (0x%x)", maptype); 928 } 929 } 930 931 int 932 pciide_compat_intr(arg) 933 void *arg; 934 { 935 struct pciide_channel *cp = arg; 936 937 #ifdef DIAGNOSTIC 938 /* should only be called for a compat channel */ 939 if (cp->compat == 0) 940 panic("pciide compat intr called for non-compat chan %p\n", cp); 941 #endif 942 return (wdcintr(&cp->wdc_channel)); 943 } 944 945 int 946 pciide_pci_intr(arg) 947 void *arg; 948 { 949 struct pciide_softc *sc = arg; 950 struct pciide_channel *cp; 951 struct channel_softc *wdc_cp; 952 int i, rv, crv; 953 954 rv = 0; 955 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 956 cp = &sc->pciide_channels[i]; 957 wdc_cp = &cp->wdc_channel; 958 959 /* If a compat channel skip. */ 960 if (cp->compat) 961 continue; 962 /* if this channel not waiting for intr, skip */ 963 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 964 continue; 965 966 crv = wdcintr(wdc_cp); 967 if (crv == 0) 968 ; /* leave rv alone */ 969 else if (crv == 1) 970 rv = 1; /* claim the intr */ 971 else if (rv == 0) /* crv should be -1 in this case */ 972 rv = crv; /* if we've done no better, take it */ 973 } 974 return (rv); 975 } 976 977 void 978 pciide_channel_dma_setup(cp) 979 struct pciide_channel *cp; 980 { 981 int drive; 982 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 983 struct ata_drive_datas *drvp; 984 985 for (drive = 0; drive < 2; drive++) { 986 drvp = &cp->wdc_channel.ch_drive[drive]; 987 /* If no drive, skip */ 988 if ((drvp->drive_flags & DRIVE) == 0) 989 continue; 990 /* setup DMA if needed */ 991 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 992 (drvp->drive_flags & DRIVE_UDMA) == 0) || 993 sc->sc_dma_ok == 0) { 994 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 995 continue; 996 } 997 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 998 != 0) { 999 /* Abort DMA setup */ 1000 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1001 continue; 1002 } 1003 } 1004 } 1005 1006 int 1007 pciide_dma_table_setup(sc, channel, drive) 1008 struct pciide_softc *sc; 1009 int channel, drive; 1010 { 1011 bus_dma_segment_t seg; 1012 int error, rseg; 1013 const bus_size_t dma_table_size = 1014 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1015 struct pciide_dma_maps *dma_maps = 1016 &sc->pciide_channels[channel].dma_maps[drive]; 1017 1018 /* If table was already allocated, just return */ 1019 if (dma_maps->dma_table) 1020 return 0; 1021 1022 /* Allocate memory for the DMA tables and map it */ 1023 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1024 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1025 BUS_DMA_NOWAIT)) != 0) { 1026 printf("%s:%d: unable to allocate table DMA for " 1027 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1028 channel, drive, error); 1029 return error; 1030 } 1031 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1032 dma_table_size, 1033 (caddr_t *)&dma_maps->dma_table, 1034 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1035 printf("%s:%d: unable to map table DMA for" 1036 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1037 channel, drive, error); 1038 return error; 1039 } 1040 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1041 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1042 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1043 1044 /* Create and load table DMA map for this disk */ 1045 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1046 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1047 &dma_maps->dmamap_table)) != 0) { 1048 printf("%s:%d: unable to create table DMA map for " 1049 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1050 channel, drive, error); 1051 return error; 1052 } 1053 if ((error = bus_dmamap_load(sc->sc_dmat, 1054 dma_maps->dmamap_table, 1055 dma_maps->dma_table, 1056 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1057 printf("%s:%d: unable to load table DMA map for " 1058 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1059 channel, drive, error); 1060 return error; 1061 } 1062 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1063 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1064 DEBUG_PROBE); 1065 /* Create a xfer DMA map for this drive */ 1066 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1067 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1068 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1069 &dma_maps->dmamap_xfer)) != 0) { 1070 printf("%s:%d: unable to create xfer DMA map for " 1071 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1072 channel, drive, error); 1073 return error; 1074 } 1075 return 0; 1076 } 1077 1078 int 1079 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1080 void *v; 1081 int channel, drive; 1082 void *databuf; 1083 size_t datalen; 1084 int flags; 1085 { 1086 struct pciide_softc *sc = v; 1087 int error, seg; 1088 struct pciide_dma_maps *dma_maps = 1089 &sc->pciide_channels[channel].dma_maps[drive]; 1090 1091 error = bus_dmamap_load(sc->sc_dmat, 1092 dma_maps->dmamap_xfer, 1093 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1094 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1095 if (error) { 1096 printf("%s:%d: unable to load xfer DMA map for" 1097 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1098 channel, drive, error); 1099 return error; 1100 } 1101 1102 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1103 dma_maps->dmamap_xfer->dm_mapsize, 1104 (flags & WDC_DMA_READ) ? 1105 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1106 1107 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1108 #ifdef DIAGNOSTIC 1109 /* A segment must not cross a 64k boundary */ 1110 { 1111 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1112 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1113 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1114 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1115 printf("pciide_dma: segment %d physical addr 0x%lx" 1116 " len 0x%lx not properly aligned\n", 1117 seg, phys, len); 1118 panic("pciide_dma: buf align"); 1119 } 1120 } 1121 #endif 1122 dma_maps->dma_table[seg].base_addr = 1123 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1124 dma_maps->dma_table[seg].byte_count = 1125 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1126 IDEDMA_BYTE_COUNT_MASK); 1127 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1128 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1129 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1130 1131 } 1132 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1133 htole32(IDEDMA_BYTE_COUNT_EOT); 1134 1135 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1136 dma_maps->dmamap_table->dm_mapsize, 1137 BUS_DMASYNC_PREWRITE); 1138 1139 /* Maps are ready. Start DMA function */ 1140 #ifdef DIAGNOSTIC 1141 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1142 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1143 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1144 panic("pciide_dma_init: table align"); 1145 } 1146 #endif 1147 1148 /* Clear status bits */ 1149 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1150 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1151 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1152 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1153 /* Write table addr */ 1154 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1155 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1156 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1157 /* set read/write */ 1158 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1159 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1160 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1161 /* remember flags */ 1162 dma_maps->dma_flags = flags; 1163 return 0; 1164 } 1165 1166 void 1167 pciide_dma_start(v, channel, drive) 1168 void *v; 1169 int channel, drive; 1170 { 1171 struct pciide_softc *sc = v; 1172 1173 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1174 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1175 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1176 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1177 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1178 } 1179 1180 int 1181 pciide_dma_finish(v, channel, drive, force) 1182 void *v; 1183 int channel, drive; 1184 int force; 1185 { 1186 struct pciide_softc *sc = v; 1187 u_int8_t status; 1188 int error = 0; 1189 struct pciide_dma_maps *dma_maps = 1190 &sc->pciide_channels[channel].dma_maps[drive]; 1191 1192 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1193 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1194 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1195 DEBUG_XFERS); 1196 1197 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1198 return WDC_DMAST_NOIRQ; 1199 1200 /* stop DMA channel */ 1201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1202 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1203 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1204 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1205 1206 /* Unload the map of the data buffer */ 1207 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1208 dma_maps->dmamap_xfer->dm_mapsize, 1209 (dma_maps->dma_flags & WDC_DMA_READ) ? 1210 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1211 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1212 1213 if ((status & IDEDMA_CTL_ERR) != 0) { 1214 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1215 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1216 error |= WDC_DMAST_ERR; 1217 } 1218 1219 if ((status & IDEDMA_CTL_INTR) == 0) { 1220 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1221 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1222 drive, status); 1223 error |= WDC_DMAST_NOIRQ; 1224 } 1225 1226 if ((status & IDEDMA_CTL_ACT) != 0) { 1227 /* data underrun, may be a valid condition for ATAPI */ 1228 error |= WDC_DMAST_UNDER; 1229 } 1230 return error; 1231 } 1232 1233 void 1234 pciide_irqack(chp) 1235 struct channel_softc *chp; 1236 { 1237 struct pciide_channel *cp = (struct pciide_channel*)chp; 1238 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1239 1240 /* clear status bits in IDE DMA registers */ 1241 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1242 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1243 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1244 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1245 } 1246 1247 /* some common code used by several chip_map */ 1248 int 1249 pciide_chansetup(sc, channel, interface) 1250 struct pciide_softc *sc; 1251 int channel; 1252 pcireg_t interface; 1253 { 1254 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1255 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1256 cp->name = PCIIDE_CHANNEL_NAME(channel); 1257 cp->wdc_channel.channel = channel; 1258 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1259 cp->wdc_channel.ch_queue = 1260 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1261 if (cp->wdc_channel.ch_queue == NULL) { 1262 printf("%s %s channel: " 1263 "can't allocate memory for command queue", 1264 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1265 return 0; 1266 } 1267 printf("%s: %s channel %s to %s mode\n", 1268 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1269 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1270 "configured" : "wired", 1271 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1272 "native-PCI" : "compatibility"); 1273 return 1; 1274 } 1275 1276 /* some common code used by several chip channel_map */ 1277 void 1278 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1279 struct pci_attach_args *pa; 1280 struct pciide_channel *cp; 1281 pcireg_t interface; 1282 bus_size_t *cmdsizep, *ctlsizep; 1283 int (*pci_intr) __P((void *)); 1284 { 1285 struct channel_softc *wdc_cp = &cp->wdc_channel; 1286 1287 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1288 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1289 pci_intr); 1290 else 1291 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1292 wdc_cp->channel, cmdsizep, ctlsizep); 1293 1294 if (cp->hw_ok == 0) 1295 return; 1296 wdc_cp->data32iot = wdc_cp->cmd_iot; 1297 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1298 wdcattach(wdc_cp); 1299 } 1300 1301 /* 1302 * Generic code to call to know if a channel can be disabled. Return 1 1303 * if channel can be disabled, 0 if not 1304 */ 1305 int 1306 pciide_chan_candisable(cp) 1307 struct pciide_channel *cp; 1308 { 1309 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1310 struct channel_softc *wdc_cp = &cp->wdc_channel; 1311 1312 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1313 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1314 printf("%s: disabling %s channel (no drives)\n", 1315 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1316 cp->hw_ok = 0; 1317 return 1; 1318 } 1319 return 0; 1320 } 1321 1322 /* 1323 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1324 * Set hw_ok=0 on failure 1325 */ 1326 void 1327 pciide_map_compat_intr(pa, cp, compatchan, interface) 1328 struct pci_attach_args *pa; 1329 struct pciide_channel *cp; 1330 int compatchan, interface; 1331 { 1332 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1333 struct channel_softc *wdc_cp = &cp->wdc_channel; 1334 1335 if (cp->hw_ok == 0) 1336 return; 1337 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1338 return; 1339 1340 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1341 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1342 pa, compatchan, pciide_compat_intr, cp); 1343 if (cp->ih == NULL) { 1344 #endif 1345 printf("%s: no compatibility interrupt for use by %s " 1346 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1347 cp->hw_ok = 0; 1348 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1349 } 1350 #endif 1351 } 1352 1353 void 1354 pciide_print_modes(cp) 1355 struct pciide_channel *cp; 1356 { 1357 wdc_print_modes(&cp->wdc_channel); 1358 } 1359 1360 void 1361 default_chip_map(sc, pa) 1362 struct pciide_softc *sc; 1363 struct pci_attach_args *pa; 1364 { 1365 struct pciide_channel *cp; 1366 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1367 pcireg_t csr; 1368 int channel, drive; 1369 struct ata_drive_datas *drvp; 1370 u_int8_t idedma_ctl; 1371 bus_size_t cmdsize, ctlsize; 1372 char *failreason; 1373 1374 if (pciide_chipen(sc, pa) == 0) 1375 return; 1376 1377 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1378 printf("%s: bus-master DMA support present", 1379 sc->sc_wdcdev.sc_dev.dv_xname); 1380 if (sc->sc_pp == &default_product_desc && 1381 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1382 PCIIDE_OPTIONS_DMA) == 0) { 1383 printf(", but unused (no driver support)"); 1384 sc->sc_dma_ok = 0; 1385 } else { 1386 pciide_mapreg_dma(sc, pa); 1387 if (sc->sc_dma_ok != 0) 1388 printf(", used without full driver " 1389 "support"); 1390 } 1391 } else { 1392 printf("%s: hardware does not support DMA", 1393 sc->sc_wdcdev.sc_dev.dv_xname); 1394 sc->sc_dma_ok = 0; 1395 } 1396 printf("\n"); 1397 if (sc->sc_dma_ok) { 1398 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1399 sc->sc_wdcdev.irqack = pciide_irqack; 1400 } 1401 sc->sc_wdcdev.PIO_cap = 0; 1402 sc->sc_wdcdev.DMA_cap = 0; 1403 1404 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1405 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1406 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1407 1408 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1409 cp = &sc->pciide_channels[channel]; 1410 if (pciide_chansetup(sc, channel, interface) == 0) 1411 continue; 1412 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1413 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1414 &ctlsize, pciide_pci_intr); 1415 } else { 1416 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1417 channel, &cmdsize, &ctlsize); 1418 } 1419 if (cp->hw_ok == 0) 1420 continue; 1421 /* 1422 * Check to see if something appears to be there. 1423 */ 1424 failreason = NULL; 1425 if (!wdcprobe(&cp->wdc_channel)) { 1426 failreason = "not responding; disabled or no drives?"; 1427 goto next; 1428 } 1429 /* 1430 * Now, make sure it's actually attributable to this PCI IDE 1431 * channel by trying to access the channel again while the 1432 * PCI IDE controller's I/O space is disabled. (If the 1433 * channel no longer appears to be there, it belongs to 1434 * this controller.) YUCK! 1435 */ 1436 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1437 PCI_COMMAND_STATUS_REG); 1438 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1439 csr & ~PCI_COMMAND_IO_ENABLE); 1440 if (wdcprobe(&cp->wdc_channel)) 1441 failreason = "other hardware responding at addresses"; 1442 pci_conf_write(sc->sc_pc, sc->sc_tag, 1443 PCI_COMMAND_STATUS_REG, csr); 1444 next: 1445 if (failreason) { 1446 printf("%s: %s channel ignored (%s)\n", 1447 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1448 failreason); 1449 cp->hw_ok = 0; 1450 bus_space_unmap(cp->wdc_channel.cmd_iot, 1451 cp->wdc_channel.cmd_ioh, cmdsize); 1452 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1453 bus_space_unmap(cp->wdc_channel.ctl_iot, 1454 cp->ctl_baseioh, ctlsize); 1455 else 1456 bus_space_unmap(cp->wdc_channel.ctl_iot, 1457 cp->wdc_channel.ctl_ioh, ctlsize); 1458 } else { 1459 pciide_map_compat_intr(pa, cp, channel, interface); 1460 } 1461 if (cp->hw_ok) { 1462 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1463 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1464 wdcattach(&cp->wdc_channel); 1465 } 1466 } 1467 1468 if (sc->sc_dma_ok == 0) 1469 return; 1470 1471 /* Allocate DMA maps */ 1472 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1473 idedma_ctl = 0; 1474 cp = &sc->pciide_channels[channel]; 1475 for (drive = 0; drive < 2; drive++) { 1476 drvp = &cp->wdc_channel.ch_drive[drive]; 1477 /* If no drive, skip */ 1478 if ((drvp->drive_flags & DRIVE) == 0) 1479 continue; 1480 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1481 continue; 1482 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1483 /* Abort DMA setup */ 1484 printf("%s:%d:%d: can't allocate DMA maps, " 1485 "using PIO transfers\n", 1486 sc->sc_wdcdev.sc_dev.dv_xname, 1487 channel, drive); 1488 drvp->drive_flags &= ~DRIVE_DMA; 1489 } 1490 printf("%s:%d:%d: using DMA data transfers\n", 1491 sc->sc_wdcdev.sc_dev.dv_xname, 1492 channel, drive); 1493 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1494 } 1495 if (idedma_ctl != 0) { 1496 /* Add software bits in status register */ 1497 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1498 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1499 idedma_ctl); 1500 } 1501 } 1502 } 1503 1504 void 1505 piix_chip_map(sc, pa) 1506 struct pciide_softc *sc; 1507 struct pci_attach_args *pa; 1508 { 1509 struct pciide_channel *cp; 1510 int channel; 1511 u_int32_t idetim; 1512 bus_size_t cmdsize, ctlsize; 1513 1514 if (pciide_chipen(sc, pa) == 0) 1515 return; 1516 1517 printf("%s: bus-master DMA support present", 1518 sc->sc_wdcdev.sc_dev.dv_xname); 1519 pciide_mapreg_dma(sc, pa); 1520 printf("\n"); 1521 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1522 WDC_CAPABILITY_MODE; 1523 if (sc->sc_dma_ok) { 1524 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1525 sc->sc_wdcdev.irqack = pciide_irqack; 1526 switch(sc->sc_pp->ide_product) { 1527 case PCI_PRODUCT_INTEL_82371AB_IDE: 1528 case PCI_PRODUCT_INTEL_82440MX_IDE: 1529 case PCI_PRODUCT_INTEL_82801AA_IDE: 1530 case PCI_PRODUCT_INTEL_82801AB_IDE: 1531 case PCI_PRODUCT_INTEL_82801BA_IDE: 1532 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1533 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1534 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1535 case PCI_PRODUCT_INTEL_82801DB_IDE: 1536 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1537 } 1538 } 1539 sc->sc_wdcdev.PIO_cap = 4; 1540 sc->sc_wdcdev.DMA_cap = 2; 1541 switch(sc->sc_pp->ide_product) { 1542 case PCI_PRODUCT_INTEL_82801AA_IDE: 1543 sc->sc_wdcdev.UDMA_cap = 4; 1544 break; 1545 case PCI_PRODUCT_INTEL_82801BA_IDE: 1546 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1547 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1548 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1549 case PCI_PRODUCT_INTEL_82801DB_IDE: 1550 sc->sc_wdcdev.UDMA_cap = 5; 1551 break; 1552 default: 1553 sc->sc_wdcdev.UDMA_cap = 2; 1554 } 1555 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1556 sc->sc_wdcdev.set_modes = piix_setup_channel; 1557 else 1558 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1559 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1560 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1561 1562 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1563 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1564 DEBUG_PROBE); 1565 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1566 WDCDEBUG_PRINT((", sidetim=0x%x", 1567 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1568 DEBUG_PROBE); 1569 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1570 WDCDEBUG_PRINT((", udamreg 0x%x", 1571 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1572 DEBUG_PROBE); 1573 } 1574 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1580 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1581 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1582 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1583 DEBUG_PROBE); 1584 } 1585 1586 } 1587 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1588 1589 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1590 cp = &sc->pciide_channels[channel]; 1591 /* PIIX is compat-only */ 1592 if (pciide_chansetup(sc, channel, 0) == 0) 1593 continue; 1594 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1595 if ((PIIX_IDETIM_READ(idetim, channel) & 1596 PIIX_IDETIM_IDE) == 0) { 1597 printf("%s: %s channel ignored (disabled)\n", 1598 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1599 continue; 1600 } 1601 /* PIIX are compat-only pciide devices */ 1602 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1603 if (cp->hw_ok == 0) 1604 continue; 1605 if (pciide_chan_candisable(cp)) { 1606 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1607 channel); 1608 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1609 idetim); 1610 } 1611 pciide_map_compat_intr(pa, cp, channel, 0); 1612 if (cp->hw_ok == 0) 1613 continue; 1614 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1615 } 1616 1617 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1618 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1619 DEBUG_PROBE); 1620 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1621 WDCDEBUG_PRINT((", sidetim=0x%x", 1622 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1623 DEBUG_PROBE); 1624 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1625 WDCDEBUG_PRINT((", udamreg 0x%x", 1626 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1627 DEBUG_PROBE); 1628 } 1629 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1636 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1637 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1638 DEBUG_PROBE); 1639 } 1640 } 1641 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1642 } 1643 1644 void 1645 piix_setup_channel(chp) 1646 struct channel_softc *chp; 1647 { 1648 u_int8_t mode[2], drive; 1649 u_int32_t oidetim, idetim, idedma_ctl; 1650 struct pciide_channel *cp = (struct pciide_channel*)chp; 1651 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1652 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1653 1654 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1655 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1656 idedma_ctl = 0; 1657 1658 /* set up new idetim: Enable IDE registers decode */ 1659 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1660 chp->channel); 1661 1662 /* setup DMA */ 1663 pciide_channel_dma_setup(cp); 1664 1665 /* 1666 * Here we have to mess up with drives mode: PIIX can't have 1667 * different timings for master and slave drives. 1668 * We need to find the best combination. 1669 */ 1670 1671 /* If both drives supports DMA, take the lower mode */ 1672 if ((drvp[0].drive_flags & DRIVE_DMA) && 1673 (drvp[1].drive_flags & DRIVE_DMA)) { 1674 mode[0] = mode[1] = 1675 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1676 drvp[0].DMA_mode = mode[0]; 1677 drvp[1].DMA_mode = mode[1]; 1678 goto ok; 1679 } 1680 /* 1681 * If only one drive supports DMA, use its mode, and 1682 * put the other one in PIO mode 0 if mode not compatible 1683 */ 1684 if (drvp[0].drive_flags & DRIVE_DMA) { 1685 mode[0] = drvp[0].DMA_mode; 1686 mode[1] = drvp[1].PIO_mode; 1687 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1688 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1689 mode[1] = drvp[1].PIO_mode = 0; 1690 goto ok; 1691 } 1692 if (drvp[1].drive_flags & DRIVE_DMA) { 1693 mode[1] = drvp[1].DMA_mode; 1694 mode[0] = drvp[0].PIO_mode; 1695 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1696 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1697 mode[0] = drvp[0].PIO_mode = 0; 1698 goto ok; 1699 } 1700 /* 1701 * If both drives are not DMA, takes the lower mode, unless 1702 * one of them is PIO mode < 2 1703 */ 1704 if (drvp[0].PIO_mode < 2) { 1705 mode[0] = drvp[0].PIO_mode = 0; 1706 mode[1] = drvp[1].PIO_mode; 1707 } else if (drvp[1].PIO_mode < 2) { 1708 mode[1] = drvp[1].PIO_mode = 0; 1709 mode[0] = drvp[0].PIO_mode; 1710 } else { 1711 mode[0] = mode[1] = 1712 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1713 drvp[0].PIO_mode = mode[0]; 1714 drvp[1].PIO_mode = mode[1]; 1715 } 1716 ok: /* The modes are setup */ 1717 for (drive = 0; drive < 2; drive++) { 1718 if (drvp[drive].drive_flags & DRIVE_DMA) { 1719 idetim |= piix_setup_idetim_timings( 1720 mode[drive], 1, chp->channel); 1721 goto end; 1722 } 1723 } 1724 /* If we are there, none of the drives are DMA */ 1725 if (mode[0] >= 2) 1726 idetim |= piix_setup_idetim_timings( 1727 mode[0], 0, chp->channel); 1728 else 1729 idetim |= piix_setup_idetim_timings( 1730 mode[1], 0, chp->channel); 1731 end: /* 1732 * timing mode is now set up in the controller. Enable 1733 * it per-drive 1734 */ 1735 for (drive = 0; drive < 2; drive++) { 1736 /* If no drive, skip */ 1737 if ((drvp[drive].drive_flags & DRIVE) == 0) 1738 continue; 1739 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1740 if (drvp[drive].drive_flags & DRIVE_DMA) 1741 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1742 } 1743 if (idedma_ctl != 0) { 1744 /* Add software bits in status register */ 1745 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1746 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1747 idedma_ctl); 1748 } 1749 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1750 pciide_print_modes(cp); 1751 } 1752 1753 void 1754 piix3_4_setup_channel(chp) 1755 struct channel_softc *chp; 1756 { 1757 struct ata_drive_datas *drvp; 1758 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1759 struct pciide_channel *cp = (struct pciide_channel*)chp; 1760 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1761 int drive; 1762 int channel = chp->channel; 1763 1764 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1765 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1766 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1767 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1768 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1769 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1770 PIIX_SIDETIM_RTC_MASK(channel)); 1771 1772 idedma_ctl = 0; 1773 /* If channel disabled, no need to go further */ 1774 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1775 return; 1776 /* set up new idetim: Enable IDE registers decode */ 1777 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1778 1779 /* setup DMA if needed */ 1780 pciide_channel_dma_setup(cp); 1781 1782 for (drive = 0; drive < 2; drive++) { 1783 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1784 PIIX_UDMATIM_SET(0x3, channel, drive)); 1785 drvp = &chp->ch_drive[drive]; 1786 /* If no drive, skip */ 1787 if ((drvp->drive_flags & DRIVE) == 0) 1788 continue; 1789 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1790 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1791 goto pio; 1792 1793 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1794 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1795 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1796 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1797 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1798 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1799 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1800 ideconf |= PIIX_CONFIG_PINGPONG; 1801 } 1802 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1803 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1804 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1805 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1806 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1807 /* setup Ultra/100 */ 1808 if (drvp->UDMA_mode > 2 && 1809 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1810 drvp->UDMA_mode = 2; 1811 if (drvp->UDMA_mode > 4) { 1812 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1813 } else { 1814 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1815 if (drvp->UDMA_mode > 2) { 1816 ideconf |= PIIX_CONFIG_UDMA66(channel, 1817 drive); 1818 } else { 1819 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1820 drive); 1821 } 1822 } 1823 } 1824 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1825 /* setup Ultra/66 */ 1826 if (drvp->UDMA_mode > 2 && 1827 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1828 drvp->UDMA_mode = 2; 1829 if (drvp->UDMA_mode > 2) 1830 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1831 else 1832 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1833 } 1834 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1835 (drvp->drive_flags & DRIVE_UDMA)) { 1836 /* use Ultra/DMA */ 1837 drvp->drive_flags &= ~DRIVE_DMA; 1838 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1839 udmareg |= PIIX_UDMATIM_SET( 1840 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1841 } else { 1842 /* use Multiword DMA */ 1843 drvp->drive_flags &= ~DRIVE_UDMA; 1844 if (drive == 0) { 1845 idetim |= piix_setup_idetim_timings( 1846 drvp->DMA_mode, 1, channel); 1847 } else { 1848 sidetim |= piix_setup_sidetim_timings( 1849 drvp->DMA_mode, 1, channel); 1850 idetim =PIIX_IDETIM_SET(idetim, 1851 PIIX_IDETIM_SITRE, channel); 1852 } 1853 } 1854 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1855 1856 pio: /* use PIO mode */ 1857 idetim |= piix_setup_idetim_drvs(drvp); 1858 if (drive == 0) { 1859 idetim |= piix_setup_idetim_timings( 1860 drvp->PIO_mode, 0, channel); 1861 } else { 1862 sidetim |= piix_setup_sidetim_timings( 1863 drvp->PIO_mode, 0, channel); 1864 idetim =PIIX_IDETIM_SET(idetim, 1865 PIIX_IDETIM_SITRE, channel); 1866 } 1867 } 1868 if (idedma_ctl != 0) { 1869 /* Add software bits in status register */ 1870 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1871 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1872 idedma_ctl); 1873 } 1874 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1875 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1876 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1877 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1878 pciide_print_modes(cp); 1879 } 1880 1881 1882 /* setup ISP and RTC fields, based on mode */ 1883 static u_int32_t 1884 piix_setup_idetim_timings(mode, dma, channel) 1885 u_int8_t mode; 1886 u_int8_t dma; 1887 u_int8_t channel; 1888 { 1889 1890 if (dma) 1891 return PIIX_IDETIM_SET(0, 1892 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1893 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1894 channel); 1895 else 1896 return PIIX_IDETIM_SET(0, 1897 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1898 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1899 channel); 1900 } 1901 1902 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1903 static u_int32_t 1904 piix_setup_idetim_drvs(drvp) 1905 struct ata_drive_datas *drvp; 1906 { 1907 u_int32_t ret = 0; 1908 struct channel_softc *chp = drvp->chnl_softc; 1909 u_int8_t channel = chp->channel; 1910 u_int8_t drive = drvp->drive; 1911 1912 /* 1913 * If drive is using UDMA, timings setups are independant 1914 * So just check DMA and PIO here. 1915 */ 1916 if (drvp->drive_flags & DRIVE_DMA) { 1917 /* if mode = DMA mode 0, use compatible timings */ 1918 if ((drvp->drive_flags & DRIVE_DMA) && 1919 drvp->DMA_mode == 0) { 1920 drvp->PIO_mode = 0; 1921 return ret; 1922 } 1923 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1924 /* 1925 * PIO and DMA timings are the same, use fast timings for PIO 1926 * too, else use compat timings. 1927 */ 1928 if ((piix_isp_pio[drvp->PIO_mode] != 1929 piix_isp_dma[drvp->DMA_mode]) || 1930 (piix_rtc_pio[drvp->PIO_mode] != 1931 piix_rtc_dma[drvp->DMA_mode])) 1932 drvp->PIO_mode = 0; 1933 /* if PIO mode <= 2, use compat timings for PIO */ 1934 if (drvp->PIO_mode <= 2) { 1935 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1936 channel); 1937 return ret; 1938 } 1939 } 1940 1941 /* 1942 * Now setup PIO modes. If mode < 2, use compat timings. 1943 * Else enable fast timings. Enable IORDY and prefetch/post 1944 * if PIO mode >= 3. 1945 */ 1946 1947 if (drvp->PIO_mode < 2) 1948 return ret; 1949 1950 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1951 if (drvp->PIO_mode >= 3) { 1952 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1953 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1954 } 1955 return ret; 1956 } 1957 1958 /* setup values in SIDETIM registers, based on mode */ 1959 static u_int32_t 1960 piix_setup_sidetim_timings(mode, dma, channel) 1961 u_int8_t mode; 1962 u_int8_t dma; 1963 u_int8_t channel; 1964 { 1965 if (dma) 1966 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1967 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1968 else 1969 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1970 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1971 } 1972 1973 void 1974 amd7x6_chip_map(sc, pa) 1975 struct pciide_softc *sc; 1976 struct pci_attach_args *pa; 1977 { 1978 struct pciide_channel *cp; 1979 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1980 int channel; 1981 pcireg_t chanenable; 1982 bus_size_t cmdsize, ctlsize; 1983 1984 if (pciide_chipen(sc, pa) == 0) 1985 return; 1986 printf("%s: bus-master DMA support present", 1987 sc->sc_wdcdev.sc_dev.dv_xname); 1988 pciide_mapreg_dma(sc, pa); 1989 printf("\n"); 1990 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1991 WDC_CAPABILITY_MODE; 1992 if (sc->sc_dma_ok) { 1993 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1994 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1995 sc->sc_wdcdev.irqack = pciide_irqack; 1996 } 1997 sc->sc_wdcdev.PIO_cap = 4; 1998 sc->sc_wdcdev.DMA_cap = 2; 1999 2000 switch (sc->sc_pp->ide_product) { 2001 case PCI_PRODUCT_AMD_PBC766_IDE: 2002 case PCI_PRODUCT_AMD_PBC768_IDE: 2003 sc->sc_wdcdev.UDMA_cap = 5; 2004 break; 2005 default: 2006 sc->sc_wdcdev.UDMA_cap = 4; 2007 } 2008 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2009 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2010 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2011 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 2012 2013 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2014 DEBUG_PROBE); 2015 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2016 cp = &sc->pciide_channels[channel]; 2017 if (pciide_chansetup(sc, channel, interface) == 0) 2018 continue; 2019 2020 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2021 printf("%s: %s channel ignored (disabled)\n", 2022 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2023 continue; 2024 } 2025 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2026 pciide_pci_intr); 2027 2028 if (pciide_chan_candisable(cp)) 2029 chanenable &= ~AMD7X6_CHAN_EN(channel); 2030 pciide_map_compat_intr(pa, cp, channel, interface); 2031 if (cp->hw_ok == 0) 2032 continue; 2033 2034 amd7x6_setup_channel(&cp->wdc_channel); 2035 } 2036 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2037 chanenable); 2038 return; 2039 } 2040 2041 void 2042 amd7x6_setup_channel(chp) 2043 struct channel_softc *chp; 2044 { 2045 u_int32_t udmatim_reg, datatim_reg; 2046 u_int8_t idedma_ctl; 2047 int mode, drive; 2048 struct ata_drive_datas *drvp; 2049 struct pciide_channel *cp = (struct pciide_channel*)chp; 2050 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2051 #ifndef PCIIDE_AMD756_ENABLEDMA 2052 int rev = PCI_REVISION( 2053 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2054 #endif 2055 2056 idedma_ctl = 0; 2057 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2058 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2059 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2060 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2061 2062 /* setup DMA if needed */ 2063 pciide_channel_dma_setup(cp); 2064 2065 for (drive = 0; drive < 2; drive++) { 2066 drvp = &chp->ch_drive[drive]; 2067 /* If no drive, skip */ 2068 if ((drvp->drive_flags & DRIVE) == 0) 2069 continue; 2070 /* add timing values, setup DMA if needed */ 2071 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2072 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2073 mode = drvp->PIO_mode; 2074 goto pio; 2075 } 2076 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2077 (drvp->drive_flags & DRIVE_UDMA)) { 2078 /* use Ultra/DMA */ 2079 drvp->drive_flags &= ~DRIVE_DMA; 2080 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2081 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2082 AMD7X6_UDMA_TIME(chp->channel, drive, 2083 amd7x6_udma_tim[drvp->UDMA_mode]); 2084 /* can use PIO timings, MW DMA unused */ 2085 mode = drvp->PIO_mode; 2086 } else { 2087 /* use Multiword DMA, but only if revision is OK */ 2088 drvp->drive_flags &= ~DRIVE_UDMA; 2089 #ifndef PCIIDE_AMD756_ENABLEDMA 2090 /* 2091 * The workaround doesn't seem to be necessary 2092 * with all drives, so it can be disabled by 2093 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2094 * triggered. 2095 */ 2096 if (sc->sc_pp->ide_product == 2097 PCI_PRODUCT_AMD_PBC756_IDE && 2098 AMD756_CHIPREV_DISABLEDMA(rev)) { 2099 printf("%s:%d:%d: multi-word DMA disabled due " 2100 "to chip revision\n", 2101 sc->sc_wdcdev.sc_dev.dv_xname, 2102 chp->channel, drive); 2103 mode = drvp->PIO_mode; 2104 drvp->drive_flags &= ~DRIVE_DMA; 2105 goto pio; 2106 } 2107 #endif 2108 /* mode = min(pio, dma+2) */ 2109 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2110 mode = drvp->PIO_mode; 2111 else 2112 mode = drvp->DMA_mode + 2; 2113 } 2114 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2115 2116 pio: /* setup PIO mode */ 2117 if (mode <= 2) { 2118 drvp->DMA_mode = 0; 2119 drvp->PIO_mode = 0; 2120 mode = 0; 2121 } else { 2122 drvp->PIO_mode = mode; 2123 drvp->DMA_mode = mode - 2; 2124 } 2125 datatim_reg |= 2126 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2127 amd7x6_pio_set[mode]) | 2128 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2129 amd7x6_pio_rec[mode]); 2130 } 2131 if (idedma_ctl != 0) { 2132 /* Add software bits in status register */ 2133 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2134 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2135 idedma_ctl); 2136 } 2137 pciide_print_modes(cp); 2138 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2139 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2140 } 2141 2142 void 2143 apollo_chip_map(sc, pa) 2144 struct pciide_softc *sc; 2145 struct pci_attach_args *pa; 2146 { 2147 struct pciide_channel *cp; 2148 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2149 int channel; 2150 u_int32_t ideconf; 2151 bus_size_t cmdsize, ctlsize; 2152 pcitag_t pcib_tag; 2153 pcireg_t pcib_id, pcib_class; 2154 2155 if (pciide_chipen(sc, pa) == 0) 2156 return; 2157 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2158 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2159 /* and read ID and rev of the ISA bridge */ 2160 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2161 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2162 printf(": VIA Technologies "); 2163 switch (PCI_PRODUCT(pcib_id)) { 2164 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2165 printf("VT82C586 (Apollo VP) "); 2166 if(PCI_REVISION(pcib_class) >= 0x02) { 2167 printf("ATA33 controller\n"); 2168 sc->sc_wdcdev.UDMA_cap = 2; 2169 } else { 2170 printf("controller\n"); 2171 sc->sc_wdcdev.UDMA_cap = 0; 2172 } 2173 break; 2174 case PCI_PRODUCT_VIATECH_VT82C596A: 2175 printf("VT82C596A (Apollo Pro) "); 2176 if (PCI_REVISION(pcib_class) >= 0x12) { 2177 printf("ATA66 controller\n"); 2178 sc->sc_wdcdev.UDMA_cap = 4; 2179 } else { 2180 printf("ATA33 controller\n"); 2181 sc->sc_wdcdev.UDMA_cap = 2; 2182 } 2183 break; 2184 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2185 printf("VT82C686A (Apollo KX133) "); 2186 if (PCI_REVISION(pcib_class) >= 0x40) { 2187 printf("ATA100 controller\n"); 2188 sc->sc_wdcdev.UDMA_cap = 5; 2189 } else { 2190 printf("ATA66 controller\n"); 2191 sc->sc_wdcdev.UDMA_cap = 4; 2192 } 2193 break; 2194 case PCI_PRODUCT_VIATECH_VT8231: 2195 printf("VT8231 ATA100 controller\n"); 2196 sc->sc_wdcdev.UDMA_cap = 5; 2197 break; 2198 case PCI_PRODUCT_VIATECH_VT8233: 2199 printf("VT8233 ATA100 controller\n"); 2200 sc->sc_wdcdev.UDMA_cap = 5; 2201 break; 2202 case PCI_PRODUCT_VIATECH_VT8233A: 2203 printf("VT8233A ATA133 controller\n"); 2204 sc->sc_wdcdev.UDMA_cap = 6; 2205 break; 2206 default: 2207 printf("unknown ATA controller\n"); 2208 sc->sc_wdcdev.UDMA_cap = 0; 2209 } 2210 2211 printf("%s: bus-master DMA support present", 2212 sc->sc_wdcdev.sc_dev.dv_xname); 2213 pciide_mapreg_dma(sc, pa); 2214 printf("\n"); 2215 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2216 WDC_CAPABILITY_MODE; 2217 if (sc->sc_dma_ok) { 2218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2219 sc->sc_wdcdev.irqack = pciide_irqack; 2220 if (sc->sc_wdcdev.UDMA_cap > 0) 2221 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2222 } 2223 sc->sc_wdcdev.PIO_cap = 4; 2224 sc->sc_wdcdev.DMA_cap = 2; 2225 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2226 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2227 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2228 2229 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2230 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2231 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2232 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2233 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2234 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2235 DEBUG_PROBE); 2236 2237 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2238 cp = &sc->pciide_channels[channel]; 2239 if (pciide_chansetup(sc, channel, interface) == 0) 2240 continue; 2241 2242 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2243 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2244 printf("%s: %s channel ignored (disabled)\n", 2245 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2246 continue; 2247 } 2248 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2249 pciide_pci_intr); 2250 if (cp->hw_ok == 0) 2251 continue; 2252 if (pciide_chan_candisable(cp)) { 2253 ideconf &= ~APO_IDECONF_EN(channel); 2254 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2255 ideconf); 2256 } 2257 pciide_map_compat_intr(pa, cp, channel, interface); 2258 2259 if (cp->hw_ok == 0) 2260 continue; 2261 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2262 } 2263 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2264 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2265 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2266 } 2267 2268 void 2269 apollo_setup_channel(chp) 2270 struct channel_softc *chp; 2271 { 2272 u_int32_t udmatim_reg, datatim_reg; 2273 u_int8_t idedma_ctl; 2274 int mode, drive; 2275 struct ata_drive_datas *drvp; 2276 struct pciide_channel *cp = (struct pciide_channel*)chp; 2277 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2278 2279 idedma_ctl = 0; 2280 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2281 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2282 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2283 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2284 2285 /* setup DMA if needed */ 2286 pciide_channel_dma_setup(cp); 2287 2288 for (drive = 0; drive < 2; drive++) { 2289 drvp = &chp->ch_drive[drive]; 2290 /* If no drive, skip */ 2291 if ((drvp->drive_flags & DRIVE) == 0) 2292 continue; 2293 /* add timing values, setup DMA if needed */ 2294 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2295 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2296 mode = drvp->PIO_mode; 2297 goto pio; 2298 } 2299 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2300 (drvp->drive_flags & DRIVE_UDMA)) { 2301 /* use Ultra/DMA */ 2302 drvp->drive_flags &= ~DRIVE_DMA; 2303 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2304 APO_UDMA_EN_MTH(chp->channel, drive); 2305 if (sc->sc_wdcdev.UDMA_cap == 6) { 2306 /* 8233a */ 2307 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2308 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2309 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2310 /* 686b */ 2311 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2312 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2313 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2314 /* 596b or 686a */ 2315 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2316 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2317 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2318 } else { 2319 /* 596a or 586b */ 2320 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2321 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2322 } 2323 /* can use PIO timings, MW DMA unused */ 2324 mode = drvp->PIO_mode; 2325 } else { 2326 /* use Multiword DMA */ 2327 drvp->drive_flags &= ~DRIVE_UDMA; 2328 /* mode = min(pio, dma+2) */ 2329 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2330 mode = drvp->PIO_mode; 2331 else 2332 mode = drvp->DMA_mode + 2; 2333 } 2334 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2335 2336 pio: /* setup PIO mode */ 2337 if (mode <= 2) { 2338 drvp->DMA_mode = 0; 2339 drvp->PIO_mode = 0; 2340 mode = 0; 2341 } else { 2342 drvp->PIO_mode = mode; 2343 drvp->DMA_mode = mode - 2; 2344 } 2345 datatim_reg |= 2346 APO_DATATIM_PULSE(chp->channel, drive, 2347 apollo_pio_set[mode]) | 2348 APO_DATATIM_RECOV(chp->channel, drive, 2349 apollo_pio_rec[mode]); 2350 } 2351 if (idedma_ctl != 0) { 2352 /* Add software bits in status register */ 2353 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2354 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2355 idedma_ctl); 2356 } 2357 pciide_print_modes(cp); 2358 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2359 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2360 } 2361 2362 void 2363 cmd_channel_map(pa, sc, channel) 2364 struct pci_attach_args *pa; 2365 struct pciide_softc *sc; 2366 int channel; 2367 { 2368 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2369 bus_size_t cmdsize, ctlsize; 2370 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2371 int interface, one_channel; 2372 2373 /* 2374 * The 0648/0649 can be told to identify as a RAID controller. 2375 * In this case, we have to fake interface 2376 */ 2377 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2378 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2379 PCIIDE_INTERFACE_SETTABLE(1); 2380 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2381 CMD_CONF_DSA1) 2382 interface |= PCIIDE_INTERFACE_PCI(0) | 2383 PCIIDE_INTERFACE_PCI(1); 2384 } else { 2385 interface = PCI_INTERFACE(pa->pa_class); 2386 } 2387 2388 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2389 cp->name = PCIIDE_CHANNEL_NAME(channel); 2390 cp->wdc_channel.channel = channel; 2391 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2392 2393 /* 2394 * Older CMD64X doesn't have independant channels 2395 */ 2396 switch (sc->sc_pp->ide_product) { 2397 case PCI_PRODUCT_CMDTECH_649: 2398 one_channel = 0; 2399 break; 2400 default: 2401 one_channel = 1; 2402 break; 2403 } 2404 2405 if (channel > 0 && one_channel) { 2406 cp->wdc_channel.ch_queue = 2407 sc->pciide_channels[0].wdc_channel.ch_queue; 2408 } else { 2409 cp->wdc_channel.ch_queue = 2410 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2411 } 2412 if (cp->wdc_channel.ch_queue == NULL) { 2413 printf("%s %s channel: " 2414 "can't allocate memory for command queue", 2415 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2416 return; 2417 } 2418 2419 printf("%s: %s channel %s to %s mode\n", 2420 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2421 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2422 "configured" : "wired", 2423 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2424 "native-PCI" : "compatibility"); 2425 2426 /* 2427 * with a CMD PCI64x, if we get here, the first channel is enabled: 2428 * there's no way to disable the first channel without disabling 2429 * the whole device 2430 */ 2431 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2432 printf("%s: %s channel ignored (disabled)\n", 2433 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2434 return; 2435 } 2436 2437 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2438 if (cp->hw_ok == 0) 2439 return; 2440 if (channel == 1) { 2441 if (pciide_chan_candisable(cp)) { 2442 ctrl &= ~CMD_CTRL_2PORT; 2443 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2444 CMD_CTRL, ctrl); 2445 } 2446 } 2447 pciide_map_compat_intr(pa, cp, channel, interface); 2448 } 2449 2450 int 2451 cmd_pci_intr(arg) 2452 void *arg; 2453 { 2454 struct pciide_softc *sc = arg; 2455 struct pciide_channel *cp; 2456 struct channel_softc *wdc_cp; 2457 int i, rv, crv; 2458 u_int32_t priirq, secirq; 2459 2460 rv = 0; 2461 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2462 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2463 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2464 cp = &sc->pciide_channels[i]; 2465 wdc_cp = &cp->wdc_channel; 2466 /* If a compat channel skip. */ 2467 if (cp->compat) 2468 continue; 2469 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2470 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2471 crv = wdcintr(wdc_cp); 2472 if (crv == 0) 2473 printf("%s:%d: bogus intr\n", 2474 sc->sc_wdcdev.sc_dev.dv_xname, i); 2475 else 2476 rv = 1; 2477 } 2478 } 2479 return rv; 2480 } 2481 2482 void 2483 cmd_chip_map(sc, pa) 2484 struct pciide_softc *sc; 2485 struct pci_attach_args *pa; 2486 { 2487 int channel; 2488 2489 /* 2490 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2491 * and base adresses registers can be disabled at 2492 * hardware level. In this case, the device is wired 2493 * in compat mode and its first channel is always enabled, 2494 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2495 * In fact, it seems that the first channel of the CMD PCI0640 2496 * can't be disabled. 2497 */ 2498 2499 #ifdef PCIIDE_CMD064x_DISABLE 2500 if (pciide_chipen(sc, pa) == 0) 2501 return; 2502 #endif 2503 2504 printf("%s: hardware does not support DMA\n", 2505 sc->sc_wdcdev.sc_dev.dv_xname); 2506 sc->sc_dma_ok = 0; 2507 2508 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2509 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2510 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2511 2512 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2513 cmd_channel_map(pa, sc, channel); 2514 } 2515 } 2516 2517 void 2518 cmd0643_9_chip_map(sc, pa) 2519 struct pciide_softc *sc; 2520 struct pci_attach_args *pa; 2521 { 2522 struct pciide_channel *cp; 2523 int channel; 2524 pcireg_t rev = PCI_REVISION(pa->pa_class); 2525 2526 /* 2527 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2528 * and base adresses registers can be disabled at 2529 * hardware level. In this case, the device is wired 2530 * in compat mode and its first channel is always enabled, 2531 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2532 * In fact, it seems that the first channel of the CMD PCI0640 2533 * can't be disabled. 2534 */ 2535 2536 #ifdef PCIIDE_CMD064x_DISABLE 2537 if (pciide_chipen(sc, pa) == 0) 2538 return; 2539 #endif 2540 printf("%s: bus-master DMA support present", 2541 sc->sc_wdcdev.sc_dev.dv_xname); 2542 pciide_mapreg_dma(sc, pa); 2543 printf("\n"); 2544 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2545 WDC_CAPABILITY_MODE; 2546 if (sc->sc_dma_ok) { 2547 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2548 switch (sc->sc_pp->ide_product) { 2549 case PCI_PRODUCT_CMDTECH_649: 2550 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2551 sc->sc_wdcdev.UDMA_cap = 5; 2552 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2553 break; 2554 case PCI_PRODUCT_CMDTECH_648: 2555 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2556 sc->sc_wdcdev.UDMA_cap = 4; 2557 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2558 break; 2559 case PCI_PRODUCT_CMDTECH_646: 2560 if (rev >= CMD0646U2_REV) { 2561 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2562 sc->sc_wdcdev.UDMA_cap = 2; 2563 } else if (rev >= CMD0646U_REV) { 2564 /* 2565 * Linux's driver claims that the 646U is broken 2566 * with UDMA. Only enable it if we know what we're 2567 * doing 2568 */ 2569 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2570 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2571 sc->sc_wdcdev.UDMA_cap = 2; 2572 #endif 2573 /* explicitly disable UDMA */ 2574 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2575 CMD_UDMATIM(0), 0); 2576 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2577 CMD_UDMATIM(1), 0); 2578 } 2579 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2580 break; 2581 default: 2582 sc->sc_wdcdev.irqack = pciide_irqack; 2583 } 2584 } 2585 2586 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2587 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2588 sc->sc_wdcdev.PIO_cap = 4; 2589 sc->sc_wdcdev.DMA_cap = 2; 2590 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2591 2592 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2593 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2594 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2595 DEBUG_PROBE); 2596 2597 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2598 cp = &sc->pciide_channels[channel]; 2599 cmd_channel_map(pa, sc, channel); 2600 if (cp->hw_ok == 0) 2601 continue; 2602 cmd0643_9_setup_channel(&cp->wdc_channel); 2603 } 2604 /* 2605 * note - this also makes sure we clear the irq disable and reset 2606 * bits 2607 */ 2608 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2609 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2610 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2611 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2612 DEBUG_PROBE); 2613 } 2614 2615 void 2616 cmd0643_9_setup_channel(chp) 2617 struct channel_softc *chp; 2618 { 2619 struct ata_drive_datas *drvp; 2620 u_int8_t tim; 2621 u_int32_t idedma_ctl, udma_reg; 2622 int drive; 2623 struct pciide_channel *cp = (struct pciide_channel*)chp; 2624 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2625 2626 idedma_ctl = 0; 2627 /* setup DMA if needed */ 2628 pciide_channel_dma_setup(cp); 2629 2630 for (drive = 0; drive < 2; drive++) { 2631 drvp = &chp->ch_drive[drive]; 2632 /* If no drive, skip */ 2633 if ((drvp->drive_flags & DRIVE) == 0) 2634 continue; 2635 /* add timing values, setup DMA if needed */ 2636 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2637 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2638 if (drvp->drive_flags & DRIVE_UDMA) { 2639 /* UltraDMA on a 646U2, 0648 or 0649 */ 2640 drvp->drive_flags &= ~DRIVE_DMA; 2641 udma_reg = pciide_pci_read(sc->sc_pc, 2642 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2643 if (drvp->UDMA_mode > 2 && 2644 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2645 CMD_BICSR) & 2646 CMD_BICSR_80(chp->channel)) == 0) 2647 drvp->UDMA_mode = 2; 2648 if (drvp->UDMA_mode > 2) 2649 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2650 else if (sc->sc_wdcdev.UDMA_cap > 2) 2651 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2652 udma_reg |= CMD_UDMATIM_UDMA(drive); 2653 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2654 CMD_UDMATIM_TIM_OFF(drive)); 2655 udma_reg |= 2656 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2657 CMD_UDMATIM_TIM_OFF(drive)); 2658 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2659 CMD_UDMATIM(chp->channel), udma_reg); 2660 } else { 2661 /* 2662 * use Multiword DMA. 2663 * Timings will be used for both PIO and DMA, 2664 * so adjust DMA mode if needed 2665 * if we have a 0646U2/8/9, turn off UDMA 2666 */ 2667 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2668 udma_reg = pciide_pci_read(sc->sc_pc, 2669 sc->sc_tag, 2670 CMD_UDMATIM(chp->channel)); 2671 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2672 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2673 CMD_UDMATIM(chp->channel), 2674 udma_reg); 2675 } 2676 if (drvp->PIO_mode >= 3 && 2677 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2678 drvp->DMA_mode = drvp->PIO_mode - 2; 2679 } 2680 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2681 } 2682 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2683 } 2684 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2685 CMD_DATA_TIM(chp->channel, drive), tim); 2686 } 2687 if (idedma_ctl != 0) { 2688 /* Add software bits in status register */ 2689 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2690 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2691 idedma_ctl); 2692 } 2693 pciide_print_modes(cp); 2694 } 2695 2696 void 2697 cmd646_9_irqack(chp) 2698 struct channel_softc *chp; 2699 { 2700 u_int32_t priirq, secirq; 2701 struct pciide_channel *cp = (struct pciide_channel*)chp; 2702 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2703 2704 if (chp->channel == 0) { 2705 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2706 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2707 } else { 2708 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2709 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2710 } 2711 pciide_irqack(chp); 2712 } 2713 2714 void 2715 cy693_chip_map(sc, pa) 2716 struct pciide_softc *sc; 2717 struct pci_attach_args *pa; 2718 { 2719 struct pciide_channel *cp; 2720 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2721 bus_size_t cmdsize, ctlsize; 2722 2723 if (pciide_chipen(sc, pa) == 0) 2724 return; 2725 /* 2726 * this chip has 2 PCI IDE functions, one for primary and one for 2727 * secondary. So we need to call pciide_mapregs_compat() with 2728 * the real channel 2729 */ 2730 if (pa->pa_function == 1) { 2731 sc->sc_cy_compatchan = 0; 2732 } else if (pa->pa_function == 2) { 2733 sc->sc_cy_compatchan = 1; 2734 } else { 2735 printf("%s: unexpected PCI function %d\n", 2736 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2737 return; 2738 } 2739 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2740 printf("%s: bus-master DMA support present", 2741 sc->sc_wdcdev.sc_dev.dv_xname); 2742 pciide_mapreg_dma(sc, pa); 2743 } else { 2744 printf("%s: hardware does not support DMA", 2745 sc->sc_wdcdev.sc_dev.dv_xname); 2746 sc->sc_dma_ok = 0; 2747 } 2748 printf("\n"); 2749 2750 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2751 if (sc->sc_cy_handle == NULL) { 2752 printf("%s: unable to map hyperCache control registers\n", 2753 sc->sc_wdcdev.sc_dev.dv_xname); 2754 sc->sc_dma_ok = 0; 2755 } 2756 2757 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2758 WDC_CAPABILITY_MODE; 2759 if (sc->sc_dma_ok) { 2760 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2761 sc->sc_wdcdev.irqack = pciide_irqack; 2762 } 2763 sc->sc_wdcdev.PIO_cap = 4; 2764 sc->sc_wdcdev.DMA_cap = 2; 2765 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2766 2767 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2768 sc->sc_wdcdev.nchannels = 1; 2769 2770 /* Only one channel for this chip; if we are here it's enabled */ 2771 cp = &sc->pciide_channels[0]; 2772 sc->wdc_chanarray[0] = &cp->wdc_channel; 2773 cp->name = PCIIDE_CHANNEL_NAME(0); 2774 cp->wdc_channel.channel = 0; 2775 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2776 cp->wdc_channel.ch_queue = 2777 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2778 if (cp->wdc_channel.ch_queue == NULL) { 2779 printf("%s primary channel: " 2780 "can't allocate memory for command queue", 2781 sc->sc_wdcdev.sc_dev.dv_xname); 2782 return; 2783 } 2784 printf("%s: primary channel %s to ", 2785 sc->sc_wdcdev.sc_dev.dv_xname, 2786 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2787 "configured" : "wired"); 2788 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2789 printf("native-PCI"); 2790 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2791 pciide_pci_intr); 2792 } else { 2793 printf("compatibility"); 2794 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2795 &cmdsize, &ctlsize); 2796 } 2797 printf(" mode\n"); 2798 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2799 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2800 wdcattach(&cp->wdc_channel); 2801 if (pciide_chan_candisable(cp)) { 2802 pci_conf_write(sc->sc_pc, sc->sc_tag, 2803 PCI_COMMAND_STATUS_REG, 0); 2804 } 2805 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2806 if (cp->hw_ok == 0) 2807 return; 2808 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2809 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2810 cy693_setup_channel(&cp->wdc_channel); 2811 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2812 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2813 } 2814 2815 void 2816 cy693_setup_channel(chp) 2817 struct channel_softc *chp; 2818 { 2819 struct ata_drive_datas *drvp; 2820 int drive; 2821 u_int32_t cy_cmd_ctrl; 2822 u_int32_t idedma_ctl; 2823 struct pciide_channel *cp = (struct pciide_channel*)chp; 2824 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2825 int dma_mode = -1; 2826 2827 cy_cmd_ctrl = idedma_ctl = 0; 2828 2829 /* setup DMA if needed */ 2830 pciide_channel_dma_setup(cp); 2831 2832 for (drive = 0; drive < 2; drive++) { 2833 drvp = &chp->ch_drive[drive]; 2834 /* If no drive, skip */ 2835 if ((drvp->drive_flags & DRIVE) == 0) 2836 continue; 2837 /* add timing values, setup DMA if needed */ 2838 if (drvp->drive_flags & DRIVE_DMA) { 2839 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2840 /* use Multiword DMA */ 2841 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2842 dma_mode = drvp->DMA_mode; 2843 } 2844 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2845 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2846 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2847 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2848 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2849 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2850 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2851 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2852 } 2853 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2854 chp->ch_drive[0].DMA_mode = dma_mode; 2855 chp->ch_drive[1].DMA_mode = dma_mode; 2856 2857 if (dma_mode == -1) 2858 dma_mode = 0; 2859 2860 if (sc->sc_cy_handle != NULL) { 2861 /* Note: `multiple' is implied. */ 2862 cy82c693_write(sc->sc_cy_handle, 2863 (sc->sc_cy_compatchan == 0) ? 2864 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2865 } 2866 2867 pciide_print_modes(cp); 2868 2869 if (idedma_ctl != 0) { 2870 /* Add software bits in status register */ 2871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2872 IDEDMA_CTL, idedma_ctl); 2873 } 2874 } 2875 2876 static int 2877 sis_hostbr_match(pa) 2878 struct pci_attach_args *pa; 2879 { 2880 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2881 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2882 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2883 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2884 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2885 } 2886 2887 void 2888 sis_chip_map(sc, pa) 2889 struct pciide_softc *sc; 2890 struct pci_attach_args *pa; 2891 { 2892 struct pciide_channel *cp; 2893 int channel; 2894 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2895 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2896 pcireg_t rev = PCI_REVISION(pa->pa_class); 2897 bus_size_t cmdsize, ctlsize; 2898 pcitag_t pchb_tag; 2899 pcireg_t pchb_id, pchb_class; 2900 2901 if (pciide_chipen(sc, pa) == 0) 2902 return; 2903 printf("%s: bus-master DMA support present", 2904 sc->sc_wdcdev.sc_dev.dv_xname); 2905 pciide_mapreg_dma(sc, pa); 2906 printf("\n"); 2907 2908 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2909 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2910 /* and read ID and rev of the ISA bridge */ 2911 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2912 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2913 2914 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2915 WDC_CAPABILITY_MODE; 2916 if (sc->sc_dma_ok) { 2917 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2918 sc->sc_wdcdev.irqack = pciide_irqack; 2919 /* 2920 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2921 * have problems with UDMA (info provided by Christos) 2922 */ 2923 if (rev >= 0xd0 && 2924 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2925 PCI_REVISION(pchb_class) >= 0x03)) 2926 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2927 } 2928 2929 sc->sc_wdcdev.PIO_cap = 4; 2930 sc->sc_wdcdev.DMA_cap = 2; 2931 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2932 /* 2933 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2934 * chipsets. 2935 */ 2936 sc->sc_wdcdev.UDMA_cap = 2937 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2938 sc->sc_wdcdev.set_modes = sis_setup_channel; 2939 2940 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2941 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2942 2943 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2944 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2945 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2946 2947 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2948 cp = &sc->pciide_channels[channel]; 2949 if (pciide_chansetup(sc, channel, interface) == 0) 2950 continue; 2951 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2952 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2953 printf("%s: %s channel ignored (disabled)\n", 2954 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2955 continue; 2956 } 2957 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2958 pciide_pci_intr); 2959 if (cp->hw_ok == 0) 2960 continue; 2961 if (pciide_chan_candisable(cp)) { 2962 if (channel == 0) 2963 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2964 else 2965 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2966 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2967 sis_ctr0); 2968 } 2969 pciide_map_compat_intr(pa, cp, channel, interface); 2970 if (cp->hw_ok == 0) 2971 continue; 2972 sis_setup_channel(&cp->wdc_channel); 2973 } 2974 } 2975 2976 void 2977 sis_setup_channel(chp) 2978 struct channel_softc *chp; 2979 { 2980 struct ata_drive_datas *drvp; 2981 int drive; 2982 u_int32_t sis_tim; 2983 u_int32_t idedma_ctl; 2984 struct pciide_channel *cp = (struct pciide_channel*)chp; 2985 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2986 2987 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2988 "channel %d 0x%x\n", chp->channel, 2989 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2990 DEBUG_PROBE); 2991 sis_tim = 0; 2992 idedma_ctl = 0; 2993 /* setup DMA if needed */ 2994 pciide_channel_dma_setup(cp); 2995 2996 for (drive = 0; drive < 2; drive++) { 2997 drvp = &chp->ch_drive[drive]; 2998 /* If no drive, skip */ 2999 if ((drvp->drive_flags & DRIVE) == 0) 3000 continue; 3001 /* add timing values, setup DMA if needed */ 3002 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3003 (drvp->drive_flags & DRIVE_UDMA) == 0) 3004 goto pio; 3005 3006 if (drvp->drive_flags & DRIVE_UDMA) { 3007 /* use Ultra/DMA */ 3008 drvp->drive_flags &= ~DRIVE_DMA; 3009 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 3010 SIS_TIM_UDMA_TIME_OFF(drive); 3011 sis_tim |= SIS_TIM_UDMA_EN(drive); 3012 } else { 3013 /* 3014 * use Multiword DMA 3015 * Timings will be used for both PIO and DMA, 3016 * so adjust DMA mode if needed 3017 */ 3018 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3019 drvp->PIO_mode = drvp->DMA_mode + 2; 3020 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3021 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3022 drvp->PIO_mode - 2 : 0; 3023 if (drvp->DMA_mode == 0) 3024 drvp->PIO_mode = 0; 3025 } 3026 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3027 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 3028 SIS_TIM_ACT_OFF(drive); 3029 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3030 SIS_TIM_REC_OFF(drive); 3031 } 3032 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3033 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3034 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3035 if (idedma_ctl != 0) { 3036 /* Add software bits in status register */ 3037 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3038 IDEDMA_CTL, idedma_ctl); 3039 } 3040 pciide_print_modes(cp); 3041 } 3042 3043 void 3044 acer_chip_map(sc, pa) 3045 struct pciide_softc *sc; 3046 struct pci_attach_args *pa; 3047 { 3048 struct pciide_channel *cp; 3049 int channel; 3050 pcireg_t cr, interface; 3051 bus_size_t cmdsize, ctlsize; 3052 pcireg_t rev = PCI_REVISION(pa->pa_class); 3053 3054 if (pciide_chipen(sc, pa) == 0) 3055 return; 3056 printf("%s: bus-master DMA support present", 3057 sc->sc_wdcdev.sc_dev.dv_xname); 3058 pciide_mapreg_dma(sc, pa); 3059 printf("\n"); 3060 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3061 WDC_CAPABILITY_MODE; 3062 if (sc->sc_dma_ok) { 3063 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3064 if (rev >= 0x20) { 3065 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3066 if (rev >= 0xC4) 3067 sc->sc_wdcdev.UDMA_cap = 5; 3068 else if (rev >= 0xC2) 3069 sc->sc_wdcdev.UDMA_cap = 4; 3070 else 3071 sc->sc_wdcdev.UDMA_cap = 2; 3072 } 3073 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3074 sc->sc_wdcdev.irqack = pciide_irqack; 3075 } 3076 3077 sc->sc_wdcdev.PIO_cap = 4; 3078 sc->sc_wdcdev.DMA_cap = 2; 3079 sc->sc_wdcdev.set_modes = acer_setup_channel; 3080 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3081 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3082 3083 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3084 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3085 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3086 3087 /* Enable "microsoft register bits" R/W. */ 3088 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3089 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3090 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3091 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3092 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3093 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3094 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3095 ~ACER_CHANSTATUSREGS_RO); 3096 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3097 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3098 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3099 /* Don't use cr, re-read the real register content instead */ 3100 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3101 PCI_CLASS_REG)); 3102 3103 /* From linux: enable "Cable Detection" */ 3104 if (rev >= 0xC2) { 3105 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3106 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3107 | ACER_0x4B_CDETECT); 3108 } 3109 3110 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3111 cp = &sc->pciide_channels[channel]; 3112 if (pciide_chansetup(sc, channel, interface) == 0) 3113 continue; 3114 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3115 printf("%s: %s channel ignored (disabled)\n", 3116 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3117 continue; 3118 } 3119 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3120 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3121 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3122 if (cp->hw_ok == 0) 3123 continue; 3124 if (pciide_chan_candisable(cp)) { 3125 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3126 pci_conf_write(sc->sc_pc, sc->sc_tag, 3127 PCI_CLASS_REG, cr); 3128 } 3129 pciide_map_compat_intr(pa, cp, channel, interface); 3130 acer_setup_channel(&cp->wdc_channel); 3131 } 3132 } 3133 3134 void 3135 acer_setup_channel(chp) 3136 struct channel_softc *chp; 3137 { 3138 struct ata_drive_datas *drvp; 3139 int drive; 3140 u_int32_t acer_fifo_udma; 3141 u_int32_t idedma_ctl; 3142 struct pciide_channel *cp = (struct pciide_channel*)chp; 3143 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3144 3145 idedma_ctl = 0; 3146 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3147 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3148 acer_fifo_udma), DEBUG_PROBE); 3149 /* setup DMA if needed */ 3150 pciide_channel_dma_setup(cp); 3151 3152 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3153 DRIVE_UDMA) { /* check 80 pins cable */ 3154 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3155 ACER_0x4A_80PIN(chp->channel)) { 3156 if (chp->ch_drive[0].UDMA_mode > 2) 3157 chp->ch_drive[0].UDMA_mode = 2; 3158 if (chp->ch_drive[1].UDMA_mode > 2) 3159 chp->ch_drive[1].UDMA_mode = 2; 3160 } 3161 } 3162 3163 for (drive = 0; drive < 2; drive++) { 3164 drvp = &chp->ch_drive[drive]; 3165 /* If no drive, skip */ 3166 if ((drvp->drive_flags & DRIVE) == 0) 3167 continue; 3168 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3169 "channel %d drive %d 0x%x\n", chp->channel, drive, 3170 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3171 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3172 /* clear FIFO/DMA mode */ 3173 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3174 ACER_UDMA_EN(chp->channel, drive) | 3175 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3176 3177 /* add timing values, setup DMA if needed */ 3178 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3179 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3180 acer_fifo_udma |= 3181 ACER_FTH_OPL(chp->channel, drive, 0x1); 3182 goto pio; 3183 } 3184 3185 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3186 if (drvp->drive_flags & DRIVE_UDMA) { 3187 /* use Ultra/DMA */ 3188 drvp->drive_flags &= ~DRIVE_DMA; 3189 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3190 acer_fifo_udma |= 3191 ACER_UDMA_TIM(chp->channel, drive, 3192 acer_udma[drvp->UDMA_mode]); 3193 /* XXX disable if one drive < UDMA3 ? */ 3194 if (drvp->UDMA_mode >= 3) { 3195 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3196 ACER_0x4B, 3197 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3198 ACER_0x4B) | ACER_0x4B_UDMA66); 3199 } 3200 } else { 3201 /* 3202 * use Multiword DMA 3203 * Timings will be used for both PIO and DMA, 3204 * so adjust DMA mode if needed 3205 */ 3206 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3207 drvp->PIO_mode = drvp->DMA_mode + 2; 3208 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3209 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3210 drvp->PIO_mode - 2 : 0; 3211 if (drvp->DMA_mode == 0) 3212 drvp->PIO_mode = 0; 3213 } 3214 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3215 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3216 ACER_IDETIM(chp->channel, drive), 3217 acer_pio[drvp->PIO_mode]); 3218 } 3219 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3220 acer_fifo_udma), DEBUG_PROBE); 3221 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3222 if (idedma_ctl != 0) { 3223 /* Add software bits in status register */ 3224 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3225 IDEDMA_CTL, idedma_ctl); 3226 } 3227 pciide_print_modes(cp); 3228 } 3229 3230 int 3231 acer_pci_intr(arg) 3232 void *arg; 3233 { 3234 struct pciide_softc *sc = arg; 3235 struct pciide_channel *cp; 3236 struct channel_softc *wdc_cp; 3237 int i, rv, crv; 3238 u_int32_t chids; 3239 3240 rv = 0; 3241 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3242 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3243 cp = &sc->pciide_channels[i]; 3244 wdc_cp = &cp->wdc_channel; 3245 /* If a compat channel skip. */ 3246 if (cp->compat) 3247 continue; 3248 if (chids & ACER_CHIDS_INT(i)) { 3249 crv = wdcintr(wdc_cp); 3250 if (crv == 0) 3251 printf("%s:%d: bogus intr\n", 3252 sc->sc_wdcdev.sc_dev.dv_xname, i); 3253 else 3254 rv = 1; 3255 } 3256 } 3257 return rv; 3258 } 3259 3260 void 3261 hpt_chip_map(sc, pa) 3262 struct pciide_softc *sc; 3263 struct pci_attach_args *pa; 3264 { 3265 struct pciide_channel *cp; 3266 int i, compatchan, revision; 3267 pcireg_t interface; 3268 bus_size_t cmdsize, ctlsize; 3269 3270 if (pciide_chipen(sc, pa) == 0) 3271 return; 3272 revision = PCI_REVISION(pa->pa_class); 3273 printf(": Triones/Highpoint "); 3274 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3275 printf("HPT374 IDE Controller\n"); 3276 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3277 printf("HPT372 IDE Controller\n"); 3278 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3279 if (revision == HPT372_REV) 3280 printf("HPT372 IDE Controller\n"); 3281 else if (revision == HPT370_REV) 3282 printf("HPT370 IDE Controller\n"); 3283 else if (revision == HPT370A_REV) 3284 printf("HPT370A IDE Controller\n"); 3285 else if (revision == HPT366_REV) 3286 printf("HPT366 IDE Controller\n"); 3287 else 3288 printf("unknown HPT IDE controller rev %d\n", revision); 3289 } else 3290 printf("unknown HPT IDE controller 0x%x\n", 3291 sc->sc_pp->ide_product); 3292 3293 /* 3294 * when the chip is in native mode it identifies itself as a 3295 * 'misc mass storage'. Fake interface in this case. 3296 */ 3297 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3298 interface = PCI_INTERFACE(pa->pa_class); 3299 } else { 3300 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3301 PCIIDE_INTERFACE_PCI(0); 3302 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3303 (revision == HPT370_REV || revision == HPT370A_REV || 3304 revision == HPT372_REV)) || 3305 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3306 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3307 interface |= PCIIDE_INTERFACE_PCI(1); 3308 } 3309 3310 printf("%s: bus-master DMA support present", 3311 sc->sc_wdcdev.sc_dev.dv_xname); 3312 pciide_mapreg_dma(sc, pa); 3313 printf("\n"); 3314 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3315 WDC_CAPABILITY_MODE; 3316 if (sc->sc_dma_ok) { 3317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3318 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3319 sc->sc_wdcdev.irqack = pciide_irqack; 3320 } 3321 sc->sc_wdcdev.PIO_cap = 4; 3322 sc->sc_wdcdev.DMA_cap = 2; 3323 3324 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3325 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3326 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3327 revision == HPT366_REV) { 3328 sc->sc_wdcdev.UDMA_cap = 4; 3329 /* 3330 * The 366 has 2 PCI IDE functions, one for primary and one 3331 * for secondary. So we need to call pciide_mapregs_compat() 3332 * with the real channel 3333 */ 3334 if (pa->pa_function == 0) { 3335 compatchan = 0; 3336 } else if (pa->pa_function == 1) { 3337 compatchan = 1; 3338 } else { 3339 printf("%s: unexpected PCI function %d\n", 3340 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3341 return; 3342 } 3343 sc->sc_wdcdev.nchannels = 1; 3344 } else { 3345 sc->sc_wdcdev.nchannels = 2; 3346 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3347 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3348 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3349 revision == HPT372_REV)) 3350 sc->sc_wdcdev.UDMA_cap = 6; 3351 else 3352 sc->sc_wdcdev.UDMA_cap = 5; 3353 } 3354 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3355 cp = &sc->pciide_channels[i]; 3356 if (sc->sc_wdcdev.nchannels > 1) { 3357 compatchan = i; 3358 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3359 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3360 printf("%s: %s channel ignored (disabled)\n", 3361 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3362 continue; 3363 } 3364 } 3365 if (pciide_chansetup(sc, i, interface) == 0) 3366 continue; 3367 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3368 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3369 &ctlsize, hpt_pci_intr); 3370 } else { 3371 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3372 &cmdsize, &ctlsize); 3373 } 3374 if (cp->hw_ok == 0) 3375 return; 3376 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3377 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3378 wdcattach(&cp->wdc_channel); 3379 hpt_setup_channel(&cp->wdc_channel); 3380 } 3381 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3382 (revision == HPT370_REV || revision == HPT370A_REV || 3383 revision == HPT372_REV)) || 3384 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3385 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3386 /* 3387 * HPT370_REV and highter has a bit to disable interrupts, 3388 * make sure to clear it 3389 */ 3390 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3391 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3392 ~HPT_CSEL_IRQDIS); 3393 } 3394 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 3395 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3396 revision == HPT372_REV ) || 3397 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3398 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3399 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3400 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3401 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3402 return; 3403 } 3404 3405 void 3406 hpt_setup_channel(chp) 3407 struct channel_softc *chp; 3408 { 3409 struct ata_drive_datas *drvp; 3410 int drive; 3411 int cable; 3412 u_int32_t before, after; 3413 u_int32_t idedma_ctl; 3414 struct pciide_channel *cp = (struct pciide_channel*)chp; 3415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3416 int revision = 3417 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 3418 3419 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3420 3421 /* setup DMA if needed */ 3422 pciide_channel_dma_setup(cp); 3423 3424 idedma_ctl = 0; 3425 3426 /* Per drive settings */ 3427 for (drive = 0; drive < 2; drive++) { 3428 drvp = &chp->ch_drive[drive]; 3429 /* If no drive, skip */ 3430 if ((drvp->drive_flags & DRIVE) == 0) 3431 continue; 3432 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3433 HPT_IDETIM(chp->channel, drive)); 3434 3435 /* add timing values, setup DMA if needed */ 3436 if (drvp->drive_flags & DRIVE_UDMA) { 3437 /* use Ultra/DMA */ 3438 drvp->drive_flags &= ~DRIVE_DMA; 3439 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3440 drvp->UDMA_mode > 2) 3441 drvp->UDMA_mode = 2; 3442 switch (sc->sc_pp->ide_product) { 3443 case PCI_PRODUCT_TRIONES_HPT374: 3444 after = hpt374_udma[drvp->UDMA_mode]; 3445 break; 3446 case PCI_PRODUCT_TRIONES_HPT372: 3447 after = hpt372_udma[drvp->UDMA_mode]; 3448 break; 3449 case PCI_PRODUCT_TRIONES_HPT366: 3450 default: 3451 switch(revision) { 3452 case HPT372_REV: 3453 after = hpt372_udma[drvp->UDMA_mode]; 3454 break; 3455 case HPT370_REV: 3456 case HPT370A_REV: 3457 after = hpt370_udma[drvp->UDMA_mode]; 3458 break; 3459 case HPT366_REV: 3460 default: 3461 after = hpt366_udma[drvp->UDMA_mode]; 3462 break; 3463 } 3464 } 3465 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3466 } else if (drvp->drive_flags & DRIVE_DMA) { 3467 /* 3468 * use Multiword DMA. 3469 * Timings will be used for both PIO and DMA, so adjust 3470 * DMA mode if needed 3471 */ 3472 if (drvp->PIO_mode >= 3 && 3473 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3474 drvp->DMA_mode = drvp->PIO_mode - 2; 3475 } 3476 switch (sc->sc_pp->ide_product) { 3477 case PCI_PRODUCT_TRIONES_HPT374: 3478 after = hpt374_dma[drvp->DMA_mode]; 3479 break; 3480 case PCI_PRODUCT_TRIONES_HPT372: 3481 after = hpt372_dma[drvp->DMA_mode]; 3482 break; 3483 case PCI_PRODUCT_TRIONES_HPT366: 3484 default: 3485 switch(revision) { 3486 case HPT372_REV: 3487 after = hpt372_dma[drvp->DMA_mode]; 3488 break; 3489 case HPT370_REV: 3490 case HPT370A_REV: 3491 after = hpt370_dma[drvp->DMA_mode]; 3492 break; 3493 case HPT366_REV: 3494 default: 3495 after = hpt366_dma[drvp->DMA_mode]; 3496 break; 3497 } 3498 } 3499 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3500 } else { 3501 /* PIO only */ 3502 switch (sc->sc_pp->ide_product) { 3503 case PCI_PRODUCT_TRIONES_HPT374: 3504 after = hpt374_pio[drvp->PIO_mode]; 3505 break; 3506 case PCI_PRODUCT_TRIONES_HPT372: 3507 after = hpt372_pio[drvp->PIO_mode]; 3508 break; 3509 case PCI_PRODUCT_TRIONES_HPT366: 3510 default: 3511 switch(revision) { 3512 case HPT372_REV: 3513 after = hpt372_pio[drvp->PIO_mode]; 3514 break; 3515 case HPT370_REV: 3516 case HPT370A_REV: 3517 after = hpt370_pio[drvp->PIO_mode]; 3518 break; 3519 case HPT366_REV: 3520 default: 3521 after = hpt366_pio[drvp->PIO_mode]; 3522 break; 3523 } 3524 } 3525 } 3526 pci_conf_write(sc->sc_pc, sc->sc_tag, 3527 HPT_IDETIM(chp->channel, drive), after); 3528 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3529 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3530 after, before), DEBUG_PROBE); 3531 } 3532 if (idedma_ctl != 0) { 3533 /* Add software bits in status register */ 3534 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3535 IDEDMA_CTL, idedma_ctl); 3536 } 3537 pciide_print_modes(cp); 3538 } 3539 3540 int 3541 hpt_pci_intr(arg) 3542 void *arg; 3543 { 3544 struct pciide_softc *sc = arg; 3545 struct pciide_channel *cp; 3546 struct channel_softc *wdc_cp; 3547 int rv = 0; 3548 int dmastat, i, crv; 3549 3550 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3551 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3552 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3553 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3554 IDEDMA_CTL_INTR) 3555 continue; 3556 cp = &sc->pciide_channels[i]; 3557 wdc_cp = &cp->wdc_channel; 3558 crv = wdcintr(wdc_cp); 3559 if (crv == 0) { 3560 printf("%s:%d: bogus intr\n", 3561 sc->sc_wdcdev.sc_dev.dv_xname, i); 3562 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3563 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3564 } else 3565 rv = 1; 3566 } 3567 return rv; 3568 } 3569 3570 3571 /* Macros to test product */ 3572 #define PDC_IS_262(sc) \ 3573 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3574 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3575 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3576 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3577 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3578 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3579 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3580 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3581 #define PDC_IS_265(sc) \ 3582 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3583 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3584 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3585 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3586 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3587 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3588 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3589 #define PDC_IS_268(sc) \ 3590 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3591 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3592 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3593 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3594 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3595 #define PDC_IS_276(sc) \ 3596 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 3597 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 3598 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2) 3599 3600 void 3601 pdc202xx_chip_map(sc, pa) 3602 struct pciide_softc *sc; 3603 struct pci_attach_args *pa; 3604 { 3605 struct pciide_channel *cp; 3606 int channel; 3607 pcireg_t interface, st, mode; 3608 bus_size_t cmdsize, ctlsize; 3609 3610 if (!PDC_IS_268(sc)) { 3611 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3612 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3613 st), DEBUG_PROBE); 3614 } 3615 if (pciide_chipen(sc, pa) == 0) 3616 return; 3617 3618 /* turn off RAID mode */ 3619 if (!PDC_IS_268(sc)) 3620 st &= ~PDC2xx_STATE_IDERAID; 3621 3622 /* 3623 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3624 * mode. We have to fake interface 3625 */ 3626 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3627 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3628 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3629 3630 printf("%s: bus-master DMA support present", 3631 sc->sc_wdcdev.sc_dev.dv_xname); 3632 pciide_mapreg_dma(sc, pa); 3633 printf("\n"); 3634 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3635 WDC_CAPABILITY_MODE; 3636 if (sc->sc_dma_ok) { 3637 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3638 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3639 sc->sc_wdcdev.irqack = pciide_irqack; 3640 } 3641 sc->sc_wdcdev.PIO_cap = 4; 3642 sc->sc_wdcdev.DMA_cap = 2; 3643 if (PDC_IS_276(sc)) 3644 sc->sc_wdcdev.UDMA_cap = 6; 3645 else if (PDC_IS_265(sc)) 3646 sc->sc_wdcdev.UDMA_cap = 5; 3647 else if (PDC_IS_262(sc)) 3648 sc->sc_wdcdev.UDMA_cap = 4; 3649 else 3650 sc->sc_wdcdev.UDMA_cap = 2; 3651 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3652 pdc20268_setup_channel : pdc202xx_setup_channel; 3653 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3654 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3655 3656 if (!PDC_IS_268(sc)) { 3657 /* setup failsafe defaults */ 3658 mode = 0; 3659 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3660 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3661 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3662 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3663 for (channel = 0; 3664 channel < sc->sc_wdcdev.nchannels; 3665 channel++) { 3666 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3667 "drive 0 initial timings 0x%x, now 0x%x\n", 3668 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3669 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3670 DEBUG_PROBE); 3671 pci_conf_write(sc->sc_pc, sc->sc_tag, 3672 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3673 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3674 "drive 1 initial timings 0x%x, now 0x%x\n", 3675 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3676 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3677 pci_conf_write(sc->sc_pc, sc->sc_tag, 3678 PDC2xx_TIM(channel, 1), mode); 3679 } 3680 3681 mode = PDC2xx_SCR_DMA; 3682 if (PDC_IS_262(sc)) { 3683 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3684 } else { 3685 /* the BIOS set it up this way */ 3686 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3687 } 3688 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3689 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3690 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3691 "now 0x%x\n", 3692 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3693 PDC2xx_SCR), 3694 mode), DEBUG_PROBE); 3695 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3696 PDC2xx_SCR, mode); 3697 3698 /* controller initial state register is OK even without BIOS */ 3699 /* Set DMA mode to IDE DMA compatibility */ 3700 mode = 3701 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3702 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3703 DEBUG_PROBE); 3704 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3705 mode | 0x1); 3706 mode = 3707 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3708 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3709 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3710 mode | 0x1); 3711 } 3712 3713 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3714 cp = &sc->pciide_channels[channel]; 3715 if (pciide_chansetup(sc, channel, interface) == 0) 3716 continue; 3717 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3718 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3719 printf("%s: %s channel ignored (disabled)\n", 3720 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3721 continue; 3722 } 3723 if (PDC_IS_265(sc)) 3724 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3725 pdc20265_pci_intr); 3726 else 3727 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3728 pdc202xx_pci_intr); 3729 if (cp->hw_ok == 0) 3730 continue; 3731 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3732 st &= ~(PDC_IS_262(sc) ? 3733 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3734 pciide_map_compat_intr(pa, cp, channel, interface); 3735 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3736 } 3737 if (!PDC_IS_268(sc)) { 3738 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3739 "0x%x\n", st), DEBUG_PROBE); 3740 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3741 } 3742 return; 3743 } 3744 3745 void 3746 pdc202xx_setup_channel(chp) 3747 struct channel_softc *chp; 3748 { 3749 struct ata_drive_datas *drvp; 3750 int drive; 3751 pcireg_t mode, st; 3752 u_int32_t idedma_ctl, scr, atapi; 3753 struct pciide_channel *cp = (struct pciide_channel*)chp; 3754 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3755 int channel = chp->channel; 3756 3757 /* setup DMA if needed */ 3758 pciide_channel_dma_setup(cp); 3759 3760 idedma_ctl = 0; 3761 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3762 sc->sc_wdcdev.sc_dev.dv_xname, 3763 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3764 DEBUG_PROBE); 3765 3766 /* Per channel settings */ 3767 if (PDC_IS_262(sc)) { 3768 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3769 PDC262_U66); 3770 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3771 /* Trim UDMA mode */ 3772 if ((st & PDC262_STATE_80P(channel)) != 0 || 3773 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3774 chp->ch_drive[0].UDMA_mode <= 2) || 3775 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3776 chp->ch_drive[1].UDMA_mode <= 2)) { 3777 if (chp->ch_drive[0].UDMA_mode > 2) 3778 chp->ch_drive[0].UDMA_mode = 2; 3779 if (chp->ch_drive[1].UDMA_mode > 2) 3780 chp->ch_drive[1].UDMA_mode = 2; 3781 } 3782 /* Set U66 if needed */ 3783 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3784 chp->ch_drive[0].UDMA_mode > 2) || 3785 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3786 chp->ch_drive[1].UDMA_mode > 2)) 3787 scr |= PDC262_U66_EN(channel); 3788 else 3789 scr &= ~PDC262_U66_EN(channel); 3790 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3791 PDC262_U66, scr); 3792 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3793 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3794 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3795 PDC262_ATAPI(channel))), DEBUG_PROBE); 3796 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3797 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3798 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3799 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3800 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3801 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3802 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3803 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3804 atapi = 0; 3805 else 3806 atapi = PDC262_ATAPI_UDMA; 3807 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3808 PDC262_ATAPI(channel), atapi); 3809 } 3810 } 3811 for (drive = 0; drive < 2; drive++) { 3812 drvp = &chp->ch_drive[drive]; 3813 /* If no drive, skip */ 3814 if ((drvp->drive_flags & DRIVE) == 0) 3815 continue; 3816 mode = 0; 3817 if (drvp->drive_flags & DRIVE_UDMA) { 3818 /* use Ultra/DMA */ 3819 drvp->drive_flags &= ~DRIVE_DMA; 3820 mode = PDC2xx_TIM_SET_MB(mode, 3821 pdc2xx_udma_mb[drvp->UDMA_mode]); 3822 mode = PDC2xx_TIM_SET_MC(mode, 3823 pdc2xx_udma_mc[drvp->UDMA_mode]); 3824 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3825 } else if (drvp->drive_flags & DRIVE_DMA) { 3826 mode = PDC2xx_TIM_SET_MB(mode, 3827 pdc2xx_dma_mb[drvp->DMA_mode]); 3828 mode = PDC2xx_TIM_SET_MC(mode, 3829 pdc2xx_dma_mc[drvp->DMA_mode]); 3830 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3831 } else { 3832 mode = PDC2xx_TIM_SET_MB(mode, 3833 pdc2xx_dma_mb[0]); 3834 mode = PDC2xx_TIM_SET_MC(mode, 3835 pdc2xx_dma_mc[0]); 3836 } 3837 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3838 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3839 if (drvp->drive_flags & DRIVE_ATA) 3840 mode |= PDC2xx_TIM_PRE; 3841 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3842 if (drvp->PIO_mode >= 3) { 3843 mode |= PDC2xx_TIM_IORDY; 3844 if (drive == 0) 3845 mode |= PDC2xx_TIM_IORDYp; 3846 } 3847 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3848 "timings 0x%x\n", 3849 sc->sc_wdcdev.sc_dev.dv_xname, 3850 chp->channel, drive, mode), DEBUG_PROBE); 3851 pci_conf_write(sc->sc_pc, sc->sc_tag, 3852 PDC2xx_TIM(chp->channel, drive), mode); 3853 } 3854 if (idedma_ctl != 0) { 3855 /* Add software bits in status register */ 3856 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3857 IDEDMA_CTL, idedma_ctl); 3858 } 3859 pciide_print_modes(cp); 3860 } 3861 3862 void 3863 pdc20268_setup_channel(chp) 3864 struct channel_softc *chp; 3865 { 3866 struct ata_drive_datas *drvp; 3867 int drive; 3868 u_int32_t idedma_ctl; 3869 struct pciide_channel *cp = (struct pciide_channel*)chp; 3870 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3871 int u100; 3872 3873 /* setup DMA if needed */ 3874 pciide_channel_dma_setup(cp); 3875 3876 idedma_ctl = 0; 3877 3878 /* I don't know what this is for, FreeBSD does it ... */ 3879 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3880 IDEDMA_CMD + 0x1, 0x0b); 3881 3882 /* 3883 * I don't know what this is for; FreeBSD checks this ... this is not 3884 * cable type detect. 3885 */ 3886 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3887 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3888 3889 for (drive = 0; drive < 2; drive++) { 3890 drvp = &chp->ch_drive[drive]; 3891 /* If no drive, skip */ 3892 if ((drvp->drive_flags & DRIVE) == 0) 3893 continue; 3894 if (drvp->drive_flags & DRIVE_UDMA) { 3895 /* use Ultra/DMA */ 3896 drvp->drive_flags &= ~DRIVE_DMA; 3897 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3898 if (drvp->UDMA_mode > 2 && u100 == 0) 3899 drvp->UDMA_mode = 2; 3900 } else if (drvp->drive_flags & DRIVE_DMA) { 3901 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3902 } 3903 } 3904 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3905 if (idedma_ctl != 0) { 3906 /* Add software bits in status register */ 3907 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3908 IDEDMA_CTL, idedma_ctl); 3909 } 3910 pciide_print_modes(cp); 3911 } 3912 3913 int 3914 pdc202xx_pci_intr(arg) 3915 void *arg; 3916 { 3917 struct pciide_softc *sc = arg; 3918 struct pciide_channel *cp; 3919 struct channel_softc *wdc_cp; 3920 int i, rv, crv; 3921 u_int32_t scr; 3922 3923 rv = 0; 3924 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3925 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3926 cp = &sc->pciide_channels[i]; 3927 wdc_cp = &cp->wdc_channel; 3928 /* If a compat channel skip. */ 3929 if (cp->compat) 3930 continue; 3931 if (scr & PDC2xx_SCR_INT(i)) { 3932 crv = wdcintr(wdc_cp); 3933 if (crv == 0) 3934 printf("%s:%d: bogus intr (reg 0x%x)\n", 3935 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3936 else 3937 rv = 1; 3938 } 3939 } 3940 return rv; 3941 } 3942 3943 int 3944 pdc20265_pci_intr(arg) 3945 void *arg; 3946 { 3947 struct pciide_softc *sc = arg; 3948 struct pciide_channel *cp; 3949 struct channel_softc *wdc_cp; 3950 int i, rv, crv; 3951 u_int32_t dmastat; 3952 3953 rv = 0; 3954 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3955 cp = &sc->pciide_channels[i]; 3956 wdc_cp = &cp->wdc_channel; 3957 /* If a compat channel skip. */ 3958 if (cp->compat) 3959 continue; 3960 /* 3961 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3962 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3963 * So use it instead (requires 2 reg reads instead of 1, 3964 * but we can't do it another way). 3965 */ 3966 dmastat = bus_space_read_1(sc->sc_dma_iot, 3967 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3968 if((dmastat & IDEDMA_CTL_INTR) == 0) 3969 continue; 3970 crv = wdcintr(wdc_cp); 3971 if (crv == 0) 3972 printf("%s:%d: bogus intr\n", 3973 sc->sc_wdcdev.sc_dev.dv_xname, i); 3974 else 3975 rv = 1; 3976 } 3977 return rv; 3978 } 3979 3980 void 3981 opti_chip_map(sc, pa) 3982 struct pciide_softc *sc; 3983 struct pci_attach_args *pa; 3984 { 3985 struct pciide_channel *cp; 3986 bus_size_t cmdsize, ctlsize; 3987 pcireg_t interface; 3988 u_int8_t init_ctrl; 3989 int channel; 3990 3991 if (pciide_chipen(sc, pa) == 0) 3992 return; 3993 printf("%s: bus-master DMA support present", 3994 sc->sc_wdcdev.sc_dev.dv_xname); 3995 3996 /* 3997 * XXXSCW: 3998 * There seem to be a couple of buggy revisions/implementations 3999 * of the OPTi pciide chipset. This kludge seems to fix one of 4000 * the reported problems (PR/11644) but still fails for the 4001 * other (PR/13151), although the latter may be due to other 4002 * issues too... 4003 */ 4004 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4005 printf(" but disabled due to chip rev. <= 0x12"); 4006 sc->sc_dma_ok = 0; 4007 } else 4008 pciide_mapreg_dma(sc, pa); 4009 4010 printf("\n"); 4011 4012 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4013 WDC_CAPABILITY_MODE; 4014 sc->sc_wdcdev.PIO_cap = 4; 4015 if (sc->sc_dma_ok) { 4016 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4017 sc->sc_wdcdev.irqack = pciide_irqack; 4018 sc->sc_wdcdev.DMA_cap = 2; 4019 } 4020 sc->sc_wdcdev.set_modes = opti_setup_channel; 4021 4022 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4023 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4024 4025 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4026 OPTI_REG_INIT_CONTROL); 4027 4028 interface = PCI_INTERFACE(pa->pa_class); 4029 4030 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4031 cp = &sc->pciide_channels[channel]; 4032 if (pciide_chansetup(sc, channel, interface) == 0) 4033 continue; 4034 if (channel == 1 && 4035 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4036 printf("%s: %s channel ignored (disabled)\n", 4037 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4038 continue; 4039 } 4040 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4041 pciide_pci_intr); 4042 if (cp->hw_ok == 0) 4043 continue; 4044 pciide_map_compat_intr(pa, cp, channel, interface); 4045 if (cp->hw_ok == 0) 4046 continue; 4047 opti_setup_channel(&cp->wdc_channel); 4048 } 4049 } 4050 4051 void 4052 opti_setup_channel(chp) 4053 struct channel_softc *chp; 4054 { 4055 struct ata_drive_datas *drvp; 4056 struct pciide_channel *cp = (struct pciide_channel*)chp; 4057 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4058 int drive, spd; 4059 int mode[2]; 4060 u_int8_t rv, mr; 4061 4062 /* 4063 * The `Delay' and `Address Setup Time' fields of the 4064 * Miscellaneous Register are always zero initially. 4065 */ 4066 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4067 mr &= ~(OPTI_MISC_DELAY_MASK | 4068 OPTI_MISC_ADDR_SETUP_MASK | 4069 OPTI_MISC_INDEX_MASK); 4070 4071 /* Prime the control register before setting timing values */ 4072 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4073 4074 /* Determine the clockrate of the PCIbus the chip is attached to */ 4075 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4076 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4077 4078 /* setup DMA if needed */ 4079 pciide_channel_dma_setup(cp); 4080 4081 for (drive = 0; drive < 2; drive++) { 4082 drvp = &chp->ch_drive[drive]; 4083 /* If no drive, skip */ 4084 if ((drvp->drive_flags & DRIVE) == 0) { 4085 mode[drive] = -1; 4086 continue; 4087 } 4088 4089 if ((drvp->drive_flags & DRIVE_DMA)) { 4090 /* 4091 * Timings will be used for both PIO and DMA, 4092 * so adjust DMA mode if needed 4093 */ 4094 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4095 drvp->PIO_mode = drvp->DMA_mode + 2; 4096 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4097 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4098 drvp->PIO_mode - 2 : 0; 4099 if (drvp->DMA_mode == 0) 4100 drvp->PIO_mode = 0; 4101 4102 mode[drive] = drvp->DMA_mode + 5; 4103 } else 4104 mode[drive] = drvp->PIO_mode; 4105 4106 if (drive && mode[0] >= 0 && 4107 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4108 /* 4109 * Can't have two drives using different values 4110 * for `Address Setup Time'. 4111 * Slow down the faster drive to compensate. 4112 */ 4113 int d = (opti_tim_as[spd][mode[0]] > 4114 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4115 4116 mode[d] = mode[1-d]; 4117 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4118 chp->ch_drive[d].DMA_mode = 0; 4119 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4120 } 4121 } 4122 4123 for (drive = 0; drive < 2; drive++) { 4124 int m; 4125 if ((m = mode[drive]) < 0) 4126 continue; 4127 4128 /* Set the Address Setup Time and select appropriate index */ 4129 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4130 rv |= OPTI_MISC_INDEX(drive); 4131 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4132 4133 /* Set the pulse width and recovery timing parameters */ 4134 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4135 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4136 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4137 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4138 4139 /* Set the Enhanced Mode register appropriately */ 4140 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4141 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4142 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4143 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4144 } 4145 4146 /* Finally, enable the timings */ 4147 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4148 4149 pciide_print_modes(cp); 4150 } 4151 4152 #define ACARD_IS_850(sc) \ 4153 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4154 4155 void 4156 acard_chip_map(sc, pa) 4157 struct pciide_softc *sc; 4158 struct pci_attach_args *pa; 4159 { 4160 struct pciide_channel *cp; 4161 int i; 4162 pcireg_t interface; 4163 bus_size_t cmdsize, ctlsize; 4164 4165 if (pciide_chipen(sc, pa) == 0) 4166 return; 4167 4168 /* 4169 * when the chip is in native mode it identifies itself as a 4170 * 'misc mass storage'. Fake interface in this case. 4171 */ 4172 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4173 interface = PCI_INTERFACE(pa->pa_class); 4174 } else { 4175 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4176 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4177 } 4178 4179 printf("%s: bus-master DMA support present", 4180 sc->sc_wdcdev.sc_dev.dv_xname); 4181 pciide_mapreg_dma(sc, pa); 4182 printf("\n"); 4183 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4184 WDC_CAPABILITY_MODE; 4185 4186 if (sc->sc_dma_ok) { 4187 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4188 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4189 sc->sc_wdcdev.irqack = pciide_irqack; 4190 } 4191 sc->sc_wdcdev.PIO_cap = 4; 4192 sc->sc_wdcdev.DMA_cap = 2; 4193 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4194 4195 sc->sc_wdcdev.set_modes = acard_setup_channel; 4196 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4197 sc->sc_wdcdev.nchannels = 2; 4198 4199 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4200 cp = &sc->pciide_channels[i]; 4201 if (pciide_chansetup(sc, i, interface) == 0) 4202 continue; 4203 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4204 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4205 &ctlsize, pciide_pci_intr); 4206 } else { 4207 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4208 &cmdsize, &ctlsize); 4209 } 4210 if (cp->hw_ok == 0) 4211 return; 4212 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4213 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4214 wdcattach(&cp->wdc_channel); 4215 acard_setup_channel(&cp->wdc_channel); 4216 } 4217 if (!ACARD_IS_850(sc)) { 4218 u_int32_t reg; 4219 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4220 reg &= ~ATP860_CTRL_INT; 4221 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4222 } 4223 } 4224 4225 void 4226 acard_setup_channel(chp) 4227 struct channel_softc *chp; 4228 { 4229 struct ata_drive_datas *drvp; 4230 struct pciide_channel *cp = (struct pciide_channel*)chp; 4231 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4232 int channel = chp->channel; 4233 int drive; 4234 u_int32_t idetime, udma_mode; 4235 u_int32_t idedma_ctl; 4236 4237 /* setup DMA if needed */ 4238 pciide_channel_dma_setup(cp); 4239 4240 if (ACARD_IS_850(sc)) { 4241 idetime = 0; 4242 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4243 udma_mode &= ~ATP850_UDMA_MASK(channel); 4244 } else { 4245 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4246 idetime &= ~ATP860_SETTIME_MASK(channel); 4247 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4248 udma_mode &= ~ATP860_UDMA_MASK(channel); 4249 4250 /* check 80 pins cable */ 4251 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4252 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4253 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4254 & ATP860_CTRL_80P(chp->channel)) { 4255 if (chp->ch_drive[0].UDMA_mode > 2) 4256 chp->ch_drive[0].UDMA_mode = 2; 4257 if (chp->ch_drive[1].UDMA_mode > 2) 4258 chp->ch_drive[1].UDMA_mode = 2; 4259 } 4260 } 4261 } 4262 4263 idedma_ctl = 0; 4264 4265 /* Per drive settings */ 4266 for (drive = 0; drive < 2; drive++) { 4267 drvp = &chp->ch_drive[drive]; 4268 /* If no drive, skip */ 4269 if ((drvp->drive_flags & DRIVE) == 0) 4270 continue; 4271 /* add timing values, setup DMA if needed */ 4272 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4273 (drvp->drive_flags & DRIVE_UDMA)) { 4274 /* use Ultra/DMA */ 4275 if (ACARD_IS_850(sc)) { 4276 idetime |= ATP850_SETTIME(drive, 4277 acard_act_udma[drvp->UDMA_mode], 4278 acard_rec_udma[drvp->UDMA_mode]); 4279 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4280 acard_udma_conf[drvp->UDMA_mode]); 4281 } else { 4282 idetime |= ATP860_SETTIME(channel, drive, 4283 acard_act_udma[drvp->UDMA_mode], 4284 acard_rec_udma[drvp->UDMA_mode]); 4285 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4286 acard_udma_conf[drvp->UDMA_mode]); 4287 } 4288 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4289 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4290 (drvp->drive_flags & DRIVE_DMA)) { 4291 /* use Multiword DMA */ 4292 drvp->drive_flags &= ~DRIVE_UDMA; 4293 if (ACARD_IS_850(sc)) { 4294 idetime |= ATP850_SETTIME(drive, 4295 acard_act_dma[drvp->DMA_mode], 4296 acard_rec_dma[drvp->DMA_mode]); 4297 } else { 4298 idetime |= ATP860_SETTIME(channel, drive, 4299 acard_act_dma[drvp->DMA_mode], 4300 acard_rec_dma[drvp->DMA_mode]); 4301 } 4302 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4303 } else { 4304 /* PIO only */ 4305 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4306 if (ACARD_IS_850(sc)) { 4307 idetime |= ATP850_SETTIME(drive, 4308 acard_act_pio[drvp->PIO_mode], 4309 acard_rec_pio[drvp->PIO_mode]); 4310 } else { 4311 idetime |= ATP860_SETTIME(channel, drive, 4312 acard_act_pio[drvp->PIO_mode], 4313 acard_rec_pio[drvp->PIO_mode]); 4314 } 4315 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4316 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4317 | ATP8x0_CTRL_EN(channel)); 4318 } 4319 } 4320 4321 if (idedma_ctl != 0) { 4322 /* Add software bits in status register */ 4323 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4324 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4325 } 4326 pciide_print_modes(cp); 4327 4328 if (ACARD_IS_850(sc)) { 4329 pci_conf_write(sc->sc_pc, sc->sc_tag, 4330 ATP850_IDETIME(channel), idetime); 4331 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4332 } else { 4333 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4334 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4335 } 4336 } 4337 4338 int 4339 acard_pci_intr(arg) 4340 void *arg; 4341 { 4342 struct pciide_softc *sc = arg; 4343 struct pciide_channel *cp; 4344 struct channel_softc *wdc_cp; 4345 int rv = 0; 4346 int dmastat, i, crv; 4347 4348 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4349 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4350 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4351 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4352 continue; 4353 cp = &sc->pciide_channels[i]; 4354 wdc_cp = &cp->wdc_channel; 4355 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4356 (void)wdcintr(wdc_cp); 4357 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4358 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4359 continue; 4360 } 4361 crv = wdcintr(wdc_cp); 4362 if (crv == 0) 4363 printf("%s:%d: bogus intr\n", 4364 sc->sc_wdcdev.sc_dev.dv_xname, i); 4365 else if (crv == 1) 4366 rv = 1; 4367 else if (rv == 0) 4368 rv = crv; 4369 } 4370 return rv; 4371 } 4372 4373 static int 4374 sl82c105_bugchk(struct pci_attach_args *pa) 4375 { 4376 4377 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4378 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4379 return (0); 4380 4381 if (PCI_REVISION(pa->pa_class) <= 0x05) 4382 return (1); 4383 4384 return (0); 4385 } 4386 4387 void 4388 sl82c105_chip_map(sc, pa) 4389 struct pciide_softc *sc; 4390 struct pci_attach_args *pa; 4391 { 4392 struct pciide_channel *cp; 4393 bus_size_t cmdsize, ctlsize; 4394 pcireg_t interface, idecr; 4395 int channel; 4396 4397 if (pciide_chipen(sc, pa) == 0) 4398 return; 4399 4400 printf("%s: bus-master DMA support present", 4401 sc->sc_wdcdev.sc_dev.dv_xname); 4402 4403 /* 4404 * Check to see if we're part of the Winbond 83c553 Southbridge. 4405 * If so, we need to disable DMA on rev. <= 5 of that chip. 4406 */ 4407 if (pci_find_device(pa, sl82c105_bugchk)) { 4408 printf(" but disabled due to 83c553 rev. <= 0x05"); 4409 sc->sc_dma_ok = 0; 4410 } else 4411 pciide_mapreg_dma(sc, pa); 4412 printf("\n"); 4413 4414 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4415 WDC_CAPABILITY_MODE; 4416 sc->sc_wdcdev.PIO_cap = 4; 4417 if (sc->sc_dma_ok) { 4418 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4419 sc->sc_wdcdev.irqack = pciide_irqack; 4420 sc->sc_wdcdev.DMA_cap = 2; 4421 } 4422 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4423 4424 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4425 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4426 4427 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4428 4429 interface = PCI_INTERFACE(pa->pa_class); 4430 4431 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4432 cp = &sc->pciide_channels[channel]; 4433 if (pciide_chansetup(sc, channel, interface) == 0) 4434 continue; 4435 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4436 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4437 printf("%s: %s channel ignored (disabled)\n", 4438 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4439 continue; 4440 } 4441 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4442 pciide_pci_intr); 4443 if (cp->hw_ok == 0) 4444 continue; 4445 pciide_map_compat_intr(pa, cp, channel, interface); 4446 if (cp->hw_ok == 0) 4447 continue; 4448 sl82c105_setup_channel(&cp->wdc_channel); 4449 } 4450 } 4451 4452 void 4453 sl82c105_setup_channel(chp) 4454 struct channel_softc *chp; 4455 { 4456 struct ata_drive_datas *drvp; 4457 struct pciide_channel *cp = (struct pciide_channel*)chp; 4458 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4459 int pxdx_reg, drive; 4460 pcireg_t pxdx; 4461 4462 /* Set up DMA if needed. */ 4463 pciide_channel_dma_setup(cp); 4464 4465 for (drive = 0; drive < 2; drive++) { 4466 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4467 : SYMPH_P1D0CR) + (drive * 4); 4468 4469 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4470 4471 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4472 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4473 4474 drvp = &chp->ch_drive[drive]; 4475 /* If no drive, skip. */ 4476 if ((drvp->drive_flags & DRIVE) == 0) { 4477 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4478 continue; 4479 } 4480 4481 if (drvp->drive_flags & DRIVE_DMA) { 4482 /* 4483 * Timings will be used for both PIO and DMA, 4484 * so adjust DMA mode if needed. 4485 */ 4486 if (drvp->PIO_mode >= 3) { 4487 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4488 drvp->DMA_mode = drvp->PIO_mode - 2; 4489 if (drvp->DMA_mode < 1) { 4490 /* 4491 * Can't mix both PIO and DMA. 4492 * Disable DMA. 4493 */ 4494 drvp->drive_flags &= ~DRIVE_DMA; 4495 } 4496 } else { 4497 /* 4498 * Can't mix both PIO and DMA. Disable 4499 * DMA. 4500 */ 4501 drvp->drive_flags &= ~DRIVE_DMA; 4502 } 4503 } 4504 4505 if (drvp->drive_flags & DRIVE_DMA) { 4506 /* Use multi-word DMA. */ 4507 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4508 PxDx_CMD_ON_SHIFT; 4509 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4510 } else { 4511 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4512 PxDx_CMD_ON_SHIFT; 4513 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4514 } 4515 4516 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4517 4518 /* ...and set the mode for this drive. */ 4519 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4520 } 4521 4522 pciide_print_modes(cp); 4523 } 4524 4525 void 4526 serverworks_chip_map(sc, pa) 4527 struct pciide_softc *sc; 4528 struct pci_attach_args *pa; 4529 { 4530 struct pciide_channel *cp; 4531 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4532 pcitag_t pcib_tag; 4533 int channel; 4534 bus_size_t cmdsize, ctlsize; 4535 4536 if (pciide_chipen(sc, pa) == 0) 4537 return; 4538 4539 printf("%s: bus-master DMA support present", 4540 sc->sc_wdcdev.sc_dev.dv_xname); 4541 pciide_mapreg_dma(sc, pa); 4542 printf("\n"); 4543 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4544 WDC_CAPABILITY_MODE; 4545 4546 if (sc->sc_dma_ok) { 4547 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4548 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4549 sc->sc_wdcdev.irqack = pciide_irqack; 4550 } 4551 sc->sc_wdcdev.PIO_cap = 4; 4552 sc->sc_wdcdev.DMA_cap = 2; 4553 switch (sc->sc_pp->ide_product) { 4554 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4555 sc->sc_wdcdev.UDMA_cap = 2; 4556 break; 4557 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4558 if (PCI_REVISION(pa->pa_class) < 0x92) 4559 sc->sc_wdcdev.UDMA_cap = 4; 4560 else 4561 sc->sc_wdcdev.UDMA_cap = 5; 4562 break; 4563 } 4564 4565 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4566 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4567 sc->sc_wdcdev.nchannels = 2; 4568 4569 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4570 cp = &sc->pciide_channels[channel]; 4571 if (pciide_chansetup(sc, channel, interface) == 0) 4572 continue; 4573 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4574 serverworks_pci_intr); 4575 if (cp->hw_ok == 0) 4576 return; 4577 pciide_map_compat_intr(pa, cp, channel, interface); 4578 if (cp->hw_ok == 0) 4579 return; 4580 serverworks_setup_channel(&cp->wdc_channel); 4581 } 4582 4583 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4584 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4585 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4586 } 4587 4588 void 4589 serverworks_setup_channel(chp) 4590 struct channel_softc *chp; 4591 { 4592 struct ata_drive_datas *drvp; 4593 struct pciide_channel *cp = (struct pciide_channel*)chp; 4594 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4595 int channel = chp->channel; 4596 int drive, unit; 4597 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4598 u_int32_t idedma_ctl; 4599 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4600 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4601 4602 /* setup DMA if needed */ 4603 pciide_channel_dma_setup(cp); 4604 4605 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4606 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4607 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4608 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4609 4610 pio_time &= ~(0xffff << (16 * channel)); 4611 dma_time &= ~(0xffff << (16 * channel)); 4612 pio_mode &= ~(0xff << (8 * channel + 16)); 4613 udma_mode &= ~(0xff << (8 * channel + 16)); 4614 udma_mode &= ~(3 << (2 * channel)); 4615 4616 idedma_ctl = 0; 4617 4618 /* Per drive settings */ 4619 for (drive = 0; drive < 2; drive++) { 4620 drvp = &chp->ch_drive[drive]; 4621 /* If no drive, skip */ 4622 if ((drvp->drive_flags & DRIVE) == 0) 4623 continue; 4624 unit = drive + 2 * channel; 4625 /* add timing values, setup DMA if needed */ 4626 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4627 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4628 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4629 (drvp->drive_flags & DRIVE_UDMA)) { 4630 /* use Ultra/DMA, check for 80-pin cable */ 4631 if (drvp->UDMA_mode > 2 && 4632 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4633 drvp->UDMA_mode = 2; 4634 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4635 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4636 udma_mode |= 1 << unit; 4637 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4638 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4639 (drvp->drive_flags & DRIVE_DMA)) { 4640 /* use Multiword DMA */ 4641 drvp->drive_flags &= ~DRIVE_UDMA; 4642 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4643 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4644 } else { 4645 /* PIO only */ 4646 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4647 } 4648 } 4649 4650 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4651 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4652 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4653 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4654 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4655 4656 if (idedma_ctl != 0) { 4657 /* Add software bits in status register */ 4658 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4659 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4660 } 4661 pciide_print_modes(cp); 4662 } 4663 4664 int 4665 serverworks_pci_intr(arg) 4666 void *arg; 4667 { 4668 struct pciide_softc *sc = arg; 4669 struct pciide_channel *cp; 4670 struct channel_softc *wdc_cp; 4671 int rv = 0; 4672 int dmastat, i, crv; 4673 4674 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4675 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4676 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4677 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4678 IDEDMA_CTL_INTR) 4679 continue; 4680 cp = &sc->pciide_channels[i]; 4681 wdc_cp = &cp->wdc_channel; 4682 crv = wdcintr(wdc_cp); 4683 if (crv == 0) { 4684 printf("%s:%d: bogus intr\n", 4685 sc->sc_wdcdev.sc_dev.dv_xname, i); 4686 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4687 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4688 } else 4689 rv = 1; 4690 } 4691 return rv; 4692 } 4693
Indexes created Thu Oct 02 10:09:58 GMT 2025