pciide.c revision 1.158
1 /* $NetBSD: pciide.c,v 1.158 2002/06/10 08:41:11 cjs Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.158 2002/06/10 08:41:11 cjs Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 181 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cy693_setup_channel __P((struct channel_softc*)); 183 184 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void sis_setup_channel __P((struct channel_softc*)); 186 static int sis_hostbr_match __P(( struct pci_attach_args *)); 187 188 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void acer_setup_channel __P((struct channel_softc*)); 190 int acer_pci_intr __P((void *)); 191 192 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void pdc202xx_setup_channel __P((struct channel_softc*)); 194 void pdc20268_setup_channel __P((struct channel_softc*)); 195 int pdc202xx_pci_intr __P((void *)); 196 int pdc20265_pci_intr __P((void *)); 197 198 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void opti_setup_channel __P((struct channel_softc*)); 200 201 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 202 void hpt_setup_channel __P((struct channel_softc*)); 203 int hpt_pci_intr __P((void *)); 204 205 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void acard_setup_channel __P((struct channel_softc*)); 207 int acard_pci_intr __P((void *)); 208 209 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void serverworks_setup_channel __P((struct channel_softc*)); 211 int serverworks_pci_intr __P((void *)); 212 213 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void sl82c105_setup_channel __P((struct channel_softc*)); 215 216 void pciide_channel_dma_setup __P((struct pciide_channel *)); 217 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 218 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 219 void pciide_dma_start __P((void*, int, int)); 220 int pciide_dma_finish __P((void*, int, int, int)); 221 void pciide_irqack __P((struct channel_softc *)); 222 void pciide_print_modes __P((struct pciide_channel *)); 223 224 struct pciide_product_desc { 225 u_int32_t ide_product; 226 int ide_flags; 227 const char *ide_name; 228 /* map and setup chip, probe drives */ 229 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 230 }; 231 232 /* Flags for ide_flags */ 233 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 234 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 235 236 /* Default product description for devices not known from this controller */ 237 const struct pciide_product_desc default_product_desc = { 238 0, 239 0, 240 "Generic PCI IDE controller", 241 default_chip_map, 242 }; 243 244 const struct pciide_product_desc pciide_intel_products[] = { 245 { PCI_PRODUCT_INTEL_82092AA, 246 0, 247 "Intel 82092AA IDE controller", 248 default_chip_map, 249 }, 250 { PCI_PRODUCT_INTEL_82371FB_IDE, 251 0, 252 "Intel 82371FB IDE controller (PIIX)", 253 piix_chip_map, 254 }, 255 { PCI_PRODUCT_INTEL_82371SB_IDE, 256 0, 257 "Intel 82371SB IDE Interface (PIIX3)", 258 piix_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371AB_IDE, 261 0, 262 "Intel 82371AB IDE controller (PIIX4)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82440MX_IDE, 266 0, 267 "Intel 82440MX IDE controller", 268 piix_chip_map 269 }, 270 { PCI_PRODUCT_INTEL_82801AA_IDE, 271 0, 272 "Intel 82801AA IDE Controller (ICH)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82801AB_IDE, 276 0, 277 "Intel 82801AB IDE Controller (ICH0)", 278 piix_chip_map, 279 }, 280 { PCI_PRODUCT_INTEL_82801BA_IDE, 281 0, 282 "Intel 82801BA IDE Controller (ICH2)", 283 piix_chip_map, 284 }, 285 { PCI_PRODUCT_INTEL_82801BAM_IDE, 286 0, 287 "Intel 82801BAM IDE Controller (ICH2)", 288 piix_chip_map, 289 }, 290 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 291 0, 292 "Intel 82201CA IDE Controller", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 296 0, 297 "Intel 82201CA IDE Controller", 298 piix_chip_map, 299 }, 300 { 0, 301 0, 302 NULL, 303 NULL 304 } 305 }; 306 307 const struct pciide_product_desc pciide_amd_products[] = { 308 { PCI_PRODUCT_AMD_PBC756_IDE, 309 0, 310 "Advanced Micro Devices AMD756 IDE Controller", 311 amd7x6_chip_map 312 }, 313 { PCI_PRODUCT_AMD_PBC766_IDE, 314 0, 315 "Advanced Micro Devices AMD766 IDE Controller", 316 amd7x6_chip_map 317 }, 318 { PCI_PRODUCT_AMD_PBC768_IDE, 319 0, 320 "Advanced Micro Devices AMD768 IDE Controller", 321 amd7x6_chip_map 322 }, 323 { PCI_PRODUCT_AMD_PBC8111_IDE, 324 0, 325 "Advanced Micro Devices AMD8111 IDE Controller", 326 amd7x6_chip_map 327 }, 328 { 0, 329 0, 330 NULL, 331 NULL 332 } 333 }; 334 335 const struct pciide_product_desc pciide_cmd_products[] = { 336 { PCI_PRODUCT_CMDTECH_640, 337 0, 338 "CMD Technology PCI0640", 339 cmd_chip_map 340 }, 341 { PCI_PRODUCT_CMDTECH_643, 342 0, 343 "CMD Technology PCI0643", 344 cmd0643_9_chip_map, 345 }, 346 { PCI_PRODUCT_CMDTECH_646, 347 0, 348 "CMD Technology PCI0646", 349 cmd0643_9_chip_map, 350 }, 351 { PCI_PRODUCT_CMDTECH_648, 352 IDE_PCI_CLASS_OVERRIDE, 353 "CMD Technology PCI0648", 354 cmd0643_9_chip_map, 355 }, 356 { PCI_PRODUCT_CMDTECH_649, 357 IDE_PCI_CLASS_OVERRIDE, 358 "CMD Technology PCI0649", 359 cmd0643_9_chip_map, 360 }, 361 { 0, 362 0, 363 NULL, 364 NULL 365 } 366 }; 367 368 const struct pciide_product_desc pciide_via_products[] = { 369 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 370 0, 371 NULL, 372 apollo_chip_map, 373 }, 374 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 375 0, 376 NULL, 377 apollo_chip_map, 378 }, 379 { 0, 380 0, 381 NULL, 382 NULL 383 } 384 }; 385 386 const struct pciide_product_desc pciide_cypress_products[] = { 387 { PCI_PRODUCT_CONTAQ_82C693, 388 IDE_16BIT_IOSPACE, 389 "Cypress 82C693 IDE Controller", 390 cy693_chip_map, 391 }, 392 { 0, 393 0, 394 NULL, 395 NULL 396 } 397 }; 398 399 const struct pciide_product_desc pciide_sis_products[] = { 400 { PCI_PRODUCT_SIS_5597_IDE, 401 0, 402 "Silicon Integrated System 5597/5598 IDE controller", 403 sis_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 NULL 409 } 410 }; 411 412 const struct pciide_product_desc pciide_acer_products[] = { 413 { PCI_PRODUCT_ALI_M5229, 414 0, 415 "Acer Labs M5229 UDMA IDE Controller", 416 acer_chip_map, 417 }, 418 { 0, 419 0, 420 NULL, 421 NULL 422 } 423 }; 424 425 const struct pciide_product_desc pciide_promise_products[] = { 426 { PCI_PRODUCT_PROMISE_ULTRA33, 427 IDE_PCI_CLASS_OVERRIDE, 428 "Promise Ultra33/ATA Bus Master IDE Accelerator", 429 pdc202xx_chip_map, 430 }, 431 { PCI_PRODUCT_PROMISE_ULTRA66, 432 IDE_PCI_CLASS_OVERRIDE, 433 "Promise Ultra66/ATA Bus Master IDE Accelerator", 434 pdc202xx_chip_map, 435 }, 436 { PCI_PRODUCT_PROMISE_ULTRA100, 437 IDE_PCI_CLASS_OVERRIDE, 438 "Promise Ultra100/ATA Bus Master IDE Accelerator", 439 pdc202xx_chip_map, 440 }, 441 { PCI_PRODUCT_PROMISE_ULTRA100X, 442 IDE_PCI_CLASS_OVERRIDE, 443 "Promise Ultra100/ATA Bus Master IDE Accelerator", 444 pdc202xx_chip_map, 445 }, 446 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 447 IDE_PCI_CLASS_OVERRIDE, 448 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 449 pdc202xx_chip_map, 450 }, 451 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 452 IDE_PCI_CLASS_OVERRIDE, 453 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 454 pdc202xx_chip_map, 455 }, 456 { PCI_PRODUCT_PROMISE_ULTRA133, 457 IDE_PCI_CLASS_OVERRIDE, 458 "Promise Ultra133/ATA Bus Master IDE Accelerator", 459 pdc202xx_chip_map, 460 }, 461 { 0, 462 0, 463 NULL, 464 NULL 465 } 466 }; 467 468 const struct pciide_product_desc pciide_opti_products[] = { 469 { PCI_PRODUCT_OPTI_82C621, 470 0, 471 "OPTi 82c621 PCI IDE controller", 472 opti_chip_map, 473 }, 474 { PCI_PRODUCT_OPTI_82C568, 475 0, 476 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 477 opti_chip_map, 478 }, 479 { PCI_PRODUCT_OPTI_82D568, 480 0, 481 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 482 opti_chip_map, 483 }, 484 { 0, 485 0, 486 NULL, 487 NULL 488 } 489 }; 490 491 const struct pciide_product_desc pciide_triones_products[] = { 492 { PCI_PRODUCT_TRIONES_HPT366, 493 IDE_PCI_CLASS_OVERRIDE, 494 NULL, 495 hpt_chip_map, 496 }, 497 { PCI_PRODUCT_TRIONES_HPT374, 498 IDE_PCI_CLASS_OVERRIDE, 499 NULL, 500 hpt_chip_map 501 }, 502 { 0, 503 0, 504 NULL, 505 NULL 506 } 507 }; 508 509 const struct pciide_product_desc pciide_acard_products[] = { 510 { PCI_PRODUCT_ACARD_ATP850U, 511 IDE_PCI_CLASS_OVERRIDE, 512 "Acard ATP850U Ultra33 IDE Controller", 513 acard_chip_map, 514 }, 515 { PCI_PRODUCT_ACARD_ATP860, 516 IDE_PCI_CLASS_OVERRIDE, 517 "Acard ATP860 Ultra66 IDE Controller", 518 acard_chip_map, 519 }, 520 { PCI_PRODUCT_ACARD_ATP860A, 521 IDE_PCI_CLASS_OVERRIDE, 522 "Acard ATP860-A Ultra66 IDE Controller", 523 acard_chip_map, 524 }, 525 { 0, 526 0, 527 NULL, 528 NULL 529 } 530 }; 531 532 const struct pciide_product_desc pciide_serverworks_products[] = { 533 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 534 0, 535 "ServerWorks OSB4 IDE Controller", 536 serverworks_chip_map, 537 }, 538 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 539 0, 540 "ServerWorks CSB5 IDE Controller", 541 serverworks_chip_map, 542 }, 543 { 0, 544 0, 545 NULL, 546 } 547 }; 548 549 const struct pciide_product_desc pciide_symphony_products[] = { 550 { PCI_PRODUCT_SYMPHONY_82C105, 551 0, 552 "Symphony Labs 82C105 IDE controller", 553 sl82c105_chip_map, 554 }, 555 { 0, 556 0, 557 NULL, 558 } 559 }; 560 561 const struct pciide_product_desc pciide_winbond_products[] = { 562 { PCI_PRODUCT_WINBOND_W83C553F_1, 563 0, 564 "Winbond W83C553F IDE controller", 565 sl82c105_chip_map, 566 }, 567 { 0, 568 0, 569 NULL, 570 } 571 }; 572 573 struct pciide_vendor_desc { 574 u_int32_t ide_vendor; 575 const struct pciide_product_desc *ide_products; 576 }; 577 578 const struct pciide_vendor_desc pciide_vendors[] = { 579 { PCI_VENDOR_INTEL, pciide_intel_products }, 580 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 581 { PCI_VENDOR_VIATECH, pciide_via_products }, 582 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 583 { PCI_VENDOR_SIS, pciide_sis_products }, 584 { PCI_VENDOR_ALI, pciide_acer_products }, 585 { PCI_VENDOR_PROMISE, pciide_promise_products }, 586 { PCI_VENDOR_AMD, pciide_amd_products }, 587 { PCI_VENDOR_OPTI, pciide_opti_products }, 588 { PCI_VENDOR_TRIONES, pciide_triones_products }, 589 { PCI_VENDOR_ACARD, pciide_acard_products }, 590 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 591 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 592 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 593 { 0, NULL } 594 }; 595 596 /* options passed via the 'flags' config keyword */ 597 #define PCIIDE_OPTIONS_DMA 0x01 598 #define PCIIDE_OPTIONS_NODMA 0x02 599 600 int pciide_match __P((struct device *, struct cfdata *, void *)); 601 void pciide_attach __P((struct device *, struct device *, void *)); 602 603 struct cfattach pciide_ca = { 604 sizeof(struct pciide_softc), pciide_match, pciide_attach 605 }; 606 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 607 int pciide_mapregs_compat __P(( struct pci_attach_args *, 608 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 609 int pciide_mapregs_native __P((struct pci_attach_args *, 610 struct pciide_channel *, bus_size_t *, bus_size_t *, 611 int (*pci_intr) __P((void *)))); 612 void pciide_mapreg_dma __P((struct pciide_softc *, 613 struct pci_attach_args *)); 614 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 615 void pciide_mapchan __P((struct pci_attach_args *, 616 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 617 int (*pci_intr) __P((void *)))); 618 int pciide_chan_candisable __P((struct pciide_channel *)); 619 void pciide_map_compat_intr __P(( struct pci_attach_args *, 620 struct pciide_channel *, int, int)); 621 int pciide_compat_intr __P((void *)); 622 int pciide_pci_intr __P((void *)); 623 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 624 625 const struct pciide_product_desc * 626 pciide_lookup_product(id) 627 u_int32_t id; 628 { 629 const struct pciide_product_desc *pp; 630 const struct pciide_vendor_desc *vp; 631 632 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 633 if (PCI_VENDOR(id) == vp->ide_vendor) 634 break; 635 636 if ((pp = vp->ide_products) == NULL) 637 return NULL; 638 639 for (; pp->chip_map != NULL; pp++) 640 if (PCI_PRODUCT(id) == pp->ide_product) 641 break; 642 643 if (pp->chip_map == NULL) 644 return NULL; 645 return pp; 646 } 647 648 int 649 pciide_match(parent, match, aux) 650 struct device *parent; 651 struct cfdata *match; 652 void *aux; 653 { 654 struct pci_attach_args *pa = aux; 655 const struct pciide_product_desc *pp; 656 657 /* 658 * Check the ID register to see that it's a PCI IDE controller. 659 * If it is, we assume that we can deal with it; it _should_ 660 * work in a standardized way... 661 */ 662 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 663 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 664 return (1); 665 } 666 667 /* 668 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 669 * controllers. Let see if we can deal with it anyway. 670 */ 671 pp = pciide_lookup_product(pa->pa_id); 672 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 673 return (1); 674 } 675 676 return (0); 677 } 678 679 void 680 pciide_attach(parent, self, aux) 681 struct device *parent, *self; 682 void *aux; 683 { 684 struct pci_attach_args *pa = aux; 685 pci_chipset_tag_t pc = pa->pa_pc; 686 pcitag_t tag = pa->pa_tag; 687 struct pciide_softc *sc = (struct pciide_softc *)self; 688 pcireg_t csr; 689 char devinfo[256]; 690 const char *displaydev; 691 692 sc->sc_pp = pciide_lookup_product(pa->pa_id); 693 if (sc->sc_pp == NULL) { 694 sc->sc_pp = &default_product_desc; 695 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 696 displaydev = devinfo; 697 } else 698 displaydev = sc->sc_pp->ide_name; 699 700 /* if displaydev == NULL, printf is done in chip-specific map */ 701 if (displaydev) 702 printf(": %s (rev. 0x%02x)\n", displaydev, 703 PCI_REVISION(pa->pa_class)); 704 705 sc->sc_pc = pa->pa_pc; 706 sc->sc_tag = pa->pa_tag; 707 #ifdef WDCDEBUG 708 if (wdcdebug_pciide_mask & DEBUG_PROBE) 709 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 710 #endif 711 sc->sc_pp->chip_map(sc, pa); 712 713 if (sc->sc_dma_ok) { 714 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 715 csr |= PCI_COMMAND_MASTER_ENABLE; 716 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 717 } 718 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 719 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 720 } 721 722 /* tell wether the chip is enabled or not */ 723 int 724 pciide_chipen(sc, pa) 725 struct pciide_softc *sc; 726 struct pci_attach_args *pa; 727 { 728 pcireg_t csr; 729 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 730 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 731 PCI_COMMAND_STATUS_REG); 732 printf("%s: device disabled (at %s)\n", 733 sc->sc_wdcdev.sc_dev.dv_xname, 734 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 735 "device" : "bridge"); 736 return 0; 737 } 738 return 1; 739 } 740 741 int 742 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 743 struct pci_attach_args *pa; 744 struct pciide_channel *cp; 745 int compatchan; 746 bus_size_t *cmdsizep, *ctlsizep; 747 { 748 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 749 struct channel_softc *wdc_cp = &cp->wdc_channel; 750 751 cp->compat = 1; 752 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 753 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 754 755 wdc_cp->cmd_iot = pa->pa_iot; 756 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 757 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 758 printf("%s: couldn't map %s channel cmd regs\n", 759 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 760 return (0); 761 } 762 763 wdc_cp->ctl_iot = pa->pa_iot; 764 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 765 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 766 printf("%s: couldn't map %s channel ctl regs\n", 767 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 768 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 769 PCIIDE_COMPAT_CMD_SIZE); 770 return (0); 771 } 772 773 return (1); 774 } 775 776 int 777 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 778 struct pci_attach_args * pa; 779 struct pciide_channel *cp; 780 bus_size_t *cmdsizep, *ctlsizep; 781 int (*pci_intr) __P((void *)); 782 { 783 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 784 struct channel_softc *wdc_cp = &cp->wdc_channel; 785 const char *intrstr; 786 pci_intr_handle_t intrhandle; 787 788 cp->compat = 0; 789 790 if (sc->sc_pci_ih == NULL) { 791 if (pci_intr_map(pa, &intrhandle) != 0) { 792 printf("%s: couldn't map native-PCI interrupt\n", 793 sc->sc_wdcdev.sc_dev.dv_xname); 794 return 0; 795 } 796 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 797 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 798 intrhandle, IPL_BIO, pci_intr, sc); 799 if (sc->sc_pci_ih != NULL) { 800 printf("%s: using %s for native-PCI interrupt\n", 801 sc->sc_wdcdev.sc_dev.dv_xname, 802 intrstr ? intrstr : "unknown interrupt"); 803 } else { 804 printf("%s: couldn't establish native-PCI interrupt", 805 sc->sc_wdcdev.sc_dev.dv_xname); 806 if (intrstr != NULL) 807 printf(" at %s", intrstr); 808 printf("\n"); 809 return 0; 810 } 811 } 812 cp->ih = sc->sc_pci_ih; 813 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 814 PCI_MAPREG_TYPE_IO, 0, 815 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 816 printf("%s: couldn't map %s channel cmd regs\n", 817 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 818 return 0; 819 } 820 821 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 822 PCI_MAPREG_TYPE_IO, 0, 823 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 824 printf("%s: couldn't map %s channel ctl regs\n", 825 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 826 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 827 return 0; 828 } 829 /* 830 * In native mode, 4 bytes of I/O space are mapped for the control 831 * register, the control register is at offset 2. Pass the generic 832 * code a handle for only one byte at the rigth offset. 833 */ 834 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 835 &wdc_cp->ctl_ioh) != 0) { 836 printf("%s: unable to subregion %s channel ctl regs\n", 837 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 838 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 839 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 840 return 0; 841 } 842 return (1); 843 } 844 845 void 846 pciide_mapreg_dma(sc, pa) 847 struct pciide_softc *sc; 848 struct pci_attach_args *pa; 849 { 850 pcireg_t maptype; 851 bus_addr_t addr; 852 853 /* 854 * Map DMA registers 855 * 856 * Note that sc_dma_ok is the right variable to test to see if 857 * DMA can be done. If the interface doesn't support DMA, 858 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 859 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 860 * non-zero if the interface supports DMA and the registers 861 * could be mapped. 862 * 863 * XXX Note that despite the fact that the Bus Master IDE specs 864 * XXX say that "The bus master IDE function uses 16 bytes of IO 865 * XXX space," some controllers (at least the United 866 * XXX Microelectronics UM8886BF) place it in memory space. 867 */ 868 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 869 PCIIDE_REG_BUS_MASTER_DMA); 870 871 switch (maptype) { 872 case PCI_MAPREG_TYPE_IO: 873 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 874 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 875 &addr, NULL, NULL) == 0); 876 if (sc->sc_dma_ok == 0) { 877 printf(", but unused (couldn't query registers)"); 878 break; 879 } 880 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 881 && addr >= 0x10000) { 882 sc->sc_dma_ok = 0; 883 printf(", but unused (registers at unsafe address " 884 "%#lx)", (unsigned long)addr); 885 break; 886 } 887 /* FALLTHROUGH */ 888 889 case PCI_MAPREG_MEM_TYPE_32BIT: 890 sc->sc_dma_ok = (pci_mapreg_map(pa, 891 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 892 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 893 sc->sc_dmat = pa->pa_dmat; 894 if (sc->sc_dma_ok == 0) { 895 printf(", but unused (couldn't map registers)"); 896 } else { 897 sc->sc_wdcdev.dma_arg = sc; 898 sc->sc_wdcdev.dma_init = pciide_dma_init; 899 sc->sc_wdcdev.dma_start = pciide_dma_start; 900 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 901 } 902 903 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 904 PCIIDE_OPTIONS_NODMA) { 905 printf(", but unused (forced off by config file)"); 906 sc->sc_dma_ok = 0; 907 } 908 break; 909 910 default: 911 sc->sc_dma_ok = 0; 912 printf(", but unsupported register maptype (0x%x)", maptype); 913 } 914 } 915 916 int 917 pciide_compat_intr(arg) 918 void *arg; 919 { 920 struct pciide_channel *cp = arg; 921 922 #ifdef DIAGNOSTIC 923 /* should only be called for a compat channel */ 924 if (cp->compat == 0) 925 panic("pciide compat intr called for non-compat chan %p\n", cp); 926 #endif 927 return (wdcintr(&cp->wdc_channel)); 928 } 929 930 int 931 pciide_pci_intr(arg) 932 void *arg; 933 { 934 struct pciide_softc *sc = arg; 935 struct pciide_channel *cp; 936 struct channel_softc *wdc_cp; 937 int i, rv, crv; 938 939 rv = 0; 940 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 941 cp = &sc->pciide_channels[i]; 942 wdc_cp = &cp->wdc_channel; 943 944 /* If a compat channel skip. */ 945 if (cp->compat) 946 continue; 947 /* if this channel not waiting for intr, skip */ 948 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 949 continue; 950 951 crv = wdcintr(wdc_cp); 952 if (crv == 0) 953 ; /* leave rv alone */ 954 else if (crv == 1) 955 rv = 1; /* claim the intr */ 956 else if (rv == 0) /* crv should be -1 in this case */ 957 rv = crv; /* if we've done no better, take it */ 958 } 959 return (rv); 960 } 961 962 void 963 pciide_channel_dma_setup(cp) 964 struct pciide_channel *cp; 965 { 966 int drive; 967 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 968 struct ata_drive_datas *drvp; 969 970 for (drive = 0; drive < 2; drive++) { 971 drvp = &cp->wdc_channel.ch_drive[drive]; 972 /* If no drive, skip */ 973 if ((drvp->drive_flags & DRIVE) == 0) 974 continue; 975 /* setup DMA if needed */ 976 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 977 (drvp->drive_flags & DRIVE_UDMA) == 0) || 978 sc->sc_dma_ok == 0) { 979 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 980 continue; 981 } 982 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 983 != 0) { 984 /* Abort DMA setup */ 985 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 986 continue; 987 } 988 } 989 } 990 991 int 992 pciide_dma_table_setup(sc, channel, drive) 993 struct pciide_softc *sc; 994 int channel, drive; 995 { 996 bus_dma_segment_t seg; 997 int error, rseg; 998 const bus_size_t dma_table_size = 999 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1000 struct pciide_dma_maps *dma_maps = 1001 &sc->pciide_channels[channel].dma_maps[drive]; 1002 1003 /* If table was already allocated, just return */ 1004 if (dma_maps->dma_table) 1005 return 0; 1006 1007 /* Allocate memory for the DMA tables and map it */ 1008 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1009 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1010 BUS_DMA_NOWAIT)) != 0) { 1011 printf("%s:%d: unable to allocate table DMA for " 1012 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1013 channel, drive, error); 1014 return error; 1015 } 1016 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1017 dma_table_size, 1018 (caddr_t *)&dma_maps->dma_table, 1019 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1020 printf("%s:%d: unable to map table DMA for" 1021 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1022 channel, drive, error); 1023 return error; 1024 } 1025 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1026 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1027 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1028 1029 /* Create and load table DMA map for this disk */ 1030 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1031 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1032 &dma_maps->dmamap_table)) != 0) { 1033 printf("%s:%d: unable to create table DMA map for " 1034 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1035 channel, drive, error); 1036 return error; 1037 } 1038 if ((error = bus_dmamap_load(sc->sc_dmat, 1039 dma_maps->dmamap_table, 1040 dma_maps->dma_table, 1041 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1042 printf("%s:%d: unable to load table DMA map for " 1043 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1044 channel, drive, error); 1045 return error; 1046 } 1047 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1048 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1049 DEBUG_PROBE); 1050 /* Create a xfer DMA map for this drive */ 1051 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1052 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1053 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1054 &dma_maps->dmamap_xfer)) != 0) { 1055 printf("%s:%d: unable to create xfer DMA map for " 1056 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1057 channel, drive, error); 1058 return error; 1059 } 1060 return 0; 1061 } 1062 1063 int 1064 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1065 void *v; 1066 int channel, drive; 1067 void *databuf; 1068 size_t datalen; 1069 int flags; 1070 { 1071 struct pciide_softc *sc = v; 1072 int error, seg; 1073 struct pciide_dma_maps *dma_maps = 1074 &sc->pciide_channels[channel].dma_maps[drive]; 1075 1076 error = bus_dmamap_load(sc->sc_dmat, 1077 dma_maps->dmamap_xfer, 1078 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1079 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1080 if (error) { 1081 printf("%s:%d: unable to load xfer DMA map for" 1082 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1083 channel, drive, error); 1084 return error; 1085 } 1086 1087 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1088 dma_maps->dmamap_xfer->dm_mapsize, 1089 (flags & WDC_DMA_READ) ? 1090 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1091 1092 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1093 #ifdef DIAGNOSTIC 1094 /* A segment must not cross a 64k boundary */ 1095 { 1096 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1097 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1098 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1099 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1100 printf("pciide_dma: segment %d physical addr 0x%lx" 1101 " len 0x%lx not properly aligned\n", 1102 seg, phys, len); 1103 panic("pciide_dma: buf align"); 1104 } 1105 } 1106 #endif 1107 dma_maps->dma_table[seg].base_addr = 1108 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1109 dma_maps->dma_table[seg].byte_count = 1110 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1111 IDEDMA_BYTE_COUNT_MASK); 1112 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1113 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1114 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1115 1116 } 1117 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1118 htole32(IDEDMA_BYTE_COUNT_EOT); 1119 1120 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1121 dma_maps->dmamap_table->dm_mapsize, 1122 BUS_DMASYNC_PREWRITE); 1123 1124 /* Maps are ready. Start DMA function */ 1125 #ifdef DIAGNOSTIC 1126 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1127 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1128 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1129 panic("pciide_dma_init: table align"); 1130 } 1131 #endif 1132 1133 /* Clear status bits */ 1134 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1135 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1136 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1137 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1138 /* Write table addr */ 1139 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1140 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1141 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1142 /* set read/write */ 1143 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1144 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1145 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1146 /* remember flags */ 1147 dma_maps->dma_flags = flags; 1148 return 0; 1149 } 1150 1151 void 1152 pciide_dma_start(v, channel, drive) 1153 void *v; 1154 int channel, drive; 1155 { 1156 struct pciide_softc *sc = v; 1157 1158 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1159 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1160 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1161 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1162 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1163 } 1164 1165 int 1166 pciide_dma_finish(v, channel, drive, force) 1167 void *v; 1168 int channel, drive; 1169 int force; 1170 { 1171 struct pciide_softc *sc = v; 1172 u_int8_t status; 1173 int error = 0; 1174 struct pciide_dma_maps *dma_maps = 1175 &sc->pciide_channels[channel].dma_maps[drive]; 1176 1177 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1178 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1179 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1180 DEBUG_XFERS); 1181 1182 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1183 return WDC_DMAST_NOIRQ; 1184 1185 /* stop DMA channel */ 1186 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1187 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1188 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1189 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1190 1191 /* Unload the map of the data buffer */ 1192 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1193 dma_maps->dmamap_xfer->dm_mapsize, 1194 (dma_maps->dma_flags & WDC_DMA_READ) ? 1195 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1196 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1197 1198 if ((status & IDEDMA_CTL_ERR) != 0) { 1199 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1200 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1201 error |= WDC_DMAST_ERR; 1202 } 1203 1204 if ((status & IDEDMA_CTL_INTR) == 0) { 1205 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1206 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1207 drive, status); 1208 error |= WDC_DMAST_NOIRQ; 1209 } 1210 1211 if ((status & IDEDMA_CTL_ACT) != 0) { 1212 /* data underrun, may be a valid condition for ATAPI */ 1213 error |= WDC_DMAST_UNDER; 1214 } 1215 return error; 1216 } 1217 1218 void 1219 pciide_irqack(chp) 1220 struct channel_softc *chp; 1221 { 1222 struct pciide_channel *cp = (struct pciide_channel*)chp; 1223 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1224 1225 /* clear status bits in IDE DMA registers */ 1226 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1227 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1228 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1229 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1230 } 1231 1232 /* some common code used by several chip_map */ 1233 int 1234 pciide_chansetup(sc, channel, interface) 1235 struct pciide_softc *sc; 1236 int channel; 1237 pcireg_t interface; 1238 { 1239 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1240 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1241 cp->name = PCIIDE_CHANNEL_NAME(channel); 1242 cp->wdc_channel.channel = channel; 1243 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1244 cp->wdc_channel.ch_queue = 1245 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1246 if (cp->wdc_channel.ch_queue == NULL) { 1247 printf("%s %s channel: " 1248 "can't allocate memory for command queue", 1249 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1250 return 0; 1251 } 1252 printf("%s: %s channel %s to %s mode\n", 1253 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1254 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1255 "configured" : "wired", 1256 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1257 "native-PCI" : "compatibility"); 1258 return 1; 1259 } 1260 1261 /* some common code used by several chip channel_map */ 1262 void 1263 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1264 struct pci_attach_args *pa; 1265 struct pciide_channel *cp; 1266 pcireg_t interface; 1267 bus_size_t *cmdsizep, *ctlsizep; 1268 int (*pci_intr) __P((void *)); 1269 { 1270 struct channel_softc *wdc_cp = &cp->wdc_channel; 1271 1272 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1273 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1274 pci_intr); 1275 else 1276 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1277 wdc_cp->channel, cmdsizep, ctlsizep); 1278 1279 if (cp->hw_ok == 0) 1280 return; 1281 wdc_cp->data32iot = wdc_cp->cmd_iot; 1282 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1283 wdcattach(wdc_cp); 1284 } 1285 1286 /* 1287 * Generic code to call to know if a channel can be disabled. Return 1 1288 * if channel can be disabled, 0 if not 1289 */ 1290 int 1291 pciide_chan_candisable(cp) 1292 struct pciide_channel *cp; 1293 { 1294 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1295 struct channel_softc *wdc_cp = &cp->wdc_channel; 1296 1297 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1298 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1299 printf("%s: disabling %s channel (no drives)\n", 1300 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1301 cp->hw_ok = 0; 1302 return 1; 1303 } 1304 return 0; 1305 } 1306 1307 /* 1308 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1309 * Set hw_ok=0 on failure 1310 */ 1311 void 1312 pciide_map_compat_intr(pa, cp, compatchan, interface) 1313 struct pci_attach_args *pa; 1314 struct pciide_channel *cp; 1315 int compatchan, interface; 1316 { 1317 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1318 struct channel_softc *wdc_cp = &cp->wdc_channel; 1319 1320 if (cp->hw_ok == 0) 1321 return; 1322 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1323 return; 1324 1325 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1326 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1327 pa, compatchan, pciide_compat_intr, cp); 1328 if (cp->ih == NULL) { 1329 #endif 1330 printf("%s: no compatibility interrupt for use by %s " 1331 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1332 cp->hw_ok = 0; 1333 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1334 } 1335 #endif 1336 } 1337 1338 void 1339 pciide_print_modes(cp) 1340 struct pciide_channel *cp; 1341 { 1342 wdc_print_modes(&cp->wdc_channel); 1343 } 1344 1345 void 1346 default_chip_map(sc, pa) 1347 struct pciide_softc *sc; 1348 struct pci_attach_args *pa; 1349 { 1350 struct pciide_channel *cp; 1351 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1352 pcireg_t csr; 1353 int channel, drive; 1354 struct ata_drive_datas *drvp; 1355 u_int8_t idedma_ctl; 1356 bus_size_t cmdsize, ctlsize; 1357 char *failreason; 1358 1359 if (pciide_chipen(sc, pa) == 0) 1360 return; 1361 1362 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1363 printf("%s: bus-master DMA support present", 1364 sc->sc_wdcdev.sc_dev.dv_xname); 1365 if (sc->sc_pp == &default_product_desc && 1366 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1367 PCIIDE_OPTIONS_DMA) == 0) { 1368 printf(", but unused (no driver support)"); 1369 sc->sc_dma_ok = 0; 1370 } else { 1371 pciide_mapreg_dma(sc, pa); 1372 if (sc->sc_dma_ok != 0) 1373 printf(", used without full driver " 1374 "support"); 1375 } 1376 } else { 1377 printf("%s: hardware does not support DMA", 1378 sc->sc_wdcdev.sc_dev.dv_xname); 1379 sc->sc_dma_ok = 0; 1380 } 1381 printf("\n"); 1382 if (sc->sc_dma_ok) { 1383 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1384 sc->sc_wdcdev.irqack = pciide_irqack; 1385 } 1386 sc->sc_wdcdev.PIO_cap = 0; 1387 sc->sc_wdcdev.DMA_cap = 0; 1388 1389 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1390 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1391 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1392 1393 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1394 cp = &sc->pciide_channels[channel]; 1395 if (pciide_chansetup(sc, channel, interface) == 0) 1396 continue; 1397 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1398 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1399 &ctlsize, pciide_pci_intr); 1400 } else { 1401 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1402 channel, &cmdsize, &ctlsize); 1403 } 1404 if (cp->hw_ok == 0) 1405 continue; 1406 /* 1407 * Check to see if something appears to be there. 1408 */ 1409 failreason = NULL; 1410 if (!wdcprobe(&cp->wdc_channel)) { 1411 failreason = "not responding; disabled or no drives?"; 1412 goto next; 1413 } 1414 /* 1415 * Now, make sure it's actually attributable to this PCI IDE 1416 * channel by trying to access the channel again while the 1417 * PCI IDE controller's I/O space is disabled. (If the 1418 * channel no longer appears to be there, it belongs to 1419 * this controller.) YUCK! 1420 */ 1421 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1422 PCI_COMMAND_STATUS_REG); 1423 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1424 csr & ~PCI_COMMAND_IO_ENABLE); 1425 if (wdcprobe(&cp->wdc_channel)) 1426 failreason = "other hardware responding at addresses"; 1427 pci_conf_write(sc->sc_pc, sc->sc_tag, 1428 PCI_COMMAND_STATUS_REG, csr); 1429 next: 1430 if (failreason) { 1431 printf("%s: %s channel ignored (%s)\n", 1432 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1433 failreason); 1434 cp->hw_ok = 0; 1435 bus_space_unmap(cp->wdc_channel.cmd_iot, 1436 cp->wdc_channel.cmd_ioh, cmdsize); 1437 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1438 bus_space_unmap(cp->wdc_channel.ctl_iot, 1439 cp->ctl_baseioh, ctlsize); 1440 else 1441 bus_space_unmap(cp->wdc_channel.ctl_iot, 1442 cp->wdc_channel.ctl_ioh, ctlsize); 1443 } else { 1444 pciide_map_compat_intr(pa, cp, channel, interface); 1445 } 1446 if (cp->hw_ok) { 1447 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1448 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1449 wdcattach(&cp->wdc_channel); 1450 } 1451 } 1452 1453 if (sc->sc_dma_ok == 0) 1454 return; 1455 1456 /* Allocate DMA maps */ 1457 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1458 idedma_ctl = 0; 1459 cp = &sc->pciide_channels[channel]; 1460 for (drive = 0; drive < 2; drive++) { 1461 drvp = &cp->wdc_channel.ch_drive[drive]; 1462 /* If no drive, skip */ 1463 if ((drvp->drive_flags & DRIVE) == 0) 1464 continue; 1465 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1466 continue; 1467 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1468 /* Abort DMA setup */ 1469 printf("%s:%d:%d: can't allocate DMA maps, " 1470 "using PIO transfers\n", 1471 sc->sc_wdcdev.sc_dev.dv_xname, 1472 channel, drive); 1473 drvp->drive_flags &= ~DRIVE_DMA; 1474 } 1475 printf("%s:%d:%d: using DMA data transfers\n", 1476 sc->sc_wdcdev.sc_dev.dv_xname, 1477 channel, drive); 1478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1479 } 1480 if (idedma_ctl != 0) { 1481 /* Add software bits in status register */ 1482 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1483 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1484 idedma_ctl); 1485 } 1486 } 1487 } 1488 1489 void 1490 piix_chip_map(sc, pa) 1491 struct pciide_softc *sc; 1492 struct pci_attach_args *pa; 1493 { 1494 struct pciide_channel *cp; 1495 int channel; 1496 u_int32_t idetim; 1497 bus_size_t cmdsize, ctlsize; 1498 1499 if (pciide_chipen(sc, pa) == 0) 1500 return; 1501 1502 printf("%s: bus-master DMA support present", 1503 sc->sc_wdcdev.sc_dev.dv_xname); 1504 pciide_mapreg_dma(sc, pa); 1505 printf("\n"); 1506 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1507 WDC_CAPABILITY_MODE; 1508 if (sc->sc_dma_ok) { 1509 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1510 sc->sc_wdcdev.irqack = pciide_irqack; 1511 switch(sc->sc_pp->ide_product) { 1512 case PCI_PRODUCT_INTEL_82371AB_IDE: 1513 case PCI_PRODUCT_INTEL_82440MX_IDE: 1514 case PCI_PRODUCT_INTEL_82801AA_IDE: 1515 case PCI_PRODUCT_INTEL_82801AB_IDE: 1516 case PCI_PRODUCT_INTEL_82801BA_IDE: 1517 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1518 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1519 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1520 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1521 } 1522 } 1523 sc->sc_wdcdev.PIO_cap = 4; 1524 sc->sc_wdcdev.DMA_cap = 2; 1525 switch(sc->sc_pp->ide_product) { 1526 case PCI_PRODUCT_INTEL_82801AA_IDE: 1527 sc->sc_wdcdev.UDMA_cap = 4; 1528 break; 1529 case PCI_PRODUCT_INTEL_82801BA_IDE: 1530 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1531 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1532 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1533 sc->sc_wdcdev.UDMA_cap = 5; 1534 break; 1535 default: 1536 sc->sc_wdcdev.UDMA_cap = 2; 1537 } 1538 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1539 sc->sc_wdcdev.set_modes = piix_setup_channel; 1540 else 1541 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1542 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1543 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1544 1545 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1546 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1547 DEBUG_PROBE); 1548 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1549 WDCDEBUG_PRINT((", sidetim=0x%x", 1550 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1551 DEBUG_PROBE); 1552 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1553 WDCDEBUG_PRINT((", udamreg 0x%x", 1554 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1555 DEBUG_PROBE); 1556 } 1557 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1558 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1559 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1560 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1561 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1563 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1564 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1565 DEBUG_PROBE); 1566 } 1567 1568 } 1569 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1570 1571 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1572 cp = &sc->pciide_channels[channel]; 1573 /* PIIX is compat-only */ 1574 if (pciide_chansetup(sc, channel, 0) == 0) 1575 continue; 1576 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1577 if ((PIIX_IDETIM_READ(idetim, channel) & 1578 PIIX_IDETIM_IDE) == 0) { 1579 printf("%s: %s channel ignored (disabled)\n", 1580 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1581 continue; 1582 } 1583 /* PIIX are compat-only pciide devices */ 1584 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1585 if (cp->hw_ok == 0) 1586 continue; 1587 if (pciide_chan_candisable(cp)) { 1588 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1589 channel); 1590 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1591 idetim); 1592 } 1593 pciide_map_compat_intr(pa, cp, channel, 0); 1594 if (cp->hw_ok == 0) 1595 continue; 1596 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1597 } 1598 1599 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1600 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1601 DEBUG_PROBE); 1602 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1603 WDCDEBUG_PRINT((", sidetim=0x%x", 1604 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1605 DEBUG_PROBE); 1606 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1607 WDCDEBUG_PRINT((", udamreg 0x%x", 1608 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1609 DEBUG_PROBE); 1610 } 1611 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1612 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1613 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1614 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1617 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1618 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1619 DEBUG_PROBE); 1620 } 1621 } 1622 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1623 } 1624 1625 void 1626 piix_setup_channel(chp) 1627 struct channel_softc *chp; 1628 { 1629 u_int8_t mode[2], drive; 1630 u_int32_t oidetim, idetim, idedma_ctl; 1631 struct pciide_channel *cp = (struct pciide_channel*)chp; 1632 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1633 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1634 1635 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1636 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1637 idedma_ctl = 0; 1638 1639 /* set up new idetim: Enable IDE registers decode */ 1640 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1641 chp->channel); 1642 1643 /* setup DMA */ 1644 pciide_channel_dma_setup(cp); 1645 1646 /* 1647 * Here we have to mess up with drives mode: PIIX can't have 1648 * different timings for master and slave drives. 1649 * We need to find the best combination. 1650 */ 1651 1652 /* If both drives supports DMA, take the lower mode */ 1653 if ((drvp[0].drive_flags & DRIVE_DMA) && 1654 (drvp[1].drive_flags & DRIVE_DMA)) { 1655 mode[0] = mode[1] = 1656 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1657 drvp[0].DMA_mode = mode[0]; 1658 drvp[1].DMA_mode = mode[1]; 1659 goto ok; 1660 } 1661 /* 1662 * If only one drive supports DMA, use its mode, and 1663 * put the other one in PIO mode 0 if mode not compatible 1664 */ 1665 if (drvp[0].drive_flags & DRIVE_DMA) { 1666 mode[0] = drvp[0].DMA_mode; 1667 mode[1] = drvp[1].PIO_mode; 1668 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1669 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1670 mode[1] = drvp[1].PIO_mode = 0; 1671 goto ok; 1672 } 1673 if (drvp[1].drive_flags & DRIVE_DMA) { 1674 mode[1] = drvp[1].DMA_mode; 1675 mode[0] = drvp[0].PIO_mode; 1676 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1677 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1678 mode[0] = drvp[0].PIO_mode = 0; 1679 goto ok; 1680 } 1681 /* 1682 * If both drives are not DMA, takes the lower mode, unless 1683 * one of them is PIO mode < 2 1684 */ 1685 if (drvp[0].PIO_mode < 2) { 1686 mode[0] = drvp[0].PIO_mode = 0; 1687 mode[1] = drvp[1].PIO_mode; 1688 } else if (drvp[1].PIO_mode < 2) { 1689 mode[1] = drvp[1].PIO_mode = 0; 1690 mode[0] = drvp[0].PIO_mode; 1691 } else { 1692 mode[0] = mode[1] = 1693 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1694 drvp[0].PIO_mode = mode[0]; 1695 drvp[1].PIO_mode = mode[1]; 1696 } 1697 ok: /* The modes are setup */ 1698 for (drive = 0; drive < 2; drive++) { 1699 if (drvp[drive].drive_flags & DRIVE_DMA) { 1700 idetim |= piix_setup_idetim_timings( 1701 mode[drive], 1, chp->channel); 1702 goto end; 1703 } 1704 } 1705 /* If we are there, none of the drives are DMA */ 1706 if (mode[0] >= 2) 1707 idetim |= piix_setup_idetim_timings( 1708 mode[0], 0, chp->channel); 1709 else 1710 idetim |= piix_setup_idetim_timings( 1711 mode[1], 0, chp->channel); 1712 end: /* 1713 * timing mode is now set up in the controller. Enable 1714 * it per-drive 1715 */ 1716 for (drive = 0; drive < 2; drive++) { 1717 /* If no drive, skip */ 1718 if ((drvp[drive].drive_flags & DRIVE) == 0) 1719 continue; 1720 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1721 if (drvp[drive].drive_flags & DRIVE_DMA) 1722 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1723 } 1724 if (idedma_ctl != 0) { 1725 /* Add software bits in status register */ 1726 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1727 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1728 idedma_ctl); 1729 } 1730 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1731 pciide_print_modes(cp); 1732 } 1733 1734 void 1735 piix3_4_setup_channel(chp) 1736 struct channel_softc *chp; 1737 { 1738 struct ata_drive_datas *drvp; 1739 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1740 struct pciide_channel *cp = (struct pciide_channel*)chp; 1741 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1742 int drive; 1743 int channel = chp->channel; 1744 1745 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1746 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1747 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1748 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1749 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1750 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1751 PIIX_SIDETIM_RTC_MASK(channel)); 1752 1753 idedma_ctl = 0; 1754 /* If channel disabled, no need to go further */ 1755 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1756 return; 1757 /* set up new idetim: Enable IDE registers decode */ 1758 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1759 1760 /* setup DMA if needed */ 1761 pciide_channel_dma_setup(cp); 1762 1763 for (drive = 0; drive < 2; drive++) { 1764 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1765 PIIX_UDMATIM_SET(0x3, channel, drive)); 1766 drvp = &chp->ch_drive[drive]; 1767 /* If no drive, skip */ 1768 if ((drvp->drive_flags & DRIVE) == 0) 1769 continue; 1770 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1771 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1772 goto pio; 1773 1774 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1775 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1776 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1777 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1778 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1779 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1780 ideconf |= PIIX_CONFIG_PINGPONG; 1781 } 1782 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1783 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1784 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1785 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1786 /* setup Ultra/100 */ 1787 if (drvp->UDMA_mode > 2 && 1788 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1789 drvp->UDMA_mode = 2; 1790 if (drvp->UDMA_mode > 4) { 1791 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1792 } else { 1793 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1794 if (drvp->UDMA_mode > 2) { 1795 ideconf |= PIIX_CONFIG_UDMA66(channel, 1796 drive); 1797 } else { 1798 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1799 drive); 1800 } 1801 } 1802 } 1803 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1804 /* setup Ultra/66 */ 1805 if (drvp->UDMA_mode > 2 && 1806 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1807 drvp->UDMA_mode = 2; 1808 if (drvp->UDMA_mode > 2) 1809 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1810 else 1811 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1812 } 1813 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1814 (drvp->drive_flags & DRIVE_UDMA)) { 1815 /* use Ultra/DMA */ 1816 drvp->drive_flags &= ~DRIVE_DMA; 1817 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1818 udmareg |= PIIX_UDMATIM_SET( 1819 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1820 } else { 1821 /* use Multiword DMA */ 1822 drvp->drive_flags &= ~DRIVE_UDMA; 1823 if (drive == 0) { 1824 idetim |= piix_setup_idetim_timings( 1825 drvp->DMA_mode, 1, channel); 1826 } else { 1827 sidetim |= piix_setup_sidetim_timings( 1828 drvp->DMA_mode, 1, channel); 1829 idetim =PIIX_IDETIM_SET(idetim, 1830 PIIX_IDETIM_SITRE, channel); 1831 } 1832 } 1833 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1834 1835 pio: /* use PIO mode */ 1836 idetim |= piix_setup_idetim_drvs(drvp); 1837 if (drive == 0) { 1838 idetim |= piix_setup_idetim_timings( 1839 drvp->PIO_mode, 0, channel); 1840 } else { 1841 sidetim |= piix_setup_sidetim_timings( 1842 drvp->PIO_mode, 0, channel); 1843 idetim =PIIX_IDETIM_SET(idetim, 1844 PIIX_IDETIM_SITRE, channel); 1845 } 1846 } 1847 if (idedma_ctl != 0) { 1848 /* Add software bits in status register */ 1849 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1850 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1851 idedma_ctl); 1852 } 1853 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1854 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1855 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1856 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1857 pciide_print_modes(cp); 1858 } 1859 1860 1861 /* setup ISP and RTC fields, based on mode */ 1862 static u_int32_t 1863 piix_setup_idetim_timings(mode, dma, channel) 1864 u_int8_t mode; 1865 u_int8_t dma; 1866 u_int8_t channel; 1867 { 1868 1869 if (dma) 1870 return PIIX_IDETIM_SET(0, 1871 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1872 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1873 channel); 1874 else 1875 return PIIX_IDETIM_SET(0, 1876 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1877 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1878 channel); 1879 } 1880 1881 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1882 static u_int32_t 1883 piix_setup_idetim_drvs(drvp) 1884 struct ata_drive_datas *drvp; 1885 { 1886 u_int32_t ret = 0; 1887 struct channel_softc *chp = drvp->chnl_softc; 1888 u_int8_t channel = chp->channel; 1889 u_int8_t drive = drvp->drive; 1890 1891 /* 1892 * If drive is using UDMA, timings setups are independant 1893 * So just check DMA and PIO here. 1894 */ 1895 if (drvp->drive_flags & DRIVE_DMA) { 1896 /* if mode = DMA mode 0, use compatible timings */ 1897 if ((drvp->drive_flags & DRIVE_DMA) && 1898 drvp->DMA_mode == 0) { 1899 drvp->PIO_mode = 0; 1900 return ret; 1901 } 1902 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1903 /* 1904 * PIO and DMA timings are the same, use fast timings for PIO 1905 * too, else use compat timings. 1906 */ 1907 if ((piix_isp_pio[drvp->PIO_mode] != 1908 piix_isp_dma[drvp->DMA_mode]) || 1909 (piix_rtc_pio[drvp->PIO_mode] != 1910 piix_rtc_dma[drvp->DMA_mode])) 1911 drvp->PIO_mode = 0; 1912 /* if PIO mode <= 2, use compat timings for PIO */ 1913 if (drvp->PIO_mode <= 2) { 1914 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1915 channel); 1916 return ret; 1917 } 1918 } 1919 1920 /* 1921 * Now setup PIO modes. If mode < 2, use compat timings. 1922 * Else enable fast timings. Enable IORDY and prefetch/post 1923 * if PIO mode >= 3. 1924 */ 1925 1926 if (drvp->PIO_mode < 2) 1927 return ret; 1928 1929 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1930 if (drvp->PIO_mode >= 3) { 1931 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1932 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1933 } 1934 return ret; 1935 } 1936 1937 /* setup values in SIDETIM registers, based on mode */ 1938 static u_int32_t 1939 piix_setup_sidetim_timings(mode, dma, channel) 1940 u_int8_t mode; 1941 u_int8_t dma; 1942 u_int8_t channel; 1943 { 1944 if (dma) 1945 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1946 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1947 else 1948 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1949 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1950 } 1951 1952 void 1953 amd7x6_chip_map(sc, pa) 1954 struct pciide_softc *sc; 1955 struct pci_attach_args *pa; 1956 { 1957 struct pciide_channel *cp; 1958 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1959 int channel; 1960 pcireg_t chanenable; 1961 bus_size_t cmdsize, ctlsize; 1962 1963 if (pciide_chipen(sc, pa) == 0) 1964 return; 1965 printf("%s: bus-master DMA support present", 1966 sc->sc_wdcdev.sc_dev.dv_xname); 1967 pciide_mapreg_dma(sc, pa); 1968 printf("\n"); 1969 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1970 WDC_CAPABILITY_MODE; 1971 if (sc->sc_dma_ok) { 1972 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1973 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1974 sc->sc_wdcdev.irqack = pciide_irqack; 1975 } 1976 sc->sc_wdcdev.PIO_cap = 4; 1977 sc->sc_wdcdev.DMA_cap = 2; 1978 1979 switch (sc->sc_pp->ide_product) { 1980 case PCI_PRODUCT_AMD_PBC766_IDE: 1981 case PCI_PRODUCT_AMD_PBC768_IDE: 1982 case PCI_PRODUCT_AMD_PBC8111_IDE: 1983 sc->sc_wdcdev.UDMA_cap = 5; 1984 break; 1985 default: 1986 sc->sc_wdcdev.UDMA_cap = 4; 1987 } 1988 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1989 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1990 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1991 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1992 1993 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1994 DEBUG_PROBE); 1995 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1996 cp = &sc->pciide_channels[channel]; 1997 if (pciide_chansetup(sc, channel, interface) == 0) 1998 continue; 1999 2000 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2001 printf("%s: %s channel ignored (disabled)\n", 2002 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2003 continue; 2004 } 2005 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2006 pciide_pci_intr); 2007 2008 if (pciide_chan_candisable(cp)) 2009 chanenable &= ~AMD7X6_CHAN_EN(channel); 2010 pciide_map_compat_intr(pa, cp, channel, interface); 2011 if (cp->hw_ok == 0) 2012 continue; 2013 2014 amd7x6_setup_channel(&cp->wdc_channel); 2015 } 2016 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2017 chanenable); 2018 return; 2019 } 2020 2021 void 2022 amd7x6_setup_channel(chp) 2023 struct channel_softc *chp; 2024 { 2025 u_int32_t udmatim_reg, datatim_reg; 2026 u_int8_t idedma_ctl; 2027 int mode, drive; 2028 struct ata_drive_datas *drvp; 2029 struct pciide_channel *cp = (struct pciide_channel*)chp; 2030 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2031 #ifndef PCIIDE_AMD756_ENABLEDMA 2032 int rev = PCI_REVISION( 2033 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2034 #endif 2035 2036 idedma_ctl = 0; 2037 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2038 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2039 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2040 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2041 2042 /* setup DMA if needed */ 2043 pciide_channel_dma_setup(cp); 2044 2045 for (drive = 0; drive < 2; drive++) { 2046 drvp = &chp->ch_drive[drive]; 2047 /* If no drive, skip */ 2048 if ((drvp->drive_flags & DRIVE) == 0) 2049 continue; 2050 /* add timing values, setup DMA if needed */ 2051 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2052 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2053 mode = drvp->PIO_mode; 2054 goto pio; 2055 } 2056 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2057 (drvp->drive_flags & DRIVE_UDMA)) { 2058 /* use Ultra/DMA */ 2059 drvp->drive_flags &= ~DRIVE_DMA; 2060 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2061 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2062 AMD7X6_UDMA_TIME(chp->channel, drive, 2063 amd7x6_udma_tim[drvp->UDMA_mode]); 2064 /* can use PIO timings, MW DMA unused */ 2065 mode = drvp->PIO_mode; 2066 } else { 2067 /* use Multiword DMA, but only if revision is OK */ 2068 drvp->drive_flags &= ~DRIVE_UDMA; 2069 #ifndef PCIIDE_AMD756_ENABLEDMA 2070 /* 2071 * The workaround doesn't seem to be necessary 2072 * with all drives, so it can be disabled by 2073 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2074 * triggered. 2075 */ 2076 if (sc->sc_pp->ide_product == 2077 PCI_PRODUCT_AMD_PBC756_IDE && 2078 AMD756_CHIPREV_DISABLEDMA(rev)) { 2079 printf("%s:%d:%d: multi-word DMA disabled due " 2080 "to chip revision\n", 2081 sc->sc_wdcdev.sc_dev.dv_xname, 2082 chp->channel, drive); 2083 mode = drvp->PIO_mode; 2084 drvp->drive_flags &= ~DRIVE_DMA; 2085 goto pio; 2086 } 2087 #endif 2088 /* mode = min(pio, dma+2) */ 2089 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2090 mode = drvp->PIO_mode; 2091 else 2092 mode = drvp->DMA_mode + 2; 2093 } 2094 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2095 2096 pio: /* setup PIO mode */ 2097 if (mode <= 2) { 2098 drvp->DMA_mode = 0; 2099 drvp->PIO_mode = 0; 2100 mode = 0; 2101 } else { 2102 drvp->PIO_mode = mode; 2103 drvp->DMA_mode = mode - 2; 2104 } 2105 datatim_reg |= 2106 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2107 amd7x6_pio_set[mode]) | 2108 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2109 amd7x6_pio_rec[mode]); 2110 } 2111 if (idedma_ctl != 0) { 2112 /* Add software bits in status register */ 2113 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2114 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2115 idedma_ctl); 2116 } 2117 pciide_print_modes(cp); 2118 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2119 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2120 } 2121 2122 void 2123 apollo_chip_map(sc, pa) 2124 struct pciide_softc *sc; 2125 struct pci_attach_args *pa; 2126 { 2127 struct pciide_channel *cp; 2128 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2129 int channel; 2130 u_int32_t ideconf; 2131 bus_size_t cmdsize, ctlsize; 2132 pcitag_t pcib_tag; 2133 pcireg_t pcib_id, pcib_class; 2134 2135 if (pciide_chipen(sc, pa) == 0) 2136 return; 2137 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2138 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2139 /* and read ID and rev of the ISA bridge */ 2140 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2141 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2142 printf(": VIA Technologies "); 2143 switch (PCI_PRODUCT(pcib_id)) { 2144 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2145 printf("VT82C586 (Apollo VP) "); 2146 if(PCI_REVISION(pcib_class) >= 0x02) { 2147 printf("ATA33 controller\n"); 2148 sc->sc_wdcdev.UDMA_cap = 2; 2149 } else { 2150 printf("controller\n"); 2151 sc->sc_wdcdev.UDMA_cap = 0; 2152 } 2153 break; 2154 case PCI_PRODUCT_VIATECH_VT82C596A: 2155 printf("VT82C596A (Apollo Pro) "); 2156 if (PCI_REVISION(pcib_class) >= 0x12) { 2157 printf("ATA66 controller\n"); 2158 sc->sc_wdcdev.UDMA_cap = 4; 2159 } else { 2160 printf("ATA33 controller\n"); 2161 sc->sc_wdcdev.UDMA_cap = 2; 2162 } 2163 break; 2164 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2165 printf("VT82C686A (Apollo KX133) "); 2166 if (PCI_REVISION(pcib_class) >= 0x40) { 2167 printf("ATA100 controller\n"); 2168 sc->sc_wdcdev.UDMA_cap = 5; 2169 } else { 2170 printf("ATA66 controller\n"); 2171 sc->sc_wdcdev.UDMA_cap = 4; 2172 } 2173 break; 2174 case PCI_PRODUCT_VIATECH_VT8231: 2175 printf("VT8231 ATA100 controller\n"); 2176 sc->sc_wdcdev.UDMA_cap = 5; 2177 break; 2178 case PCI_PRODUCT_VIATECH_VT8233: 2179 printf("VT8233 ATA100 controller\n"); 2180 sc->sc_wdcdev.UDMA_cap = 5; 2181 break; 2182 case PCI_PRODUCT_VIATECH_VT8233A: 2183 printf("VT8233A ATA100 controller\n"); 2184 sc->sc_wdcdev.UDMA_cap = 5; 2185 break; 2186 default: 2187 printf("unknown ATA controller\n"); 2188 sc->sc_wdcdev.UDMA_cap = 0; 2189 } 2190 2191 printf("%s: bus-master DMA support present", 2192 sc->sc_wdcdev.sc_dev.dv_xname); 2193 pciide_mapreg_dma(sc, pa); 2194 printf("\n"); 2195 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2196 WDC_CAPABILITY_MODE; 2197 if (sc->sc_dma_ok) { 2198 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2199 sc->sc_wdcdev.irqack = pciide_irqack; 2200 if (sc->sc_wdcdev.UDMA_cap > 0) 2201 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2202 } 2203 sc->sc_wdcdev.PIO_cap = 4; 2204 sc->sc_wdcdev.DMA_cap = 2; 2205 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2206 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2207 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2208 2209 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2210 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2211 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2212 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2213 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2214 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2215 DEBUG_PROBE); 2216 2217 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2218 cp = &sc->pciide_channels[channel]; 2219 if (pciide_chansetup(sc, channel, interface) == 0) 2220 continue; 2221 2222 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2223 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2224 printf("%s: %s channel ignored (disabled)\n", 2225 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2226 continue; 2227 } 2228 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2229 pciide_pci_intr); 2230 if (cp->hw_ok == 0) 2231 continue; 2232 if (pciide_chan_candisable(cp)) { 2233 ideconf &= ~APO_IDECONF_EN(channel); 2234 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2235 ideconf); 2236 } 2237 pciide_map_compat_intr(pa, cp, channel, interface); 2238 2239 if (cp->hw_ok == 0) 2240 continue; 2241 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2242 } 2243 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2244 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2245 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2246 } 2247 2248 void 2249 apollo_setup_channel(chp) 2250 struct channel_softc *chp; 2251 { 2252 u_int32_t udmatim_reg, datatim_reg; 2253 u_int8_t idedma_ctl; 2254 int mode, drive; 2255 struct ata_drive_datas *drvp; 2256 struct pciide_channel *cp = (struct pciide_channel*)chp; 2257 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2258 2259 idedma_ctl = 0; 2260 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2261 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2262 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2263 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2264 2265 /* setup DMA if needed */ 2266 pciide_channel_dma_setup(cp); 2267 2268 for (drive = 0; drive < 2; drive++) { 2269 drvp = &chp->ch_drive[drive]; 2270 /* If no drive, skip */ 2271 if ((drvp->drive_flags & DRIVE) == 0) 2272 continue; 2273 /* add timing values, setup DMA if needed */ 2274 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2275 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2276 mode = drvp->PIO_mode; 2277 goto pio; 2278 } 2279 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2280 (drvp->drive_flags & DRIVE_UDMA)) { 2281 /* use Ultra/DMA */ 2282 drvp->drive_flags &= ~DRIVE_DMA; 2283 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2284 APO_UDMA_EN_MTH(chp->channel, drive); 2285 if (sc->sc_wdcdev.UDMA_cap == 5) { 2286 /* 686b */ 2287 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2288 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2289 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2290 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2291 /* 596b or 686a */ 2292 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2293 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2294 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2295 } else { 2296 /* 596a or 586b */ 2297 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2298 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2299 } 2300 /* can use PIO timings, MW DMA unused */ 2301 mode = drvp->PIO_mode; 2302 } else { 2303 /* use Multiword DMA */ 2304 drvp->drive_flags &= ~DRIVE_UDMA; 2305 /* mode = min(pio, dma+2) */ 2306 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2307 mode = drvp->PIO_mode; 2308 else 2309 mode = drvp->DMA_mode + 2; 2310 } 2311 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2312 2313 pio: /* setup PIO mode */ 2314 if (mode <= 2) { 2315 drvp->DMA_mode = 0; 2316 drvp->PIO_mode = 0; 2317 mode = 0; 2318 } else { 2319 drvp->PIO_mode = mode; 2320 drvp->DMA_mode = mode - 2; 2321 } 2322 datatim_reg |= 2323 APO_DATATIM_PULSE(chp->channel, drive, 2324 apollo_pio_set[mode]) | 2325 APO_DATATIM_RECOV(chp->channel, drive, 2326 apollo_pio_rec[mode]); 2327 } 2328 if (idedma_ctl != 0) { 2329 /* Add software bits in status register */ 2330 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2331 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2332 idedma_ctl); 2333 } 2334 pciide_print_modes(cp); 2335 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2336 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2337 } 2338 2339 void 2340 cmd_channel_map(pa, sc, channel) 2341 struct pci_attach_args *pa; 2342 struct pciide_softc *sc; 2343 int channel; 2344 { 2345 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2346 bus_size_t cmdsize, ctlsize; 2347 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2348 int interface, one_channel; 2349 2350 /* 2351 * The 0648/0649 can be told to identify as a RAID controller. 2352 * In this case, we have to fake interface 2353 */ 2354 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2355 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2356 PCIIDE_INTERFACE_SETTABLE(1); 2357 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2358 CMD_CONF_DSA1) 2359 interface |= PCIIDE_INTERFACE_PCI(0) | 2360 PCIIDE_INTERFACE_PCI(1); 2361 } else { 2362 interface = PCI_INTERFACE(pa->pa_class); 2363 } 2364 2365 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2366 cp->name = PCIIDE_CHANNEL_NAME(channel); 2367 cp->wdc_channel.channel = channel; 2368 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2369 2370 /* 2371 * Older CMD64X doesn't have independant channels 2372 */ 2373 switch (sc->sc_pp->ide_product) { 2374 case PCI_PRODUCT_CMDTECH_649: 2375 one_channel = 0; 2376 break; 2377 default: 2378 one_channel = 1; 2379 break; 2380 } 2381 2382 if (channel > 0 && one_channel) { 2383 cp->wdc_channel.ch_queue = 2384 sc->pciide_channels[0].wdc_channel.ch_queue; 2385 } else { 2386 cp->wdc_channel.ch_queue = 2387 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2388 } 2389 if (cp->wdc_channel.ch_queue == NULL) { 2390 printf("%s %s channel: " 2391 "can't allocate memory for command queue", 2392 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2393 return; 2394 } 2395 2396 printf("%s: %s channel %s to %s mode\n", 2397 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2398 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2399 "configured" : "wired", 2400 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2401 "native-PCI" : "compatibility"); 2402 2403 /* 2404 * with a CMD PCI64x, if we get here, the first channel is enabled: 2405 * there's no way to disable the first channel without disabling 2406 * the whole device 2407 */ 2408 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2409 printf("%s: %s channel ignored (disabled)\n", 2410 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2411 return; 2412 } 2413 2414 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2415 if (cp->hw_ok == 0) 2416 return; 2417 if (channel == 1) { 2418 if (pciide_chan_candisable(cp)) { 2419 ctrl &= ~CMD_CTRL_2PORT; 2420 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2421 CMD_CTRL, ctrl); 2422 } 2423 } 2424 pciide_map_compat_intr(pa, cp, channel, interface); 2425 } 2426 2427 int 2428 cmd_pci_intr(arg) 2429 void *arg; 2430 { 2431 struct pciide_softc *sc = arg; 2432 struct pciide_channel *cp; 2433 struct channel_softc *wdc_cp; 2434 int i, rv, crv; 2435 u_int32_t priirq, secirq; 2436 2437 rv = 0; 2438 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2439 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2440 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2441 cp = &sc->pciide_channels[i]; 2442 wdc_cp = &cp->wdc_channel; 2443 /* If a compat channel skip. */ 2444 if (cp->compat) 2445 continue; 2446 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2447 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2448 crv = wdcintr(wdc_cp); 2449 if (crv == 0) 2450 printf("%s:%d: bogus intr\n", 2451 sc->sc_wdcdev.sc_dev.dv_xname, i); 2452 else 2453 rv = 1; 2454 } 2455 } 2456 return rv; 2457 } 2458 2459 void 2460 cmd_chip_map(sc, pa) 2461 struct pciide_softc *sc; 2462 struct pci_attach_args *pa; 2463 { 2464 int channel; 2465 2466 /* 2467 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2468 * and base adresses registers can be disabled at 2469 * hardware level. In this case, the device is wired 2470 * in compat mode and its first channel is always enabled, 2471 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2472 * In fact, it seems that the first channel of the CMD PCI0640 2473 * can't be disabled. 2474 */ 2475 2476 #ifdef PCIIDE_CMD064x_DISABLE 2477 if (pciide_chipen(sc, pa) == 0) 2478 return; 2479 #endif 2480 2481 printf("%s: hardware does not support DMA\n", 2482 sc->sc_wdcdev.sc_dev.dv_xname); 2483 sc->sc_dma_ok = 0; 2484 2485 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2486 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2487 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2488 2489 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2490 cmd_channel_map(pa, sc, channel); 2491 } 2492 } 2493 2494 void 2495 cmd0643_9_chip_map(sc, pa) 2496 struct pciide_softc *sc; 2497 struct pci_attach_args *pa; 2498 { 2499 struct pciide_channel *cp; 2500 int channel; 2501 pcireg_t rev = PCI_REVISION(pa->pa_class); 2502 2503 /* 2504 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2505 * and base adresses registers can be disabled at 2506 * hardware level. In this case, the device is wired 2507 * in compat mode and its first channel is always enabled, 2508 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2509 * In fact, it seems that the first channel of the CMD PCI0640 2510 * can't be disabled. 2511 */ 2512 2513 #ifdef PCIIDE_CMD064x_DISABLE 2514 if (pciide_chipen(sc, pa) == 0) 2515 return; 2516 #endif 2517 printf("%s: bus-master DMA support present", 2518 sc->sc_wdcdev.sc_dev.dv_xname); 2519 pciide_mapreg_dma(sc, pa); 2520 printf("\n"); 2521 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2522 WDC_CAPABILITY_MODE; 2523 if (sc->sc_dma_ok) { 2524 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2525 switch (sc->sc_pp->ide_product) { 2526 case PCI_PRODUCT_CMDTECH_649: 2527 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2528 sc->sc_wdcdev.UDMA_cap = 5; 2529 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2530 break; 2531 case PCI_PRODUCT_CMDTECH_648: 2532 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2533 sc->sc_wdcdev.UDMA_cap = 4; 2534 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2535 break; 2536 case PCI_PRODUCT_CMDTECH_646: 2537 if (rev >= CMD0646U2_REV) { 2538 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2539 sc->sc_wdcdev.UDMA_cap = 2; 2540 } else if (rev >= CMD0646U_REV) { 2541 /* 2542 * Linux's driver claims that the 646U is broken 2543 * with UDMA. Only enable it if we know what we're 2544 * doing 2545 */ 2546 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2547 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2548 sc->sc_wdcdev.UDMA_cap = 2; 2549 #endif 2550 /* explicitly disable UDMA */ 2551 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2552 CMD_UDMATIM(0), 0); 2553 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2554 CMD_UDMATIM(1), 0); 2555 } 2556 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2557 break; 2558 default: 2559 sc->sc_wdcdev.irqack = pciide_irqack; 2560 } 2561 } 2562 2563 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2564 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2565 sc->sc_wdcdev.PIO_cap = 4; 2566 sc->sc_wdcdev.DMA_cap = 2; 2567 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2568 2569 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2570 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2571 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2572 DEBUG_PROBE); 2573 2574 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2575 cp = &sc->pciide_channels[channel]; 2576 cmd_channel_map(pa, sc, channel); 2577 if (cp->hw_ok == 0) 2578 continue; 2579 cmd0643_9_setup_channel(&cp->wdc_channel); 2580 } 2581 /* 2582 * note - this also makes sure we clear the irq disable and reset 2583 * bits 2584 */ 2585 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2586 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2587 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2588 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2589 DEBUG_PROBE); 2590 } 2591 2592 void 2593 cmd0643_9_setup_channel(chp) 2594 struct channel_softc *chp; 2595 { 2596 struct ata_drive_datas *drvp; 2597 u_int8_t tim; 2598 u_int32_t idedma_ctl, udma_reg; 2599 int drive; 2600 struct pciide_channel *cp = (struct pciide_channel*)chp; 2601 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2602 2603 idedma_ctl = 0; 2604 /* setup DMA if needed */ 2605 pciide_channel_dma_setup(cp); 2606 2607 for (drive = 0; drive < 2; drive++) { 2608 drvp = &chp->ch_drive[drive]; 2609 /* If no drive, skip */ 2610 if ((drvp->drive_flags & DRIVE) == 0) 2611 continue; 2612 /* add timing values, setup DMA if needed */ 2613 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2614 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2615 if (drvp->drive_flags & DRIVE_UDMA) { 2616 /* UltraDMA on a 646U2, 0648 or 0649 */ 2617 drvp->drive_flags &= ~DRIVE_DMA; 2618 udma_reg = pciide_pci_read(sc->sc_pc, 2619 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2620 if (drvp->UDMA_mode > 2 && 2621 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2622 CMD_BICSR) & 2623 CMD_BICSR_80(chp->channel)) == 0) 2624 drvp->UDMA_mode = 2; 2625 if (drvp->UDMA_mode > 2) 2626 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2627 else if (sc->sc_wdcdev.UDMA_cap > 2) 2628 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2629 udma_reg |= CMD_UDMATIM_UDMA(drive); 2630 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2631 CMD_UDMATIM_TIM_OFF(drive)); 2632 udma_reg |= 2633 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2634 CMD_UDMATIM_TIM_OFF(drive)); 2635 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2636 CMD_UDMATIM(chp->channel), udma_reg); 2637 } else { 2638 /* 2639 * use Multiword DMA. 2640 * Timings will be used for both PIO and DMA, 2641 * so adjust DMA mode if needed 2642 * if we have a 0646U2/8/9, turn off UDMA 2643 */ 2644 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2645 udma_reg = pciide_pci_read(sc->sc_pc, 2646 sc->sc_tag, 2647 CMD_UDMATIM(chp->channel)); 2648 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2649 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2650 CMD_UDMATIM(chp->channel), 2651 udma_reg); 2652 } 2653 if (drvp->PIO_mode >= 3 && 2654 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2655 drvp->DMA_mode = drvp->PIO_mode - 2; 2656 } 2657 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2658 } 2659 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2660 } 2661 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2662 CMD_DATA_TIM(chp->channel, drive), tim); 2663 } 2664 if (idedma_ctl != 0) { 2665 /* Add software bits in status register */ 2666 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2667 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2668 idedma_ctl); 2669 } 2670 pciide_print_modes(cp); 2671 } 2672 2673 void 2674 cmd646_9_irqack(chp) 2675 struct channel_softc *chp; 2676 { 2677 u_int32_t priirq, secirq; 2678 struct pciide_channel *cp = (struct pciide_channel*)chp; 2679 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2680 2681 if (chp->channel == 0) { 2682 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2683 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2684 } else { 2685 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2686 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2687 } 2688 pciide_irqack(chp); 2689 } 2690 2691 void 2692 cy693_chip_map(sc, pa) 2693 struct pciide_softc *sc; 2694 struct pci_attach_args *pa; 2695 { 2696 struct pciide_channel *cp; 2697 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2698 bus_size_t cmdsize, ctlsize; 2699 2700 if (pciide_chipen(sc, pa) == 0) 2701 return; 2702 /* 2703 * this chip has 2 PCI IDE functions, one for primary and one for 2704 * secondary. So we need to call pciide_mapregs_compat() with 2705 * the real channel 2706 */ 2707 if (pa->pa_function == 1) { 2708 sc->sc_cy_compatchan = 0; 2709 } else if (pa->pa_function == 2) { 2710 sc->sc_cy_compatchan = 1; 2711 } else { 2712 printf("%s: unexpected PCI function %d\n", 2713 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2714 return; 2715 } 2716 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2717 printf("%s: bus-master DMA support present", 2718 sc->sc_wdcdev.sc_dev.dv_xname); 2719 pciide_mapreg_dma(sc, pa); 2720 } else { 2721 printf("%s: hardware does not support DMA", 2722 sc->sc_wdcdev.sc_dev.dv_xname); 2723 sc->sc_dma_ok = 0; 2724 } 2725 printf("\n"); 2726 2727 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2728 if (sc->sc_cy_handle == NULL) { 2729 printf("%s: unable to map hyperCache control registers\n", 2730 sc->sc_wdcdev.sc_dev.dv_xname); 2731 sc->sc_dma_ok = 0; 2732 } 2733 2734 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2735 WDC_CAPABILITY_MODE; 2736 if (sc->sc_dma_ok) { 2737 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2738 sc->sc_wdcdev.irqack = pciide_irqack; 2739 } 2740 sc->sc_wdcdev.PIO_cap = 4; 2741 sc->sc_wdcdev.DMA_cap = 2; 2742 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2743 2744 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2745 sc->sc_wdcdev.nchannels = 1; 2746 2747 /* Only one channel for this chip; if we are here it's enabled */ 2748 cp = &sc->pciide_channels[0]; 2749 sc->wdc_chanarray[0] = &cp->wdc_channel; 2750 cp->name = PCIIDE_CHANNEL_NAME(0); 2751 cp->wdc_channel.channel = 0; 2752 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2753 cp->wdc_channel.ch_queue = 2754 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2755 if (cp->wdc_channel.ch_queue == NULL) { 2756 printf("%s primary channel: " 2757 "can't allocate memory for command queue", 2758 sc->sc_wdcdev.sc_dev.dv_xname); 2759 return; 2760 } 2761 printf("%s: primary channel %s to ", 2762 sc->sc_wdcdev.sc_dev.dv_xname, 2763 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2764 "configured" : "wired"); 2765 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2766 printf("native-PCI"); 2767 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2768 pciide_pci_intr); 2769 } else { 2770 printf("compatibility"); 2771 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2772 &cmdsize, &ctlsize); 2773 } 2774 printf(" mode\n"); 2775 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2776 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2777 wdcattach(&cp->wdc_channel); 2778 if (pciide_chan_candisable(cp)) { 2779 pci_conf_write(sc->sc_pc, sc->sc_tag, 2780 PCI_COMMAND_STATUS_REG, 0); 2781 } 2782 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2783 if (cp->hw_ok == 0) 2784 return; 2785 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2786 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2787 cy693_setup_channel(&cp->wdc_channel); 2788 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2789 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2790 } 2791 2792 void 2793 cy693_setup_channel(chp) 2794 struct channel_softc *chp; 2795 { 2796 struct ata_drive_datas *drvp; 2797 int drive; 2798 u_int32_t cy_cmd_ctrl; 2799 u_int32_t idedma_ctl; 2800 struct pciide_channel *cp = (struct pciide_channel*)chp; 2801 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2802 int dma_mode = -1; 2803 2804 cy_cmd_ctrl = idedma_ctl = 0; 2805 2806 /* setup DMA if needed */ 2807 pciide_channel_dma_setup(cp); 2808 2809 for (drive = 0; drive < 2; drive++) { 2810 drvp = &chp->ch_drive[drive]; 2811 /* If no drive, skip */ 2812 if ((drvp->drive_flags & DRIVE) == 0) 2813 continue; 2814 /* add timing values, setup DMA if needed */ 2815 if (drvp->drive_flags & DRIVE_DMA) { 2816 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2817 /* use Multiword DMA */ 2818 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2819 dma_mode = drvp->DMA_mode; 2820 } 2821 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2822 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2823 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2824 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2825 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2826 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2827 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2828 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2829 } 2830 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2831 chp->ch_drive[0].DMA_mode = dma_mode; 2832 chp->ch_drive[1].DMA_mode = dma_mode; 2833 2834 if (dma_mode == -1) 2835 dma_mode = 0; 2836 2837 if (sc->sc_cy_handle != NULL) { 2838 /* Note: `multiple' is implied. */ 2839 cy82c693_write(sc->sc_cy_handle, 2840 (sc->sc_cy_compatchan == 0) ? 2841 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2842 } 2843 2844 pciide_print_modes(cp); 2845 2846 if (idedma_ctl != 0) { 2847 /* Add software bits in status register */ 2848 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2849 IDEDMA_CTL, idedma_ctl); 2850 } 2851 } 2852 2853 static int 2854 sis_hostbr_match(pa) 2855 struct pci_attach_args *pa; 2856 { 2857 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 2858 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 2859 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 2860 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 2861 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 2862 } 2863 2864 void 2865 sis_chip_map(sc, pa) 2866 struct pciide_softc *sc; 2867 struct pci_attach_args *pa; 2868 { 2869 struct pciide_channel *cp; 2870 int channel; 2871 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2872 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2873 pcireg_t rev = PCI_REVISION(pa->pa_class); 2874 bus_size_t cmdsize, ctlsize; 2875 pcitag_t pchb_tag; 2876 pcireg_t pchb_id, pchb_class; 2877 2878 if (pciide_chipen(sc, pa) == 0) 2879 return; 2880 printf("%s: bus-master DMA support present", 2881 sc->sc_wdcdev.sc_dev.dv_xname); 2882 pciide_mapreg_dma(sc, pa); 2883 printf("\n"); 2884 2885 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2886 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2887 /* and read ID and rev of the ISA bridge */ 2888 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2889 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2890 2891 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2892 WDC_CAPABILITY_MODE; 2893 if (sc->sc_dma_ok) { 2894 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2895 sc->sc_wdcdev.irqack = pciide_irqack; 2896 /* 2897 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2898 * have problems with UDMA (info provided by Christos) 2899 */ 2900 if (rev >= 0xd0 && 2901 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2902 PCI_REVISION(pchb_class) >= 0x03)) 2903 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2904 } 2905 2906 sc->sc_wdcdev.PIO_cap = 4; 2907 sc->sc_wdcdev.DMA_cap = 2; 2908 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2909 /* 2910 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 2911 * chipsets. 2912 */ 2913 sc->sc_wdcdev.UDMA_cap = 2914 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 2915 sc->sc_wdcdev.set_modes = sis_setup_channel; 2916 2917 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2918 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2919 2920 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2921 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2922 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2923 2924 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2925 cp = &sc->pciide_channels[channel]; 2926 if (pciide_chansetup(sc, channel, interface) == 0) 2927 continue; 2928 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2929 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2930 printf("%s: %s channel ignored (disabled)\n", 2931 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2932 continue; 2933 } 2934 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2935 pciide_pci_intr); 2936 if (cp->hw_ok == 0) 2937 continue; 2938 if (pciide_chan_candisable(cp)) { 2939 if (channel == 0) 2940 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2941 else 2942 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2943 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2944 sis_ctr0); 2945 } 2946 pciide_map_compat_intr(pa, cp, channel, interface); 2947 if (cp->hw_ok == 0) 2948 continue; 2949 sis_setup_channel(&cp->wdc_channel); 2950 } 2951 } 2952 2953 void 2954 sis_setup_channel(chp) 2955 struct channel_softc *chp; 2956 { 2957 struct ata_drive_datas *drvp; 2958 int drive; 2959 u_int32_t sis_tim; 2960 u_int32_t idedma_ctl; 2961 struct pciide_channel *cp = (struct pciide_channel*)chp; 2962 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2963 2964 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2965 "channel %d 0x%x\n", chp->channel, 2966 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2967 DEBUG_PROBE); 2968 sis_tim = 0; 2969 idedma_ctl = 0; 2970 /* setup DMA if needed */ 2971 pciide_channel_dma_setup(cp); 2972 2973 for (drive = 0; drive < 2; drive++) { 2974 drvp = &chp->ch_drive[drive]; 2975 /* If no drive, skip */ 2976 if ((drvp->drive_flags & DRIVE) == 0) 2977 continue; 2978 /* add timing values, setup DMA if needed */ 2979 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2980 (drvp->drive_flags & DRIVE_UDMA) == 0) 2981 goto pio; 2982 2983 if (drvp->drive_flags & DRIVE_UDMA) { 2984 /* use Ultra/DMA */ 2985 drvp->drive_flags &= ~DRIVE_DMA; 2986 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2987 SIS_TIM_UDMA_TIME_OFF(drive); 2988 sis_tim |= SIS_TIM_UDMA_EN(drive); 2989 } else { 2990 /* 2991 * use Multiword DMA 2992 * Timings will be used for both PIO and DMA, 2993 * so adjust DMA mode if needed 2994 */ 2995 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2996 drvp->PIO_mode = drvp->DMA_mode + 2; 2997 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2998 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2999 drvp->PIO_mode - 2 : 0; 3000 if (drvp->DMA_mode == 0) 3001 drvp->PIO_mode = 0; 3002 } 3003 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3004 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 3005 SIS_TIM_ACT_OFF(drive); 3006 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3007 SIS_TIM_REC_OFF(drive); 3008 } 3009 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3010 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3011 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3012 if (idedma_ctl != 0) { 3013 /* Add software bits in status register */ 3014 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3015 IDEDMA_CTL, idedma_ctl); 3016 } 3017 pciide_print_modes(cp); 3018 } 3019 3020 void 3021 acer_chip_map(sc, pa) 3022 struct pciide_softc *sc; 3023 struct pci_attach_args *pa; 3024 { 3025 struct pciide_channel *cp; 3026 int channel; 3027 pcireg_t cr, interface; 3028 bus_size_t cmdsize, ctlsize; 3029 pcireg_t rev = PCI_REVISION(pa->pa_class); 3030 3031 if (pciide_chipen(sc, pa) == 0) 3032 return; 3033 printf("%s: bus-master DMA support present", 3034 sc->sc_wdcdev.sc_dev.dv_xname); 3035 pciide_mapreg_dma(sc, pa); 3036 printf("\n"); 3037 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3038 WDC_CAPABILITY_MODE; 3039 if (sc->sc_dma_ok) { 3040 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3041 if (rev >= 0x20) { 3042 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3043 if (rev >= 0xC4) 3044 sc->sc_wdcdev.UDMA_cap = 5; 3045 else if (rev >= 0xC2) 3046 sc->sc_wdcdev.UDMA_cap = 4; 3047 else 3048 sc->sc_wdcdev.UDMA_cap = 2; 3049 } 3050 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3051 sc->sc_wdcdev.irqack = pciide_irqack; 3052 } 3053 3054 sc->sc_wdcdev.PIO_cap = 4; 3055 sc->sc_wdcdev.DMA_cap = 2; 3056 sc->sc_wdcdev.set_modes = acer_setup_channel; 3057 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3058 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3059 3060 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3061 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3062 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3063 3064 /* Enable "microsoft register bits" R/W. */ 3065 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3066 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3067 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3068 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3069 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3070 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3071 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3072 ~ACER_CHANSTATUSREGS_RO); 3073 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3074 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3075 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3076 /* Don't use cr, re-read the real register content instead */ 3077 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3078 PCI_CLASS_REG)); 3079 3080 /* From linux: enable "Cable Detection" */ 3081 if (rev >= 0xC2) { 3082 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3083 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3084 | ACER_0x4B_CDETECT); 3085 } 3086 3087 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3088 cp = &sc->pciide_channels[channel]; 3089 if (pciide_chansetup(sc, channel, interface) == 0) 3090 continue; 3091 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3092 printf("%s: %s channel ignored (disabled)\n", 3093 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3094 continue; 3095 } 3096 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3097 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3098 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3099 if (cp->hw_ok == 0) 3100 continue; 3101 if (pciide_chan_candisable(cp)) { 3102 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3103 pci_conf_write(sc->sc_pc, sc->sc_tag, 3104 PCI_CLASS_REG, cr); 3105 } 3106 pciide_map_compat_intr(pa, cp, channel, interface); 3107 acer_setup_channel(&cp->wdc_channel); 3108 } 3109 } 3110 3111 void 3112 acer_setup_channel(chp) 3113 struct channel_softc *chp; 3114 { 3115 struct ata_drive_datas *drvp; 3116 int drive; 3117 u_int32_t acer_fifo_udma; 3118 u_int32_t idedma_ctl; 3119 struct pciide_channel *cp = (struct pciide_channel*)chp; 3120 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3121 3122 idedma_ctl = 0; 3123 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3124 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3125 acer_fifo_udma), DEBUG_PROBE); 3126 /* setup DMA if needed */ 3127 pciide_channel_dma_setup(cp); 3128 3129 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3130 DRIVE_UDMA) { /* check 80 pins cable */ 3131 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3132 ACER_0x4A_80PIN(chp->channel)) { 3133 if (chp->ch_drive[0].UDMA_mode > 2) 3134 chp->ch_drive[0].UDMA_mode = 2; 3135 if (chp->ch_drive[1].UDMA_mode > 2) 3136 chp->ch_drive[1].UDMA_mode = 2; 3137 } 3138 } 3139 3140 for (drive = 0; drive < 2; drive++) { 3141 drvp = &chp->ch_drive[drive]; 3142 /* If no drive, skip */ 3143 if ((drvp->drive_flags & DRIVE) == 0) 3144 continue; 3145 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3146 "channel %d drive %d 0x%x\n", chp->channel, drive, 3147 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3148 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3149 /* clear FIFO/DMA mode */ 3150 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3151 ACER_UDMA_EN(chp->channel, drive) | 3152 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3153 3154 /* add timing values, setup DMA if needed */ 3155 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3156 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3157 acer_fifo_udma |= 3158 ACER_FTH_OPL(chp->channel, drive, 0x1); 3159 goto pio; 3160 } 3161 3162 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3163 if (drvp->drive_flags & DRIVE_UDMA) { 3164 /* use Ultra/DMA */ 3165 drvp->drive_flags &= ~DRIVE_DMA; 3166 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3167 acer_fifo_udma |= 3168 ACER_UDMA_TIM(chp->channel, drive, 3169 acer_udma[drvp->UDMA_mode]); 3170 /* XXX disable if one drive < UDMA3 ? */ 3171 if (drvp->UDMA_mode >= 3) { 3172 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3173 ACER_0x4B, 3174 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3175 ACER_0x4B) | ACER_0x4B_UDMA66); 3176 } 3177 } else { 3178 /* 3179 * use Multiword DMA 3180 * Timings will be used for both PIO and DMA, 3181 * so adjust DMA mode if needed 3182 */ 3183 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3184 drvp->PIO_mode = drvp->DMA_mode + 2; 3185 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3186 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3187 drvp->PIO_mode - 2 : 0; 3188 if (drvp->DMA_mode == 0) 3189 drvp->PIO_mode = 0; 3190 } 3191 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3192 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3193 ACER_IDETIM(chp->channel, drive), 3194 acer_pio[drvp->PIO_mode]); 3195 } 3196 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3197 acer_fifo_udma), DEBUG_PROBE); 3198 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3199 if (idedma_ctl != 0) { 3200 /* Add software bits in status register */ 3201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3202 IDEDMA_CTL, idedma_ctl); 3203 } 3204 pciide_print_modes(cp); 3205 } 3206 3207 int 3208 acer_pci_intr(arg) 3209 void *arg; 3210 { 3211 struct pciide_softc *sc = arg; 3212 struct pciide_channel *cp; 3213 struct channel_softc *wdc_cp; 3214 int i, rv, crv; 3215 u_int32_t chids; 3216 3217 rv = 0; 3218 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3219 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3220 cp = &sc->pciide_channels[i]; 3221 wdc_cp = &cp->wdc_channel; 3222 /* If a compat channel skip. */ 3223 if (cp->compat) 3224 continue; 3225 if (chids & ACER_CHIDS_INT(i)) { 3226 crv = wdcintr(wdc_cp); 3227 if (crv == 0) 3228 printf("%s:%d: bogus intr\n", 3229 sc->sc_wdcdev.sc_dev.dv_xname, i); 3230 else 3231 rv = 1; 3232 } 3233 } 3234 return rv; 3235 } 3236 3237 void 3238 hpt_chip_map(sc, pa) 3239 struct pciide_softc *sc; 3240 struct pci_attach_args *pa; 3241 { 3242 struct pciide_channel *cp; 3243 int i, compatchan, revision; 3244 pcireg_t interface; 3245 bus_size_t cmdsize, ctlsize; 3246 3247 if (pciide_chipen(sc, pa) == 0) 3248 return; 3249 revision = PCI_REVISION(pa->pa_class); 3250 printf(": Triones/Highpoint "); 3251 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3252 printf("HPT374 IDE Controller\n"); 3253 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3254 if (revision == HPT370_REV) 3255 printf("HPT370 IDE Controller\n"); 3256 else if (revision == HPT370A_REV) 3257 printf("HPT370A IDE Controller\n"); 3258 else if (revision == HPT366_REV) 3259 printf("HPT366 IDE Controller\n"); 3260 else 3261 printf("unknown HPT IDE controller rev %d\n", revision); 3262 } else 3263 printf("unknown HPT IDE controller 0x%x\n", 3264 sc->sc_pp->ide_product); 3265 3266 /* 3267 * when the chip is in native mode it identifies itself as a 3268 * 'misc mass storage'. Fake interface in this case. 3269 */ 3270 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3271 interface = PCI_INTERFACE(pa->pa_class); 3272 } else { 3273 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3274 PCIIDE_INTERFACE_PCI(0); 3275 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3276 (revision == HPT370_REV || revision == HPT370A_REV)) || 3277 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3278 interface |= PCIIDE_INTERFACE_PCI(1); 3279 } 3280 3281 printf("%s: bus-master DMA support present", 3282 sc->sc_wdcdev.sc_dev.dv_xname); 3283 pciide_mapreg_dma(sc, pa); 3284 printf("\n"); 3285 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3286 WDC_CAPABILITY_MODE; 3287 if (sc->sc_dma_ok) { 3288 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3289 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3290 sc->sc_wdcdev.irqack = pciide_irqack; 3291 } 3292 sc->sc_wdcdev.PIO_cap = 4; 3293 sc->sc_wdcdev.DMA_cap = 2; 3294 3295 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3296 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3297 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3298 revision == HPT366_REV) { 3299 sc->sc_wdcdev.UDMA_cap = 4; 3300 /* 3301 * The 366 has 2 PCI IDE functions, one for primary and one 3302 * for secondary. So we need to call pciide_mapregs_compat() 3303 * with the real channel 3304 */ 3305 if (pa->pa_function == 0) { 3306 compatchan = 0; 3307 } else if (pa->pa_function == 1) { 3308 compatchan = 1; 3309 } else { 3310 printf("%s: unexpected PCI function %d\n", 3311 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3312 return; 3313 } 3314 sc->sc_wdcdev.nchannels = 1; 3315 } else { 3316 sc->sc_wdcdev.nchannels = 2; 3317 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3318 sc->sc_wdcdev.UDMA_cap = 6; 3319 else 3320 sc->sc_wdcdev.UDMA_cap = 5; 3321 } 3322 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3323 cp = &sc->pciide_channels[i]; 3324 if (sc->sc_wdcdev.nchannels > 1) { 3325 compatchan = i; 3326 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3327 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3328 printf("%s: %s channel ignored (disabled)\n", 3329 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3330 continue; 3331 } 3332 } 3333 if (pciide_chansetup(sc, i, interface) == 0) 3334 continue; 3335 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3336 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3337 &ctlsize, hpt_pci_intr); 3338 } else { 3339 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3340 &cmdsize, &ctlsize); 3341 } 3342 if (cp->hw_ok == 0) 3343 return; 3344 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3345 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3346 wdcattach(&cp->wdc_channel); 3347 hpt_setup_channel(&cp->wdc_channel); 3348 } 3349 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3350 (revision == HPT370_REV || revision == HPT370A_REV)) || 3351 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3352 /* 3353 * HPT370_REV and highter has a bit to disable interrupts, 3354 * make sure to clear it 3355 */ 3356 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3357 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3358 ~HPT_CSEL_IRQDIS); 3359 } 3360 /* set clocks, etc (mandatory on 374, optional otherwise) */ 3361 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3362 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3363 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3364 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3365 return; 3366 } 3367 3368 void 3369 hpt_setup_channel(chp) 3370 struct channel_softc *chp; 3371 { 3372 struct ata_drive_datas *drvp; 3373 int drive; 3374 int cable; 3375 u_int32_t before, after; 3376 u_int32_t idedma_ctl; 3377 struct pciide_channel *cp = (struct pciide_channel*)chp; 3378 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3379 3380 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3381 3382 /* setup DMA if needed */ 3383 pciide_channel_dma_setup(cp); 3384 3385 idedma_ctl = 0; 3386 3387 /* Per drive settings */ 3388 for (drive = 0; drive < 2; drive++) { 3389 drvp = &chp->ch_drive[drive]; 3390 /* If no drive, skip */ 3391 if ((drvp->drive_flags & DRIVE) == 0) 3392 continue; 3393 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3394 HPT_IDETIM(chp->channel, drive)); 3395 3396 /* add timing values, setup DMA if needed */ 3397 if (drvp->drive_flags & DRIVE_UDMA) { 3398 /* use Ultra/DMA */ 3399 drvp->drive_flags &= ~DRIVE_DMA; 3400 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3401 drvp->UDMA_mode > 2) 3402 drvp->UDMA_mode = 2; 3403 after = (sc->sc_wdcdev.nchannels == 2) ? 3404 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3405 hpt374_udma[drvp->UDMA_mode] : 3406 hpt370_udma[drvp->UDMA_mode]) : 3407 hpt366_udma[drvp->UDMA_mode]; 3408 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3409 } else if (drvp->drive_flags & DRIVE_DMA) { 3410 /* 3411 * use Multiword DMA. 3412 * Timings will be used for both PIO and DMA, so adjust 3413 * DMA mode if needed 3414 */ 3415 if (drvp->PIO_mode >= 3 && 3416 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3417 drvp->DMA_mode = drvp->PIO_mode - 2; 3418 } 3419 after = (sc->sc_wdcdev.nchannels == 2) ? 3420 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3421 hpt374_dma[drvp->DMA_mode] : 3422 hpt370_dma[drvp->DMA_mode]) : 3423 hpt366_dma[drvp->DMA_mode]; 3424 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3425 } else { 3426 /* PIO only */ 3427 after = (sc->sc_wdcdev.nchannels == 2) ? 3428 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3429 hpt374_pio[drvp->PIO_mode] : 3430 hpt370_pio[drvp->PIO_mode]) : 3431 hpt366_pio[drvp->PIO_mode]; 3432 } 3433 pci_conf_write(sc->sc_pc, sc->sc_tag, 3434 HPT_IDETIM(chp->channel, drive), after); 3435 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3436 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3437 after, before), DEBUG_PROBE); 3438 } 3439 if (idedma_ctl != 0) { 3440 /* Add software bits in status register */ 3441 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3442 IDEDMA_CTL, idedma_ctl); 3443 } 3444 pciide_print_modes(cp); 3445 } 3446 3447 int 3448 hpt_pci_intr(arg) 3449 void *arg; 3450 { 3451 struct pciide_softc *sc = arg; 3452 struct pciide_channel *cp; 3453 struct channel_softc *wdc_cp; 3454 int rv = 0; 3455 int dmastat, i, crv; 3456 3457 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3458 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3459 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3460 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3461 IDEDMA_CTL_INTR) 3462 continue; 3463 cp = &sc->pciide_channels[i]; 3464 wdc_cp = &cp->wdc_channel; 3465 crv = wdcintr(wdc_cp); 3466 if (crv == 0) { 3467 printf("%s:%d: bogus intr\n", 3468 sc->sc_wdcdev.sc_dev.dv_xname, i); 3469 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3470 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3471 } else 3472 rv = 1; 3473 } 3474 return rv; 3475 } 3476 3477 3478 /* Macros to test product */ 3479 #define PDC_IS_262(sc) \ 3480 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3481 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3482 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3483 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3484 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3485 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3486 #define PDC_IS_265(sc) \ 3487 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3488 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3489 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3490 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3491 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3492 #define PDC_IS_268(sc) \ 3493 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3494 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3495 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3496 3497 void 3498 pdc202xx_chip_map(sc, pa) 3499 struct pciide_softc *sc; 3500 struct pci_attach_args *pa; 3501 { 3502 struct pciide_channel *cp; 3503 int channel; 3504 pcireg_t interface, st, mode; 3505 bus_size_t cmdsize, ctlsize; 3506 3507 if (!PDC_IS_268(sc)) { 3508 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3509 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3510 st), DEBUG_PROBE); 3511 } 3512 if (pciide_chipen(sc, pa) == 0) 3513 return; 3514 3515 /* turn off RAID mode */ 3516 if (!PDC_IS_268(sc)) 3517 st &= ~PDC2xx_STATE_IDERAID; 3518 3519 /* 3520 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3521 * mode. We have to fake interface 3522 */ 3523 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3524 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3525 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3526 3527 printf("%s: bus-master DMA support present", 3528 sc->sc_wdcdev.sc_dev.dv_xname); 3529 pciide_mapreg_dma(sc, pa); 3530 printf("\n"); 3531 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3532 WDC_CAPABILITY_MODE; 3533 if (sc->sc_dma_ok) { 3534 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3535 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3536 sc->sc_wdcdev.irqack = pciide_irqack; 3537 } 3538 sc->sc_wdcdev.PIO_cap = 4; 3539 sc->sc_wdcdev.DMA_cap = 2; 3540 if (PDC_IS_265(sc)) 3541 sc->sc_wdcdev.UDMA_cap = 5; 3542 else if (PDC_IS_262(sc)) 3543 sc->sc_wdcdev.UDMA_cap = 4; 3544 else 3545 sc->sc_wdcdev.UDMA_cap = 2; 3546 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3547 pdc20268_setup_channel : pdc202xx_setup_channel; 3548 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3549 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3550 3551 if (!PDC_IS_268(sc)) { 3552 /* setup failsafe defaults */ 3553 mode = 0; 3554 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3555 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3556 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3557 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3558 for (channel = 0; 3559 channel < sc->sc_wdcdev.nchannels; 3560 channel++) { 3561 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3562 "drive 0 initial timings 0x%x, now 0x%x\n", 3563 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3564 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3565 DEBUG_PROBE); 3566 pci_conf_write(sc->sc_pc, sc->sc_tag, 3567 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3568 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3569 "drive 1 initial timings 0x%x, now 0x%x\n", 3570 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3571 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3572 pci_conf_write(sc->sc_pc, sc->sc_tag, 3573 PDC2xx_TIM(channel, 1), mode); 3574 } 3575 3576 mode = PDC2xx_SCR_DMA; 3577 if (PDC_IS_262(sc)) { 3578 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3579 } else { 3580 /* the BIOS set it up this way */ 3581 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3582 } 3583 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3584 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3585 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3586 "now 0x%x\n", 3587 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3588 PDC2xx_SCR), 3589 mode), DEBUG_PROBE); 3590 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3591 PDC2xx_SCR, mode); 3592 3593 /* controller initial state register is OK even without BIOS */ 3594 /* Set DMA mode to IDE DMA compatibility */ 3595 mode = 3596 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3597 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3598 DEBUG_PROBE); 3599 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3600 mode | 0x1); 3601 mode = 3602 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3603 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3604 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3605 mode | 0x1); 3606 } 3607 3608 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3609 cp = &sc->pciide_channels[channel]; 3610 if (pciide_chansetup(sc, channel, interface) == 0) 3611 continue; 3612 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3613 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3614 printf("%s: %s channel ignored (disabled)\n", 3615 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3616 continue; 3617 } 3618 if (PDC_IS_265(sc)) 3619 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3620 pdc20265_pci_intr); 3621 else 3622 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3623 pdc202xx_pci_intr); 3624 if (cp->hw_ok == 0) 3625 continue; 3626 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3627 st &= ~(PDC_IS_262(sc) ? 3628 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3629 pciide_map_compat_intr(pa, cp, channel, interface); 3630 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3631 } 3632 if (!PDC_IS_268(sc)) { 3633 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3634 "0x%x\n", st), DEBUG_PROBE); 3635 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3636 } 3637 return; 3638 } 3639 3640 void 3641 pdc202xx_setup_channel(chp) 3642 struct channel_softc *chp; 3643 { 3644 struct ata_drive_datas *drvp; 3645 int drive; 3646 pcireg_t mode, st; 3647 u_int32_t idedma_ctl, scr, atapi; 3648 struct pciide_channel *cp = (struct pciide_channel*)chp; 3649 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3650 int channel = chp->channel; 3651 3652 /* setup DMA if needed */ 3653 pciide_channel_dma_setup(cp); 3654 3655 idedma_ctl = 0; 3656 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3657 sc->sc_wdcdev.sc_dev.dv_xname, 3658 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3659 DEBUG_PROBE); 3660 3661 /* Per channel settings */ 3662 if (PDC_IS_262(sc)) { 3663 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3664 PDC262_U66); 3665 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3666 /* Trim UDMA mode */ 3667 if ((st & PDC262_STATE_80P(channel)) != 0 || 3668 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3669 chp->ch_drive[0].UDMA_mode <= 2) || 3670 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3671 chp->ch_drive[1].UDMA_mode <= 2)) { 3672 if (chp->ch_drive[0].UDMA_mode > 2) 3673 chp->ch_drive[0].UDMA_mode = 2; 3674 if (chp->ch_drive[1].UDMA_mode > 2) 3675 chp->ch_drive[1].UDMA_mode = 2; 3676 } 3677 /* Set U66 if needed */ 3678 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3679 chp->ch_drive[0].UDMA_mode > 2) || 3680 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3681 chp->ch_drive[1].UDMA_mode > 2)) 3682 scr |= PDC262_U66_EN(channel); 3683 else 3684 scr &= ~PDC262_U66_EN(channel); 3685 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3686 PDC262_U66, scr); 3687 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3688 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3689 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3690 PDC262_ATAPI(channel))), DEBUG_PROBE); 3691 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3692 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3693 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3694 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3695 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3696 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3697 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3698 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3699 atapi = 0; 3700 else 3701 atapi = PDC262_ATAPI_UDMA; 3702 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3703 PDC262_ATAPI(channel), atapi); 3704 } 3705 } 3706 for (drive = 0; drive < 2; drive++) { 3707 drvp = &chp->ch_drive[drive]; 3708 /* If no drive, skip */ 3709 if ((drvp->drive_flags & DRIVE) == 0) 3710 continue; 3711 mode = 0; 3712 if (drvp->drive_flags & DRIVE_UDMA) { 3713 /* use Ultra/DMA */ 3714 drvp->drive_flags &= ~DRIVE_DMA; 3715 mode = PDC2xx_TIM_SET_MB(mode, 3716 pdc2xx_udma_mb[drvp->UDMA_mode]); 3717 mode = PDC2xx_TIM_SET_MC(mode, 3718 pdc2xx_udma_mc[drvp->UDMA_mode]); 3719 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3720 } else if (drvp->drive_flags & DRIVE_DMA) { 3721 mode = PDC2xx_TIM_SET_MB(mode, 3722 pdc2xx_dma_mb[drvp->DMA_mode]); 3723 mode = PDC2xx_TIM_SET_MC(mode, 3724 pdc2xx_dma_mc[drvp->DMA_mode]); 3725 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3726 } else { 3727 mode = PDC2xx_TIM_SET_MB(mode, 3728 pdc2xx_dma_mb[0]); 3729 mode = PDC2xx_TIM_SET_MC(mode, 3730 pdc2xx_dma_mc[0]); 3731 } 3732 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3733 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3734 if (drvp->drive_flags & DRIVE_ATA) 3735 mode |= PDC2xx_TIM_PRE; 3736 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3737 if (drvp->PIO_mode >= 3) { 3738 mode |= PDC2xx_TIM_IORDY; 3739 if (drive == 0) 3740 mode |= PDC2xx_TIM_IORDYp; 3741 } 3742 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3743 "timings 0x%x\n", 3744 sc->sc_wdcdev.sc_dev.dv_xname, 3745 chp->channel, drive, mode), DEBUG_PROBE); 3746 pci_conf_write(sc->sc_pc, sc->sc_tag, 3747 PDC2xx_TIM(chp->channel, drive), mode); 3748 } 3749 if (idedma_ctl != 0) { 3750 /* Add software bits in status register */ 3751 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3752 IDEDMA_CTL, idedma_ctl); 3753 } 3754 pciide_print_modes(cp); 3755 } 3756 3757 void 3758 pdc20268_setup_channel(chp) 3759 struct channel_softc *chp; 3760 { 3761 struct ata_drive_datas *drvp; 3762 int drive; 3763 u_int32_t idedma_ctl; 3764 struct pciide_channel *cp = (struct pciide_channel*)chp; 3765 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3766 int u100; 3767 3768 /* setup DMA if needed */ 3769 pciide_channel_dma_setup(cp); 3770 3771 idedma_ctl = 0; 3772 3773 /* I don't know what this is for, FreeBSD does it ... */ 3774 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3775 IDEDMA_CMD + 0x1, 0x0b); 3776 3777 /* 3778 * I don't know what this is for; FreeBSD checks this ... this is not 3779 * cable type detect. 3780 */ 3781 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3782 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3783 3784 for (drive = 0; drive < 2; drive++) { 3785 drvp = &chp->ch_drive[drive]; 3786 /* If no drive, skip */ 3787 if ((drvp->drive_flags & DRIVE) == 0) 3788 continue; 3789 if (drvp->drive_flags & DRIVE_UDMA) { 3790 /* use Ultra/DMA */ 3791 drvp->drive_flags &= ~DRIVE_DMA; 3792 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3793 if (drvp->UDMA_mode > 2 && u100 == 0) 3794 drvp->UDMA_mode = 2; 3795 } else if (drvp->drive_flags & DRIVE_DMA) { 3796 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3797 } 3798 } 3799 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3800 if (idedma_ctl != 0) { 3801 /* Add software bits in status register */ 3802 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3803 IDEDMA_CTL, idedma_ctl); 3804 } 3805 pciide_print_modes(cp); 3806 } 3807 3808 int 3809 pdc202xx_pci_intr(arg) 3810 void *arg; 3811 { 3812 struct pciide_softc *sc = arg; 3813 struct pciide_channel *cp; 3814 struct channel_softc *wdc_cp; 3815 int i, rv, crv; 3816 u_int32_t scr; 3817 3818 rv = 0; 3819 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3820 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3821 cp = &sc->pciide_channels[i]; 3822 wdc_cp = &cp->wdc_channel; 3823 /* If a compat channel skip. */ 3824 if (cp->compat) 3825 continue; 3826 if (scr & PDC2xx_SCR_INT(i)) { 3827 crv = wdcintr(wdc_cp); 3828 if (crv == 0) 3829 printf("%s:%d: bogus intr (reg 0x%x)\n", 3830 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3831 else 3832 rv = 1; 3833 } 3834 } 3835 return rv; 3836 } 3837 3838 int 3839 pdc20265_pci_intr(arg) 3840 void *arg; 3841 { 3842 struct pciide_softc *sc = arg; 3843 struct pciide_channel *cp; 3844 struct channel_softc *wdc_cp; 3845 int i, rv, crv; 3846 u_int32_t dmastat; 3847 3848 rv = 0; 3849 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3850 cp = &sc->pciide_channels[i]; 3851 wdc_cp = &cp->wdc_channel; 3852 /* If a compat channel skip. */ 3853 if (cp->compat) 3854 continue; 3855 /* 3856 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3857 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3858 * So use it instead (requires 2 reg reads instead of 1, 3859 * but we can't do it another way). 3860 */ 3861 dmastat = bus_space_read_1(sc->sc_dma_iot, 3862 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3863 if((dmastat & IDEDMA_CTL_INTR) == 0) 3864 continue; 3865 crv = wdcintr(wdc_cp); 3866 if (crv == 0) 3867 printf("%s:%d: bogus intr\n", 3868 sc->sc_wdcdev.sc_dev.dv_xname, i); 3869 else 3870 rv = 1; 3871 } 3872 return rv; 3873 } 3874 3875 void 3876 opti_chip_map(sc, pa) 3877 struct pciide_softc *sc; 3878 struct pci_attach_args *pa; 3879 { 3880 struct pciide_channel *cp; 3881 bus_size_t cmdsize, ctlsize; 3882 pcireg_t interface; 3883 u_int8_t init_ctrl; 3884 int channel; 3885 3886 if (pciide_chipen(sc, pa) == 0) 3887 return; 3888 printf("%s: bus-master DMA support present", 3889 sc->sc_wdcdev.sc_dev.dv_xname); 3890 3891 /* 3892 * XXXSCW: 3893 * There seem to be a couple of buggy revisions/implementations 3894 * of the OPTi pciide chipset. This kludge seems to fix one of 3895 * the reported problems (PR/11644) but still fails for the 3896 * other (PR/13151), although the latter may be due to other 3897 * issues too... 3898 */ 3899 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3900 printf(" but disabled due to chip rev. <= 0x12"); 3901 sc->sc_dma_ok = 0; 3902 } else 3903 pciide_mapreg_dma(sc, pa); 3904 3905 printf("\n"); 3906 3907 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 3908 WDC_CAPABILITY_MODE; 3909 sc->sc_wdcdev.PIO_cap = 4; 3910 if (sc->sc_dma_ok) { 3911 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3912 sc->sc_wdcdev.irqack = pciide_irqack; 3913 sc->sc_wdcdev.DMA_cap = 2; 3914 } 3915 sc->sc_wdcdev.set_modes = opti_setup_channel; 3916 3917 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3918 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3919 3920 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3921 OPTI_REG_INIT_CONTROL); 3922 3923 interface = PCI_INTERFACE(pa->pa_class); 3924 3925 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3926 cp = &sc->pciide_channels[channel]; 3927 if (pciide_chansetup(sc, channel, interface) == 0) 3928 continue; 3929 if (channel == 1 && 3930 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3931 printf("%s: %s channel ignored (disabled)\n", 3932 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3933 continue; 3934 } 3935 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3936 pciide_pci_intr); 3937 if (cp->hw_ok == 0) 3938 continue; 3939 pciide_map_compat_intr(pa, cp, channel, interface); 3940 if (cp->hw_ok == 0) 3941 continue; 3942 opti_setup_channel(&cp->wdc_channel); 3943 } 3944 } 3945 3946 void 3947 opti_setup_channel(chp) 3948 struct channel_softc *chp; 3949 { 3950 struct ata_drive_datas *drvp; 3951 struct pciide_channel *cp = (struct pciide_channel*)chp; 3952 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3953 int drive, spd; 3954 int mode[2]; 3955 u_int8_t rv, mr; 3956 3957 /* 3958 * The `Delay' and `Address Setup Time' fields of the 3959 * Miscellaneous Register are always zero initially. 3960 */ 3961 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3962 mr &= ~(OPTI_MISC_DELAY_MASK | 3963 OPTI_MISC_ADDR_SETUP_MASK | 3964 OPTI_MISC_INDEX_MASK); 3965 3966 /* Prime the control register before setting timing values */ 3967 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3968 3969 /* Determine the clockrate of the PCIbus the chip is attached to */ 3970 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3971 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3972 3973 /* setup DMA if needed */ 3974 pciide_channel_dma_setup(cp); 3975 3976 for (drive = 0; drive < 2; drive++) { 3977 drvp = &chp->ch_drive[drive]; 3978 /* If no drive, skip */ 3979 if ((drvp->drive_flags & DRIVE) == 0) { 3980 mode[drive] = -1; 3981 continue; 3982 } 3983 3984 if ((drvp->drive_flags & DRIVE_DMA)) { 3985 /* 3986 * Timings will be used for both PIO and DMA, 3987 * so adjust DMA mode if needed 3988 */ 3989 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3990 drvp->PIO_mode = drvp->DMA_mode + 2; 3991 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3992 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3993 drvp->PIO_mode - 2 : 0; 3994 if (drvp->DMA_mode == 0) 3995 drvp->PIO_mode = 0; 3996 3997 mode[drive] = drvp->DMA_mode + 5; 3998 } else 3999 mode[drive] = drvp->PIO_mode; 4000 4001 if (drive && mode[0] >= 0 && 4002 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4003 /* 4004 * Can't have two drives using different values 4005 * for `Address Setup Time'. 4006 * Slow down the faster drive to compensate. 4007 */ 4008 int d = (opti_tim_as[spd][mode[0]] > 4009 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4010 4011 mode[d] = mode[1-d]; 4012 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4013 chp->ch_drive[d].DMA_mode = 0; 4014 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4015 } 4016 } 4017 4018 for (drive = 0; drive < 2; drive++) { 4019 int m; 4020 if ((m = mode[drive]) < 0) 4021 continue; 4022 4023 /* Set the Address Setup Time and select appropriate index */ 4024 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4025 rv |= OPTI_MISC_INDEX(drive); 4026 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4027 4028 /* Set the pulse width and recovery timing parameters */ 4029 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4030 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4031 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4032 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4033 4034 /* Set the Enhanced Mode register appropriately */ 4035 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4036 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4037 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4038 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4039 } 4040 4041 /* Finally, enable the timings */ 4042 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4043 4044 pciide_print_modes(cp); 4045 } 4046 4047 #define ACARD_IS_850(sc) \ 4048 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4049 4050 void 4051 acard_chip_map(sc, pa) 4052 struct pciide_softc *sc; 4053 struct pci_attach_args *pa; 4054 { 4055 struct pciide_channel *cp; 4056 int i; 4057 pcireg_t interface; 4058 bus_size_t cmdsize, ctlsize; 4059 4060 if (pciide_chipen(sc, pa) == 0) 4061 return; 4062 4063 /* 4064 * when the chip is in native mode it identifies itself as a 4065 * 'misc mass storage'. Fake interface in this case. 4066 */ 4067 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4068 interface = PCI_INTERFACE(pa->pa_class); 4069 } else { 4070 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4071 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4072 } 4073 4074 printf("%s: bus-master DMA support present", 4075 sc->sc_wdcdev.sc_dev.dv_xname); 4076 pciide_mapreg_dma(sc, pa); 4077 printf("\n"); 4078 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4079 WDC_CAPABILITY_MODE; 4080 4081 if (sc->sc_dma_ok) { 4082 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4083 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4084 sc->sc_wdcdev.irqack = pciide_irqack; 4085 } 4086 sc->sc_wdcdev.PIO_cap = 4; 4087 sc->sc_wdcdev.DMA_cap = 2; 4088 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4089 4090 sc->sc_wdcdev.set_modes = acard_setup_channel; 4091 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4092 sc->sc_wdcdev.nchannels = 2; 4093 4094 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4095 cp = &sc->pciide_channels[i]; 4096 if (pciide_chansetup(sc, i, interface) == 0) 4097 continue; 4098 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4099 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4100 &ctlsize, pciide_pci_intr); 4101 } else { 4102 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4103 &cmdsize, &ctlsize); 4104 } 4105 if (cp->hw_ok == 0) 4106 return; 4107 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4108 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4109 wdcattach(&cp->wdc_channel); 4110 acard_setup_channel(&cp->wdc_channel); 4111 } 4112 if (!ACARD_IS_850(sc)) { 4113 u_int32_t reg; 4114 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4115 reg &= ~ATP860_CTRL_INT; 4116 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4117 } 4118 } 4119 4120 void 4121 acard_setup_channel(chp) 4122 struct channel_softc *chp; 4123 { 4124 struct ata_drive_datas *drvp; 4125 struct pciide_channel *cp = (struct pciide_channel*)chp; 4126 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4127 int channel = chp->channel; 4128 int drive; 4129 u_int32_t idetime, udma_mode; 4130 u_int32_t idedma_ctl; 4131 4132 /* setup DMA if needed */ 4133 pciide_channel_dma_setup(cp); 4134 4135 if (ACARD_IS_850(sc)) { 4136 idetime = 0; 4137 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4138 udma_mode &= ~ATP850_UDMA_MASK(channel); 4139 } else { 4140 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4141 idetime &= ~ATP860_SETTIME_MASK(channel); 4142 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4143 udma_mode &= ~ATP860_UDMA_MASK(channel); 4144 4145 /* check 80 pins cable */ 4146 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4147 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4148 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4149 & ATP860_CTRL_80P(chp->channel)) { 4150 if (chp->ch_drive[0].UDMA_mode > 2) 4151 chp->ch_drive[0].UDMA_mode = 2; 4152 if (chp->ch_drive[1].UDMA_mode > 2) 4153 chp->ch_drive[1].UDMA_mode = 2; 4154 } 4155 } 4156 } 4157 4158 idedma_ctl = 0; 4159 4160 /* Per drive settings */ 4161 for (drive = 0; drive < 2; drive++) { 4162 drvp = &chp->ch_drive[drive]; 4163 /* If no drive, skip */ 4164 if ((drvp->drive_flags & DRIVE) == 0) 4165 continue; 4166 /* add timing values, setup DMA if needed */ 4167 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4168 (drvp->drive_flags & DRIVE_UDMA)) { 4169 /* use Ultra/DMA */ 4170 if (ACARD_IS_850(sc)) { 4171 idetime |= ATP850_SETTIME(drive, 4172 acard_act_udma[drvp->UDMA_mode], 4173 acard_rec_udma[drvp->UDMA_mode]); 4174 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4175 acard_udma_conf[drvp->UDMA_mode]); 4176 } else { 4177 idetime |= ATP860_SETTIME(channel, drive, 4178 acard_act_udma[drvp->UDMA_mode], 4179 acard_rec_udma[drvp->UDMA_mode]); 4180 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4181 acard_udma_conf[drvp->UDMA_mode]); 4182 } 4183 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4184 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4185 (drvp->drive_flags & DRIVE_DMA)) { 4186 /* use Multiword DMA */ 4187 drvp->drive_flags &= ~DRIVE_UDMA; 4188 if (ACARD_IS_850(sc)) { 4189 idetime |= ATP850_SETTIME(drive, 4190 acard_act_dma[drvp->DMA_mode], 4191 acard_rec_dma[drvp->DMA_mode]); 4192 } else { 4193 idetime |= ATP860_SETTIME(channel, drive, 4194 acard_act_dma[drvp->DMA_mode], 4195 acard_rec_dma[drvp->DMA_mode]); 4196 } 4197 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4198 } else { 4199 /* PIO only */ 4200 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4201 if (ACARD_IS_850(sc)) { 4202 idetime |= ATP850_SETTIME(drive, 4203 acard_act_pio[drvp->PIO_mode], 4204 acard_rec_pio[drvp->PIO_mode]); 4205 } else { 4206 idetime |= ATP860_SETTIME(channel, drive, 4207 acard_act_pio[drvp->PIO_mode], 4208 acard_rec_pio[drvp->PIO_mode]); 4209 } 4210 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4211 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4212 | ATP8x0_CTRL_EN(channel)); 4213 } 4214 } 4215 4216 if (idedma_ctl != 0) { 4217 /* Add software bits in status register */ 4218 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4219 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4220 } 4221 pciide_print_modes(cp); 4222 4223 if (ACARD_IS_850(sc)) { 4224 pci_conf_write(sc->sc_pc, sc->sc_tag, 4225 ATP850_IDETIME(channel), idetime); 4226 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4227 } else { 4228 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4229 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4230 } 4231 } 4232 4233 int 4234 acard_pci_intr(arg) 4235 void *arg; 4236 { 4237 struct pciide_softc *sc = arg; 4238 struct pciide_channel *cp; 4239 struct channel_softc *wdc_cp; 4240 int rv = 0; 4241 int dmastat, i, crv; 4242 4243 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4244 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4245 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4246 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4247 continue; 4248 cp = &sc->pciide_channels[i]; 4249 wdc_cp = &cp->wdc_channel; 4250 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4251 (void)wdcintr(wdc_cp); 4252 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4253 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4254 continue; 4255 } 4256 crv = wdcintr(wdc_cp); 4257 if (crv == 0) 4258 printf("%s:%d: bogus intr\n", 4259 sc->sc_wdcdev.sc_dev.dv_xname, i); 4260 else if (crv == 1) 4261 rv = 1; 4262 else if (rv == 0) 4263 rv = crv; 4264 } 4265 return rv; 4266 } 4267 4268 static int 4269 sl82c105_bugchk(struct pci_attach_args *pa) 4270 { 4271 4272 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4273 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4274 return (0); 4275 4276 if (PCI_REVISION(pa->pa_class) <= 0x05) 4277 return (1); 4278 4279 return (0); 4280 } 4281 4282 void 4283 sl82c105_chip_map(sc, pa) 4284 struct pciide_softc *sc; 4285 struct pci_attach_args *pa; 4286 { 4287 struct pciide_channel *cp; 4288 bus_size_t cmdsize, ctlsize; 4289 pcireg_t interface, idecr; 4290 int channel; 4291 4292 if (pciide_chipen(sc, pa) == 0) 4293 return; 4294 4295 printf("%s: bus-master DMA support present", 4296 sc->sc_wdcdev.sc_dev.dv_xname); 4297 4298 /* 4299 * Check to see if we're part of the Winbond 83c553 Southbridge. 4300 * If so, we need to disable DMA on rev. <= 5 of that chip. 4301 */ 4302 if (pci_find_device(pa, sl82c105_bugchk)) { 4303 printf(" but disabled due to 83c553 rev. <= 0x05"); 4304 sc->sc_dma_ok = 0; 4305 } else 4306 pciide_mapreg_dma(sc, pa); 4307 printf("\n"); 4308 4309 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4310 WDC_CAPABILITY_MODE; 4311 sc->sc_wdcdev.PIO_cap = 4; 4312 if (sc->sc_dma_ok) { 4313 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4314 sc->sc_wdcdev.irqack = pciide_irqack; 4315 sc->sc_wdcdev.DMA_cap = 2; 4316 } 4317 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4318 4319 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4320 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4321 4322 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4323 4324 interface = PCI_INTERFACE(pa->pa_class); 4325 4326 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4327 cp = &sc->pciide_channels[channel]; 4328 if (pciide_chansetup(sc, channel, interface) == 0) 4329 continue; 4330 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4331 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4332 printf("%s: %s channel ignored (disabled)\n", 4333 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4334 continue; 4335 } 4336 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4337 pciide_pci_intr); 4338 if (cp->hw_ok == 0) 4339 continue; 4340 pciide_map_compat_intr(pa, cp, channel, interface); 4341 if (cp->hw_ok == 0) 4342 continue; 4343 sl82c105_setup_channel(&cp->wdc_channel); 4344 } 4345 } 4346 4347 void 4348 sl82c105_setup_channel(chp) 4349 struct channel_softc *chp; 4350 { 4351 struct ata_drive_datas *drvp; 4352 struct pciide_channel *cp = (struct pciide_channel*)chp; 4353 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4354 int pxdx_reg, drive; 4355 pcireg_t pxdx; 4356 4357 /* Set up DMA if needed. */ 4358 pciide_channel_dma_setup(cp); 4359 4360 for (drive = 0; drive < 2; drive++) { 4361 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4362 : SYMPH_P1D0CR) + (drive * 4); 4363 4364 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4365 4366 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4367 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4368 4369 drvp = &chp->ch_drive[drive]; 4370 /* If no drive, skip. */ 4371 if ((drvp->drive_flags & DRIVE) == 0) { 4372 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4373 continue; 4374 } 4375 4376 if (drvp->drive_flags & DRIVE_DMA) { 4377 /* 4378 * Timings will be used for both PIO and DMA, 4379 * so adjust DMA mode if needed. 4380 */ 4381 if (drvp->PIO_mode >= 3) { 4382 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4383 drvp->DMA_mode = drvp->PIO_mode - 2; 4384 if (drvp->DMA_mode < 1) { 4385 /* 4386 * Can't mix both PIO and DMA. 4387 * Disable DMA. 4388 */ 4389 drvp->drive_flags &= ~DRIVE_DMA; 4390 } 4391 } else { 4392 /* 4393 * Can't mix both PIO and DMA. Disable 4394 * DMA. 4395 */ 4396 drvp->drive_flags &= ~DRIVE_DMA; 4397 } 4398 } 4399 4400 if (drvp->drive_flags & DRIVE_DMA) { 4401 /* Use multi-word DMA. */ 4402 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4403 PxDx_CMD_ON_SHIFT; 4404 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4405 } else { 4406 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4407 PxDx_CMD_ON_SHIFT; 4408 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4409 } 4410 4411 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4412 4413 /* ...and set the mode for this drive. */ 4414 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4415 } 4416 4417 pciide_print_modes(cp); 4418 } 4419 4420 void 4421 serverworks_chip_map(sc, pa) 4422 struct pciide_softc *sc; 4423 struct pci_attach_args *pa; 4424 { 4425 struct pciide_channel *cp; 4426 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4427 pcitag_t pcib_tag; 4428 int channel; 4429 bus_size_t cmdsize, ctlsize; 4430 4431 if (pciide_chipen(sc, pa) == 0) 4432 return; 4433 4434 printf("%s: bus-master DMA support present", 4435 sc->sc_wdcdev.sc_dev.dv_xname); 4436 pciide_mapreg_dma(sc, pa); 4437 printf("\n"); 4438 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4439 WDC_CAPABILITY_MODE; 4440 4441 if (sc->sc_dma_ok) { 4442 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4443 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4444 sc->sc_wdcdev.irqack = pciide_irqack; 4445 } 4446 sc->sc_wdcdev.PIO_cap = 4; 4447 sc->sc_wdcdev.DMA_cap = 2; 4448 switch (sc->sc_pp->ide_product) { 4449 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4450 sc->sc_wdcdev.UDMA_cap = 2; 4451 break; 4452 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4453 if (PCI_REVISION(pa->pa_class) < 0x92) 4454 sc->sc_wdcdev.UDMA_cap = 4; 4455 else 4456 sc->sc_wdcdev.UDMA_cap = 5; 4457 break; 4458 } 4459 4460 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4461 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4462 sc->sc_wdcdev.nchannels = 2; 4463 4464 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4465 cp = &sc->pciide_channels[channel]; 4466 if (pciide_chansetup(sc, channel, interface) == 0) 4467 continue; 4468 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4469 serverworks_pci_intr); 4470 if (cp->hw_ok == 0) 4471 return; 4472 pciide_map_compat_intr(pa, cp, channel, interface); 4473 if (cp->hw_ok == 0) 4474 return; 4475 serverworks_setup_channel(&cp->wdc_channel); 4476 } 4477 4478 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4479 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4480 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4481 } 4482 4483 void 4484 serverworks_setup_channel(chp) 4485 struct channel_softc *chp; 4486 { 4487 struct ata_drive_datas *drvp; 4488 struct pciide_channel *cp = (struct pciide_channel*)chp; 4489 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4490 int channel = chp->channel; 4491 int drive, unit; 4492 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4493 u_int32_t idedma_ctl; 4494 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4495 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4496 4497 /* setup DMA if needed */ 4498 pciide_channel_dma_setup(cp); 4499 4500 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4501 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4502 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4503 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4504 4505 pio_time &= ~(0xffff << (16 * channel)); 4506 dma_time &= ~(0xffff << (16 * channel)); 4507 pio_mode &= ~(0xff << (8 * channel + 16)); 4508 udma_mode &= ~(0xff << (8 * channel + 16)); 4509 udma_mode &= ~(3 << (2 * channel)); 4510 4511 idedma_ctl = 0; 4512 4513 /* Per drive settings */ 4514 for (drive = 0; drive < 2; drive++) { 4515 drvp = &chp->ch_drive[drive]; 4516 /* If no drive, skip */ 4517 if ((drvp->drive_flags & DRIVE) == 0) 4518 continue; 4519 unit = drive + 2 * channel; 4520 /* add timing values, setup DMA if needed */ 4521 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4522 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4523 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4524 (drvp->drive_flags & DRIVE_UDMA)) { 4525 /* use Ultra/DMA, check for 80-pin cable */ 4526 if (drvp->UDMA_mode > 2 && 4527 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4528 drvp->UDMA_mode = 2; 4529 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4530 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4531 udma_mode |= 1 << unit; 4532 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4533 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4534 (drvp->drive_flags & DRIVE_DMA)) { 4535 /* use Multiword DMA */ 4536 drvp->drive_flags &= ~DRIVE_UDMA; 4537 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4538 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4539 } else { 4540 /* PIO only */ 4541 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4542 } 4543 } 4544 4545 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4546 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4547 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4548 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4549 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4550 4551 if (idedma_ctl != 0) { 4552 /* Add software bits in status register */ 4553 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4554 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4555 } 4556 pciide_print_modes(cp); 4557 } 4558 4559 int 4560 serverworks_pci_intr(arg) 4561 void *arg; 4562 { 4563 struct pciide_softc *sc = arg; 4564 struct pciide_channel *cp; 4565 struct channel_softc *wdc_cp; 4566 int rv = 0; 4567 int dmastat, i, crv; 4568 4569 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4570 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4571 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4572 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4573 IDEDMA_CTL_INTR) 4574 continue; 4575 cp = &sc->pciide_channels[i]; 4576 wdc_cp = &cp->wdc_channel; 4577 crv = wdcintr(wdc_cp); 4578 if (crv == 0) { 4579 printf("%s:%d: bogus intr\n", 4580 sc->sc_wdcdev.sc_dev.dv_xname, i); 4581 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4582 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4583 } else 4584 rv = 1; 4585 } 4586 return rv; 4587 } 4588
Indexes created Thu Sep 25 08:09:54 GMT 2025